Controller for switching converters

Abstract

A controller circuit (1012) is configured to receive measurement signals (1040, 1050, 1072) representative of the power converter state and a control signal (1062) representative of the power converter resonant period. Based on the power converter state and the power converter resonant period, the controller circuit (1012) determines a charge interval, a first dead time interval, a discharge interval, and a second dead time interval for the switching cycle. The first dead time interval follows the charge interval. The discharge interval follows the first dead time interval. The second dead time interval follows the discharge interval. The controller circuit (1012) provides a first drive signal (1030) and a second drive signal (1032) based on the charge interval, the first dead time interval, the discharge interval, and the second dead time interval.

Description

[Technical Field]

[0001] A power supply system can transmit power from an alternating current (AC) source to a load. The power supply system can rectify the AC voltage to generate a direct current (DC) voltage. The power supply system can also include a power converter, such as a switch-mode power converter, to regulate the DC voltage to a target DC voltage and provide the regulated DC voltage to the load. The power supply system can use various techniques to improve the efficiency of the power transfer, such as reducing the phase delay between the AC current drawn from the AC source and the AC voltage, and reducing power losses during switching of the power converter. Summary of the Invention

[0002] In one example, an apparatus includes a controller circuit having a first control input and a second control input and a first control output and a second control output. The controller circuit is configured to: 1) receive a measurement signal representing a power converter state at the first control input; 2) receive a control signal representing a power converter resonant period at the second control input; 3) determine a charge interval of a switching cycle, a first dead time interval of the switching cycle, a discharge interval of the switching cycle, and a second dead time interval of the switching cycle based on the power converter state and the power converter resonant period; and 4) provide a first drive signal at the first control output and a second drive signal at the second control output within the switching cycle. The first dead time interval follows the charge interval, the discharge interval follows the first dead time interval, and the second dead time interval follows the discharge interval. Within the charge interval, the first drive signal has a first state and the second drive signal has a second state. Within the first dead time interval and the second dead time interval, the first drive signal and the second drive signal have second states. Within the discharge interval, the first drive signal has a second state and the second drive signal has a first state.

[0003] In another example, a method includes: 1) receiving a measurement signal representative of a power converter state; 2) receiving a control signal representative of a power converter resonant period; 3) determining a charge interval of a switching cycle, a first dead time interval of the switching cycle, a discharge interval of the switching cycle, and a second dead time interval of the switching cycle based on the power converter state and the power converter resonant period; and 4) providing a first drive signal and a second drive signal within the switching cycle. The first dead time interval follows the charge interval, the discharge interval follows the first dead time interval, and the second dead time interval follows the discharge interval. Within the charge interval, the first drive signal has a first state and the second drive signal has a second state. Within the first and second dead time intervals, the first and second drive signals have second states. Within the discharge interval, the first drive signal has a second state and the second drive signal has the first state.

[0004] In a further example, an apparatus includes a power converter and a controller circuit. The power converter has a positive input, a negative input, a positive output, and a negative output. The power converter includes a first switch, a second switch, and an inductor. The first switch and the second switch are series-coupled between the positive output and the negative output. A first current terminal of the first switch is coupled to a second current terminal of the second switch and to the inductor. The controller circuit is configured to: 1) receive a measurement signal representative of a state of the power converter; 2) receive a control signal representative of a resonant period of the power converter; 3) determine a charge interval of a switching cycle of the power converter, a first dead time interval of the switching cycle, a discharge interval of the switching cycle, and a second dead time interval of the switching cycle based on the state of the power converter and the resonant period of the power converter; and 4) provide a first drive signal to the first switch and a second drive signal to the second switch within the switching cycle. The first dead time interval follows the charge interval, the discharge interval follows the first dead time interval, and the second dead time interval follows the discharge interval. During the charge interval, the first drive signal has a first state and the second drive signal has a second state. During the first and second dead time intervals, the first and second drive signals have second states. During the discharge interval, the first drive signal has a second state and the second drive signal has the first state. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic diagram of an exemplary power transfer system.

[0006] [Figure 2] 2 is a waveform diagram illustrating an example of the phase relationship between the input voltage and the input current of the power transmission system of FIG. 1.

[0007] [Figure 3] FIG. 2 is a schematic diagram of an example power supply system that may be part of the power transmission system of FIG. 1.

[0008] [Figure 4] 4 includes waveform diagrams illustrating an example operation of the power supply system of FIG. 3. [Figure 5] 4 includes waveform diagrams illustrating an example operation of the power supply system of FIG. 3.

[0009] [Figure 6] FIG. 2 is a schematic diagram of an example power supply system that may be part of the power transmission system of FIG. 1.

[0010] [Figure 7] 7 is a waveform diagram illustrating an example operation of the power supply system of FIGS. 3 and 6. FIG. [Figure 8] 7 is a waveform diagram illustrating an example operation of the power supply system of FIGS. 3 and 6. FIG. [Figure 9] 7 is a waveform diagram illustrating an example operation of the power supply system of FIGS. 3 and 6. FIG.

[0011] [Figure 10] FIG. 2 is a schematic diagram of an example power supply system that may be part of the power transmission system of FIG. 1.

[0012] [Figure 11] FIG. 11 is a block diagram illustrating example internal components of the power supply system of FIG.

[0013] [Figure 12A] 11 includes waveform diagrams illustrating currents and voltages in the power supply system of FIG. 10.

[0014] [Figure 12B] FIG. 12B is a state plan view illustrating the relationship between the voltage and current waveforms of FIG. 12A.

[0015] [Figure 13] FIG. 12 is a block diagram of an example of the generalized interval calculation circuit shown in FIG. 11.

[0016] [Figure 14]FIG. 1 is a block diagram of an example spacing calculation circuit including switching frequency compensation.

[0017] [Figure 15] FIG. 15 is a block diagram of an example compensation circuit that may be part of the spacing compensation circuit of FIG. 14.

[0018] [Figure 16] FIG. 2 is a block diagram of an example interval calculation circuit including an example switching frequency compensation circuit.

[0019] [Figure 17] FIG. 15 is a block diagram of an example switching frequency compensation circuit that may be part of the spacing compensation circuit of FIG. 14.

[0020] [Figure 18] 12 is a flowchart of an example method of switching period adjustment that may be implemented by the interval compensation circuit of FIG. 11.

[0021] [Figure 19] 12 is a flowchart of an exemplary method of adaptive gain adjustment that may be implemented by the interval calculation circuit of FIG.

[0022] [Figure 20] FIG. 12 is a block diagram of an example compensation circuit 2000 that may be part of the interval calculation circuit of FIG.

[0023] [Figure 21] FIG. 2 is a block diagram of an example interval calculation circuit including an example inductor current compensation circuit.

[0024] [Figure 22] FIG. 22 is a block diagram of an example inductor current compensation circuit element that may be used in the interval calculation circuit of FIG. 21. [Figure 23] FIG. 22 is a block diagram of an example inductor current compensation circuit element that may be used in the interval calculation circuit of FIG. 21.

[0025] [Figure 24] 12 is a block diagram of an example time constant estimation circuit that can provide input to the example interval calculation circuit of FIG. 11.

[0026] [Figure 25] 11 includes a schematic diagram illustrating example internal components of the power supply system of FIG. 10. [Figure 26] 11 includes waveform diagrams illustrating the operation of the power supply system of FIG. 10. [Figure 27] 11 includes waveform diagrams illustrating the operation of the power supply system of FIG. 10.

[0027] [Figure 28] 11 is a graph illustrating an example operation of the power supply system of FIG.

[0028] [Figure 29] FIG. 26 is a block diagram illustrating an example hardware system that may be part of the example power supply system of FIGS.

[0029] [Figure 30] 4 is a flowchart illustrating an example method of controlling a power converter. DETAILED DESCRIPTION OF THE INVENTION

[0030] 1 is a schematic diagram illustrating an example of a power transmission system 100. The power transmission system 100 may include an AC power source 102, a power supply system 104, and a load 106. The power source 104 may include a positive input 105a, a negative input 105b, a positive output 107a, and a negative output 107b. The AC power source 102 generates an AC input voltage signal 108 (V inThe AC input voltage signal 108 may have positive half-cycles when the voltage signal is positive (e.g., between T0 and T1 and between T2 and T3) and negative half-cycles when the voltage signal is negative (e.g., between T1 and T2). During the positive half-cycles, the positive input 105a may receive a higher voltage than the negative input 105b, and during the negative half-cycles, the polarity is reversed and the positive input 105a may receive a lower voltage than the negative input 105b. The AC input current signal 110 (I in An AC input current signal (labeled (t)) may also flow into the positive input 105a and return to the AC power source 102 from the negative input 105b during a positive half-cycle of the AC input voltage signal 108. An AC input current signal may also flow into the negative input 105b and return to the AC power source 102 from the positive input 105a during a negative half-cycle of the AC input voltage signal 108.

[0031] The power supply system 104 generates a DC output voltage signal 112 (V out Positive output 107a may provide a positive power supply rail, and negative output 107b may provide a negative power supply rail. Power supply system 104 may provide a DC output voltage signal 112 to load 106, which may include electronic components that operate on DC voltage. Power supply system 104 also generates an output DC current signal 114 (I ) that may flow from positive output 107a, through load 106, and back to negative output 107b. out (t)). The power transfer system 100 can include a capacitor 118 to reduce ripple in the DC output voltage signal 112 and perform a filtering operation to output the DC current signal 114.

[0032] To generate the DC output voltage signal 112 from the AC input voltage signal 108, the power supply system 104 may include a rectifier circuit 120 and a power conversion circuit 122. The rectifier circuit 120 may perform a rectification operation to convert the AC input voltage signal 108 into a DC input voltage signal 130. As part of the rectification circuit, the rectifier circuit 120 may pass a positive voltage of the AC input voltage signal 108 during a positive half-cycle as the DC input voltage signal 130. The rectifier circuit 120 may also block a negative voltage of the AC input voltage signal 108 during a negative half-cycle in a half-wave rectification operation, or convert a negative voltage to a positive voltage in a full-wave rectification operation to generate the pulsating DC input voltage signal 130. The power conversion circuit 122 may then generate the DC output voltage signal 112 from the DC input voltage signal 130 based on a conversion ratio. If the power conversion circuit 122 is a step-up converter (e.g., a boost converter), the conversion ratio may be higher than 1, and the DC output voltage signal 112 can be higher than the DC input voltage signal 130. If the power conversion circuit 122 is a step-down converter (e.g., a buck converter), the conversion ratio may be lower than 1, and the DC output voltage signal 112 can be lower than the DC input voltage signal 130.

[0033] In addition to generating the DC output voltage signal 112, the power conversion circuit 122 may perform power factor correction. Power factor may be defined as the ratio of the real power, measured in watts (W), consumed by the load 106 divided by the total apparent power, measured in volt-amperes (VA), circulating between the AC power source 102 and the load 106. A high power factor (close to unity) may indicate that much of the power supplied by the AC power source 102 (apparent power) is delivered to and consumed by the load 106. Power factor correction may be performed to increase the power factor to unity.

[0034] The power factor (PF) can be determined by the phase relationship φ between the AC input voltage signal 108 and the AC input current signal 110 according to the following equation: PF=cos(φ) (Equation 1)

[0035] 2 illustrates example phase relationships φ between AC input voltage signal 108 and AC input current signal 110 and corresponding power improvement factor charts 202 and 204. In chart 202, AC input voltage signal 108 and AC input current signal 110 have zero phase difference, which may lead to a power factor of unity. In chart 204, AC input voltage signal 108 and AC input current signal 110 have a phase difference of φ, which may result in a power factor less than unity. As shown in FIG. 2, the amplitude of AC input current signal 110 (with a reduced power factor) in chart 204 is increased so that the same amount of power is consumed by load 106 as in chart 202, where the power factor is unity. Thus, increasing the power factor can improve the efficiency of power transfer by power supply system 104.

[0036] FIG. 3 is a schematic diagram of an example power supply system 104. Referring to FIG. 3, the power supply system 104 may include diodes 302a, 302b, 302c, and 302d coupled between the positive input 105a and the negative input 105b, forming a diode bridge 304. The diode bridge 304 may be part of the rectifier circuit 120 and may perform full-wave rectification to generate the pulsating DC input voltage signal 130 from the AC input voltage signal 108. The power conversion circuit 122 may also include an inductor 306, a switch 308, and a switch 310, and may be coupled to a controller 312 that controls the switches 308 and 310. The inductor 306 and the switches 308 and 310 may be coupled at a node 314, and the switches 308 and 310 may be coupled in series between the positive output 107a and the negative output 107b. The voltage at node 314 can switch between the positive and negative power supply rails within a switching cycle and can be a switching node. In Figure 3, negative output 107b can be coupled to ground. In another example, negative output 107b can be coupled to a low impedance voltage source to provide a reference voltage and to provide a return path for output DC current signal 114.

[0037] The inductor 306 and the switches 308 and 310 may be configured as a boost converter. The switch 308 may be a main switch for controlling the flow of the AC input current signal 110 through the inductor 306 to store magnetic energy in the inductor. The switch 310 may be a synchronous rectifier (SR). When enabled, the switch 310 allows the inductor 306 to discharge and supply current to the load 106. When disabled, the body diode of the switch 310 may block the flow of current from the load 106 back to the inductor 306. Each of the switches 308 and 310 may include a transistor such as a silicon field-effect transistor (FET) or a gallium nitride (GaN) high electron mobility transistor (HEMT). In the example shown in FIG. 3, each of the switches 308 and 310 may be an n-channel FET (NFET). Each switch may include a body diode and parasitic capacitance. In FIG. 3, diode 316 and capacitor 318 may represent the respective body diode and parasitic capacitance of switch 308, and diode 326 and capacitor 328 may represent the respective body diode and parasitic capacitance of switch 310.

[0038] The controller 312 generates a control signal 330 (V in FIG. 3) to enable / disable the main switch 308 in each switching cycle. M The controller 312 can also generate a control signal 332 (labeled V in FIG. 3) to enable / disable the SR switch 310 in each switching cycle. SR The controller 312 can generate a DC output voltage signal 112 (V out (t)) (see FIG. 1 ) and the DC input voltage signal 130 (V in,dc The controller 312 can receive a magnitude measurement 350 of the voltage V(t) and a reference DC output voltage 360.M and V SR The timing and duration of V is controlled based on measurements and criteria to achieve a target value for the DC output voltage signal 112. The controller 312 also controls the control signal V based on measurements of the AC input voltage signal 108. M and V SR The duration of the voltage V can be determined to reduce the phase difference between the AC input voltage signal 108 and the AC input current signal 110, reduce harmonic distortion in the AC input current signal 110, and improve the power factor. L may occur across the inductor 306 , which may affect the AC input current signal 110 and the DC output voltage signal 112 .

[0039] 4 includes waveform diagrams illustrating an example operation of the power conversion circuit 122 of FIG. 3. FIG. 4 includes graphs 402, 404, 406, and 408. Graph 402 illustrates the waveform of the control signal 330 (V M ) versus time, graph 404 illustrates the evolution of control signal 332 (V SR ), both of which are controlled by controller 312. Also, graph 406 illustrates the variation of inductor current through inductor 306 over time, and graph 408 illustrates the variation of voltage at node 314 over time.

[0040] A first switching cycle (sw1) begins at T0. Between T0 and T1 may be a first charging interval, during which the controller 312 charges V M In a first state, a VSR signal is provided to enable the main switch 308, and in a second state, a VSR signal is provided to disable the SR switch 310. The first state can be opposite to the second state. If the main switch and the SR switch 310 are NFETs, then V M Signal and V SR The signals may each be a gate voltage that exceeds the source voltage by at least the conduction threshold of the NFET, and V M and V SRThe signals may each be a gate voltage below the sum of the source voltage and the conduction threshold. With the main switch 308 enabled, the voltage at node 314 may be grounded, and the voltage V across the inductor 306 L is a DC input voltage signal 130 (V in,dc ) from the AC power source 102. The inductor 306 may be charged within a first charging interval between T0 and T1, and an increasing positive charging current may flow from the inductor 306 toward the switch 308, charging the inductor 306. The diode 326 may be reverse biased and prevent current from flowing from the load 106 / capacitor 118 back to the switch 308 and ground. The inductor 306 has an inductance L such that the AC input current signal 110 (I in (t)) L can be increased based on the following formula: TIFF2025529182000002.tif1547 (Formula 2)

[0041] In Equation 2, the DC input voltage signal 130 (V in,dc ) is positive, so the inductor current dI L / d t The slope of is also positive, and the inductor current increases between times T0 and T1. The positive inductor current may reach (or be close to) a peak at time T1. The duration between times T0 and T1 is t, which represents the duration of the turn-on interval of the primary switch 308 during which the primary switch 308 is enabled. M , the positive peak inductor current I p,peak However, V is calculated based on the following formula: in,dc and t M may be related to. TIFF2025529182000003.tif1552 (Formula 3)

[0042] Between T1 and T2, the controller 312 M Signal and V SRThe duration between T1 and T2 (t dt1 ) is the first resonant interval (t res1 During the first resonant interval, the inductor current from inductor 306 can charge capacitor 318 and discharge capacitor 328, and the voltage at node 314 is pulled to the positive power supply rail (e.g., V out ) until it is clamped to t dt1 t may be or include the peak resonant transition interval. Because the peak inductor current is used to charge capacitor 318 and discharge capacitor 328, t res1 can be relatively short.

[0043] Between T2 and T3 may be a discharge interval, during which the controller 312 sets V M V to set the signal to a second state and enable the SR switch 310. SR The signal is set in a first state. Inductor 306 dissipates the stored magnetic energy and provides a discharge current to load 106 and capacitor 118. Node 314 is connected to V out By this, the inductor voltage V L is V in,dc -V out The rate of change of the inductor current is as follows: TIFF2025529182000004.tif1561 (Formula 4)

[0044] In step-up conversion mode, V in,dc V out Because it is lower, V L becomes negative and the inductor 306 discharges, supplying current to the load 106 and / or capacitor 118. The inductor current decreases with increasing input current I in In conjunction with (t), negative dIL / d t Due to this, a positive peak current (I p,peak ) may decrease linearly from T1 to T2. The inductor current continues to fall between T2 and T3 and may become negative. The negative inductor current may flow toward the AC power source 102, removing charge from the capacitor 318 of the main switch 308 and adding charge to the capacitor 328 of the SR switch 310. The duration between T2 and T3 is t SR which represents the turn-on interval of the SR switch 310 during which the SR switch is enabled. The negative discharge current of the inductor when the SR switch 310 is disabled may be the SR turn-off current.

[0045] The SR turn-off current is determined by the positive peak charging current, the inductance of inductor 306, which sets the rate of decrease of the inductor current, and the SR switch 310t. SR In some examples, the controller 312 may determine the SR turn-off current required to remove the charge on the capacitor 318 of the main switch 308 based on the duration of the turn-on interval. SR may be determined and charge may be added to the capacitor 328 of the SR switch 310 during the following resonant interval. By this arrangement, the node 314 may fall to the negative power supply rail (e.g., ground) before the primary switch 308 is re-enabled. Because the voltage across the primary switch 308 is zero (or less than zero) when the state of the primary switch 308 is changed, zero voltage switching (ZVS) is achieved, which may reduce power loss during switching of the primary switch 308.

[0046] In some examples, the controller 312 may be configured to receive the DC input voltage signal 130 (V in,dc ) and DC output voltage signal 112 (V out ) based on comparing t SR The DC input voltage is then increased by a positive peak inductor current (I p,peak) can affect the amount of charge stored on capacitor 318 of main switch 308, which in turn affects the amount of SR turn-off current required to discharge capacitor 318 and bring the voltage at node 314 to ground during the second resonant interval. in,dc V out If the SR turn-off current is less than or equal to half of V, then zero SR turn-off current may be sufficient. in,dc V out , the controller 312 adjusts the turn-on interval t of the SR switch 310 so that the SR turn-off current is negative (flows towards the AC power source 102). SR The controller 312 can extend V in,dc , V out Based on the inductance of the inductor 306 and the total capacitance of the capacitors 318, 328, the minimum SR turn-off current and when to disable the SR switch 310 can be determined.

[0047] Between T3 and T5, the controller 312 controls V M Signal and V SR A second dead time interval (t ) may be achieved during which both the first and second signals may be set to a second state, disabling both switches 308 and 310. dt2 ) duration of the second resonant interval (t res2 During the second resonance interval, the negative inductor current can remove charge from the capacitor 318 of the main switch 308 and add charge to the capacitor 328 of the SR switch 310. This causes the voltage at node 314 to drop to ground due to resonance. Thus, t dt2 may be or include the valley resonance transition interval. The controller 312 controls the SR turn-off current and V in,dc And, V out and the resonant frequency based on the total capacitance of the capacitors 318 and 328 and the inductance of the inductor 306, tres2 The voltage at node 314 may fall to the negative power supply rail (e.g., ground in FIG. 3) at the end of the second resonant interval at time T4.

[0048] Between T4 and T5, the voltage at node 314 drops to ground and V in,dc This may be part of the second charging interval, since the positive inductor voltage V L may be induced across inductor 306. The inductor current may flow through diode 316 of main switch 308. Inductor 306 may be charged between T4 and T5, and the polarity of the inductor current may change during the second charging interval or may depend on the initial conditions at T4.

[0049] At T5, the controller 312 M The signal may be set to a first state to enable the primary switch 308 and begin a new switching cycle sw2 that ends at time T6. At T5, the voltage across the primary switch 308 is zero when the primary switch 308 is enabled, thereby achieving zero voltage switching (ZVS), which reduces the power dissipation caused by enabling / disabling the primary switch 308 and can further improve the efficiency of the power conversion circuit 122.

[0050] Average inductor voltage V in steady state L is equal to zero, the DC input voltage signal 130 (V in,dc ) and DC output voltage signal 112 (V out ) is the turn-on interval (T M ) and the turn-on interval (t SR ) can be related to the following: V in,dc ×t M +(V in,dc -V out )×t SR =0 (Formula 5)

[0051] From Equation 5, the DC output voltage signal 123(V out) is calculated based on the DC input voltage signal 130 (V in,dc ) may be related to TIFF2025529182000005.tif1751 (Formula 6)

[0052] Referring again to FIG. 3, the controller 312 receives a measurement 350 of the DC input voltage signal 130, a measurement 340 of the DC output voltage signal 112, and a reference DC output voltage signal 360 at the beginning of a switching cycle and, based on those measurements and Equation 6, determines the t M and t SR For example, the controller 312 may include a proportional-integral (PI) controller that integrates the difference between the DC output voltage signal 112 and the reference DC output voltage signal 360 and sets the t for that switching cycle based on a comparison of the integrated difference to the DC input voltage signal 130, as in Equation 6. M and t SR Determine.

[0053] The controller 312 also calculates the t M and / or t SR can be set for power factor correction operation. In some examples, the controller 312 M and t SRcan be set to operate the power conversion circuit 122 in critical conduction mode (CRM), in which the controller 312 enables the primary switch 308 when the inductor current is at (or close to) zero at the beginning of each switching period, as shown in FIG. 4 . Critical conduction mode can provide various advantages. For example, because the primary switch 308 is enabled and the SR switch 310 is disabled when the inductor current is zero, zero-voltage switching (ZVS) can be achieved, which reduces power dissipation caused by enabling / disabling the switches and improves the efficiency of the power conversion circuit 122. Also, because no current flows through the SR switch 310 when it is disabled, the diode 326 of the SR switch 310 does not require a fast recovery time, which allows the SR switch 310 to be implemented by a relatively low-bandwidth device and / or allows the power conversion circuit 122 to operate at a higher switching frequency.

[0054] 5 includes a chart 502 illustrating CRM operation by the controller 312 over a half-cycle of the AC input voltage signal 108. Chart 502 includes graphs 504, 506, 508, 510, 512, and 514. Graph 504 represents the reference DC output voltage 160. Graph 506 represents the positive half-cycle of the DC input voltage signal 130, or the AC input voltage signal 108. Graph 508 represents the inductor current through the inductor 306, and graph 510 represents the positive half-cycle of the AC input current signal 110 (I in ) of the main switch 308. M Graph 514 represents the V SR Represents the transition of a signal.

[0055] 5, in each switching cycle, the controller 312 generates a target positive peak current I p,peak Based on the main switch turn-on interval (t M), which can set the average input current over a switching cycle. To reduce the phase difference between the AC input current signal 110 and the AC input voltage signal 108, the controller 312 determines the duration of t such that the average input current for each switching cycle has a fixed relationship with the AC input voltage signal for the respective switching cycle. M Referring again to Equation 3, because the DC input voltage signal 130 (which reflects the AC input voltage signal 108) is proportional to the positive peak current in a switching cycle, the controller 312 can determine t based on the target current delivered to the load 106 and capacitor 118. M The controller 312 can also adjust the SR switch turn-on interval (t SR ) is adjusted to provide time for the inductor current to decay from its peak positive value to zero, and to adjust the DC output voltage signal 112 (V out ) and DC input voltage signal 130 (V in,dc ) can be adjusted. Thus, the frequency of the switching cycles can be varied. The switching cycle period can be maximized when the DC input voltage signal 130 approaches the reference DC output voltage 160, and the controller 312 adjusts the step-up ratio between t SR t can be increased to decrease the step-up ratio. Also, the switching frequency can be maximized when the DC input voltage signal 130 approaches zero, and the controller 312 can SR For example, in FIG. 5, t M (3) and t SR (3) and the third cycle period including t M (4) and t SR The fourth cycle period, including (4), can have the maximum duration within the half cycle, t M (0) and t SR The 0th cycle period, including (0), and t M (7) and tSR The seventh cycle period, including (7), may have the smallest duration within the half cycle.

[0056] FIG. 6 is a schematic diagram of another example of a power supply system 104, in which the operation of the rectifier circuit 120 and the power conversion circuit 122 is performed using a set of switches and their body diodes. Referring to FIG. 6, the power supply system 104 may include a power conversion circuit 122 and a controller 612 coupled to the power conversion circuit 122, where the power conversion circuit 122 includes an inductor current 602 and switches 602, 604, 606, and 608. The switches 602, 604, and the inductor 306 are coupled at a node 614, and the switches 602 and 604 are coupled in series between the positive output 107a and the negative output 107b. The node 614 may be a switching node, switching between the positive and negative power supply rails. Additionally, the switches 606 and 608 are coupled at a node 620, and the switches 606 and 608 are also coupled in series between the positive output 107a and the negative output 107b. Inductor 306 is coupled between positive input 105a and node 614, and node 620 between switches 606 and 608 is coupled to negative input 105b.

[0057] The switches 602, 604, 606, and 608 may be NFETs. The switches 602 and 604 are connected to the AC input voltage signal 108 (V in), and switches 606 and 608 may switch every half cycle of the AC input voltage signal. Each of switches 602 and 604 may have a higher bandwidth than the respective switches 606 and 608. In some examples, each of switches 602 and 604 may include a transistor such as an NFET or a GaN HEMT, and each of switches 606 and 608 may include a FET. Switch 602 may have a body diode 616 and a parasitic capacitor 618, and switch 604 may have a body diode 626 and a parasitic capacitor 628. Switch 606 may have a body diode 627, and switch 608 may have a body diode 629. For simplicity, the parasitic capacitances of switches 606 and 608 have been omitted.

[0058] In some examples, switches 602, 604, 606, and 608 and inductor 306 can be configured as a totem-pole boost rectifier. Controller 612 can generate control signals 630 (labeled VG1), 632 (labeled VG2), and 636 (labeled VG3) to enable / disable switches 602, 604, 606, and 608 to perform rectification, power factor correction, and step-up conversion operations, respectively.

[0059] The negative input 105b receives a lower voltage than the positive input 105a, V inDuring the positive half-cycle of the , switch 606 is enabled to couple the negative power supply rail (and negative input 107b) to the negative input 105b to receive the lower input voltage, while inductor 306 (when switch 604 is enabled) can connect the positive power supply rail (and positive output 107a) to the positive input 105a. Thus, positive output 107a can have a positive polarity, and negative output 107b can have a negative polarity. Also, switch 608 is disabled, causing inductor current to flow through capacitor 118 and load 106 and back to AC power source 102 through switch 606. Controller 612 can operate switch 602 as a main switch and switch 604 as an SR switch. Controller 612 controls the control signal V M 4. The same series of control signals VG1 and V SR The same series of control signals VG2 can be generated for V in In each switching cycle of the positive half cycle of M ), switch 602 is enabled and switch 604 is disabled. The charging interval also includes a first charging interval during which the inductor is charged. The charging interval is followed by a first dead-time interval (t dt1 ) followed by the first dead time interval, t res1 and a first resonance interval t res1 , the voltage at node 614 resonates with the positive power supply rail (e.g., V out ) after the first dead time interval. SR ) and the discharge interval (t SR ), switch 602 is disabled, switch 604 is enabled, and the inductor discharges. After the discharge interval, a second resonant interval t occurs during which the voltage at node 614 resonantly transitions to the negative power supply rail (e.g., ground). res2 and a second dead time interval (t dt2) follows. After a second dead-time interval, a new switching cycle may begin. ZVS may be achieved if the voltage at node 614 completes a transition to ground by the end of the second resonant interval, such that the voltage across switch 602 is zero (or below zero) when switch 602 changes from a disabled state to an enabled state to begin a new switching cycle.

[0060] The negative input 105b receives a higher voltage than the positive input 105a, V in During the negative half-cycle of V, switch 608 couples the positive power supply rail (and positive input 107a) to the negative input 105b to allow it to receive a higher input voltage, while the negative power supply rail (and negative output 107b) is coupled to the positive input 105a to maintain the same polarity between the positive and negative power supply rails over the positive and negative half-cycles. Also, switch 606 is disabled, allowing the inductor current to flow through capacitor 118 and load 106 and back to AC power source 102 through switch 602. Controller 612 can operate switch 604 as a main switch and switch 602 as an SR switch. Controller 612 controls the control signal V M 4. The same series of control signals VG2 and V SR The same series of control signals VG1 and VG2 can be generated. in In each switching cycle of the negative half cycle of M ), switch 602 is enabled, switch 604 is disabled, and the inductor is charged. After the charging interval, a first dead time interval (t dt1 ) followed by the first dead time interval (t dt1 ), both switches are disabled and the voltage at node 614 resonantly transitions to the negative power supply rail (e.g., ground). A discharge interval (t SR ) and the discharge interval (t SR), switch 602 is disabled and switch 604 is enabled, discharging the inductor. After the discharge interval, a second dead time interval (t dt2 ) followed by a second dead time interval (t dt2 ), the voltage at node 614 resonates with the positive power supply rail (e.g., V out ), followed by charging of the inductor, after a second dead-time interval, a new switching cycle can begin. The voltage at node 614 must reach V by the end of the second interval so that the voltage across switch 602 is zero (or below zero) when switch 602 changes from a disabled to an enabled state to begin a new switching cycle. out If the transition to , ZVS can be achieved.

[0061] The controller 612 receives the DC output voltage signal 112 (V out ) and the magnitude measurement 650 of the AC input voltage signal 108 (V in ) and the reference DC output voltage 360. The controller 612 can determine whether the AC input voltage signal 108 is in a positive half-cycle or a negative half-cycle based on the measurement 660. The controller 612 also controls the t M and t of switch 604 SR can be determined based on measurements 650 and the reference DC output voltage 360 ​​in both half cycles.

[0062] 3 and 6 in CRM, a controller (such as controllers 312 and 612) may measure the inductor current through inductor 306 as the inductor current drops during the SR switch turn-on interval and disable the SR switch when the inductor current crosses zero or reaches a minimum SR turn-off current sufficient for the voltage across the primary switch to complete a transition to one of the power supply rails in the second resonant period to achieve zero voltage switching (ZVS). The controller may, as described above, shorten the SR switch turn-on interval (t SR The controller may also extend the second dead time interval (t dt2 Specifically, the controller may detect the inductor current within a switching cycle and determine the duration of the turn-on interval (t SR ) and adjust the timing of the control signals for the main switch and the SR switch within the same switching cycle.

[0063] FIG. 7 illustrates an example operation of the power conversion circuit 122 during two switching cycles and V SR Graph 702 includes graphs 702, 704, 706, and 708, which illustrate the effect of delays in adjusting the control signal. M The transition of the control signal is illustrated in graph 704, where V SR Graph 706 illustrates the evolution of the inductor current over time, and graph 708 illustrates the evolution of the voltage at node 314 / 614 over time. The time representation is based on FIG.

[0064] 7, toward the end of the first switching cycle sw1, at time T3, the inductor current crosses zero. The controller can disable the SR switch at time T3 to provide an SR turn-off current sufficient to complete the transition of node 314 / 614 to one of the power supply rails. When the SR switch is disabled at time T3, the negative inductor current becomes I n0 However, the delay T D The SR switch turns off at time T3 ’ As a result, the inductor current becomes more negative after time T3, and I n1 reaches its peak.

[0065] Various sources of delay D This can contribute to and increase the inductor current. For example, circuits involved in inductor current measurement, such as current sensors and ADCs, have limited bandwidth and may introduce delays in providing current measurement data to the controller. The controller may also introduce delays in calculating the amount of target SR turn-off current for a switching cycle based on the AC input voltage and DC output voltage, and in determining whether to disable the SR switch by comparing the target SR turn-off current with the inductor current indicated by the current measurement data. The controller may also include circuits, such as pulse-width modulation (PWM) circuits and drive circuits, to generate and send control signals to the main switch and the SR switch. These circuits may also introduce additional delays in generating the control signals.

[0066] The additional negative peak inductor current can increase the current ripple, which can cause additional power loss and increase distortion in the AC input current. Specifically, the average current in each switching cycle is the sum of the negative peak current and the positive peak current I p,peakIf the negative peak current becomes more negative compared to the target negative peak current of a switching cycle, the average AC input current over the switching cycle may not track the AC input current, which may lead to substantial distortion.

[0067] To reduce distortion, the controller may increase the positive peak current of that switching cycle (e.g., increasing the turn-on interval t of the primary switch to coincide with the negative peak current). M (by increasing the peak current). Such an arrangement can preserve the shape of the average inductor current over a switching cycle, and the average inductor current can have a constant relationship to the AC input voltage. However, increasing the positive peak current in each switching cycle can result in additional power being drawn from the AC power source, much of which is lost to the negative inductor current that does not flow to the load. This can increase power losses in the power supply system 104 and reduce the efficiency of power transfer from the AC power source 102 to the load 106.

[0068] 8 illustrates graphs 802 and 804 of example variations in inductor current over time for the power supply system 104. Graph 802 shows the delay T D Graph 804 illustrates the inductor current transition without a delay T of approximately 100 nanoseconds (ns) within the same half cycle. D 8 illustrates the evolution of the inductor current with the delay T. Referring to FIG. 8, within intervals 812 and 814 near zero AC input voltage, the inductor current has a larger current ripple in graph 804 than in graph 802. For example, at the beginning and end of a half cycle, without the delay the maximum current ripple is 4 amperes (A), but with the delay the maximum current ripple is 13 A. In the operation of graph 802, the delay T D However, as noted above, the controller can extend the turn-on interval of the SR switch to provide additional negative inductor current to discharge the primary switch into the second resonant interval.D is also the turn-on interval of the SR switch (t SR ) may also be extended to provide additional negative inductor current. The increased current ripple in intervals 812 and 814 may substantially increase power losses in power supply system 104 and reduce the efficiency of power transfer from AC power source 102 to load 106.

[0069] Also, referring again to FIG. 7, after determining that the SR switch is to be disabled at T3, the controller initiates a second dead time interval (t dt2 ) to determine that the primary switch is enabled to start the next switching cycle (sw2) at time T4 to achieve ZVS for the primary switch while decreasing the interval during which the body diode of the primary switch conducts the inductor current as in FIG. 4. The controller may determine the duration of the SR turn-off current (the inductor current when the SR switch is disabled) and the input voltage (V in FIG. 6) as described above. in or V in Figure 3 in , dc) and the output voltage V out , based on the parasitic capacitance of the main switch and the resonant frequency of the inductor 306 where the SR switch is at the switching node, the second resonant interval t res2 can be determined, and the second dead time interval t dt2 The duration of the second resonant interval t between different switching cycles res2 Dynamically change to match or adapt to the

[0070] FIG. 9 shows the second resonance interval t versus time within a half cycle of the AC input voltage. res29 illustrates a graph 900 of an example variation in the duration of the SR turn-off current. In the operation depicted in FIG. 9, a minimum amount of SR turn-off current is provided in each switching cycle to allow the switching node (e.g., node 314 / 614) to transition to one of the power supply rails. Also, a minimum second resonant interval is provided in each switching cycle for the switching node to complete the transition, and the duration of the second resonant interval varies according to the SR turn-off current. The second dead-time interval duration (t dt2 ) is also adjusted to coincide with the second resonance interval in each switching cycle. In the example of FIG. res2 may be minimum at the beginning and end of the half cycle. Between 0 and approximately 2 milliseconds (ms), the controller SR ) can be set to have zero SR turn-off current, and t res2 can increase with the AC input voltage, peaking at approximately 0.28 ms. Between 2 ms and 4.1 ms, the controller can extend the turn-on interval of the SR switch to increase the negative SR turn-off current, t res2 The turn-on interval of the SR switch increases with the AC input voltage, reaching a maximum of 4.1 ms. Between 4.1 ms and 6.5 ms, the turn-on interval of the SR switch decreases with the AC input voltage, thereby reducing the negative SR turn-off current and t res2 Between 6.5ms and 8.2ms (end of half cycle), the controller increases the turn-on interval t SR can be set so that there is zero SR turn-off current, t res2 may decrease with AC input voltage.

[0071] The controller initiates a second dead-time interval t dt2The operation illustrated in graph 900, which adjusts the duration of the second resonant interval based on the minimum SR turn-off current to match the shifting second resonant interval, may use a lot of power for sensing, processing, and calculation, and may be prone to errors and reduce the efficiency of the power converter. Specifically, to adjust the duration of the second resonant interval in each switching cycle, the controller may receive measurements of the SR turn-off current from a current sensor in each switching cycle, determine the resonant time based on the SR turn-off current, and perform calculations to determine the dead time for adapting the resonant time. However, this may require the current sensor to have high bandwidth and high accuracy, and such a current sensor may consume a lot of power. Furthermore, calculating the duration of the second dead time interval may require extensive calculations, and performing such calculations in each switching cycle may result in significant power consumption by the controller.

[0072] Also, adjusting the duration of the second dead-time interval based on the SR turn-off current may introduce errors. Specifically, the controller adjusts the duration t of the on-time of the SR switch based on the SR turn-off current. SR and the duration of the second dead time interval (and the second resonance interval) t dt2 may be determined based on measuring the SR turn-off current, which may be represented by the inductor current when the SR switch is disabled. However, as noted above, the circuits involved in inductor current detection, such as the current sensor and ADC, have limited bandwidth and may cause delays in providing the current measurement data to the controller. Due to the delay, t dt2 The current measurement data used by the controller to determine t may not reflect the actual inductor current when the SR switch is disabled, which can result in t SR and t dt2 Errors may be introduced in the determination of t dt2If t is too short, the controller may enable the main switch before transitioning the voltage at node 314 / 614 to one of the power supply rails, which may lead to non-ZVS and additional power loss in switching the main switch. dt2 If the time t1 is too long, the controller may enable the primary switch long after the voltage at node 314 / 614 transitions to one of the power rails. This may cause inductor current to flow through the body diode of the primary switch (e.g., diode 316 in FIG. 3, body diode 616 in FIG. 6 during the positive half-cycle, body diode 626 in FIG. 6 during the negative half-cycle, etc.), such as between T4 and T5 in FIG. 4. Because the body diode has a higher resistance than the enabled primary switch, it may result in greater power loss, which reduces the efficiency of the power supply system 104.

[0073] FIG. 10 is a schematic diagram of a power conversion circuit 122 that can address at least some of the above problems. Referring to FIG. 10, the power conversion circuit 122 may include an inductor 306, a switch 1008, a switch 1010, and a controller 1012 coupled to the power conversion circuit 122. The controller 1012 may control the switches 1008 and 1010. The controller 1012 may be part of a microcontroller (MCU), an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). The inductor 306 and the switches 1008 and 1010 may be coupled at a node 1014, and the switches 1008 and 1010 may be coupled in series between the positive output 107a and the negative output 107b. In some examples, the switches 1008 and 1010 can be part of the boost converter of FIG. 3 , where the switches 1008 and 1010 correspond to the main switch 308 and the SR switch 310, respectively, of FIG. 3 , and the inductor 306 is coupled to the positive input 105 a through the rectifier circuit 120 (e.g., the diode bridge 304). In some examples, the switches 1008 and 1010 can also be part of a totem-pole boost converter, where the switches 602 and 604, respectively, of FIG. 6 . The inductor 306 can be directly coupled to the positive input 105 a. During a positive half-cycle of the AC input voltage signal 108, the switch 1008 can operate as the main switch, and the switch 1010 can operate as the SR switch. During a negative half-cycle of the AC input voltage signal 108, the switch 1008 can operate as the SR switch, and the switch 1010 can operate as the main switch. In FIG. 10, the body diodes and parasitic capacitances of switches 1008 and 1010 are omitted for simplicity.

[0074] The controller 1012 may generate a control signal 1030 (labeled as VG1 in FIG. 10 ) for enabling / disabling the switch 1008 and a control signal 1032 (labeled as VG2 in FIG. 10 ) for enabling / disabling the switch 1010 in each switching cycle. The controller 1012 may provide the control signal 1030 at a first control output coupled to a first power converter control terminal (e.g., a control terminal of the switch 1008). The controller 1012 may provide the control signal 1032 at a second control output coupled to a second power converter control terminal (e.g., a control terminal of the switch 1010). As in FIG. 4 , when the controller 1012 operates the switch 1008 as a main switch and the switch 1010 as an SR switch, the controller 1012 may generate a first dead-time interval (t t ) between the end of the turn-on interval of the switch 1008 and the beginning of the turn-on interval of the switch 1010 within a switching cycle. dt1 ) and a second dead time interval (t ) between the end of the turn-on interval of switch 1010 and the beginning of the turn-on interval of switch 1008 of two adjacent switching cycles. dt2 Additionally, when the controller 1012 operates the switch 1010 as a main switch and the switch 1008 as an SR switch, the controller 1012 may also include a first dead time interval (t ) between the end of the turn-on interval of the switch 1010 and the beginning of the turn-on interval of the switch 1008 within a switching cycle. dt1 ) and a second dead time interval (t ) between the end of the turn-on interval of switch 1008 and the beginning of the turn-on interval of switch 1010 of two adjacent switching cycles. dt2 ) may be included.

[0075] In some examples, to simplify the calculations involved in determining the timing of the VG1 and VG2 control signals, the controller 1012 may time the duration of the second dead-time interval by adjusting the AC input voltage signal 108 (V in) to a constant value over multiple switching cycles within a cycle of t dt1 ) and the turn-on interval of the main switch (t M ) and the turn-on interval (t SR ) can be determined. In some examples, the controller 1012 can set the duration of the second dead-time interval based on a programmed value. Because the controller 1012 does not need to calculate the duration of the second dead-time interval for each switching cycle, the calculations involved in determining the timing of the control signals for VG1 and VG2 can be significantly reduced. The controller 1012 can determine the turn-on interval (t ) of the SR switch to adjust the SR turn-off current such that the switching node 1014 can complete its transition to a target voltage (e.g., one of the positive / negative power supply rails) within the second dead-time interval so that the activation of the main switch can be under ZVS conditions. SR ) can be adjusted. This mechanism also allows the second resonance interval t res2 be maintained at a constant value across different switching cycles within a cycle of the AC input voltage signal. When switch 1010 operates as an SR switch, controller 1012 can adjust the turn-on interval of switch 1010 before switch 1008 (operating as the primary switch) is enabled to allow switching node 1014 to complete a transition to the negative power supply rail at the end of the second dead-time interval. When switch 1008 operates as an SR switch, controller 1012 can adjust the turn-on interval of switch 1008 before switch 1010 (operating as the primary switch) is enabled to allow switching node 1014 to complete a transition to the positive power supply rail at the end of the second dead-time interval.

[0076] The controller 1012 receives a DC output voltage signal 112 (V out(t)) and the AC input voltage signal 108 (V in (t)) and a reference DC output voltage 1060. In some examples, the controller 1012 may also receive programming data 1062 used to determine the turn-on interval of the switch 1008, the turn-on interval of the switch 1010, the first dead time interval, and / or the second dead time interval. The programming data 1062 may include a resonant time constant of a resonant circuit including the inductor 306 and a capacitor representing, for example, the total parasitic capacitance of the switches 1008 and 1010 at the switching node 1014 coupled to the inductor 306. TIFF2025529182000006.tif1130, where L may represent the inductance of the inductor 306 and C may represent the capacitance. In some examples, the programming data 1062 may include a value representing the resonant impedance of the formed resonant circuit. The controller 1012 may include a value representing the charge interval / turn-on interval (t M ) and the discharge interval / turn-on interval (t SR ) to obtain the target DC output voltage signal 112. The controller 1012 can also determine the duration of the control signals VG1 and VG2 based on measurements of the AC input voltage signal 108 to maintain a constant relationship between the AC input current signal 110 and the AC input voltage signal 108, as described above.

[0077] The power conversion circuit 122 may also include a transition measurement circuit 1070 to determine the status of a transition of the switching node 1014 when the primary switch (one of the switches 1008 or 1010) changes state at the beginning of a switching cycle. The transition measurement circuit 1070 may be coupled to the switching node 1014 and may receive at least one of a control signal 1030 (VG1) or a control signal 1032 (VG2) from the controller 1012. Based on the voltage of the switching node 1014, the transition measurement circuit 1070 may determine whether the switching node 1014 transitions to a target voltage (e.g., one of the positive or negative power supply rails) at the beginning of a switching cycle to achieve zero-voltage switching (ZVS) of the primary switch of the power converter. Based on one of the control signals 1030 or 1032, the transition measurement circuit 1070 may also generate an indication signal 1072 indicating whether the switching node 1014 completes the transition before the controller 1012 enables the primary switch. In some examples, the transition measurement circuit 1070 may include a comparator for comparing the voltage of the switching node 1014 with a threshold value based on a target voltage, and digital logic circuitry for generating an indication signal 1072 based on the output of the comparator and the timing of a control signal from the controller 1012 targeted at the main switch (one of VG1 or VG2).

[0078] If switches 1008 and 1010 are part of a boost converter in which switch 1008 is a primary switch and switch 1010 is an SR switch, then transition measurement circuit 1070 can generate an indication signal 1072 based on whether switching node 1014 transitions to the negative power supply rail before primary switch 1008 is enabled by control signal VG1. Also, if switches 1008 and 1010 are part of a totem-pole boost converter, transition measurement circuit 1070 can also receive measurement 1050 of AC input voltage signal 108. If power supply system 104 is in a positive half-cycle of the AC input voltage with switch 1008 operating as a primary switch and switch 1010 operating as an SR switch, then transition measurement circuit 1070 can generate an indication signal 1072 based on whether switching node 1014 transitions to the negative power supply rail before primary switch 1008 is enabled by control signal VG1. When the power supply system 104 is in a negative half-cycle of the AC input voltage with the switch 1008 operating as an SR switch and the switch 1010 operating as a main switch, the transition measurement circuit 1070 can generate an indication signal 1072 based on whether the switching node 1014 transitions to the positive power rail before the main switch 1010 is enabled by the control signal VG2.

[0079] The controller 1012 can adjust the switching cycle based on the indication signal 1072. If the indication signal 1072 indicates that the switching node 1014 has completed a transition before the main switch 1008 changes from a disabled state to an enabled state, such an indication indicates that the switching node has completed a transition before the second dead-time interval t dt2 This may reflect that the SR turn-off current is more than sufficient to complete the transition within t. Thus, the controller 1012 may reduce the duration of the switching cycle period, which may result in t SRThis may also result in a decrease in the duration of the second dead-time interval t, generating less SR turn-off current and making the SR turn-off current less negative when the SR switch is disabled. However, if the indication signal 1072 indicates that the switching node 1014 did not complete the transition before the controller 1012 enabled the primary switch 1008, such an indication may be an indication that the switching node did not complete the transition before the second dead-time interval t dt2 This may reflect insufficient SR turn-off current to complete the transition within t SR This may also lead to an increase in the duration of t, which may increase the SR turn-off current, which may become more negative when the SR switch is disabled. SR and the turn-off current of SR can be adjusted so that the switching node 1014 is dt2 The transition to the target voltage (e.g., ground) can be completed within t dt2 and t res2 This includes the case where is fixed over a switching cycle.

[0080] In the example power supply system 104 described herein, the controller 1012 determines the first dead time interval (t dt1 ) and charging interval (t M ) and the discharge interval (t SR ) and the timing of the control signals 1030 and 1032 are determined as the second dead time interval (t dt2 ) and can be determined based on the transcendental equation, t for a switching cycle. dt1 , t dt2 , t M , and t SRThe angle representing the duration of t is variable. In some cases, such equations can be solved using iterative numerical methods, but these can be computationally intensive and unsuitable for real-time implementation. Also, the phase angle determined by iterative numerical methods may or may not represent an exact analytical solution to the equation, thereby determining the t to provide switching under ZVS conditions. dt1 , t dt2 , t M , and t SR This may reduce the accuracy of determining the duration of one of the variables, t dt2 By presetting a particular value of , such equations can be solved with exact analytical methods, which allows t dt1 , t dt2 , t M , and t SR This reduces the complexity of calculating the duration of t, and increases the speed of the calculation. dt1 , t dt2 , t M , and t SR is calculated as part of the exact analytical solution, the calculated value is dt1 , t dt2 , t M , and t SR In some examples, the controller 1012 can set the angle of the second dead-time interval, which may represent the valley resonance transition interval, to 90°, allowing for analytical solution formulas and the use of mathematical identities to simplify calculations. The interval values ​​are calculated and used to generate the control signals 1030 and 1032.

[0081] The controller 1012 does not rely on high bandwidth current sensors, thereby reducing circuit complexity and cost. Accurate dead time control reduces hard switching and improves switching transistor performance. Also, due to reduced computational complexity, t dt1 , t dt2 , t M , and t SR can be updated quickly, so t dt1, t dt2 , t M , and t SR This can reduce the delay in adjusting the input voltage, which can reduce current ripple and distortion (eg, total harmonic distortion (THD)).

[0082] FIG. 11 is a block diagram of exemplary internal components of the controller 1012. As shown in FIG. 11, the controller 1012 may include a reference generation circuit 1102, an interval calculation circuit 1116, and a pulse-width modulation (PWM) generation circuit 1114. The controller 1012 further includes a control logic circuit 1118 for controlling the operation of these components and a memory 1120 for supporting the operation. As described above, the controller 1012 may be part of a programmable logic circuit such as a microcontroller (MCU), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The memory 1220 may include volatile and / or nonvolatile memory such as static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, erasable programmable read-only memory (EPROM), etc. If the controller 1012 is an MCU, each of the circuits 1102-1108 may be implemented by instructions executable by the MCU, and the memory 1120 may store instructions executable by the MCU. If the controller 1012 is an ASIC or FPGA, each of the circuits 1102-1108 can be implemented by dedicated circuit elements including logic circuits. The memory 1220 can also provide storage for input and output data for each circuit.

[0083] The reference generating circuit 1102 generates a reference current I ref The reference current may be adjusted to generate a digital value 1122 representing the magnitude of the AC input voltage signal 110 (I in (t)) and the AC input voltage signal 108 (V in) The reference current information may also be provided by an outer control loop for controlling the power supply system 104 to provide a DC output voltage that matches the reference DC output voltage.

[0084] The reference generation circuit 1102 may generate I ref In some examples, the reference generation circuit 1102 may generate a peak value or amplitude I of the reference current. ref,amp The reference generation circuit 1102 can receive a digital value 1123 from the output control loop that represents the normalized V. The reference generation circuit 1102 also receives the measurement 1050, from which the normalized V in (e.g., with an amplitude of 1 V) and I ref,amp The normalized V in In some examples, the reference generation circuit 1102 may also generate a digital value 1122 by multiplying it by a DC output voltage signal 112 (V out ) and reference DC output voltage 1060 (V out,ref ) can receive a measurement value 1040 representing the DC output voltage signal 112 and the reference DC output voltage signal 1060. The reference generation circuit 1102 includes a subtraction circuit for generating a difference between the DC output voltage signal 112 and the reference DC output voltage signal 1060, and an internal I ref,amp The reference generation circuit 1102 can then include a proportional-integral (PI) controller to generate I ref,amp , the normalized V from the measurement 1050 in By multiplying with I ref The digital value 1122 can be generated.

[0085] The interval calculation circuit 1116 generates a digital value 1136 (t M ) and the digital value 1138 (t SR ) and a digital value 1140 (t dt1 ) and a digital value 1142 (t dt2) can be generated. The interval calculation circuit 1116 can receive the digital value 1122, the measurement value 1050, the measurement value 1040, the display signal 1072, and the programming data 1062, and can generate digital values ​​1136-1142 based on the digital value 1122, the measurement value 1050, the measurement value 1040, the display signal 1072, and the programming data 1062. The interval calculation circuit 1116 provides the digital values ​​1136-1142 to the control logic circuit 1118. The control logic circuit 1118 can control the PWM generation circuit 1114 to generate the control signal VG1 or VG2 at the PWM output based on the digital values ​​1136-1142.

[0086] The PWM generator circuit 1114 can generate a digital value (e.g., a logic 1 for a first state and a logic 0 for a second state) that represents the control signal VG1 or VG2. The PWM generator circuit 1114 can then transmit the digital value to a driver circuit (not shown in FIG. 11 ) to convert the digital value into an analog voltage signal to drive the switches 1008 and 1010. The control logic circuit 1118 controls the PWM generator circuit 1114 to SR , t M , t dt1 , and t dt2 A series of control signals VG1 and VG2 can be generated having timing defined by:

[0087] In some examples, the control logic 1118 may include a state machine for controlling the PWM generator 1114 to generate the control signals VG1 and VG2 and to control read and write operations to the memory 1120. The state machine may be configured to set the count values ​​based on the counters to t SR , t M , t dt1 , and t dt2The control logic circuit 1118 can operate by comparing the measured value 1050 representing the AC input voltage signal 108 with the digital values ​​1136, 1138, 1140, and 1142 representing the AC input voltage signal 108. The control logic circuit 1118 can also receive a measurement 1050 representing the AC input voltage signal 108, determine whether the system is operating on a positive half-cycle or a negative half-cycle of the AC input voltage, and generate the control signals VG1 and VG2 accordingly.

[0088] FIG. 12A includes waveform diagrams illustrating current and voltage in the power supply system of FIG. 10. Time domain graph 1202 illustrates current flow in inductor 306 through a charge / discharge cycle. Time domain graph 1204 illustrates voltage across switch 1008 through a charge / discharge cycle. Time domain graphs 1202 and 1204 are similar to graphs 406 and 408 shown in FIG. 4. During interval t1, switch 1008 is closed, switch 1010 is open, and current flowing through inductor 306 increases to charge inductor 306. During interval t2, switches 1008 and 1010 are open. During interval t3, switch 1010 is closed and switch 1008 is open while inductor 306 is discharging. During interval t4, switches 1008 and 1010 are open. Interval t1 is the charging interval t M where interval t2 is the first dead time interval t dt1 and the interval t3 is the discharge interval t SR and interval t4 is the second dead time interval t M can be expressed as:

[0089] 12B is an example state plane diagram illustrating the relationship between voltage and current in time domain graphs 1202 and 1204. The state plane diagram maps the time domain graphs 1202 and 1204 to a graph that illustrates the dependence of the time domain waveforms. L (v) is mapped to the state dependence, i L (v) to j L (m). Normalization is expressed as follows: TIFF2025529182000008.tif11997In formula, V OUT is the output voltage of the power supply system 104. V BASE is the base voltage selected for normalization. L is the inductance of the inductor 306. C is the capacity at the switch node 1014 . R0 is the resonant impedance of the resonant circuit including L and C. I BASE is the base current chosen for normalization. V IN is the output voltage of the power supply system 104. i L is the current flowing in inductor 306. ω0 is the angular resonant frequency of the resonant circuit including L and C. M is the normalized (output voltage V OUT is the input voltage (normalized to j L is the normalized current. θ is the angle corresponding to the time interval between the time domain graphs 1202 and 1204 . fsw is, for example, the switching frequency determined in the interval calculation circuit 1116. F is the normalized current, F=fsw / f0, The file is TIFF2025529182000009.tif1631.

[0090] The following system equations can be derived from the normalized state plane diagram of FIG. 12B: TIFF2025529182000010.tif111150

[0091] Equations 15 to 22 are L1 , J L2 , J L3 , J L4 , θ1, θ2, θ3, θ4, M, F, and J L12A, θ1 is the angle representing interval t1 (charging interval) in FIG. 12A, θ2 is the angle representing interval t2 (first dead time interval) in FIG. 12A, θ3 is the angle representing interval t3 (discharging interval) in FIG. 12A, and θ4 is the angle representing interval t4 (second dead time interval, or valley resonance transition interval) and switching cycle period in FIG. 12A. While the simultaneous equations can have their own solution, the equations are transcendental. In some examples, the solution to the equations (J L1 , J L2 , J L3 , J L4 , θ1, θ2, θ3, θ4, M, F, and J L While the values ​​of θ and θ (including θ and θ) can be found using iterative numerical methods, such methods are computationally intensive and may not be suitable for real-time implementation. Also, iterative numerical methods may or may not provide an accurate analytical solution, reducing accuracy in determining the interval to achieve ZVS.

[0092] In some examples, the controller 1012 can determine the solutions to Equations 15-22 in real time based on a series of equations derived from Equations 15-22 with θ4 set to a specific value, so that θ4 is not an unknown variable to be solved for. In some examples, the controller 1012 can set θ4 to 90° (or π / 2). Setting θ4 to 90° reduces the resonant period The valley resonance transition interval (second dead time interval t4 or t dt2 ) can be provided. TIFF2025529182000012.tif1530 (Formula 23)

[0093] With θ4 set to 90°, the following mathematical identities can be applied to simplify some of Equations 15-22: TIFF2025529182000013.tif1573 (Formula 24)

[0094] For example, Equation 18 can be simplified as shown in Equation 25 below, and Equations 15 to 22 can be solved analytically. TIFF2025529182000014.tif1642 (Formula 25)

[0095] The following equations can be derived from equations 15 to 22 based on equations 23 to 25. TIFF2025529182000015.tif126138

[0096] The interval calculation circuit 1116 can implement Equations 26-34 with θ4 set to 90 degrees or π / 2 to determine an accurate analytical solution including values ​​for θ1, θ2, and θ3, and determine the durations of the charge interval, first dead time interval, discharge interval, and second dead time interval based on θ1, θ2, θ3, and θ4. L3 and J L4 Equations 26 and 27 may depend on the ratio between the input voltage and the output voltage. In some examples, the interval calculation circuit 1116 may implement a different set of equations derived from Equations 15-22 by setting θ4 to a different value other than 90° or π / 2.

[0097] 13 is a block diagram of an example of a generalized interval calculation circuit 1116 configured to solve Equations 26 through 34. The interval calculation circuit 1116 includes a feedforward (FF) circuit 1302, a feedback circuit 1303, a state plane solver circuit 1308, and an angle-to-interval conversion circuit 1310. The feedback circuit 1303 includes a compensation circuit 1304 and a state plane parameter generation circuit 1306.

[0098] The interval calculation circuit 1116 receives as input a digital value x REF [k], x[k], V IN , V OUT , Tau(τ), and Ro, and from these values ​​generate three input variables used to solve Equations 26-34. The index "k" indicates a particular sampling time, or x REFand x may represent particular samples of the output voltage and the input voltage (V OUT / V IN ) and the ratio between the current reference and the output voltage and the resonant impedance (e.g., TIFF2025529182000016.tif1628) can be used as two of the three variables. The third variable (denoted x[k]) is a measurement used for negative feedback, for example, to adjust the switching cycle period. The third variable can be ZVD (Zero Voltage Switching Detection), i L , i L1 , or i L2 and so on, may represent a measurement of the operation of the power supply system 104 during the first or second dead time periods.

[0099] The interval calculation circuit 1116 also calculates a feedforward value y[k]. The feedforward value is determined by the target switching frequency (or switching cycle period), the charging interval (I L1 ) target peak inductor current during the discharge interval (I L2 ) may represent an initial target operating state of the power supply system 104, such as a target peak inductor current, a target average inductor current, a target charge interval duration, a target discharge interval duration, etc. In some examples, the target state may be a target operating state of the power supply system 104 to achieve ZVS. The interval calculation circuit 1116 may use x[k] as negative feedback to adjust the value of y[k], where y[k] is normalized by the interval calculation circuit 1116 and used in conjunction with M and J as inputs to Equations 26-34. LIt is used together with (Equations 11 and 12). As will be shown in the example below, the value y[k] can be adjusted by a compensator.

[0100] Various measured values ​​can be used as x[k]. Table 1 shows examples of x[k] and x[k] values ​​that can be used with x[k]. REF The corresponding example for [k] is shown below. TIFF2025529182000017.tif73102

[0101] ZVD[k] may be a sample of the indication signal 1072 that indicates whether zero voltage switching (ZVS) is detected. L [k] can be a sample of the average current (average power conversion current) flowing in inductor 306. L1 [k] can be a sample of the peak current through inductor 306 during the charging interval (FIG. 12A). L2 [k] can be the peak current flowing through inductor 306 during the discharge interval (FIG. 12A). The reference signal x[k] associated with each x[k] REF [k] represents the desired / target value of x[k]. For example, i LREF [k] can be a target power converter current, such as a target average power converter current (target average inductor current), a desired peak charge current, or a desired peak discharge current.

[0102] Examples of y[k] provided by the interval calculation circuit 1116 based on x[k] are shown below in Table 2. In various examples of the interval calculation circuit 1116, y[k] can be any of the variables in Equations 26-34 except for x[k]. TIFF2025529182000018.tif4958TIFF2025529182000019.tif4756

[0103] The FF circuit 1302 determines y FF [k] Provide Feedforward Values: Additional information about the feedforward calculation is provided for specific implementations. y FF [k]=f(v IN [k],v OUT [k],x[k],x REF [k]) (Equation 35)

[0104] The FF circuit 1302 uses the feedforward value y[k] to generate y[k] at the feedforward output. FF [k] is provided to the feedforward input of the compensation circuit 1304. The compensation circuit 1304 provides y FF [k], and the feedback components x[k] and x[k] received at the feedback input of the compensation circuit 1304. REF [k] can be provided. Additional information regarding the y[k] calculation is provided for specific implementations. y[k]=f(y FF [k],x[k],x REF [k]) (Equation 36)

[0105] Compensation circuit 1304 provides y[k] to state plane parameter generation circuit 1306. State plane parameter generation circuit 1306 generates normalized state plane parameter values ​​(Equations 37-39) that are used to solve Equations 26-34. State plane parameter generation circuit provides the parameter values ​​at its parameter output to state plane solver circuit 1308. TIFF2025529182000020.tif4691In formula, v[k] is a measured voltage such as the converter input voltage, converter output voltage, or converter switch-node capacitor voltage, and Y BASE [k] is the base associated with the selected y[k]. For example, referring to Table 2, if y[k] is F[k], then Y BASE = f0, and y[k] is θ1 or θ3, Y BASE =1 / ω0, or y[k] is i L , i L1 , or i L2 If Y BASE =I BASE is.

[0106] To solve Equations 26 to 34, the state plane solver circuit 1308 uses the parameter values ​​(M[k], J[k]) received from the state plane parameter generation circuit 1306 as solver inputs. L [k], y norm [k]). According to Equation 33, θ is set to 90°. The state plane solver circuit 1308 provides the values ​​of angles θ, θ, θ, and θ at the solver output to the angle inputs of the angle-to-interval converter circuit 1310.

[0107] The angle-to-interval conversion circuit 1310 converts interval values ​​t M , t SR , t dt1 , and t dt2 (t1, t3, t2, and t4 in FIG. 12A) are determined based on θ1, θ3, θ2, and θ4, respectively. The angle-to-spacing conversion circuit 1310 can determine the spacing values ​​as follows: TIFF2025529182000021.tif1181 (Formula 40) where τ[k] is the resonant time constant of the power supply system 104, as described above. The angle-to-spacing converter circuit 1310 converts t M , t SR , t dt1 , and t dt2 to the interval input of the control logic circuit 1118.

[0108] Figure 14 shows the interval value t M , t SR , t dt1 , and t dt2 To determine the average inductor current (i L13 , the switching frequency compensation circuit 1404 and the state plane parameter generation circuit 1406 can be part of the feedback circuit 1303, the state plane solver circuit 1408 can be part of the state plane solver circuit 1308, and the angle-to-interval conversion circuit 1410 can be part of the interval conversion circuit 1310. The interval calculation circuit 1116 receives as input a digital value I L,REF , I L [k], V IN , V OUT , Tau(τ), and Ro.

[0109] The FF switching frequency circuit 1402 determines the feedforward (FF) switching frequency value (F SW,FF [k]). The feedforward switching frequency value may represent an initial estimate of the switching frequency value, which may then be adjusted by the feedback circuit 1303. In some examples, the FF switching frequency circuit 1402 provides F SW,FF [k] can be provided. TIFF2025529182000022.tif11106 (Formula 41)

[0110] In some examples, the FF switching frequency circuit 1402 determines the F based on an approximation that ignores (or otherwise does not take into account) resonant transitions. SW,FF [k] may be generated. TIFF2025529182000023.tif1983 (Formula 42) In the formula, I ZVScan be a constant value representing the negative current used for ZVS when resonant transitions of the switching node are absent or not otherwise taken into account.

[0111] The FF switching frequency circuit 1402 is f sw To generate [k], F SW,FF [k] to the switching frequency compensation circuit 1404. The switching frequency compensation circuit 1404 calculates F SW,FF [k] is the switching period adjustment value T sw.ajd By combining with [k], f sw [k] can be provided. TIFF2025529182000024.tif1481 ​​(Formula 43)

[0112] Figure 15 shows the T sw,ajd [k]. The compensation circuitry 1500 includes a difference circuit 1502 and a compensation circuit 1504. The difference circuit 1502 calculates the difference between i L [k] and i L,REF [k] and provides the error signal to compensation circuit 1504. Compensation circuit 1504 L [k" and i L,REF [k] to reduce the difference between T sw,ajd It may include a proportional-integral-derivative (PID) controller (or other control process) that modulates [k].

[0113] Returning to FIG. 14, the switching frequency compensation circuit 1404 calculates the T sw,ajd [k] to the state plane parameter generation circuit 1406. The state plane parameter generation circuit 1406 may generate the normalized state plane parameters as follows: TIFF2025529182000025.tif4593

[0114] The state plane parameter generation circuit 1406 outputs M[k], J L The state plane solver circuit 1408 applies the parameter values ​​received from the state plane parameter generation circuit 1406 to Equations 47-54 to determine θ1, θ2, and θ3. J L4 [k]=1-M[k] (Equation 47) TIFF2025529182000026.tif104167

[0115] As in Equation 33, θ4 is set to 90° (or π / 2) in Equation 53. The state plane solver circuit 1408 provides values ​​of θ1, θ2, θ3, and θ4 to an angle-to-spacing conversion circuit 1410.

[0116] The angle-to-interval conversion circuit 1410 converts the duration values ​​t for the charge interval, the discharge interval, the first dead time, and the second dead time. M , t SR , t dt1 , and t dt2 The angle-to-interval conversion circuit 1410 may determine the interval time values ​​t1, t2, t3, and t4 as follows: TIFF2025529182000027.tif1283 (Formula 55) where τ[k] is the resonant time constant of the power supply system 104 TIFF2025529182000028.tif929. Referring again to FIG. 12A, t1 is t M t2 corresponds to t dt1 t3 corresponds to t SR t4 corresponds to t dt2 The angle-to-spacing converter circuit 1410 converts t M , t SR , t dt1 , and t dt2 to the control logic circuit 1118.

[0117] 16 is a block diagram of an example interval calculation circuit 1116 that uses ZVD feedback (indicating a ZVS or non-ZVS state) to adjust the switching frequency. The interval calculation circuit 1116 includes a FF switching frequency circuit 1602, a switching frequency compensation circuit 1604, a state plane parameter generation circuit 1406, a state plane solver circuit 1408, and an angle-to-interval conversion circuit 1410. The interval calculation circuit 1116 receives as input a digital value I L_REF , ZVD M [k], V IN , V OUT , Tau(τ), and Ro. ZVD M is the feedback of ZVD in switching the main switch (e.g., switch 1008 in FIG. 10, display signal 1072).

[0118] The FF switching frequency circuit 1602 determines the FF switching frequency value (F SW,FF In some examples, the FF switching frequency circuit 1602 provides f [k] according to Equation 42. SW,FF [k] can be generated.

[0119] The FF switching frequency circuit 1602 is f sw To generate [k], F SW,FF [k] to the switching frequency compensation circuit 1604. The switching frequency compensation circuit 1604 calculates f according to Equation 43. sw [k] can be provided.

[0120] Figure 17 shows the T sw,ajd 17 is a block diagram of a compensation circuit element 1700 of the FF switching frequency circuit 1602 for generating [k]. The compensation circuit element 1700 includes a difference circuit 1702 and a compensation circuit 1704. The difference circuit 1702 is a ZVD M The difference between [k] and the logic "1" value (or ZVD M [k] is a logic 1 value or is in an asserted state) and provides the error signal to compensation circuit 1704. Compensation circuit 1704M Based on whether [k] is a logic 1 value, T sw,ajd The compensation circuit 1704 may include a proportional-integral-derivative (PID) controller (or other control process) that modulates [k] to a higher or lower value. M If [k] is a logic 1 value, T sw,ajd [k] can be reduced, and ZVD M If [k] is not a logical 1 value, T sw,ajd [k] can be increased.

[0121] Returning to FIG. 16, the switching frequency compensation circuit 1404 calculates T sw,ajd [k] to the state plane parameter generation circuit 1406. The state plane parameter generation circuit 1406 can generate the normalized state plane parameters according to Equations 44 to 46.

[0122] The state plane parameter generation circuit 1406 outputs M[k], J L The state plane solver circuit 1408 applies the parameter values ​​received from the state plane parameter generation circuit 1406 to solve Equations 47-54 for θ1, θ2, and θ3.

[0123] As in Equation 33, θ4 is set to 90° in Equation 53. The state plane solver circuit 1408 provides values ​​of θ1, θ2, θ3, and θ4 to the angle-to-spacing conversion circuit 1410.

[0124] The angle-to-interval conversion circuit 1410 converts the time values ​​t for the charge interval, the discharge interval, the first dead time, and the second dead time. M , t SR , t dt1 , and t dt2based on θ1, θ3, θ2, and θ4, respectively. The angle-to-interval converter circuit 1410 may determine the time values ​​according to Equation 40. The angle-to-interval converter circuit 1410 converts t M , t SR , t dt1 , and t dt2 to the control logic circuit 1118.

[0125] FIG. 18 shows the compensation circuit 1704 with the switching cycle period adjustment value T sw,ajd 18 is a flowchart of a method for determining [k]. In block 1802, the compensation circuit 1704 determines the ZVD M Whether [k] is a logic 1 value (ZVD M In block 1802, ZVD M In response to [k] being asserted, in block 1804, the compensation circuit 1704 sw,ajd The value of [k] is T sw,ajd [k] can be decreased relative to its previous value. TIFF2025529182000029.tif13111 (Formula 56) During the ceremony, ΔT SW is the change value (e.g., 0.5, 1, etc.), k ZVD is the gain factor.

[0126] ZVD at block 1802 M In response to [k] not being asserted, at block 1806, the compensation circuit 1704 sw,ajd The value of [k] is T sw,ajd [k] can be increased relative to its previous value. TIFF2025529182000030.tif11109 (Formula 57)

[0127] FIG. 19 shows the gain coefficient (k ZVD19 is a flowchart of a method for adjusting the ZVD. M (ZVD M [k]) is ZVD M The preceding value of (ZVD M [k-1]) (e.g., whether the gain coefficients are the same in successive switching cycles). M If the current and previous values ​​of are the same, then in block 1904 the compensation circuit 1704 calculates T sw,ajd The gain coefficient (k ZVD ) can be increased. k ZVD =k ZVD +Δk ZVD,1 (Formula 58) In the formula, Δk ZVD,1 is the change value applied to increase the gain.

[0128] If the current and previous values ​​of ZVDM are not the same in block 1902, then in block 1906 the compensation circuit 1704 calculates T sw,ajd The gain coefficient (k ZVD ) can be reduced. k ZVD =k ZVD -Δk ZVD,2 (Formula 59) In the formula, Δk ZVD,2 is the change value applied to reduce the gain.

[0129] FIG. 20 shows the frequency f of the FF switching frequency circuit 1602 or the FF switching frequency circuit 1402. SW,FF I for the calculation of [k] ZVS 20 is a block diagram of compensation circuitry 2000 that can be used to generate I ZVS[k] may be adaptively adjusted to account for resonant transitions, rather than being a constant as in Equation 42. Compensation circuitry 2000 includes a difference circuit 2002 and a compensation circuit 2004. Difference circuit 2002 calculates the previous value of the switching frequency (f SW [k-1]) and its feedforward component (f SW,FF [k-1]), which may represent additional time provided to account for resonant transitions of the switching node. Compensation circuit 2004 calculates I based on the error signal. ZVS It may include a proportional-integral-derivative (PID) controller (or other control process) that modulates [k].

[0130] The FF switching frequency circuit 1402 or the FF switching frequency circuit 1602 outputs the adjusted I ZVS,adj Based on [k], F SW,FF [k] can be generated as follows: TIFF2025529182000031.tif2291 (Formula 60)

[0131] Figure 21 shows the time t based on the average inductor current and peak charging current. M , t SR , t dt1 , and t dt2 21. The interval calculation circuit 1116 includes a FF peak current circuit 2102, a peak current compensation module 2104, a state plane parameter generation circuit 2106, a state plane solver circuit 2108, and an angle-to-interval conversion circuit 1410. The interval calculation circuit 1116 receives as input a digital value I LREF , I L [k], V IN , V OUT , Tau(τ), and Ro.

[0132] The FF peak current circuit 2102 determines the FF peak current value (i L1,FF [k]). i L1,FF [k]=f(v IN [k],vOUT [k],i L,REF [k]) (Formula 61)

[0133] In some examples, the FF peak current circuit 2102 calculates i according to Equation 62. L1,FF [k] can be generated. i L1,FF [k]=2i L,REF [k] (Equation 62)

[0134] The FF peak current circuit 2102 is L1 To generate [k], i L1,FF [k] to the peak current compensation module 2104. The switching frequency compensation circuit 1604 calculates i as follows: L1 [k] can be provided. i L1 [k]=i L1,COMP [k]+i L1,FF [k] (Equation 63)

[0135] Figure 22 shows the i L1,COMP [k]. The compensation circuitry 2200 includes a difference circuit 2202 and a compensation circuit 2204. The difference circuit 2202 calculates the average current (i L [k]) and the reference current (i L,REF [k]) and provides the error signal to compensation circuit 2204. Compensation circuit 2204 L [k" and i L,REF [k] based on the error signal to reduce the difference between i L1,COMP It may include a proportional-integral-derivative (PID) controller (or other control process) that modulates [k].

[0136] Returning to FIG. 21, the peak current compensation module 2104 calculates the peak current, i L1 [k] to the state plane parameter generation circuit 2106. The state plane parameter generation circuit 2106 generates the normalized state plane parameters M[k] and J[k] according to Equations 44 and 45. LThe state plane parameter generation circuit 2106 can generate the normalized state plane parameters J L1 [k] can be generated as follows: TIFF2025529182000032.tif1554 (Formula 64)

[0137] The state plane parameter generation circuit 1406 outputs M[k], J L [k”, and J L1 [k]. The state plane solver circuit 2108 applies the parameter values ​​received from the state plane parameter generation circuit 2106 to solve Equations 65-72 for θ1, θ3, θ2, and θ4. TIFF2025529182000033.tif109152

[0138] The state plane solver circuit 2108 provides values ​​of θ1, θ2, θ3, and θ4 to the angle-to-interval converter circuit 1410. The angle-to-interval converter circuit 1410 converts the time values ​​t for the charge interval, the discharge interval, the first dead time, and the second dead time. M , t SR , t dt1 , and t dt2 based on θ1, θ3, θ2, and θ4, respectively. The angle-to-interval converter circuit 1410 may determine the time values ​​according to Equation 40. The angle-to-interval converter circuit 1410 converts t M , t SR , t dt1 , and t dt2 to the control logic circuit 1118.

[0139] In another example of an interval calculation circuit 1116 similar to that shown in FIG. 21, an FF peak current circuit 2102 calculates an FF peak current value (i L2,FF [k]). i L2,FF [k]=f(v IN [k],v OUT [k],i L,REF[k]) (Formula 73)

[0140] In some examples, the FF peak current circuit 2102 calculates i according to Equation 74. L2,FF [k] can be generated. i L2,FF [k]=2i L,REF [k] (Formula 74)

[0141] The FF peak current circuit 2102 is L2 To generate [k], i L2,FF [k] to the peak current compensation module 2104. The peak current compensation module 2104 provides i L2 [k] can be provided as follows: i L2 [k]=i L2,COMP [k]+i L2,FF [k] (Equation 75) In the formula, i L2,COMP [k] is the number of L1,COMP [k]) is provided by compensation circuitry 2200.

[0142] Figure 23 shows the i L2,COMP 2 is a block diagram of compensation circuitry 2300 of FF peak current circuit 2102 for generating [k]. Compensation circuitry 2300 includes a difference circuit 2302 and a compensation circuit 2304. Difference circuit 2302 calculates the average current (i L [k]) and the reference current (i L,REF [k]) and provides the error signal to compensation circuit 2304. Compensation circuit 2304 L [k" and i L,REF [k] based on the error signal to reduce the difference between i L2,COMP It may include a proportional-integral-derivative (PID) controller (or other control process) that modulates [k].

[0143] The peak current compensation module 2104 uses i L2[k] to the state plane parameter generation circuit 2106. The state plane parameter generation circuit 2106 generates the normalized state plane parameters M[k] and J[k] according to Equations 44 and 45. L The state plane parameter generation circuit 2106 can generate the normalized state plane parameters J L2 [k] can be generated as follows: TIFF2025529182000034.tif1651 (Formula 76)

[0144] The state plane parameter generation circuit 2106 outputs M[k], J L [k”, and J L1 [k]. The state plane solver circuit 2108 applies the parameter values ​​received from the state plane parameter generation circuit 2106 to solve Equations 77-84 for θ1, θ3, θ2, and θ4. TIFF2025529182000035.tif36135TIFF2025529182000036.tif74148

[0145] The state plane solver circuit 2108 provides values ​​of θ1, θ2, θ3, and θ4 to the angle-to-interval converter circuit 1410. The angle-to-interval converter circuit 1410 converts the time values ​​t for the charge interval, the discharge interval, the first dead time, and the second dead time. M , t SR , t dt1 , and t dt2 based on θ1, θ3, θ2, and θ4, respectively. The angle-to-interval converter circuit 1410 may determine the time values ​​according to Equation 40. The angle-to-interval converter circuit 1410 converts t M , t SR , t dt1 , and t dt2 to the control logic circuit 1118.

[0146] 24 is a block diagram of an example time constant estimation circuit 2402 used in conjunction with the interval calculation circuit 1116. If the resonant time constant τ[k] provided to the interval calculation circuit 1116 does not reflect the actual resonant time constant of the power supply system 104 (e.g., the L and C values ​​provided to the controller 1012 are inaccurate), the interval t calculated based on τ[k] may be M , t SR , t dt1 , and t dt2 The duration value of may not be equal to the interval for achieving ZVS. Therefore, the time constant estimation circuit 2402 estimates the ZVD (ZVD R Based on the detection (or non-detection) of the resonant time constant τ[k], the value of the resonant time constant τ[k] can be adjusted (indication signal 1072 in FIG. 10), and the interval calculation circuit 1116 uses the adjusted resonant time constant to calculate t M , t SR , t dt1 , and t dt2 The compensator 2404 may adjust the value of τ[k] to achieve ZVS of the power converter rectifier switch (e.g., switch 1010). The compensator 2404 may include a PID controller or other control circuit to adjust τ[k]. The time constant estimation circuit 2402 may determine the duration of the time value t M , t SR , t dt1 , and t dt2 The adjusted power converter resonant period τ[k] may be provided to the interval calculation circuit 1116 for use in calculating τ[k].

[0147] 25 illustrates an example of the internal components and their operation of the transition measurement circuit 1070. The transition measurement circuit 1070 may include a voltage measurement circuit 2502, a threshold generation circuit 2504, a comparator 2506, and a processing circuit 2508. The voltage measurement circuit 2502 may be coupled across a main switch 2510 (which may be one of switches 1008 or 1010) of the power converter to measure a voltage difference across the main switch 1010. If the main switch 2510 includes a FET, the voltage measurement circuit 2502 may provide a voltage signal 2512 based on a voltage difference between current terminals 2514 and 2516 (e.g., drain and source terminals) of the FET, where the current terminal 2514 may be coupled to ground and the current terminal 2516 may be coupled to a switching node (e.g., switching node 1014) and an inductor (e.g., inductor 306). In some examples, the voltage measurement circuit 2502 may include a differential amplifier for generating the voltage signal 2512. Additionally, the threshold generation circuit 2504 may output a threshold voltage 2522 representing a zero voltage difference across the main switch 2510. The threshold voltage 2522 may be the voltage signal 2512 provided by the voltage measurement circuit 2502 when the voltage difference is zero. The comparator 2506 may compare the voltage signal 2512 against the threshold voltage 2522 to provide a decision signal 2530, the decision signal indicating whether the voltage difference across the main switch 2510 is zero. In the example of FIG. 25 , the comparator 2506 may provide a logic one for the decision signal 2530 when the voltage difference between the current terminals 2514 and 2516 is less than or equal to zero and may provide a logic zero for the decision signal 2530 when the voltage difference between the current terminals 2514 and 2516 is greater than zero.

[0148] Also, the processing circuit 2508 may be coupled to a control terminal 2532 (e.g., a gate terminal) of the main switch 2510 and to the output of the comparator 2506. The processing circuit 2508 may generate an indication signal 1072 based on the decision signal 2530 and a control signal 2543 (e.g., one of VG1 or VG2) at the control terminal 2532 to indicate whether the main switch 2510 switches states after the switching node 1014 transitions fully to ground, so that there is zero voltage difference across the main switch 2510 and ZVS can be obtained. In some examples, the processing circuit 2508 may include a pulse generation circuit.

[0149] Figures 26 and 27 illustrate graphs of signals 2512, 2534, 2530, and indicator signal 1072 over time, where indicator signal 1072 is provided by example transition measurement circuit 1070 of Figure 25. Figure 26 illustrates graphs 2602, 2604, 2606, and 2608 of signals 2512, 2534, 2530, and indicator signal 1072, respectively, when indicator signal 1072 indicates ZVS. Figure 27 illustrates graphs 2702, 2704, 2706, and 2708 of signals 2512, 2534, 2530, and 1072, respectively, when indicator signal 1072 indicates non-ZVS.

[0150] 26, at time T0, the voltage difference across the primary switch 2510 drops below zero, and the signal 2512 also drops below the threshold voltage 252. This causes the decision signal 2530 to be asserted at time T0. The asserted decision signal 2530 may enable the pulse generator of the transition measurement circuit 1070. At T1, after T0, the control signal 2534 changes from the second state to the first state, enabling the primary switch 2510. The rising edge of the control signal 2534 at T1 triggers the pulse generator to generate a pulse for the indication signal 1072; the pulse may indicate a ZVS condition because the primary switch 2510 changes state when the voltage across the primary switch is zero.

[0151] 27, at T3, the control signal 2534 changes from the second state to the first state, enabling the primary switch 2522 when the voltage difference across the primary switch 2510 is still above zero and the signal 2512 is above the threshold voltage 2522. This causes the decision signal 2530 to be deasserted, which may disable the pulse generator of the transition measurement circuit 1070. Accordingly, the indication signal 1072 may be deasserted, which may indicate a non-ZVS condition because the primary switch 2510 changes state when the voltage across the primary switch is above zero.

[0152] 28 illustrates an example state diagram 2850 of the state machine in the control logic 1118 when operating in switching mode. The control logic 1118 can reset counters and start in state 2842 when the switching mode begins. In some examples, the control logic 1118 may reset counters while in state 2842, respectively. M , t SR , t dt1 , and t dt2 After receiving the digital values, the control logic 1118 can proceed to the charging state 2852 via edge 2844.

[0153] When in the charging state 2852, the control logic circuit 1118 may first reset a counter and control the PWM generator circuit 1114 to set a control signal for a primary switch (e.g., switch 1008) to a first state to enable the primary switch and set a control signal for an SR switch (e.g., switch 1010) to a second state to disable the SR switch. The counter may increment over time, and the control logic circuit 1118 / PWM generator circuit 1114 may increment the counter value when the counter value reaches t, as indicated by transition edge 2854. M When the digital value is below 1136, which represents the current, the battery can remain in charging mode.

[0154] When the counter value matches the digital value 1124 / 1136, the control logic circuit 1118 can reset the counter and transition to a first dead-time state 2862 via transition edge 2864. Within the first dead-time state 2862, the PWM generator circuit 1114 sets both VG1 and VG2 to a second state. The counter can increment over time after the reset is released, and the control logic circuit 1118 / PWM generator circuit 1114 can increment the counter value over time until the first dead-time interval t dt1 The first dead time state can be maintained when the digital value of the first dead time is less than 1140, which represents the duration of the first dead time.

[0155] When the counter value matches the digital value 1140, the control logic circuit 1118 can reset the counter and transition to a discharging state 2872 via transition edge 2874. In the discharging state 2872, the PWM generating circuit 1114 can set the control signal for the primary switch (e.g., switch 1008) to a second state to disable the primary switch and set the control signal for the SR switch (e.g., switch 1010) to a first state to enable the SR switch. The counter can increment for time after the reset is released, and the control logic circuit 1118 / PWM generating circuit 1114 can increment the counter value to the charge interval t, as indicated by transition edge 2876. SR When the digital value falls below 1128, which represents the duration of the discharge, the battery can remain in the discharge state.

[0156] When the counter value matches the digital value 1128, the control logic circuit 1118 may reset the counter and transition to a second dead-time state 2882 via transition edge 2884. Within the second dead-time state 2882, the PWM generator circuit 1114 sets both control signals VG1 and VG2 low. The counter may increment over time after the reset is released, and the PWM generator circuit 1114 determines when the counter value reaches the second dead-time interval t, as indicated by transition edge 2886. dt2The control logic 1118 may remain in the first dead time state when the counter value falls below digital value 1142, which represents the duration of the first dead time. When the counter value matches digital value 1142, the control logic 1118 may enter state 2892 via edge 2894, where the switching mode is terminated.

[0157] Figure 29 illustrates an example of a hardware system 2900 that may be used as described herein above. For example, the hardware system 2900 may implement the functionality of the controller 1012. Figure 29 provides only a generalized illustration of various components, any or all of which may be used as appropriate.

[0158] Hardware system 2900 is shown including hardware elements that may be electrically coupled (or otherwise in communication, as appropriate) via bus 2905. The hardware elements may include a processing unit 2910, which may include, without limitation, one or more general-purpose processors, one or more application-specific processors (e.g., digital signal processing (DSP) chips, graphics acceleration processors, application-specific integrated circuits (ASICs), and / or the like), and / or other processing structures or means. For example, processing unit 2910 may perform calculations according to Equations 26-84 above. As shown in FIG. 29 , some embodiments may have a separate digital signal processor (DSP) 2920, depending on the desired functionality. For example, DSP 2920 may process output voltage measurements 1040 and input voltage measurements 1050 of power conversion circuit 122. In some examples, the hardware system 2900 can include one or more input devices 2970, which can include user interface related devices (e.g., touch screen, touch pad, microphone, buttons, dials, switches, and / or the like). Similarly, one or more output devices 2915 can be associated with interacting with a user (e.g., a display, light emitting diodes (LEDs), speakers). The hardware system 2900 can further include a sensor 2940. For example, the sensor 2940 can include various components of the transition measurement circuit 1070.

[0159] Hardware system 2900 may further include and / or be in communication with memory 2960. Memory 2960 may include, but is not limited to, local and / or network-accessible storage, disk drives, drive arrays, optical storage devices, solid-state storage devices, such as programmable, flash-updatable, and / or read-only memory (ROM). Such storage devices may be configured to implement any suitable data storage, such as various file systems, database structures, and / or the like.

[0160] In some examples, memory 2960 may provide memory 1120 of FIG. 11 to provide storage to support calculations according to Equations 26-84. Memory 2960 may also include software elements (not shown in FIG. 29) including an operating system, device drivers, executable libraries, and / or other code, such as one or more application programs, which may include computer programs provided by various embodiments, and / or may be designed to implement various methods and / or configure systems provided by other embodiments as described herein. By way of example only, one or more procedures described for operations described herein may be implemented as code and / or instructions in memory 2960 executable by hardware system 2900 (and / or processing unit 2910 or DSP 2920 within hardware system 2900). In some aspects, such code and / or instructions may be used to configure and / or adapt a general-purpose computer (or other device) to perform one or more operations described herein.

[0161] FIG. 30 includes a flowchart of an example method 3000 for controlling a power conversion circuit, such as the power conversion circuit 122 of FIGS. 3, 6, and 10. For example, the method 3000 can be performed by the controller 1012. The power conversion circuit can include an inductor (e.g., inductor 306), a first switch (e.g., one of switches 308, 602 / 604, or 1008), and a second switch (e.g., one of switches 310, 604 / 602, or 1010). The inductor and the first and second switches can be coupled at a switching node (e.g., one of nodes 314, 614, or 1014), and the first and second switches can be coupled in series between the positive and negative outputs of the power converter. The first switch can operate as a main switch, and the second switch can operate as an SR switch.

[0162] The power converter may be part of a power supply system (e.g., power supply system 104), which further includes a first measurement circuit (e.g., one of measurement circuits 352, 662, or 1052) coupled across the positive and negative inputs for measuring the input voltage to the power converter, and a second measurement circuit (e.g., one of measurement circuits 342, 652, or 1042) for measuring the output voltage of the power converter. The power supply system 104 may also include a third measurement circuit (e.g., transient measurement circuit 1070) for measuring transient states of the inductor current or the switching node voltage. FIG. 25 illustrates an example of transient measurement circuit 1070. In some examples, the third measurement circuit may be coupled to the first and second current terminals of one of the first or second switches, as shown in FIG. 25. In some examples, the third measurement circuit may be coupled to the first and second current terminals of both the first or second switches. In some examples, the third measurement circuit may be coupled to the switching node.

[0163] In step 3002, the controller receives a first measurement of an input voltage to the power converter from a first measurement circuit, which may be part of the power converter state. The first measurement may include a digital value generated by an ADC of the first measurement circuit, and the first measurement may indicate a magnitude and polarity of the input voltage for a current switching cycle.

[0164] In step 3004, the controller receives from the second measurement circuit a second measurement of the output voltage to the power converter, which may be part of the power converter state. The second measurement may include a digital value generated by an ADC of the second measurement circuit, and the second measurement may indicate the magnitude of the output voltage.

[0165] In step 3006, the controller receives a third measurement signal from a third measurement circuit coupled to a current terminal of a first switch of the power converter, a current terminal of a second switch of the power converter, and / or an inductor of the power converter. The third measurement signal may indicate a voltage across the first switch when the first switch changes state. The indication signal may indicate whether the voltage has completed transition to a target voltage (e.g., ground, output voltage) and whether ZVS is detected, such that the voltage difference across the primary switch (first or second switch) is zero or below zero when the primary switch changes state. In some examples, the third measurement signal may represent a current (e.g., an average current) flowing in the inductor. The detection of ZVS or non-ZVS and the average current flowing in the inductor may be part of the power converter status.

[0166] In step 3008, the controller receives a control signal representing a predetermined power conversion resonant period. The resonant period can be calculated based on a specified inductance of the inductor and, in some examples, a specified capacitance at the switching node. In some examples, the resonant period can be adaptively determined based on a ZVD signal measured at the switching of a rectifying switch (e.g., switch 1010), as shown in FIG.

[0167] In step 3010, the controller may determine, based on the first, second, and third measurement signals, a charge interval of a switching cycle in which the inductor is charged, a discharge interval of a switching cycle in which the inductor is discharged, and a first dead time interval following the charge interval and preceding the discharge interval. For example, the controller may determine values ​​of θ1, θ2, and θ3 by solving Equations 26-33, 44-54, 64-72, or 76-84. The controller may use the values ​​of θ1, θ2, and θ3 to solve Equation 40 to determine t M , t SR , and t dt1 The value of can be determined.

[0168] In step 3012, the controller can determine a second dead-time interval following the discharge interval and preceding the charge interval based on a predetermined power converter resonant period. For example, the controller can set θ4 to π / 2, as in Equation 33, Equation 53, Equation 71, or Equation 83. The controller uses the value of θ4 to solve Equation 40 to determine t dt2 The value of can be determined.

[0169] In step 3014, the controller can provide the first drive signal and the second drive signal based on the charge interval, the discharge interval, the first dead time interval, and the second dead time interval. For example, the interval calculation circuit 1116 can calculate t M , t SR , and t dt1 , and t dt2may be provided to the control logic circuit 1118. The control logic circuit 1118 may control the PWM generation circuit 1114 to generate VG1 or VG2 to control the switching of the first switch and the second switch.

[0170] Within a charging interval, the controller can enable the first switch and disable the second switch to charge the inductor with the input current, with the inductor current increasing to reach a peak current at the end of the charging interval. The controller can set the first control signal to a first state (e.g., a gate voltage higher than the source voltage by the conduction threshold of the NFET of the first switch) to enable the first switch and the second control signal to a second state (e.g., a gate voltage below the sum of the source voltage and the conduction threshold of the NFET of the second switch) to disable the second switch.

[0171] Within a first dead-time interval after the charging interval, the controller can disable both the first and second switches. The controller can set both the first control signal and the second control signal to a second state to disable both the first switch and the second switch.

[0172] During a discharge interval after the first dead-time interval, the controller can disable the first switch and enable the second switch to discharge the inductor to provide output current to the load, and the inductor current can decrease from the peak current to an SR turn-off current at the end of the discharge interval. The SR turn-off current can be zero or a negative current. The controller can set the first control signal to a second state to disable the first switch and the second control signal to a first state to enable the second switch.

[0173] Within a second dead time interval after the discharge interval, the controller can set both the first control signal and the second control signal to a second state to disable both the first switch and the second switch.

[0174] The controller 1012 provides integrated control that ensures accurate and optimal dead-time for ZVS of both the main and rectifier switches in a ZVS quasi-square-wave (QSW) converter using precise average inductor current control. The current and voltage waveforms provided by the controller 1012 are beneficial from the standpoint of optimizing hardware design and efficiency. Existing control techniques have limited performance due to their reliance on high-bandwidth current sensors or open-loop control based on approximations or look-up tables. Control inaccuracies can result in poor tracking of the current reference, but more importantly, can lead to ZVS losses in both the main and rectifier devices, which can lead to significant losses in semiconductor devices, especially in high-frequency designs.

[0175] The ZVS-QSW converter is described by a system of transcendental equations. A set of solutions can only be found using iterative numerical methods, which are not feasible for real-time implementation. The controller 1012 sets the angle of the valley resonant transition interval to 90° and uses mathematical identities to simplify and analytically solve the set of equations. This provides an accurate solution for the waveforms and timing for the ZVS-QSW converter, with the constraint that the valley resonant transition interval angle (θ4) is set to 90°. The calculated timing is used to generate the gate pulses.

[0176] Inputs to the controller 1012 may be the inductor current reference, the converter input and output voltages, and the ZVD signal of the primary switch. The dead time before turning on the primary switch remains fixed at a value corresponding to a valley resonant transition interval angle (θ4) of 90°. The formula assumes a switching frequency based on an approximate estimation. Using the analytical solution described above, the timing is calculated and gate pulses are applied accordingly. The switching frequency may be adaptively adjusted, for example, based on the ZVD signal. Once the switching frequency is adjusted to achieve ZVS, the average inductor current may be equal to the current reference, and the dead time calculated by the controller 1012 may correspond to the duration of the resonant transition interval.

[0177] As shown in FIGS. 11 to 30, M , t SR , t dt1 , and t dt2 The algorithm / method implemented in determining t can provide various advantages. Specifically, the controller 1012 can determine an accurate analytical solution without using iterative numerical methods, thereby enabling the controller 1012 to determine an accurate analytical solution for t M , t SR , t dt1 , and t dt2 The computational and memory resources involved in calculating t are reduced, and these interval values ​​can be calculated and updated in real time. Also, because an accurate analytical solution is determined, the dead-time interval and switching frequency for ZVS can be determined more accurately, thereby reducing hard switching and third-quadrant conduction losses, and therefore improving (or even maximizing) the performance of the semiconductor switching devices. The controller 1012 provides ZVS at all operating points, resulting in low losses. The controller 1012 also calculates t under light load conditions. M , t SR , t dt1 , and t dt2 Due to the reduced delay in calculating / adjusting the THD, the controller 1012 can provide low total harmonic distortion (THD). For example, the THD can be approximately 9% at no load and less than 4% at full load. The controller 1012 can provide excellent transient response and no-load operation (e.g., low dissipation without burst or discontinuous mode operation).

[0178] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform a certain action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B through an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not substantially change the functional relationship between device A and device B.

[0179] Also, in this description, the phrase "based on" means "based at least in part on." Thus, if X is based on Y, then X can be a function of Y and any number of other coefficients.

[0180] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0181] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably and, unless specifically stated to the contrary, are used generally to refer to an interconnection between, or termination of, a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0182] A circuit or device described herein as including certain components may instead be adapted to be combined with those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only the semiconductor elements (e.g., a semiconductor die and / or integrated circuit (IC) package) in a single physical device and may be adapted to be combined with at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, during or after manufacture, to form the described structure.

[0183] While the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted with little or no modification to the remaining circuit elements. For example, field effect transistors ("FETs") (such as n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar transistors (BJTs—e.g., NPN or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Devices may also be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0184] The claims may refer to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate and the current terminals are the drain and source. In the context of a BJT, the control input is the base and the current terminals are the collector and emitter.

[0185] A reference herein to a FET being "on" means that the FET's conduction channel is present and drain current can flow through the FET. A reference herein to a FET being "off" means that the FET's conduction channel is not present and drain current does not flow through the FET. However, an "off" FET may still have current flowing through the transistor's body diode.

[0186] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to the replacement of the component. A component shown as a resistor, unless otherwise noted, generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0187] While some elements of the described examples are included in an integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) incorporated in or on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in or on the same printed circuit board.

[0188] Use of the term "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within ±10 percent of that parameter, or, if the parameter is zero, a reasonable range of values ​​around zero.

[0189] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. It is a device, A controller circuit having first and second control inputs and first and second control outputs, A first measurement signal representing the power converter state is received at the first control input. The second control input receives a control signal representing the duration of the power converter resonance period. Based on the power converter state and the power converter resonance period, the charging interval of the switching cycle, the first dead time interval of the switching cycle following the charging interval, the discharge interval of the switching cycle following the first dead time interval, and the second dead time interval of the switching cycle following the discharge interval are determined. Within the switching cycle, a first drive signal is provided at the first control output, and a second drive signal is provided at the second control output. The controller circuit is configured as follows: Within the aforementioned charging interval, the first drive signal has a first state, and the second drive signal has a second state. Within the first and second dead time intervals, the first and second drive signals have the second state. A device in which, within the discharge interval, the first drive signal has the second state and the second drive signal has the first state.

2. The apparatus according to claim 1, An apparatus in which the first control output is coupled to a first power converter control terminal, the second control output is coupled to a second power converter control terminal, and the first state is the opposite of the second state.

3. The apparatus according to claim 1, A device in which the power converter state is at least one of the following: a zero-voltage switching (ZVS) state of the preceding switching cycle, a non-ZVS state of the preceding switching cycle, the average power converter current of the preceding switching cycle, the peak current within the charging interval of the preceding switching cycle, the peak current within the discharging interval of the preceding switching cycle, the power converter input voltage of the preceding switching cycle, and the power converter output voltage of the preceding switching cycle.

4. The apparatus according to claim 3, The apparatus further comprises a controller circuit configured to determine the second dead time interval based on one-quarter of the resonant period of the power converter.

5. The apparatus according to claim 4, The controller circuit further includes a third control input and a fourth control input, The controller circuit, At the third control input, a second measurement signal representing the power converter input voltage is received. At the fourth control input, a third measurement signal representing the output voltage of the power converter is received. Based on the power converter input voltage and the power converter output voltage, the charging interval, the discharging interval, and the first dead time interval are determined. A device further configured in this way.

6. The apparatus according to claim 5, The controller circuit further includes a fifth control input and a sixth control input, The controller circuit, At the fifth control input, a reference signal representing the target power converter current is received. A second control signal representing the resonant impedance of the power converter is received at the sixth control input. Based on the first, second, and third measurement signals and the reference signal, the operation parameter signal is determined. Based on the operating parameter signal, the second dead time interval, and the power converter resonant impedance, the charging interval, the first dead time interval, and the discharge interval are determined. A device further configured in this way.

7. The apparatus according to claim 6, The aforementioned operating parameter signal indicates a certain period of the switching cycle. The controller circuit, Based on the power converter input voltage and the power converter output voltage, the feedforward component for the period is determined. Based on the power converter state, the feedback component for the period is determined. Based on the aforementioned period, the second dead time interval, the power converter resonance period, and the power converter resonance impedance, the charging interval, the first dead time interval, and the discharge interval are determined. A device further configured in this way.

8. The apparatus according to claim 7, The controller circuit, In response to the power converter state exhibiting the ZVS state, the feedback component is reduced. The feedback component is increased in response to the power converter state exhibiting the non-ZVS state. A device further configured in this way.

9. The apparatus according to claim 8, The controller circuit, The gain coefficient is determined based on whether the power converter state exhibits the ZVS state in a continuous switching cycle. The feedback component is increased or decreased based on the gain coefficient. A device further configured in this way.

10. The apparatus according to claim 7, The aforementioned target power converter current represents the target average power converter current. The controller circuit, In response to the power converter state indicating that the average inductor current exceeds the target power converter current, the feedback component is reduced. In response to the power converter state indicating that the average inductor current is lower than the target power converter current, the feedback component is increased. A device further configured in this way.

11. The apparatus according to claim 6, The aforementioned operating parameter signal indicates the peak current within the charging interval. The controller circuit, Based on the power converter input voltage and the power converter output voltage, the feedforward component of the peak current is determined. Based on the power converter state, the feedback component of the peak current is determined. Based on the peak current, the second dead time interval, the power converter resonance period, and the power converter resonance impedance, the charging interval, the first dead time interval, and the discharge interval are determined. A device further configured in this way.

12. The apparatus according to claim 6, The controller circuit, A feedforward circuit having a first feedforward input coupled to the first control input, a second feedforward input coupled to the second control input, a third feedforward input coupled to the fifth control input, and a feedforward output, A feedback circuit having a first feedback input coupled to the first control input, a second feedback input coupled to the second control input, a third feedback input coupled to the third control input, a fourth feedback input coupled to the fourth control input, a fifth feedback input coupled to the fifth control input, a sixth feedback input coupled to the sixth control input, and a parameter output, A state-plane solver circuit having a solver input coupled to the parameter output and first, second, third, and fourth solver outputs, An angle-to-interval conversion circuit having a first angle input coupled to the first solver output, a second angle input coupled to the second solver output, a third angle input coupled to the third solver output, a fourth angle input coupled to the fourth solver output, and first, second, third, and fourth interval outputs, A PWM generator circuit having a first interval input coupled to the first interval output, a second interval input coupled to the second interval output, a third interval input coupled to the third interval output, a fourth interval input coupled to the fourth interval output, a first pulse width modulation (PWM) output coupled to the first control output, and a second PWM output coupled to the second control output, A device including a device.

13. The apparatus according to claim 12, The feedforward circuit is configured to provide the feedforward component of the operating parameter signal at the feedforward output based on the power converter input voltage, the power converter output voltage, and the reference signal. The aforementioned feedback circuit Based on the power converter state and the reference signal, the feedback component of the operating parameter signal is determined. Based on the combination of the feedforward component and the feedback component, the operating parameter signal is provided. A state plane parameter is provided at the parameter output based on the power converter input voltage, the power converter output voltage, the reference signal, the operating parameter signal having the feedforward component and the feedback component, and at least one of the power converter resonance period and the power converter resonance impedance. It is configured in such a way, The aforementioned state-plane solver circuit, Based on the state plane parameter and a fourth angle equal to 90 degrees, the first angle, the second angle, and the third angle are determined. The first, second, third, and fourth angles are provided in the first, second, third, and fourth solver outputs, respectively. It is configured in such a way, The angle-interval conversion circuit, Based on the first angle and the power converter resonance period, the charging interval is provided at the first interval output. Based on the second angle and the power converter resonance period, the first dead time interval is provided in the second interval output. Based on the third angle and the power converter resonance period, the discharge interval is provided at the third interval output. Based on the fourth angle and the power converter resonance period, the second dead time interval is provided at the fourth interval output. A device configured in such a way.

14. The apparatus according to claim 3, A device in which the ZVS state and the non-ZVS state are the main switches of a power converter.

15. The apparatus according to claim 3, The power converter state indicates one of the following: the ZVS state of the power converter rectifier switch and the non-ZVS state of the power converter rectifier switch. The controller circuit, Based on the power converter resonance period and the power converter state, the adjusted power converter resonance period is determined. Based on the adjusted power converter resonance period, the second dead time interval of the switching cycle is determined. A device further configured in this way.

16. It is a method, Receiving a measurement signal that indicates the power converter status, Receiving a first control signal representing the duration of the power converter's resonant period, Based on the power converter state and the power converter resonance period, the charging interval of the switching cycle, the first dead time interval of the switching cycle following the charging interval, the discharge interval of the switching cycle following the first dead time interval, and the second dead time cycle of the switching cycle following the first dead time interval are determined. To provide a first drive signal and a second drive signal within the aforementioned switching cycle, Includes, Within the aforementioned charging interval, the first drive signal has a first state, and the second drive signal has a second state. Within the first and second dead time intervals, the first and second drive signals have the second state. A method wherein, within the discharge interval, the first drive signal has the second state and the second drive signal has the first state.

17. The method according to claim 16, A method wherein the power converter state is at least one of the following: a zero-voltage switching (ZVS) state of the preceding switching cycle; a non-ZVS state of the preceding switching cycle; the average power converter current of the preceding switching cycle; the peak current within the charging interval of the preceding switching cycle; the peak current within the discharging interval of the preceding switching cycle; the power converter input voltage of the preceding switching cycle; and the power converter output voltage of the preceding switching cycle.

18. The method according to claim 16, A method further comprising determining the second dead time interval based on one-quarter of the resonant period of the power converter.

19. The method according to claim 16, Receiving a reference signal representing the target power converter current, Receiving a second control signal representing the resonant impedance of the power converter, The operation parameter signal is determined based on the power converter state, the power converter input voltage, the power converter output voltage, and the reference signal. Based on the aforementioned operating parameter signal, the second dead time interval, and the power converter resonant impedance, the charging interval, the first dead time interval, and the discharge interval are determined. Methods that further include the above.

20. It is a device, A power converter having a positive input, a negative input, a positive output, and a negative output, comprising: a first switch having a first current terminal; a second switch having a second current terminal; and an inductor coupled to the first current terminal of the first switch and the second current terminal of the second switch, wherein the first switch and the second switch are coupled in series between the positive output and the negative output; A controller circuit, A measurement signal representing the state of the power converter is received, The power converter receives a control signal representing the resonant period, Based on the state of the power converter and the resonance period of the power converter, the charging interval of the switching cycle of the power converter, the first dead time interval of the switching cycle following the charging interval, the discharge interval of the switching cycle following the first dead time interval, and the second dead time cycle of the switching cycle following the discharge interval are determined. Within the switching cycle, a first drive signal is provided to the first switch, and a second drive signal is provided to the second switch. The controller circuit is configured as follows: Includes, Within the aforementioned charging interval, the first drive signal has a first state, and the second drive signal has a second state. Within the first and second dead time intervals, the first and second drive signals have the second state. A device in which, within the discharge interval, the first drive signal has the second state and the second drive signal has the first state.

21. The apparatus according to claim 20, The apparatus further comprises a controller circuit configured to determine the second dead time interval based on one-quarter of the resonant period of the power converter.

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