Single-gate three-dimensional (3D) dynamic random access memory (DRAM) device

Abstract

The memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active area, a cell transistor having a single gate above the active area in the first direction, and a cell capacitor having a bottom electrode layer electrically connected to the active area.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate generally to semiconductor device manufacturing, and more particularly to single-gate three-dimensional dynamic random access memory devices and methods for forming the same. [Background technology]

[0002] Three-dimensional (3D) dynamic random access memory (DRAM) devices pose manufacturability challenges due to their three-dimensional (3D) design and small size. As the number of vertical stacks of memory cells in a 3D DRAM device increases (as chip density increases), the height of each vertical stack needs to be reduced. Typically, a 3D DRAM device includes individual memory cells, each of which includes a field-effect transistor (FET) with a double-gate structure, in which two gates (and word lines connected to the two gates) are disposed on the sides of the active area along the direction of the vertical stack. However, this structure imposes limitations on reducing the vertical height without increasing word line resistance or bit line capacitance.

[0003] Therefore, there is a need for a 3D DRAM device structure, and a method for fabricating such a 3D DRAM device structure, in which the height of each vertical stack of memory cells is reduced without increasing word line resistance or bit line capacitance. Summary of the Invention

[0004] An embodiment of the present disclosure provides a memory cell array including a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active area, a cell transistor having a single gate above the active area in the first direction, and a cell capacitor having a bottom electrode layer electrically connected to the active area.

[0005] An embodiment of the present disclosure provides a method for forming a cell transistor in a semiconductor memory device, the method including: depositing a stacking mold including a plurality of unit stacks, each unit stack including a thicker channel layer, a thicker sacrificial layer on the thicker channel layer, a thinner channel layer on the thicker sacrificial layer, and a thinner sacrificial layer on the thinner channel layer, stacked in a first direction; forming a transistor slit through the stacking mold in the first direction; forming a first recess in the thicker sacrificial layer from a sidewall of the transistor slit and a second recess in the thinner sacrificial layer from a sidewall of the transistor slit; partially filling the first recess and entirely filling the second recess with a first insulator layer from a sidewall of the transistor slit; and removing the first insulator layer on the sidewall of the transistor slit and in the first recess.

[0006] An embodiment of the present disclosure provides a method for forming a cell capacitor in a semiconductor memory device, the method including: depositing a stacking mold including a plurality of unit stacks, each unit stack including a thicker channel layer, a thicker sacrificial layer on the thicker channel layer, a thinner channel layer on the thicker sacrificial layer, and a thinner sacrificial layer on the thinner channel layer, stacked in a first direction; forming a transistor slit through the stacking mold in the first direction; forming a first opening in the thicker sacrificial layer from a sidewall of the capacitor slit and a second opening in the thinner sacrificial layer from a sidewall of the capacitor slit; partially filling the first opening and entirely filling the second opening with a spacer layer from the sidewall of the capacitor slit; and removing the spacer layer on the sidewall of the capacitor slit and in the first opening.

[0007] So that the above-recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments, since the present disclosure may admit of other equally effective embodiments, and therefore should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1A] 1 is a schematic diagram of a portion of a three-dimensional (3D) memory cell array of dynamic random access memory (DRAM) cells, according to one embodiment. [Figure 1B] 1 is a schematic diagram of a DRAM cell. [Figure 2A] 1 is a top view of a portion of a semiconductor structure, according to one embodiment. [Figure 2B] 2B is a cross-sectional view of a portion of the semiconductor structure taken along line BB' shown in FIG. 2A. [Figure 3] FIG. 1 depicts a process flow diagram of a method for forming a cell transistor in a semiconductor structure, according to one embodiment. [Figure 4A] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4B] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4C] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4D] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4E] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4F] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4G] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4H]4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 4I] 4A-4D are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 3. [Figure 5A] FIG. 5 depicts a process flow diagram of a method 500 for forming a cell capacitor in a semiconductor structure formed by the method of FIG. 3. [Figure 5B] FIG. 5 depicts a process flow diagram of a method 500 for forming a cell capacitor in a semiconductor structure formed by the method of FIG. 3. [Figure 6A] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6B] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6C] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6D] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6E] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6F] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6G] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6H] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6I] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6J] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6K] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6L] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6M]6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6N] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6O] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0009] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further specification. A Cartesian coordinate system including an X-axis, a Y-axis, and a Z-axis is used in the figures and the following description. Directions represented by arrows in the figures are assumed to be positive for convenience. It is contemplated that elements disclosed in some embodiments may be beneficially utilized in other implementations without specific specification.

[0010]

[0003] Embodiments described herein provide single-gate three-dimensional (3D) dynamic random access memory (DRAM) devices and methods for forming cell transistors and cell capacitors in single-gate 3D DRAM devices. With a single-gate structure, the word line connected to the gate can be shorter than in a double-gate structure, allowing the height of each vertical stack of memory cells to be reduced without increasing gate resistance or bit line capacitance. Furthermore, in single-gate 3D DRAM devices, the active area can be epitaxially grown, preventing collapse when the height of each vertical stack of memory cells is reduced.

[0004] Embodiments described herein also provide methods for forming single-gate 3D DRAM devices in a two-color stacking mold, for example, made of silicon (Si) and silicon germanium (SiGe).

[0011] FIG. 1A is a schematic diagram of a portion of a three-dimensional (3D) memory cell array 100 of dynamic random access memory (DRAM) cells M (also referred to as "memory cells") in accordance with one or more embodiments of the present disclosure.

[0012] As shown in FIG. 1B, a single memory cell M includes an access transistor Q and a storage capacitor C. The memory cell M stores a data bit by storing a packet of charge (i.e., binary 1) or no charge (i.e., binary 0) on the storage capacitor C. The data bit is input and output by a bit line BL connected to the source / drain of the access transistor Q, and the input is controlled by a word line WL connected to the gate of the access transistor Q.

[0013] The memory cell array 100 includes memory levels L stacked in the Z direction. n (n=1, 2, ...) (a first memory level L1 and a second memory level L2 are shown). n includes a two-dimensional (2D) array of memory cells M. Although only two memory levels are shown in FIG. 1A, memory cell array 100 may include more memory levels L1 stacked above a second memory level L2 in the Z direction. n (n=3, 4, ...).

[0014] In the memory cell array 100, bit lines BL extend vertically in the Z direction, and word lines WL extend horizontally in the X direction. Each bit line BL is linked to the source / drain of an access transistor Q aligned vertically in the Z direction. Each word line WL is linked to the gate of an access transistor aligned horizontally in the Y direction.

[0015] 2A is a top view of a portion of a semiconductor structure 200 that may form a 3D memory cell array, such as a portion of memory cell array 100, in accordance with one or more embodiments of the present disclosure. FIG. 2B is a cross-sectional view of the portion of semiconductor structure 200 along line B-B' shown in FIG. 2A. As shown, three memory levels L1, L2, and L3 are stacked in the Z direction on a substrate 202. Semiconductor structure 200 includes more memory levels L1, L2, and L3 stacked in the Z direction above a third memory level L3. n (n=4, 5, ...) (not shown).

[0016] The semiconductor structure 200 includes a left field effect transistor (FET) module TR L , the left FET module TR in the X direction by the trench 204 L Right FET module separated from TR R The semiconductor structure 200 includes a left FET module TR in the X direction. L The left capacitor module C adjacent to L and the right FET module TR in the X direction R The right capacitor module C adjacent to R and a left FET module TR. L and left capacitor module C L is a number of sections S in the Y direction. Lm (m=1, 2, 3, ...) (one S Lm (shown in Figure 2A). Right FET module TR R and right capacitor module C R is a number of sections S in the Y direction. Rm (m=1, 2, 3, ...) (one S Rm (See Figure 2A). Lm (m=1, 2, 3, ...) for each memory level L n Left FET module TR in (n=1, 2, ...) L and left capacitor module C Lrespectively form an access transistor Q and a storage capacitor C, which together form a memory cell M. Similarly, each section S Rm (m=1, 2, 3, ...) for each memory level L n Right FET module T in (n=1, 2, ...) R and right capacitor module C R respectively form an access transistor Q (also called a "cell transistor") and a storage capacitor C (also called a "cell capacitor"), and the access transistor Q and the storage capacitor C together form a memory cell M. One section S Lm and one section S Rm Although only (m=1, 2, 3, . . . ) sections are shown, more sections may be arranged along the Y direction.

[0017] The term "substrate" as used herein refers to a layer of material that serves as a foundation for subsequent processing operations and includes a surface to be cleaned. The substrate 202 may be a silicon-based material or any suitable insulating or conductive material, as appropriate. The substrate 202 may be crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0018] (Cell transistor Q Ln and Q Rn (called memory level L) n FET module TR in (n=1, 2, 3, ...) L and TR REach includes an active area 206 and a gate 208 above the active area 206 in the Z direction. In the single-gate 3D DRAM structure described herein, the cell transistor Q Ln and Q Rn Each of the active regions 206 has a single gate 208, in contrast to a conventional double-gate 3D DRAM structure. The word line connected to the gate in a single-gate 3D structure can be shorter than in a double-gate structure, thereby reducing the word line resistance. Lower word line resistance leads to faster operating speeds due to reduced resistance-capacitance (RC) delay caused by the word line. Lower bit line capacitance can lower the required cell capacitance, which reduces the capacitor area. The gates 208 are part of a word line layer 210 extending in the Y direction. A cross section of each active region 206 serves as the source / drain of a corresponding access transistor Q. An offset 212 is formed between the gate 208 and the source / drain. The active regions 206 have a gate oxide layer 214 above the active regions 206 in the Z direction. n FET module TR in (n=1, 2, 3, ...) L and TR R (Cell transistor Q Ln and Q Rn ) is the memory level L n+1 A spacer layer 216 disposed directly below and in contact with the active region 206 in the adjacent memory level L n+1 FET module TR L and TR R (Cell transistor Q Ln+1 and Q Rn+1 ) The spacer layer 216 also separates the memory level L n (n=1, 2, 3, ...) adjacent sections (e.g., S Lm and S Lm±1 , S Rm and S Rm±1) to separate the active regions 206. The active regions 206 may each have a width in the Y direction of between about 20 nm and about 60 nm, e.g., about 40 nm, and a thickness in the Z direction of between about 10 nm and about 30 nm, e.g., about 20 nm. The horizontal spacing between adjacent active regions 206 in the Y direction may be between about 140 nm and about 180 nm, e.g., 160 nm, and the vertical spacing between adjacent active regions 206 in the Z direction may be between about 50 nm and about 70 nm, e.g., about 60 nm. The bit lines (BL) may have a width in the Y direction of between about 40 nm and about 120 nm, e.g., about 80 nm, and a thickness in the X direction of between about 40 nm and about 120 nm, e.g., about 80 nm. In some memory array designs, the bit lines (BL) span the trenches 204 and are connected to the left FET modules TR L and right FET module TR R The width of the bit line BL in the X direction is the width of the trench 204. In these designs, the left FET module TR L Upper word line WL and right FET module TR R The upper word line WL addresses two logical word lines and can be controlled separately. In some other memory array designs, two separate bit lines BL, i.e., the left FET module TR, are used. L The upper and right FET modules TR R The bit lines BL are isolated from each other and can be separately connected to different global bit lines.

[0019] The active region 206 may be formed from silicon (Si) or indium gallium zinc oxide (IGZO). The active region 206 may be epitaxially grown, thereby forming the memory level L n(n=1, 2, ...) is reduced in height without collapsing. The word line layer 210 may be formed from tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt), or a conductive oxide or nitride thereof, or any combination thereof. The offset 212 may be formed from silicon nitride (Si3N4). The gate oxide layer 214 may be formed from a high-k dielectric material, such as silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), zirconium oxide (ZrO), vanadium oxide (VO), titanium oxide (TiO), aluminum oxide (AlO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium oxide (NbO), tantalum pentoxide (TaO), or any combination thereof. The spacer layer 216 may be formed from a dielectric material, such as silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), boron-doped silicon oxycarbonitride (SiOCBN), or any combination thereof.

[0020] The semiconductor structure 200 is divided into adjacent sections S Lm (m=1, 2, 3, ...) and S Rm (m=1, 2, 3, ...) (for example, as shown in Figure 2A, section S Lm and S Rm The section S further includes a bit line BL extending in the Z direction within the trench 204. Lm and S Rm The bit lines BL between (m=1, 2, 3, ...) are connected to all memory levels L n (n=1, 2, 3, ...) in Section S Lm In the left FET module TR L The active region 206 in Section S Lm and S RmThe bit lines BL between (m=1, 2, 3, ...) are further connected to all memory levels L n (n=1, 2, 3, ...) in Section S Rm Right FET module TR R The active region 206 is electrically connected to the active region 206 in the semiconductor substrate 200 .

[0021] The bit line BL may be formed from a metal such as tungsten (W), molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof.

[0022] Memory Level L n Left capacitor module C in (n=1, 2, 3, ...) L and right capacitor module C R are the memory levels L n The capacitor 206 includes a bottom electrode layer 218 electrically connected to the active region 206 within the active region 206, a top electrode layer 220 that is grounded (not shown), and a high-k dielectric layer 222 between the bottom electrode layer 218 and the top electrode layer 220. The bottom electrode layer 218 and the top electrode layer 220 may serve as the two plates of a capacitor C. The bottom electrode layer 218 and the top electrode layer 220 may be formed from titanium nitride (TiN), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or a conductive metal nitride, or any combination thereof. The high-k dielectric layer 222 may be formed from a high-k dielectric material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), vanadium oxide (Vo2), titanium oxide (TiO2), tin oxide (SnO2), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium oxide (Nb2O5), tantalum pentoxide (Ta2O5), or any combination thereof.

[0023] The semiconductor structure 200 further includes an insulator layer 224 on the top spacer layer 216. The insulator layer 224 may be formed from silicon oxide (SiO2) and may act as an etch stop layer during the patterning process.

[0024] FIG. 3 depicts a process flow diagram of a method 300 of forming a cell transistor in a semiconductor structure 200. FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, and 4I are cross-sectional views of a portion of the semiconductor structure 200 corresponding to various states of the method 300. It should be understood that FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, and 4I depict only partial schematic views of the semiconductor structure 200, and that the semiconductor structure 200 may include any number of transistor sections and additional materials having the aspects depicted in the figures. Also, it should be noted that while the method depicted in FIG. 3 is described sequentially, other process sequences including one or more operations omitted and / or added and / or rearranged in another desired order are within the scope of the embodiments of the present disclosure provided herein.

[0025] The method 300 begins at block 302, where a mold deposition process is performed to deposit a stacking mold 402 on the substrate 202 and an insulator layer 224 on the stacking mold 402, as shown in FIG. 4A. The insulator layer 224 may be formed of silicon oxide (SiO) and may serve as an etch stop layer during patterning of the stacking mold 402. The stacking mold 402 includes a plurality of unit stacks stacked in the Z direction: a thicker channel layer 402A, a thicker sacrificial layer 402B on the thicker channel layer 402A, a thinner channel layer 402a on the thicker sacrificial layer 402B, and a thinner sacrificial layer 402b on the thinner channel layer 402a. The thicker channel layer 402A and the thinner channel layer 402a may be formed from a first material. The thicker sacrificial layer 402B and the thinner sacrificial layer 402b may be formed from a second material. The etch selectivity of the second material (i.e., the ratio of the etch rate of the second material to the etch rate of the first material) is between about 10:1 and 500:1. Examples of the first material include pure silicon (Si) and indium gallium zinc oxide (IGZO). Examples of the second material include silicon germanium (SiGe) having a germanium (Ge) concentration between about 1% and about 50%, silicon dioxide (SiO2), borophosphosilicate glass (BPSG), borophosphosilicate glass (BSG), and phosphosilicate glass (PSG). The thicker channel layer 402A may each be between about 1.1 times and about 2 times, for example, by 2 times, the thickness t of each of the thinner channel layers 402a. a Thickness greater than t A The thicker sacrificial layers 402B each have a thickness t b Thickness greater than t B The thicker channel layer 402A has a thickness t A and the thickness t of the thicker sacrificial layer 402B B The thickness t of the thinner channel layer 402b can be between about 10 nm and about 40 nm, for example, about 20 nm. a and the thickness t of the thinner sacrificial layer 402bb can be between about 5 nm and about 20 nm, for example, about 10 nm.

[0026] 4A, the number of unit stacks, each consisting of a thicker channel layer 402A, a thicker sacrificial layer 402B, a thinner channel layer 402a, and a thinner sacrificial layer 402b, is 2. However, the number of unit stacks may be greater than 100, for example, about 200.

[0027] The mold deposition process in block 302 may include any suitable deposition process, such as chemical vapor deposition (CVD), an epitaxial deposition process, or the like.

[0028] 4B, a transistor slit patterning process is performed to form transistor slits 404 through the stacking mold 402 and the insulator layer 224 in the Z direction. The transistor slits 404 may have a width in the X direction of between about 50 nm and about 200 nm, for example, about 100 nm, and a depth in the Y direction of between about 50 nm and about 200 nm.

[0029] The transistor slit patterning process in block 304 may include any suitable lithography and etching process, such as photolithography.

[0030] In block 306, a recess formation process is performed to form recesses 406 in the thicker sacrificial layer 402B and recesses 408 in the thinner sacrificial layer 402b in the stacking mold 402 from the sidewalls of the transistor slits 404, as shown in FIG. 4C. The recesses 406 are each formed by a thickness t B The recesses 408 each have a height corresponding to the thickness t b The recesses 406 and 408 may have a width between 50 nm and about 300 nm, for example, about 150 nm.

[0031] The recess formation process in block 306 may include a wet etching process using a hydrofluoric acid (HF)-hydrogen peroxide (H2O2) based mixture, for example, a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) in a volume ratio of 1:2:3.

[0032] In block 308, an insulator formation process is performed to partially fill the recess 408 from the sidewalls of the transistor slit 404 and to entirely fill the recess 408 with an insulator layer 410, as shown in FIG. 4D. The insulator layer 410 is conformally deposited on the exposed surfaces within the transistor slit 404. The insulator layer 410 is formed from silicon oxide (SiO2) and has a thickness of 100 Å. b (the height of each of the recesses 408, for example, about 10 nm) to t B (the thickness of each of the recesses 406, e.g., about 20 nm), such that the recesses 406 are partially filled with the insulator layer 410 and the recesses 408 are entirely filled with the insulator layer 410.

[0033] The insulator formation process in block 308 may include any suitable deposition process, such as atomic layer deposition (ALD).

[0034] In block 310, an insulator removal process is performed to remove the insulator layer 410 on the sidewalls of the transistor slit 404 and within the recess 406, as shown in Figure 4E. The insulator layer 410 in the recess 408 remains.

[0035] The dielectric removal process in block 310 may include an etching process using a hydrofluoric acid (HF) solution.

[0036] In block 312, a channel trimming process is performed to partially remove the portion of the thicker channel layer 402A adjacent to the recess 406 in the Z direction and to fully remove the portion of the thinner channel layer 402a adjacent to the recess 406 in the Z direction, as shown in FIG. 4F. The portions of the thicker channel layer 402A and the thinner channel layer 402a are trimmed to a thickness t of the thin channel layer 402a. a , about 10 nm) from the recess 406. This allows the exposed portions 402A' of the thicker channel layer 402A to be trimmed away from the recess 406 by a thickness equal to the thickness t A from the thickness t of the thinner channel layer 402a a The thickness (t A -t a , for example, between about 5 nm and about 20 nm, for example, about 10 nm), and the extended recesses 406′ each have a thickness t B and the thickness t of the thinner channel layer 402b a Twice the total height (t B +2t a , for example, between about 20 nm and about 60 nm, for example, about 40 nm).

[0037] The channel trimming process in block 312 may include a wet etching process using tetramethyl ammonium hydroxide (TMAH, (CH3)4NOH), which has a high etch selectivity to silicon oxide (SiO2), or a dry etching process such as reactive ion etching (RIE).

[0038] In block 314, a gate oxide formation process is performed to form a gate oxide layer 214 on the exposed portion 402A' of the thicker channel layer 402A, as shown in Figure 4G. The gate oxide layer 214 may have a thickness between about 1 nm and about 5 nm.

[0039] The gate oxide formation process in block 314 may include a suitable thermal oxidation process for oxidizing the surface of the exposed portion 402A′ of the thicker channel layer 402A, such as an enhanced in-situ steam generation (eISSG) process utilizing nitrous oxide (NO) gas, an in-situ steam generation (ISSG) process utilizing H and O gases, or a rapid thermal oxidation (RTO) process utilizing NH and O gases.

[0040] In block 316, as shown in FIG. 4H, a word line layer formation process is performed to form a barrier metal layer 412 on the inner surface of the extended recess 406′ and a word line layer 210 on the exposed surface of the barrier metal layer 412. The barrier metal layer 412 and the word line layer 210 are then recessed from the transistor slit 404. This node isolation process ensures isolation of vertically adjacent access transistors Q. The word line layer 210 may be formed from a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The barrier metal layer 412 may be formed from a barrier metal material, such as titanium nitride (TiN) or tantalum nitride (TaN).

[0041] The wordline layer formation process in block 316 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0042] In block 318, a transistor slit fill process is performed to fill the transistor slits 404 with an insulator layer 414, as shown in FIG. 4I. The insulator layer 414 may be formed from silicon oxide (SiO). As shown, the left FET module TR L and right FET module TR R is formed.

[0043] The transistor slit fill process in block 318 may include any suitable deposition process, such as atomic layer deposition (ALD).

[0044] 5A and 5B depict a process flow diagram of method 500 for forming a cell capacitor in semiconductor structure 200 formed by method 300. FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, 6K, 6L, 6M, 6N, and 6O are cross-sectional views of a portion of semiconductor structure 200 corresponding to various states of method 500. It should be understood that FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, 6K, 6L, 6M, 6N, and 6O depict only partial schematic views of semiconductor structure 200, and that semiconductor structure 200 may include any number of transistor sections and additional materials having the aspects depicted in the figures. Also, it should be noted that although the methods illustrated in FIGS. 5A and 5B are described sequentially, other process sequences that include one or more operations omitted and / or added and / or rearranged in another desired order are within the scope of the embodiments of the present disclosure provided herein.

[0045] The method 500 begins at block 502, where the left FET module TR is turned on, as shown in FIG. 6A. L and right FET module TR R A capacitor slit patterning process is performed to form capacitor slits 602 through both the stacking mold 402 and the insulator layer 224. The capacitor slits 602 may each have a width between about 80 nm and about 200 nm.

[0046] The capacitor slit patterning process in block 502 may include any suitable lithography and etching process, such as photolithography.

[0047] In block 504, a selective sacrificial layer removal process is performed to form an opening 604 in the thicker sacrificial layer 402B and an opening 606 in the thinner sacrificial layer 402b from the sidewalls of the capacitor slit 602, as shown in FIG. 6B. The thicker sacrificial layer 402B is removed, and each opening 604 is removed by the thickness t B The thinner sacrificial layers 402b have been removed, and the openings 604 have been formed with a height corresponding to the thickness t b An opening 606 is formed having a height corresponding to the height of the opening 606 .

[0048] The selective sacrificial layer removal process in block 504 may include a wet etching process using a hydrofluoric acid (HF)-hydrogen peroxide (H2O2) based mixture, for example, a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) in a volume ratio of 1:2:3.

[0049] In block 506, a spacer formation process is performed to partially fill opening 604 and entirely fill opening 606 with spacer layer 216 from the sidewalls of capacitor slit 602, as shown in FIG. 6C. Spacer layer 216 is conformally deposited on the exposed surfaces within capacitor slit 602, as shown in FIG. 6C. Spacer layer 216 is formed from silicon oxide (SiO2) and has a thickness of 100 Å. b (the height of each of the openings 606, for example, about 10 nm) to t B The openings 604 may have a thickness between about half the height of the openings 604 (e.g., about 20 nm), such that the openings 604 are partially filled with the spacer layer 216 and the openings 606 are entirely filled with the spacer layer 216. The spacer layer 216 in the openings 606 merges with the insulator layer 410 formed in the transistor slits 404.

[0050] The spacer formation process in block 506 may include any suitable deposition process, such as atomic layer deposition (ALD).

[0051] At block 508, a spacer removal process is performed to remove the spacer layer 216 on the sidewalls of the capacitor slit 602 and within the opening 604, as shown in Figure 6D. The spacer layer 216 in the opening 606 remains.

[0052] The spacer removal process in block 508 may include an etching process using a hydrofluoric acid (HF) solution.

[0053] In block 510, a channel trimming process is performed to partially remove the portion of the thicker channel layer 402A adjacent to the opening 604 in the Z direction and to fully remove the portion of the thinner channel layer 402a adjacent to the opening 604 in the Z direction from the opening 604, as shown in FIG. 6E. The portions of the thicker channel layer 402A and the thinner channel layer 402a are removed by a thickness t of the thin channel layer 402a. a 4. The remaining portions 402A" of the thicker channel layer 402A are trimmed away from the opening 604 by a thickness equal to the thickness t of the thicker channel layer 402A (for example, about 10 nm). This results in the entire thinner channel layer 402a being removed, and the thicker channel layer 402A being partially removed. The remaining portions 402A" of the thicker channel layer 402A are each trimmed away by a thickness equal to the thickness t of the thicker channel layer 402A. A from the thickness t of the thinner channel layer 402a a The thickness (t A -t a , for example, between about 5 nm and about 20 nm, for example, about 10 nm), and the extended openings 604′ each have a thickness t B and the thickness t of the thinner channel layer 402b a The sum of 2 times (t B +2t a , for example, between about 20 nm and about 60 nm, for example, about 40 nm).

[0054] The channel trimming process in block 510 may include a wet etching process using tetramethyl ammonium hydroxide (TMAH, (CH)NOH), which has a high etch selectivity to silicon oxide (SiO), or a dry etching process such as reactive ion etching (RIE).

[0055] At block 512, an insulator fill process is performed to fill the widened opening 604' with an insulator layer 608, as shown in Figure 6F. The insulator layer 608 may be formed from silicon nitride (Si3N4).

[0056] The dielectric fill process in block 512 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0057] 6G, an insulator removal process is performed to partially remove the insulator layer 608. The remaining insulator layers 212 on the sidewalls of the word line layer 210 (in other words, the inner surfaces of the enlarged openings 604′ opposite the capacitor slits 602 in the X direction) may each have a thickness of between about 5 nm and about 50 nm. The remaining insulator layers 212 on the inner surfaces of the enlarged openings 604′ serve as an offset between the word line layer 210 and the source / drain (S / D) to be formed.

[0058] The dielectric removal process in block 514 may include a dry etching process, such as reactive ion etching (RIE).

[0059] In block 516, a channel trimming process is performed to remove the remaining portions 402A" of the thicker channel layer 402A outside the offset 212 in the enlarged opening 604', as shown in FIG. 6H. The removed portions 402A" of the thicker channel layer 402A each have a thickness t Afrom the thickness t of the thinner channel layer 402a a The thickness (t A -t a , for example, about 10 nm). A portion 402A' of the thicker channel layer 402A adjacent to the word line layer 210 in the Z direction remains. As a result, the widened opening 604' is further widened to an opening 604'' so that the area of ​​the cell capacitor to be formed can be enlarged.

[0060] The channel trimming process in block 516 may include a wet etching process using tetramethyl ammonium hydroxide (TMAH, (CH3)4NOH) or a dry etching process such as reactive ion etching (RIE).

[0061] In block 518, a doping process is performed to dope the portion 402A′ of the thicker channel layer 402A inside the offset 212 with an n-type dopant, such as phosphorus (P) or arsenide (As), from the side 610 adjacent to the enlarged opening 604″, as shown in FIG. 6I.

[0062] The doping process at block 518 may include gas phase doping.

[0063] In block 520, a bottom electrode deposition process is performed to conformally deposit a bottom electrode layer 218 on the exposed surfaces in the enlarged opening 604'', as shown in FIG. 6J. The bottom electrode layer 218 may be formed from titanium nitride (TiN) and may have a thickness of between about 1 nm and 10 nm.

[0064] The bottom electrode deposition process in block 520 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0065] At block 522, a capacitor high-k dielectric deposition process is performed to conformally deposit a high-k dielectric layer 222 on the exposed surface of the bottom electrode layer 218 in the enlarged opening 604'' and on the sidewalls of the capacitor slit 602, as shown in FIG. 6K. The high-k dielectric layer 222 may be formed from a high-k dielectric material such as hafnium oxide (HfO), zirconium dioxide (ZrO), aluminum oxide (AlO), or any combination thereof.

[0066] The capacitor high-k dielectric deposition process in block 522 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0067] In block 524, a top electrode deposition process is performed to conformally deposit a top electrode layer 220 in the enlarged opening 604'' and on the exposed surface of the high-k dielectric layer 222 in the capacitor slit 602, as shown in FIG. 6L. The top electrode layer 220 may be formed from titanium nitride (TiN).

[0068] The top electrode deposition process in block 524 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0069] After the deposition process, the semiconductor structure 200 may be planarized through the use of a chemical mechanical planarization (CMP) process.

[0070] In block 526, a bitline (BL) patterning process is performed to form BL openings 612, as shown in FIG. 6M.

[0071] The BL patterning process in block 524 may include any suitable lithography and etching process, such as photolithography.

[0072] In block 526, a doping process is performed to dope portion 402A' of thicker channel layer 402A inside offset 212 with an n-type dopant, such as phosphorus (P) or arsenide (As), from side 614 adjacent to BL opening 612, as shown in FIG. 6N. Doped portion 402A' of thicker channel layer 402A serves as active region 206 shown in FIG. 2B. Sides 610 and 614 of active region 206 serve as source / drains.

[0073] The doping process at block 526 may include gas phase doping.

[0074] In block 528, as shown in FIG. 6O, a bit line metal formation process is performed to form a barrier metal layer 616 on the inner surface of the BL opening 612 and a bit line metal layer 618 on the exposed surface of the barrier metal layer 616. The bit line metal layer 618 may be formed from a contact plug metal material such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The barrier metal layer 616 may be formed from a barrier metal material that is titanium nitride (TiN) or tantalum nitride (TaN). The bit line metal layer 618 and the barrier metal layer 616 serve as the bit line BL shown in FIGS. 1A and 1B.

[0075] The bitline metal formation process in block 528 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0076] After the deposition process, the semiconductor structure 200 may be planarized through the use of a chemical mechanical planarization (CMP) process.

[0077]

[0003] Embodiments described herein provide a single-gate three-dimensional (3D) dynamic random access memory (DRAM) device, for example, a method for forming a cell transistor and a cell capacitor in a single-gate 3D DRAM device in a two-color stacking mold made of silicon (Si) and silicon germanium (SiGe). With a single-gate structure, the word line connected to the gate can be shorter than in a double-gate structure, thereby allowing the height of each vertical stack of memory cells to be reduced without increasing gate resistance or bit line capacitance. Furthermore, in a single-gate 3D DRAM device, the active area can be epitaxially grown, thereby preventing collapse when the height of each vertical stack of memory cells is reduced.

[0078] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: an active region; a cell transistor having a single gate above the active region in the first direction; a cell capacitor having a bottom electrode layer electrically connected to the active region; Multiple memory levels, A memory cell array comprising:

2. each of the plurality of memory levels a word line layer extending from the single gate of the cell transistor in a second direction perpendicular to the first direction; The memory cell array of claim 1 further comprising:

3. the active area of ​​each of the plurality of memory levels overlies and is in contact with a spacer in the first direction; The memory cell array of claim 1 .

4. the active region comprises silicon (Si) or indium gallium zinc oxide (IGZO); The memory cell array of claim 1 .

5. the active region is epitaxially grown; The memory cell array of claim 1 .

6. a bit line in contact with each of the plurality of memory levels, the bit line extending in the first direction; The memory cell array of claim 1 further comprising:

7. 1. A method of forming a cell transistor in a semiconductor memory device, comprising: depositing a stacking mold comprising a plurality of unit stacks, each unit stack comprising: a thicker channel layer; a thicker sacrificial layer on the thicker channel layer; a thinner channel layer on the thicker sacrificial layer; and a thinner sacrificial layer on the thinner channel layer, stacked in a first direction; forming a transistor slit through the stacking mold in the first direction; forming a first recess in the thicker sacrificial layer and a second recess in the thinner sacrificial layer from a sidewall of the transistor slit; partially filling the first recess and entirely filling the second recess with a first insulating layer from the sidewall of the transistor slit; removing the first insulator layer on the sidewalls of the transistor slit and within the first recess; A method comprising:

8. each of the thicker channel layers being between 1.1 and 2 times thicker than each of the thinner channel layers; each of the thicker sacrificial layers being between 1.1 and 2 times thicker than each of the thinner sacrificial layers; The method of claim 7.

9. the thicker channel layer and the thinner channel layer each comprise silicon or indium gallium zinc oxide (IGZO); The thicker sacrificial layer and the thinner sacrificial layer are made of silicon germanium (SiGe), silicon oxide (SiO ２ ), borophosphosilicate glass (BPSG), borophosphosilicate glass (BSG), or phosphosilicate glass (PSG), The method of claim 7.

10. the first insulator layer having a thickness between 1 / 2 the thickness of each of the thinner sacrificial layers and 1 / 2 the thickness of each of the thicker sacrificial layers; The method of claim 7.

11. partially removing a portion of the thicker channel layer adjacent to the first recess in the first direction and fully removing a portion of the thinner channel layer adjacent to the first recess in the first direction; forming a gate oxide layer on the exposed portion of the thicker channel layer; forming a barrier metal layer on an inner surface of the first recess and a word line layer on an exposed surface of the barrier metal layer; filling the transistor slits with a second insulating layer; The method of claim 7 further comprising:

12. The method of claim 7 , wherein the depositing the stacking mold comprises an epitaxial deposition process.

13. 1. A method of forming a cell capacitor in a semiconductor memory device, comprising: depositing a stacking mold comprising a plurality of unit stacks, each unit stack comprising: a thicker channel layer; a thicker sacrificial layer on the thicker channel layer; a thinner channel layer on the thicker sacrificial layer; and a thinner sacrificial layer on the thinner channel layer, stacked in a first direction; forming a transistor slit through the stacking mold in the first direction; forming a first opening in the thicker sacrificial layer and a second opening in the thinner sacrificial layer from a sidewall of the capacitor slit; partially filling the first opening and entirely filling the second opening with a spacer layer from the sidewall of the capacitor slit; removing the spacer layer on the sidewalls of the capacitor slit and within the first opening; A method comprising:

14. each of the thicker channel layers being between 1.1 and 2 times thicker than each of the thinner channel layers; each of the thicker sacrificial layers being between 1.1 and 2 times thicker than each of the thinner sacrificial layers; The method of claim 13.

15. the thicker channel layer and the thinner channel layer each comprise silicon or indium gallium zinc oxide (IGZO); The thicker sacrificial layer and the thinner sacrificial layer are made of silicon germanium (SiGe), silicon oxide (SiO ２ ), borophosphosilicate glass (BPSG), borophosphosilicate glass (BSG), or phosphosilicate glass (PSG), The method of claim 13.

16. the spacer layer has a thickness between 1 / 2 the thickness of each of the thinner sacrificial layers and 1 / 2 the thickness of each of the thicker sacrificial layers; The method of claim 13.

17. performing a first channel trimming process comprising partially removing, from the first opening, a portion of the thicker channel layer adjacent to the first opening in the first direction, and completely removing, from the first opening, a portion of the thinner channel layer adjacent to the first opening in the first direction; forming an offset on an inner surface of the first opening opposite the capacitor slit in a second direction orthogonal to the first direction; removing a remaining portion of the thicker channel layer adjacent the first opening in the first direction; and The method of claim 13 further comprising:

18. conformally depositing a bottom electrode layer on the exposed surface in the first opening; conformally depositing a high-k dielectric layer on the exposed surface of the bottom electrode layer in the first opening and on the sidewalls of the capacitor slit; conformally depositing a top electrode layer on the exposed surface of the high-k dielectric layer in the first opening and in the capacitor slit; 20. The method of claim 17, further comprising:

19. forming a bit line opening; forming a barrier metal layer on an inner surface of the bit line opening and a bit line metal layer on an exposed surface of the barrier metal layer; 20. The method of claim 18, further comprising:

20. doping the remaining portion of the thicker channel layer adjacent to the first opening in the first direction from the first opening after performing the first channel trimming process; doping the remaining portion of the thicker channel layer adjacent to the first opening in the first direction from the bit line opening after forming the bit line opening; 20. The method of claim 19 further comprising:

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