Vertical charge transfer image sensor and method of manufacturing the same

Abstract

The present invention relates to a vertical charge transfer pixel sensor (VPS) and a method for fabricating a VPS. In a VPS, shallow trench isolation (STI) and deep trench isolation (DTI) are formed on one side of a semiconductor substrate. Each DTI includes a deep trench extending through the semiconductor substrate, a trench electrode filled within the deep trench, and a first isolation dielectric. The DTI defines multiple substrate cells within a pixel area. Each substrate cell includes a photo-sensing region and a charge readout region separated from each other by one STI. At least one substrate electrode is formed on the other side of the semiconductor substrate, contacting each substrate cell and separated from the trench electrode. The DTI provides physical inter-pixel isolation, which ensures good photoelectric conversion efficiency, effectively avoids inter-pixel crosstalk, and facilitates pixel miniaturization. Furthermore, the trench electrode provides an operable electrode terminal for the VPS, which allows for various operating modes.

Description

[Technical Field]

[0001] The present invention relates to light sensing technology, and more particularly to vertical charge transfer pixel sensors (VPS) and methods for fabricating VPS. [Background technology]

[0002] A vertical charge transfer pixel sensor (VPS) is an image sensor that utilizes a semiconductor substrate and floating gate transistors to provide imaging capabilities. Referring to FIGS. 1 and 2, each VPS pixel includes a semiconductor substrate 10 having a photo-sensing region 11 and a charge readout region 12, which are separated from each other by shallow trench isolation (STI). A gate dielectric layer 13, a floating gate FG, an inter-gate dielectric layer 14, and a control gate CG are formed on the front side of the semiconductor substrate 10, all of which extend from the photo-sensing region 11 to the charge readout region 12. A source region S and a drain region D are formed in the charge readout region 12 on either side of the control gate (CG). Thus, each pixel includes a MOS capacitor on the photo-sensing region 11 and a readout transistor formed in the charge readout region 12, which are connected to each other. During VPS operation, light enters the semiconductor substrate 10 from its backside and generates photoelectrons. The photoelectrons then migrate toward the control gate CG under the action of an appropriate bias voltage and collect on the underside of the gate dielectric layer 13 above the photosensitive region 11, or cross the potential barrier into the floating gate (FG). This induces a drain current change and / or a threshold voltage change in the readout transistor. Such changes can be detected and used for photoelectric sensing and imaging.

[0003] Compared to conventional photodiode-based semiconductor sensors (e.g., CMOS image sensors), VPSs have a higher full-well charge capacity for a given pixel size, thus offering a higher signal-to-noise ratio and significant advantages in pixel miniaturization.

[0004] Currently, the most difficult aspect of VPS-based pixel scaling is how to ensure the desired photoelectric conversion efficiency while avoiding pixel-to-pixel crosstalk. Summary of the Invention

[0005] The present invention provides a vertical charge transfer pixel sensor (VPS) having a desired photoelectric conversion efficiency and no pixel-to-pixel crosstalk, and a method for manufacturing such a VPS.

[0006] In one aspect, the present invention provides a method for producing a pharmaceutical composition comprising: a first doped semiconductor substrate having a pixel area and a peripheral area; shallow trench isolations and deep trench isolations formed on a first side of the semiconductor substrate, each of the deep trench isolations including a deep trench extending through the semiconductor substrate, a trench electrode and a first isolation dielectric filled in the deep trench, the first isolation dielectric insulating the trench electrode from the semiconductor substrate, and the deep trench isolations defining a plurality of substrate cells in a pixel area, each of the substrate cells including a photo-sensing region and a charge readout region separated from each other by one of the shallow trench isolations; a gate dielectric layer formed on a surface of each substrate cell and extending from the light sensing region to the charge readout region, a floating gate, an inter-gate dielectric layer and a control gate, and source and drain regions formed on either side of each control gate in each charge readout region; at least one substrate electrode formed on a second side of the semiconductor substrate, the at least one substrate electrode contacting two adjacent substrate cells and separated from the corresponding trench electrode; We provide VPS, including

[0007] Optionally, the semiconductor substrate may further have a trench electrode pick-up area around the pixel area, and the trench electrode in the deep trench extends from the pixel area to the trench electrode pick-up area and extends from the bottom to the top of the deep trench within the trench electrode pick-up area.

[0008] Optionally, the VPS may further include a trench electrode connection formed in the trench electrode pickup area and covering the trench electrode.

[0009] Optionally, in the pixel area, the first isolation dielectric filled in the deep trench may include a linear oxide layer and a deep trench filling layer, where the linear oxide layer is interposed between the trench electrode and the semiconductor substrate, and the deep trench filling layer covers the trench electrode and is located on top of the deep trench.

[0010] Optionally, at least one substrate electrode may be formed on a second side of the semiconductor substrate corresponding to the deep trench in the pixel area, and a second isolation dielectric is interposed between the at least one substrate electrode and the trench electrode.

[0011] Optionally, the second isolation dielectric may include a high-k material.

[0012] Optionally, the control gates formed over each substrate cell may be connected to form a plurality of word lines, each word line extending across multiple ones of the substrate cells.

[0013] In another aspect, the present invention provides a method for producing a VPS, comprising the steps of: providing a semiconductor substrate having a pixel area; forming shallow trench isolations and deep trench isolations on a first side of a semiconductor substrate, each of the deep trench isolations including a deep trench extending through the semiconductor substrate, a trench electrode and a first isolation dielectric filled in the deep trench, the first isolation dielectric insulating the trench electrode from the semiconductor substrate, and the deep trench isolations defining a plurality of substrate cells in a pixel area, each of the substrate cells including a photo-sensing region and a charge readout region separated from each other by one of the shallow trench isolations; forming a gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate on a surface of each substrate cell, the gate dielectric layer extending from the photo-sensing region to the charge readout region, and forming source and drain regions on either side of each control gate in each charge readout region; thinning the semiconductor substrate from a second side of the semiconductor substrate until the deep trench isolation is exposed, and forming at least one substrate electrode on the second side contacting two adjacent substrate cells and being separated from the corresponding trench electrode; The present invention provides a method comprising:

[0014] Optionally, forming shallow trench isolation and deep trench isolation formed on the first side of the semiconductor substrate comprises: forming a pad oxide layer and a first hard mask layer on a surface of a semiconductor substrate, and forming shallow trench isolation extending through the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate; forming a second hard mask layer overlying the first hard mask layer and the shallow trench isolation; forming a deep trench extending through the second hard mask layer, the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate; forming a linear oxide layer and a conductive layer in the deep trench, the linear oxide layer covering the semiconductor substrate exposed in the deep trench, the conductive layer covering the linear oxide layer and filling the deep trench, and a top surface of the conductive layer being higher than a surface of the semiconductor substrate; etching back the conductive layer in the pixel area until a top surface of the conductive layer is lowered below a surface of the semiconductor substrate, forming a space at the top of the deep trench in the pixel area, and a remaining portion of the conductive layer forms a trench electrode; forming a deep trench fill layer in the space, the linear oxide layer and the deep trench fill layer constituting a first isolation dielectric; may include:

[0015] Optionally, the semiconductor substrate may further have a trench electrode pick-up area around the pixel area, and the trench electrode in the deep trench extends from the pixel area to the trench electrode pick-up area and extends from the bottom to the top of the deep trench within the trench electrode pick-up area.

[0016] Optionally, forming at least one substrate electrode comprises: forming a first trench in a deep trench isolation exposed on a second side of the semiconductor substrate, wherein a trench electrode and a substrate cell around the trench electrode are exposed in the first trench; forming a second isolation dielectric on the second side, the second isolation dielectric filling the first trench and covering a surface of the substrate cell; forming a second trench whose bottom is located around the top of the first trench, wherein a substrate cell around the deep trench isolation is exposed at a side of the second trench and the trench electrode is covered by a second isolation dielectric; filling the second trench with a conductive material to form at least one substrate electrode; may include:

[0017] The VPS and method of the present invention have the following advantages: First, deep trench isolation extends through the semiconductor substrate and defines multiple substrate cells within the pixel area, each corresponding to a VPS pixel. In this way, deep trench isolation provides physical separation between pixels, ensuring good photoelectric conversion efficiency of the VPS, effectively avoiding pixel-to-pixel crosstalk, and facilitating pixel miniaturization.

[0018] Second, at least one substrate electrode is formed on the second side of the semiconductor substrate (ie, the side away from the control gate), leaving a larger area for the control gate and further facilitating pixel miniaturization.

[0019] Third, deep trench isolation includes a deep trench extending through a semiconductor substrate, a trench electrode, and a first isolation dielectric filled within the deep trench. The first isolation dielectric separates the trench electrode from the semiconductor substrate. The trench electrode provides an operable electrode terminal for the VPS, which can cooperate with other electrode terminals of the sensor to support various operational modes.

[0020] Fourth, by connecting the trench electrode to the substrate electrode and applying a positive bias voltage for photodetection between the substrate electrode and the trench electrode, the potential barrier at the interface between the deep trench isolation and the substrate cell can be increased. This reduces the probability of photoelectron capture at the interface, contributing to improved photoelectric conversion efficiency and helping to alleviate dark current and white pixel issues. Furthermore, the positive bias voltage can be flexibly adjusted, allowing the isolation dielectric between the trench electrode and the substrate cell to be made of an inexpensive low-k material.

[0021] Fifth, after the light sensing and charge readout cycles are completed, a negative bias voltage can be applied between the substrate electrode and the trench electrode to reset the sensor and release the charges trapped around the deep trench isolation boundary, which helps reduce background noise in the next light sensing and charge readout cycle. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a schematic plan view of a VPS pixel. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line XX′ in FIG. [Figure 3] FIG. 1 is a schematic plan view of a VPS according to one embodiment of the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view of a portion taken along line AA′ in FIG. [Figure 5] 1 is a flowchart of a method for manufacturing a VPS according to one embodiment of the present invention. [Figure 6A] 1A-1D are schematic cross-sectional views of structures resulting from steps in a method of manufacturing a VPS according to one embodiment of the present invention. [Figure 6B] 3A-3C are schematic cross-sectional views of alternative structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6C] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6D] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6E] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6F] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6G] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6H]10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6I-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6I-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6J-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6J-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6K-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6K-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6L-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6L-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6M-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6M-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6N-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6N-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6O-1]10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6O-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6P-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6P-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6Q-1] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6Q-2] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6Q-3] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6R] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6S] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6T] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6U] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. [Figure 6V] 10A-10C are schematic cross-sectional views of yet other structures resulting from steps in a method of fabricating a VPS according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] A vertical charge transfer pixel sensor according to a specific embodiment of the present invention and a method for manufacturing the same will be described in more detail below with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are provided in a highly simplified format, not necessarily drawn to scale, solely for the purpose of helping to explain the disclosed embodiments in a more convenient and clear manner. The embodiments of the present invention should not be construed as being limited to the specific shapes of the regions shown herein, but should be construed to include deviations in shape resulting, for example, from manufacturing. For clarity, similar elements will generally be labeled with similar reference numerals throughout the drawings that help explain the embodiments disclosed herein, and repeated descriptions thereof will be omitted.

[0024] Referring to FIGS. 3 and 4, an embodiment of the present invention is a vertical charge transfer pixel sensor (hereinafter referred to as a "VPS sensor"), comprising: a semiconductor substrate 100 having a pixel area A1; shallow trench isolation STI and deep trench isolation DTI formed on one side of a semiconductor substrate 100, each deep trench isolation DTI including a deep trench DT extending through the semiconductor substrate 100, a trench electrode E1 and a first isolation dielectric (e.g., a linear oxide layer 105 and a deep trench filling layer 107, in particular) filled in the deep trench DT, the first isolation dielectric insulating the trench electrode E1 from the semiconductor substrate 100, and the deep trench isolation DTI defining a plurality of substrate cells 110 within a pixel area A1, each substrate cell 110 including a photo-sensing region 110a and a charge readout region 110b separated from each other by one of the shallow trench isolation STIs; a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 111 and a control gate CG formed on the surface of each substrate cell 110 and extending from the photo-sensing region 110a to the charge readout region 110b, and a source region S and a drain region D formed on either side of each control gate CG in each charge readout region 110b; a substrate electrode E2 formed on the other side of the semiconductor substrate 100, the substrate electrode E2 contacting each substrate cell 110 and being separated from the trench electrode E1; The present invention includes a vertical charge transfer pixel sensor including:

[0025] The semiconductor substrate 100 may be any of a variety of suitable semiconductor substrates known in the art and may be made of materials including silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, etc. For example, the semiconductor substrate 100 may be doped with ions. In a particular example, the semiconductor substrate may be a silicon substrate doped with boron or boron difluoride. In the former case, the doped boron ions may be present in a concentration of, for example, 1×10 12 / cm 2 ~2×10 12 / cm 2 The semiconductor substrate 100 may have a p-body region (PW, not shown) formed in the charge readout region 110b, and the source region S and drain region D may be, for example, n-doped areas formed on top of the p-body region. Note that although the floating gate transistor in the VPS pixel is described herein primarily as an n-type device by way of example, it will be understood that the floating gate transistor may also be a p-type device, in which case an n-body region is formed in the charge readout region 110b, and the source region S and drain region D are p-doped areas.

[0026] Optionally, the plurality of substrate cells 110 in the pixel area A1 may be arranged in an array, and each of the plurality of substrate cells 110 corresponds to one pixel, including a MOS capacitor formed on the photo-sensing region 110a of the substrate cell 110 and a readout transistor formed in the charge readout region 110b of the substrate cell 110.

[0027] 3, in this embodiment, the semiconductor substrate 100 further includes a peripheral area around the pixel area A1, in which some circuitry of the VPS may be formed. However, the present invention is not so limited, and in some embodiments, the peripheral area may be provided by a separate substrate that may be stacked and connected to the semiconductor substrate 100.

[0028] In this embodiment, a portion of the peripheral area is used as the trench electrode pickup area A2, and a connection with the trench electrode E1 is formed. The deep trench DT and the trench electrode E1 therein extend from the pixel area A1 to the trench electrode pickup area A2. In the pixel area A1, the trench electrode E1 is below the lower surface of the gate dielectric layer 108 and is covered by the deep trench fill layer 107. In the trench electrode pickup area A2, the trench electrode E1 extends from the bottom to the top of the deep trench DT and optionally protrudes beyond the surface of the semiconductor substrate 100 (see FIG. 6Q-2). Optionally, the VPS may further include a trench electrode connection E1-T, which is formed in the trench electrode pickup area A2 to cover the trench electrode E1, and which is electrically connected to the trench electrode E1.

[0029] In some embodiments, the substrate electrode E2 may be formed on the other side of the semiconductor substrate 100 corresponding to the deep trench DT in the pixel area A1, and a second isolation dielectric 113 may be provided between the substrate electrode E2 and the trench electrode E1.

[0030] In some embodiments, the second isolation dielectric 113 may include a high-k material (dielectric constant greater than 3.9). Optionally, the second isolation dielectric 113 may further cover the edge of the other side of the semiconductor substrate 100.

[0031] In some embodiments, the control gates CG above each substrate cell 110 may be connected to form multiple word lines WL, each of which extends across several of the substrate cells 110.

[0032] Thus, each VPS pixel includes a substrate cell 110, a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 111, and a control gate CG, all formed on the substrate cell 110, and a source region S and a drain region D formed in the charge readout region 110b on either side of the control gate CG. The photo-sensing region 110a, and the gate dielectric layer 108, floating gate FG, inter-gate dielectric layer 111, and control gate CG thereon form a MOS capacitor for light sensing, and the source region S and drain region D in the charge readout region 110b, and the gate dielectric layer 108, floating gate FG, inter-gate dielectric layer 111, and control gate CG on the charge readout region 110b form a readout transistor for charge readout.

[0033] As an example, the VPS may implement the following process to achieve light sensing and readout.

[0034] First, a photo-sensing operation is performed. A negative bias voltage (e.g., −3 V) is applied to the semiconductor substrate 100, and a positive bias voltage is applied to the control gate CG to form a continuous depletion region in the semiconductor substrate 100. When photons enter the depletion region from the side of the semiconductor substrate 100 away from the control gate CG, the photons are excited into photoelectrons. The photoelectrons are then driven by the electric field to collect on the underside of the gate dielectric layer 108 above the photo-sensing region 110a or cross the potential barrier to enter the floating gate FG. Because the photo-sensing region 110a and the floating gate FG above the charge readout region 110b are continuous, any change in the floating gate FG above the charge readout region 110b will then cause a drain current change and / or a threshold voltage change in the readout transistor.

[0035] A charge read operation follows, in which the source region S and the semiconductor substrate 100 are grounded (0V) and a positive bias voltage (e.g., greater than 0V and less than 3V) is applied to the drain region D, allowing detection of drain current changes or threshold voltage changes of the read transistor.

[0036] A reset operation is then performed, applying a negative bias voltage to the control gate CG and a positive bias voltage (e.g., greater than 0 V and less than 3 V) to the semiconductor substrate 100 and the source region S to emit photoelectrons onto the underside of the gate dielectric layer 108 or into the floating gate FG.

[0037] According to embodiments of the present invention, trench electrode E1 provides an operable electrode terminal for the VPS, which can cooperate with other electrode terminals of the sensor (e.g., electrode terminals individually connected to the control gate, source and drain regions, and substrate electrode) to enable various operational modes. In some embodiments, trench electrode E1 can function as a connecting terminal for substrate electrode E2, and a positive bias voltage can be applied between substrate electrode E2 and trench electrode E1 to increase the potential barrier at the interface between the deep trench isolation DTI and substrate cell 110. This can reduce the probability of photoelectrons being trapped at the interface, contributing to improved photoelectric conversion efficiency and helping to alleviate dark current and white pixel issues. Furthermore, following a photo-sensing and charge readout cycle, a negative bias voltage can be applied between the substrate electrode and trench electrode to reset the sensor and release charges trapped around the deep trench isolation boundary. This helps reduce background noise during subsequent photo-sensing and charge readout operations.

[0038] Embodiments of the present invention also include methods by which the above VPS can be obtained, which are described below with reference to Figures 5 and 6A-6V.

[0039] FIG. 6A is a schematic cross-sectional view of a structure resulting from forming a pad oxide layer and a first hard mask layer on a semiconductor substrate. The cross-sectional view of FIG. 6A is, for example, a cross-sectional view taken along line AA′ in the plan view of FIG. 3. Referring to FIGS. 3 and 5 (Step S1) and FIG. 6A, a semiconductor substrate 100 of a first doping type is provided, and the semiconductor substrate 100 has a pixel area A1. The semiconductor substrate 100 is, for example, a p-doped (p−) silicon substrate. A photo-sensing pixel is formed in the pixel area A1. The semiconductor substrate 100 may include a trench electrode pickup area A2 around the pixel area A1.

[0040] 5, in step S2, shallow trench isolation STI and deep trench isolation DTI are then formed on one side of the semiconductor substrate 100. In particular, this can be achieved by performing the following process.

[0041] 6A, a pad oxide layer 101 and a first hard mask layer 102 are formed on a surface of a semiconductor substrate 100. For example, the pad oxide layer 101 includes a silicon oxide having a given thickness. For example, the first hard mask layer 102 includes a silicon nitride having a given thickness.

[0042] FIG. 6B is a schematic cross-sectional view of a structure resulting from forming a shallow trench in a semiconductor substrate. As shown in FIG. 6B, the location where the shallow trench isolation STI will be formed can be defined using a photolithography process. One or more etching processes can then be performed to form a shallow trench ST, which extends through the first hard mask layer 102, the pad oxide layer 101, and a portion of the semiconductor substrate 100. The shallow trench ST can have a depth D1 of approximately 100 nm to 400 nm, for example, approximately 200 nm.

[0043] 6C is a schematic cross-sectional view of a structure resulting from forming a shallow trench fill layer. As shown in FIG. 6C, an oxide layer (not shown) is formed on the inner surface of the shallow trench ST, and then a shallow trench fill layer 103 is deposited. The shallow trench fill layer 103 fills the shallow trench ST and is deposited to a certain thickness above the first hard mask layer 102. The shallow trench fill layer 103 may include silicon oxide or another isolation dielectric. Optionally, to reduce the risk of electrical leakage in the active area of ​​the semiconductor substrate 100 subsequently defined by the shallow trench ST as a result of removing the first hard mask layer 102 and the pad oxide layer 101, the portion of the shallow trench ST formed in the first hard mask layer 102 and the pad oxide layer 101 may be widened before the oxide layer is formed on the inner surface of the shallow trench ST.

[0044] 6D is a schematic cross-sectional view of the structure resulting from planarizing the shallow trench fill layer 103. As shown in FIG. 6D, the shallow trench fill layer 103 is planarized (e.g., by chemical mechanical polishing (CMP)) to expose the top surface of the first hard mask layer 102. The remaining portion of the shallow trench fill layer 103 fills the shallow trench ST, forming the shallow trench isolation STI.

[0045] FIG. 6E is a schematic cross-sectional view of the structure resulting from forming the second hard mask layer. As shown in FIG. 6E, a second hard mask layer 104 (e.g., silicon nitride) is formed, covering the shallow trench isolation STI and the first hard mask layer 102. The combined thickness of the first hard mask layer 102 and the second hard mask layer 104 is approximately 2000 Å. A photolithography process is then performed to define the location where the deep trench isolation DTI will be formed. One or more etching processes are then performed to form a deep trench DT extending through the second hard mask layer 104, the first hard mask layer 102, the pad oxide layer 101, and a portion of the semiconductor substrate 100. The deep trench DT has a depth D2 that is deeper than the depth D1 of the shallow trench ST described above. For example, the depth D2 of the deep trench DT can be in the range of 1.5 μm to 2.5 μm. Furthermore, the depth D2 may be greater than 1.8 μm, for example, about 2 μm. The deep trench DT may have an opening width D3 of, for example, about 80 nm.

[0046] The cross-sectional view of FIG. 6E may be, for example, a cross-sectional view taken along line AA′ in the plan view of FIG. 3 . Referring to FIGS. 3 and 6E , a portion of a deep trench DT is formed in a pixel area A1 of a semiconductor substrate 100 to partition the pixel area A1 into a plurality of substrate cells 110. A portion of a shallow trench isolation STI is formed in each substrate cell 110. Each substrate cell 110 includes a photo-sensing region 110a and a charge readout region 110b, which are separated from each other by the shallow trench isolation STI. The deep trench DT extends from the pixel area A1 into the trench electrode pickup area A2. For example, as shown in FIG. 3 , the deep trench DT in the trench electrode pickup area A2 may have a width greater than the deep trench DT in the pixel area A1. One or more trench electrode pickup areas A2 may be present on each side of the pixel area A1.

[0047] FIG. 6F is a schematic cross-sectional view of the structure resulting from forming the linear oxide layer. As shown in FIG. 6F, a linear oxide layer 105 is formed on the inner surface of the deep trench DT, and the linear oxide layer 105 covers the semiconductor substrate 100 exposed in the deep trench DT. Prior to this, the portions of the deep trench DT within the second hard mask layer 104, the first hard mask layer 102, and the pad oxide layer 101 may be widened. An annealing process may then be performed to repair lattice defects in the semiconductor substrate 100 that may have been introduced by the formation of the deep trench DT. The annealing process may be performed, for example, at a temperature of approximately 1100° C.

[0048] FIG. 6G is a schematic cross-sectional view of the structure resulting from forming the conductive layer. As shown in FIG. 6G, a conductive material is deposited in the deep trenches DT and the second hard mask layer 104 to form the conductive layer 106. The conductive layer 106 fills the deep trenches DT and is deposited above the second hard mask layer 104 to a certain thickness. The conductive layer 106 may be formed of a conductive material with good light-shielding properties. Optionally, the conductive layer 106 may include one or a combination of two or more of tungsten, tungsten silicide, titanium, titanium nitride, and doped polysilicon. In this embodiment, the conductive layer 106 may be, for example, doped polysilicon. After deposition is completed, the doped polysilicon may be annealed and recrystallized to an appropriate grain size.

[0049] 6H is a schematic cross-sectional view of the structure resulting from planarizing the conductive layer. As shown in FIG. 6H, the conductive layer 106 is planarized (e.g., by CMP) to expose the top surface of the second hard mask layer 104. The remaining portion of the conductive layer 106 fills the deep trench DT.

[0050] Next, an etch-back process is performed on the conductive layer 106 in the pixel area A1, which progresses to a depth below the surface of the semiconductor substrate 100, forming a space above the deep trench DT in the pixel area A1. FIGS. 6I-1 and 6I-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from etching back the conductive layer. Specifically, FIG. 6I-1 is a cross-sectional view taken along line AA' in the plan view of FIG. 3, for example, and FIG. 6I-2 is a cross-sectional view taken along line BB' in the plan view of FIG. 3, for example. As shown in FIG. 6I-1, as a result of etching back the conductive layer 106 in the pixel area A1, the conductive layer 106 in the pixel area A1 is locally thinned, the deep trench DT in the pixel area A1 is partially emptied, and a space is formed. After the etch-back process is completed, the top surface of the trench conductive layer 106 in the pixel area A1 is locally lower than the top surface of the semiconductor substrate 100. 6I-2, in the trench electrode pickup area A2, the conductive layer 106 still extends to the top end of the deep trench DT. The remaining portion of the trench conductive layer 106 forms the trench electrode E1.

[0051] 6J-1 and 6J-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from forming a deep trench fill layer. As shown in FIGS. 6J-1 and 6J-2, a deep trench fill layer 107 is deposited. The deep trench fill layer 107 covers the trench conductive layer 106 in the pixel area A1 and the trench electrode pickup area A2 and is deposited to a certain thickness above the second hard mask layer 104. The deep trench fill layer 107 may include silicon oxide or another isolation dielectric. Here, the linear oxide layer 105 and the deep trench fill layer 107 are collectively referred to as a first isolation dielectric. The trench electrode E1 is buried within the first isolation dielectric and insulated from the semiconductor substrate 100.

[0052] 6K-1 and 6K-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from planarizing the deep trench fill layer. As shown in FIGS. 6K-1 and 6K-2, the deep trench fill layer 107 is planarized (e.g., by CMP) to expose the upper surface of the second hard mask layer 104. As a result of the above steps, a deep trench isolation DTI is formed in the semiconductor substrate 100 so as to be embedded within one side of the semiconductor substrate 100. In the pixel area A1, the deep trench isolation DTI includes a linear oxide layer 105, a portion of the trench electrode E1, and the deep trench fill layer 107, which are filled within the deep trench DT. In the trench electrode pickup area A2, the deep trench isolation DTI includes a linear oxide layer 105 and a portion of the trench electrode E1, which are filled within the deep trench DT. The trench electrode E1 extends from the pixel area A1 to the trench electrode pickup area A2.

[0053] 5, in step S3, a gate dielectric layer, a floating gate FG, an inter-gate dielectric layer, and a control gate CG are formed on the surface of each substrate cell 110, each extending from the photo-sensing region 110a to the charge readout region 110b. Furthermore, in the charge readout region 110b, source and drain regions are formed on both sides of the control gate CG, which will be described in more detail below.

[0054] 6L-1 and 6L-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from removing the hard mask layers. As shown in FIGS. 6L-1 and 6L-2, the second hard mask layer 104 and the first hard mask layer 102 are removed. As a result, the deep trench isolation DTI protrudes beyond the surface of the semiconductor substrate 100 to a level higher than the shallow trench isolation STI. The deep trench isolation DTI in the pixel area A1 surrounds the individual substrate cells 110. An ion implantation process may then be performed to form a body region (not shown) in the charge readout region 110b. For example, p-type ions may be implanted in the ion implantation process. The pad oxide layer 101 is then removed, and a gate dielectric layer 108 is then formed on the surface of the semiconductor substrate 100.

[0055] 6M-1 and 6M-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area of ​​the structure resulting from forming a floating gate material layer, respectively. As shown in FIGS. 6M-1 and 6M-2, polysilicon is deposited to form a floating gate material layer 109, which fills the gap between the shallow trench isolation STI and the deep trench isolation DTI and is deposited to a certain thickness above the deep trench isolation DTI.

[0056] 6N-1 and 6N-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from planarizing the floating gate material layer. As shown in FIGS. 6N-1 and 6N-2, the floating gate material layer 109 is planarized to expose the deep trench fill layer 107 in the pixel area A1 and the trench electrode E1 in the trench electrode pickup area A2. The remaining portion of the floating gate material layer 109 is separated by deep trench isolation DTI.

[0057] 6O-1 and 6O-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from forming the inter-gate dielectric layer. As shown in FIGS. 6O-1 and 6O-2, the deep trench fill layer 107 is thinned using an etch-back process so that the top surface of the deep trench isolation DTI in the pixel area A1 is lowered (but still not lower than the surface of the semiconductor substrate 100), forming a trench T1 between the substrate cells 110. An inter-gate dielectric layer 111 is then conformally formed on the semiconductor substrate 100, and then the inter-gate dielectric layer 111 in the trench electrode pickup area A2 is removed to expose the underlying floating gate material layer 109. For example, the inter-gate dielectric layer 111 may be an oxide-nitride-oxide (ONO) stack consisting of a lower silicon oxide layer, a silicon nitride layer, and an upper silicon oxide layer.

[0058] 6P-1 and 6P-2 are schematic cross-sectional views of the pixel area and trench electrode pickup area, respectively, of the structure resulting from forming the control gate material layer. As shown in FIGS. 6P-1 and 6P-2, doped polysilicon is deposited on the semiconductor substrate 100 to form the control gate material layer 112. The floating gate material layer 109 in the trench electrode pickup area A2 may be retained or removed before the control gate material layer 112 is formed.

[0059] 6Q-1 and 6Q-3 are schematic cross-sectional views of the pixel area of ​​the structure resulting from forming the control gate and floating gate. For example, FIG. 6Q-1 is a cross-sectional view taken along line AA' in the plan view of FIG. 3. For example, FIG. 6Q-3 is a cross-sectional view taken along line CC' in the plan view of FIG. 3. FIG. 6Q-2 is a schematic cross-sectional view of the trench electrode pickup area of ​​the structure resulting from forming the trench electrode connection. For example, FIG. 6Q-2 is a cross-sectional view taken along line BB' in the plan view of FIG. 3. As shown in FIGS. 3, 6Q-1, 6Q-2, and 6Q-3, a photolithography process and one or more etching processes are performed to form floating gates FG and control gates CG on individual substrate cells 110, and to etch the control gate material layer 112 in the trench electrode pickup area A2 to form trench electrode connection E1-T in the trench electrode pickup area A2.

[0060] In particular, an anisotropic etching process can be performed to sequentially etch the control gate material layer 112, the inter-gate dielectric layer 111, and the floating gate material layer 109 in the pixel area A1. The remaining portions of the control gate material layer 112 form a plurality of word lines (WL) in the pixel area A1, each of the word lines extending across two or more of the substrate cells 110 and the deep trench isolations DTI therebetween. The word lines function as control gates CG, which reside above the floating gates FG and are spaced apart from the floating gates FG by the inter-gate dielectric layer 111.

[0061] The trench electrode connection E1-T is formed in the trench electrode pickup area A2 to connect to the trench electrode E1 and is isolated from the control gate CG in the pixel area A1. A voltage can be applied to the trench electrode E1 via the trench electrode connection E1-T. Although FIG. 3 shows the deep trenches DT in the pixel area A1 as extending laterally to the trench electrode pickup areas A2 at both ends, the present invention is not so limited. Since the deep trenches DT in the pixel area A1 can be connected, in some embodiments, the lateral extension of the deep trenches DT to the peripheral area A2 can be configured as needed. For example, each of the deep trenches DT in the pixel area A1 may extend to the trench electrode pickup area A2 at only one end.

[0062] 3, for example, in the substrate cell 110, the control gate CG may have a larger width across the photo-sensing region 110a than across the charge readout region 110b. An etching process is performed to expose portions of the gate dielectric layer 108 on both sides of the control gate CG over the charge readout region 110b. Furthermore, the exposed portions of the gate dielectric layer 108 may be stripped away, and spacers are formed on the sidewalls of the gate dielectric layer 108, the floating gate FG, the inter-gate dielectric layer 111, and the control gate CG. Then, ions are implanted into the exposed charge readout region 110b on both sides of the control gate CG to form a source region S and a drain region D.

[0063] 5, in step S4, the semiconductor substrate 100 is thinned from the other side until the deep trench isolation DTI is exposed, and a substrate electrode E2 is formed on the other side to contact each substrate cell 110 and be separated from the trench electrode E1. A voltage can be applied to the substrate cells 110 via the substrate electrode E2.

[0064] FIG. 6R is a schematic cross-sectional view of a structure resulting from thinning the semiconductor substrate from the other side. For example, FIG. 6R is a cross-sectional view taken along line AA′ in the plan view of FIG. 3. As shown in FIG. 6R, the semiconductor substrate 100 is thinned from the side away from the control gate CG, exposing the deep trench isolation DTI. More precisely, for example, the trench electrode E1 in the deep trench DT may be exposed, and the trench electrode E1 may be partially removed in the thinning process. As a result, the deep trench isolation DTI in the pixel area A1 extends through the semiconductor substrate 100, thereby providing complete physical separation between the substrate cells 110.

[0065] As shown in FIG. 6S, a photolithography and etching process is performed on the surface of the thinned semiconductor substrate 100 to form a first trench T2 in the exposed deep trench isolation DTI. The trench electrode E1 and the substrate cell 110 around the trench electrode are exposed at the inner surface of the first trench T2. For example, the first trench T2 may have an inverted trapezoidal cross section.

[0066] 6T, a dielectric material is deposited in the first trench T2 and on the surface of the substrate cell 110 to form the second isolation dielectric 113. Thus, the second isolation dielectric 113 fills the first trench T2 and covers the surface of the substrate cell 110.

[0067] As shown in FIG. 6U, photolithography and etching processes are performed to form a second trench T3 aligned with the first trench T2. The bottom surface of the second trench T3 is located around the top end of the first trench T2, and the substrate cell 110 around the deep trench isolation DTI is exposed at the side of the second trench T3. The second isolation dielectric 113 covering the trench electrode E1 is exposed at the bottom of the second trench T3. Furthermore, the substrate cell 110 around the deep trench isolation DTI may also be exposed at the bottom of the second trench T3.

[0068] The second isolation dielectric 113 may be a high-k material (dielectric constant k greater than 3.9), which can increase the potential barrier at the interface between the first trench T2 and the semiconductor substrate 100 (interface passivation). This can reduce the probability of photoelectrons being trapped at the interface, contributing to improved photoelectric conversion efficiency. Examples of high-k materials include Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), and TiO2.

[0069] 6V, a conductive material is filled into the second trench T3 to form a substrate electrode E2, which may include one or a combination of titanium, titanium nitride, tantalum nitride, aluminum, a copper alloy, and an aluminum alloy.

[0070] The VPS and method of the present invention provide the following benefits: The deep trench isolation DTI formed on one side of the semiconductor substrate 100 provides physical inter-pixel separation, thereby ensuring good photoelectric conversion efficiency of the VPS, effectively avoiding inter-pixel crosstalk, and facilitating pixel miniaturization. The substrate electrode E2 is formed on the other side of the semiconductor substrate 100 (i.e., the side away from the control gate CG), leaving a larger area for the control gate CG and further facilitating pixel miniaturization. The trench electrode E1 in the deep trench isolation DTI provides an operable electrode terminal for the VPS, which can cooperate with other electrode terminals of the sensor (e.g., electrode terminals individually connected to the control gate, source region, drain region, and substrate electrode) to enable various operation modes. For example, the trench electrode E1 may be connected to the substrate electrode E2, and a positive bias voltage may be applied for light sensing between the substrate electrode E2 and the trench electrode E1 to increase the potential barrier at the interface between the deep trench isolation and the substrate cell. This reduces the probability of photoelectrons being trapped at the interface, contributing to improved photoelectric conversion efficiency and helping to mitigate dark current and white pixel issues. Furthermore, the positive bias voltage can be flexibly adjusted, allowing the isolation dielectric between the trench electrode and the substrate cell to be selected as an inexpensive low-k material (dielectric constant ≤ 3.9). As another example, after the photodetection and charge readout cycles are completed, a negative bias voltage can be applied between the substrate electrode and the trench electrode to reset the sensor and release the charges trapped around the boundary of the deep trench isolation. This helps reduce background noise in the next photodetection and charge readout cycle.

[0071] It should be noted that the embodiments disclosed herein are described incrementally, with the description of each embodiment focusing on differences from the others. Cross-references may be made to common or similar features between the embodiments.

[0072] Although the present invention has been described with reference to several preferred embodiments, it is by no means intended to be limited to these embodiments. In light of the above teachings, those skilled in the art will be able to make various possible variations and modifications to the disclosed embodiments without departing from the scope of the present invention. Accordingly, any and all such simple variations, equivalent substitutions, and modifications made to the above-described embodiments without departing from the scope of the present invention are intended to be included within the scope of the present invention.

Claims

1. a semiconductor substrate having a pixel area; shallow trench isolations and deep trench isolations formed on a first side of the semiconductor substrate, each of the deep trench isolations including a deep trench extending through the semiconductor substrate, a trench electrode and a first isolation dielectric filled in the deep trench, the first isolation dielectric insulating the trench electrode from the semiconductor substrate, the deep trench isolations defining a plurality of substrate cells in the pixel area, each of the substrate cells including a photo-sensing region and a charge readout region separated from one another by one of the shallow trench isolations; a gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate formed on a surface of each of the substrate cells and extending from the photo-sensing region to the charge readout region, and source and drain regions formed on either side of each of the control gates in each of the charge readout regions; at least one substrate electrode formed on a second side of the semiconductor substrate, the at least one substrate electrode contacting two adjacent substrate cells and separated from the corresponding trench electrode; 1. A vertical charge transfer pixel sensor comprising:

2. 2. The vertical charge transfer pixel sensor of claim 1, wherein the semiconductor substrate further comprises a trench electrode pickup area around the pixel area, and the trench electrode in the deep trench extends from the pixel area to the trench electrode pickup area and extends from a bottom to a top of the deep trench within the trench electrode pickup area.

3. a trench electrode connection portion formed in the trench electrode pickup area and covering the trench electrode; The vertical charge transfer pixel sensor of claim 2 further comprising:

4. 2. The vertical charge transfer pixel sensor of claim 1, wherein in the pixel area, the first isolation dielectric filled in the deep trench comprises a linear oxide layer and a deep trench fill layer, the linear oxide layer being interposed between the trench electrode and the semiconductor substrate, and the deep trench fill layer covering the trench electrode and located on top of the deep trench.

5. 2. The vertical charge transfer pixel sensor of claim 1, wherein the at least one substrate electrode is formed on the second side of the semiconductor substrate corresponding to the deep trench in the pixel area, and a second isolation dielectric is interposed between the at least one substrate electrode and the trench electrode.

6. The vertical charge transfer pixel sensor of claim 5 , wherein the second isolation dielectric comprises a high dielectric constant material.

7. 2. The vertical charge transfer pixel sensor of claim 1, wherein the control gates formed on each of the substrate cells are connected to form a plurality of word lines, each word line extending across a plurality of the substrate cells.

8. 1. A method of manufacturing a vertical charge transfer pixel sensor, comprising: providing a semiconductor substrate having a pixel area; forming shallow trench isolations and deep trench isolations on a first side of the semiconductor substrate, each of the deep trench isolations including a deep trench extending through the semiconductor substrate, a trench electrode and a first isolation dielectric filled in the deep trench, the first isolation dielectric insulating the trench electrode from the semiconductor substrate, the deep trench isolations defining a plurality of substrate cells in the pixel area, each of the substrate cells including a photo-sensing region and a charge readout region separated from one another by one of the shallow trench isolations; forming a gate dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate on a surface of each substrate cell, the gate dielectric layer extending from the photo-sensing region to the charge readout region, and forming source and drain regions on either side of the respective control gate in the respective charge readout region; thinning the semiconductor substrate from a second side of the semiconductor substrate until the deep trench isolation is exposed, and forming at least one substrate electrode on the second side contacting two adjacent substrate cells and separated from the corresponding trench electrode; A method comprising:

9. forming the shallow trench isolation and the deep trench isolation formed on the first side of the semiconductor substrate, forming a pad oxide layer and a first hard mask layer on a surface of the semiconductor substrate, and forming the shallow trench isolation extending through the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate; forming a second hard mask layer covering the first hard mask layer and the shallow trench isolation; forming the deep trench extending through the second hard mask layer, the first hard mask layer, the pad oxide layer, and a portion of the semiconductor substrate; forming a linear oxide layer and a conductive layer in the deep trench, the linear oxide layer covering the semiconductor substrate exposed in the deep trench, the conductive layer covering the linear oxide layer and filling the deep trench, and a top surface of the conductive layer being higher than the surface of the semiconductor substrate; etching back the conductive layer in the pixel area until the top surface of the conductive layer is recessed below the surface of the semiconductor substrate, forming a space at the top of the deep trench in the pixel area, and a remaining portion of the conductive layer forms the trench electrode; forming a deep trench fill layer in the space, the linear oxide layer and the deep trench fill layer constituting the first isolation dielectric; The method of claim 8, comprising:

10. 10. The method of claim 8 or 9, wherein the semiconductor substrate further comprises a trench electrode pick-up area around the pixel area, and the trench electrode in the deep trench extends from the pixel area to the trench electrode pick-up area and extends from a bottom to a top of the deep trench within the trench electrode pick-up area.

11. forming the at least one substrate electrode; forming a first trench in the deep trench isolation exposed on the second side of the semiconductor substrate, wherein the trench electrode and the substrate cell around the trench electrode are exposed in the first trench; forming a second isolation dielectric on the second side, the second isolation dielectric filling the first trench and covering a surface of the substrate cell; forming a second trench whose bottom is located around the top of the first trench, the substrate cell around the deep trench isolation being exposed at the side of the second trench, and the trench electrode being covered by the second isolation dielectric; filling the second trench with a conductive material to form the at least one substrate electrode; 10. The method of claim 8 or 9, comprising:

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