Semiconductor rectifier and manufacturing method thereof

Abstract

The present application relates to a semiconductor rectifier device and a method for manufacturing the same, the semiconductor rectifier device comprising: an epitaxial layer having a top surface and a bottom surface facing opposite to each other; a first doped region having a first conductivity type located in the epitaxial layer; a first trench structure located in the first doped region and extending from the top surface to the bottom surface; a second trench structure located in the first doped region, extending from the top surface to the bottom surface and adjacent to the first trench structure; a second doped region having a second conductivity type and a depth less than that of the first trench structure, located in the epitaxial layer between the first and second trench structures and extending from the top surface to the bottom surface; and a metal layer located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure, and the second doped region, the top surface of which contacts the epitaxial layer forming a Schottky contact.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor rectifier structure and a method for manufacturing the same, and more particularly to a Schottky barrier rectifier structure and a method for manufacturing the same. [Background technology]

[0002] As is well known, power rectifiers are essential in power circuits. With the advancement of technology and the times, power rectifiers are increasingly required to have excellent power switching performance and low power consumption. Schottky rectifiers have a relatively low forward voltage, which is advantageous for forward power loss. However, Schottky rectifiers also have a relatively high reverse leakage current, which leads to relatively high reverse power loss. The Schottky barrier height affects the forward voltage (VF) and reverse current (IR). For example, lowering the Schottky barrier height can lower the VF, but this increases the IR, resulting in increased reverse power loss. The technical bottleneck in this field is how to simultaneously lower the VF and the IR while maintaining the breakdown voltage (BV). Summary of the Invention

[0003] An embodiment of the present disclosure relates to a semiconductor rectifier device comprising: an epitaxial layer having a top surface and a bottom surface facing opposite to each other; a first doped region having a first conductivity type located in the epitaxial layer; a first trench structure located in the first doped region and extending from the top surface toward the bottom surface; a second trench structure located in the first doped region and extending from the top surface toward the bottom surface and adjacent to the first trench structure; a second doped region having a second conductivity type and a depth less than that of the first trench structure located in the epitaxial layer between the first trench structure and the second trench structure and extending from the top surface toward the bottom surface; and a metal layer located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure, and the second doped region, the top surface of which contacts the epitaxial layer forming a Schottky contact.

[0004] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor rectifier device, the method including: forming an epitaxial layer having a first conductivity type on a substrate; forming a first trench structure and a second trench structure adjacent to the first trench in the epitaxial layer; forming a doped region having a second conductivity type in the epitaxial layer between the first trench structure and the second trench structure; and forming a metal layer on the epitaxial layer to cover the first trench structure, the second trench structure, and the doped region.

[0005] Aspects of some embodiments of the present disclosure may be best understood when reading the following detailed description in conjunction with the drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 illustrate one or more stages in a method for fabricating a semiconductor rectifier device according to some embodiments of the present disclosure.

[0007]

[0013] Like reference numerals are used in the drawings and detailed description to designate the same or similar assemblies.

[0014] Several embodiments of the present disclosure can be readily understood from the following detailed description and by reference to the drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 2] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 3] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 4] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 5] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 6] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 7] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 8] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 9] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 10] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. [Figure 11] 1 illustrates one or more steps in a method for fabricating a semiconductor rectifier device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following disclosure provides many different embodiments or examples of various features for implementing the provided targets. Specific examples of assemblies and arrangements are described below. Of course, these are merely exemplary and are not intended to be limiting. In this disclosure, references to forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which other features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, this disclosure may repeat drawing numerals and / or symbols in each example. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between each of the embodiments and / or arrangements discussed.

[0010] In the following, examples of the present disclosure are discussed in detail. However, it should be understood that the present disclosure provides many preferred concepts that can be embodied in a variety of specific environments. The specific examples discussed are illustrative only and do not limit the scope of the present disclosure.

[0011] The present disclosure provides a semiconductor rectifier structure and a manufacturing method thereof. Compared with conventional semiconductor rectifier manufacturing methods, the semiconductor rectifier of the present disclosure has a Schottky barrier structure. Furthermore, the Schottky barrier rectifier of the present disclosure has a relatively low electric field strength at the metal-semiconductor interface, which can reduce IR while maintaining a low VF and improve reverse leakage. Therefore, the structure of the present disclosure can reduce IR without increasing VF, providing a rectifier with improved reverse leakage.

[0012] 1-10 illustrate one or more stages in a method for manufacturing a semiconductor rectifier device 1 according to some embodiments of the present disclosure. At least some of these figures have been simplified to allow a better understanding of aspects of the present disclosure.

[0013] Referring to FIG. 1 , the method for fabricating a semiconductor rectifier device 1 includes performing epitaxial growth on a surface 11A of a substrate 11 to form an epitaxial layer 12 and forming a doped region 25 in the epitaxial layer 12. The substrate 11 has opposite surfaces 11A and 11B. In some embodiments, the surfaces 11A and 11B may be horizontal. For ease of explanation, the direction perpendicular to the surfaces 11A and 11B is defined as the vertical direction, while the direction perpendicular to the vertical direction is defined as the horizontal direction. In some embodiments, the surface 11A is the top surface of the substrate 11, and the surface 11B is the bottom surface of the substrate 11. In some embodiments, the surface 11A is the top surface of a silicon wafer. The substrate 11 shown in FIG. 1 may simply be a portion of the silicon wafer near the top surface. The material of the substrate 11 may be polycrystalline silicon or single crystal silicon. The substrate 11 may include a doped region 24. For example, substrate 11 may include p-type doped regions and n-type doped regions that may be configured for n-type transistors and configured as p-type transistors. The N-type doped regions are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The P-type doped regions are doped with p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. The N-type or P-type doped regions may be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping process. Doped region 24 of substrate 11 extends from surface 11A toward surface 11B. In some embodiments, doped region 24 of substrate 11 covers the entire surface 11A. In some embodiments, doped region 24 of substrate 11 has a first conductivity type. For ease of explanation, the following description will be given taking N-type as an example for the first type and P-type as an example for the second type, but the present disclosure is not limited thereto, and the N-type (first type) or P-type (second type) substrate 11 can be adjusted according to the conductivity type of the semiconductor rectifier device 1. It should be noted that the substrate 11 shown in FIG. 1 may simply be a portion near the top surface of a silicon wafer, or may simply be a portion of the doped region 24 of the substrate 11.In some embodiments, doped region 24 of substrate 11 is a cathode doped region of semiconductor rectifier device 1. In some embodiments, doped region 24 of substrate 11 forms a concentration range of 1*10. 19 ~7*10 19 / cubic centimeter (cm -3 )

[0014] The epitaxial layer 12 has the same conductivity type as the substrate 11, i.e., is doped with a first type of dopant. The material of the epitaxial layer 12 may be polycrystalline silicon, single-crystal silicon, silicon carbide, silicon germanium, or other suitable semiconductor material. In some embodiments, the epitaxial layer 12 is formed as an N-type epitaxial layer by epitaxially introducing ions having N-type electrical properties, eliminating the need for additional ion implantation. Thus, the ions having N-type electrical properties are distributed throughout the epitaxial layer 12, forming doped regions 25 located throughout the epitaxial layer 12. The epitaxial layer 12 may have a surface 12A and a surface 12B opposite to the surface 12A. In some embodiments, the surfaces 12A and 12B may be horizontal surfaces. In some embodiments, the surface 12A is the top surface of the epitaxial layer 12, and the surface 12B is the bottom surface of the epitaxial layer 12. In some embodiments, the surface of surface 12B of epitaxial layer 12 contacts surface 11A of substrate 11.

[0015] The thickness and doping concentration of epitaxial layer 12 can be adjusted depending on the voltage needs of the device. In some embodiments, the thickness of epitaxial layer 12 ranges from 6 to 12 micrometers (μm). In some embodiments, the thickness of epitaxial layer 12 ranges from 8 to 10 μm. In some embodiments, epitaxial layer 12 may have a uniform doping concentration, for example, a doping concentration of 5*10 14 ~1*10 16 cm -3In some embodiments, epitaxial layer 12 may have a doping concentration that increases gradually from surface 12A to surface 12B, e.g., a doping concentration of 4*10 ohms near surface 12A. In some embodiments, epitaxial layer 12 may have a doping concentration gradient ... 15 ~7*10 15 cm -3 and the doping concentration close to the surface 12B is 1*10 16 ~4*10 16 cm -3 In some embodiments, ions having N-type electrical properties are introduced during the epitaxial growth, where the concentration of the introduced ions decreases with the time of epitaxial growth, thereby forming the epitaxial layer 12 with a gradually decreasing doping concentration.

[0016] In the above-described embodiment of the doping gradient of epitaxial layer 12, the doping concentration at surface 12A of epitaxial layer 12 is reduced. A reduction in the doping concentration at surface 12A increases the resistivity of surface 12A, while an increase in the doping concentration within epitaxial layer 12 reduces the resistivity therein, thereby further reducing VF while maintaining BV. In some embodiments, the doping concentration of the portion of epitaxial layer 12 adjacent to surface 12A is approximately one power lower than the doping concentration of the portion adjacent to surface 12B, i.e., the difference in concentration between the two is approximately 1*10 cm. -3 is.

[0017] Referring to FIG. 2 , the method for fabricating semiconductor rectifier device 1 includes forming a patterned layer 51 on surface 12A of epitaxial layer 12 to expose a portion of epitaxial layer 12. Patterned layer 51 is used to define the location of a trench to be subsequently formed. In some embodiments, patterned layer 51 has openings 511 and 512, exposing a portion of epitaxial layer 12. Patterned layer 51 may be a material layer suitable for use as a mask in a subsequent etching process, such as a photomask, a hardening layer, or a dielectric layer (e.g., an oxide or nitride layer). In some embodiments, patterned layer 51 includes an oxide (e.g., silicon oxide). In some embodiments, an oxide layer is formed to cover surface 12A of epitaxial layer 12, a patterned photomask is formed on the oxide layer, and a portion of the oxide layer is removed using the patterned photomask. The patterned photomask is then removed to form patterned layer 51 exposing a portion of epitaxial layer 12.

[0018] Referring to FIG. 3 , the method for manufacturing the semiconductor rectifier device 1 includes performing an etching process on the epitaxial layer 12 using the patterning layer 51 as a mask to form a plurality of trenches (trenches 41 and 42 shown in FIG. 3 ). The plurality of trenches are adjacent to each other and extend from the surface 12A toward the surface 12B of the epitaxial layer 12. Because they are formed through the same etching step, the plurality of trenches have approximately the same depth. In some embodiments, the trenches 41 and 42 have approximately the same depth D40. In some embodiments, the depth D40 of the trench 41 or the trench 42 is 5 to 30 μm. In some embodiments, the depth D40 of the trench 41 or the trench 42 is 8 to 10 μm. The widths of the trenches 41 and 42 can be determined by the openings 511 and 512. In some embodiments, the trenches 41 and the trench 42 have approximately the same width W40. In some embodiments, the width W40 of trench 41 or trench 42 is 0.5 to 3 μm. In some embodiments, the width W40 of trench 41 or trench 42 is 1.3 to 1.7 μm. The width and depth of trench 41 and trench 42 can be set and adjusted based on the voltage required by the device, and within the scope of the above embodiments, the greater the value of the depth D40 of trenches 41, 42, the lower the resistivity of epitaxial layer 12.

[0019] Referring to FIG. 4 , the method for fabricating semiconductor rectifier device 1 includes forming trenches 41 and 42 to be filled with dielectric layer 13. In some embodiments, dielectric layer 13 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition processes. In some embodiments, dielectric layer 13 can be formed by thermal oxidation techniques. In some embodiments, dielectric layer 13 is deposited in trenches 41 and 42. In some embodiments, dielectric layer 13 can be conformally deposited on the inner surfaces of trenches 41 and 42 (including opposing sidewalls and a bottom extending between the sidewalls) and on surface 12A of epitaxial layer 12. In some embodiments, dielectric layer 13 fills trenches 41 and 42 via a deposition process, and can further be subjected to lithography and etching processes to partially remove dielectric layer 13 to form at least one recess in dielectric layer 13. The thickness of dielectric layer 13 can be set and adjusted based on the voltage required by the device. In some embodiments, the thickness of dielectric layer 13 is 0.1 to 2 μm. In some embodiments, the thickness of dielectric layer 13 is 0.2 to 1.2 μm. In some embodiments, the thickness of dielectric layer 13 is 0.5 to 0.8 μm.

[0020] Since the voltage of semiconductor rectifier device 1 is largely determined by the doping concentration of epitaxial layer 12 and the thickness of dielectric layer 13 together, the steps shown in FIGS.

[0021] 5, the method for fabricating semiconductor rectifier device 1 includes forming trenches 41 and 42 that are filled with semiconductor material layer 14. In some embodiments, semiconductor material layer 14 can be formed by physical vapor deposition (PVD), CVD, or other deposition processes. In some embodiments, semiconductor material layer 14 fills trenches 41 and 42 and covers surface 12A of epitaxial layer 12. In some embodiments, semiconductor material layer 14 comprises polycrystalline silicon.

[0022] 6 , the method for manufacturing the semiconductor rectifier device 1 includes removing portions of the semiconductor material layer 14 and the dielectric layer 13 located outside the trenches 41 and 42. In some embodiments, the semiconductor material layer 14 outside the trenches 41 and 42 is removed to form a first electrode layer 141 and a second electrode layer 142, respectively. In some embodiments, the semiconductor material layer 14 is subjected to a polishing process, such as a chemical mechanical polishing (CMP) process, to remove the semiconductor material layer 14 outside the trenches 41 and 42. In other embodiments, the method for removing the portions of the semiconductor material layer 14 outside the trenches 41 and 42 may further include an etching process, such as a wet etching or a dry etching process. In some embodiments, after removing the semiconductor material layer 14 on the surface 12A of the epitaxial layer 12, a similar process is performed on the dielectric layer 13 to form a first dielectric layer 131 and a second dielectric layer 132, respectively, in the trenches 41 and 42. In some embodiments, first dielectric layer 131 surrounds first electrode layer 141, and second dielectric layer 132 surrounds second electrode layer 142. For ease of description, first electrode layer 141 and first dielectric layer 131 are collectively referred to as first trench structure 151, and similarly, second electrode layer 142 and second dielectric layer 132 are collectively referred to as second trench structure 152. In some embodiments, top surfaces of first electrode layer 141 and second electrode layer 142 are flush with surface 12A. In some embodiments, top surfaces of first dielectric layer 131 and second dielectric layer 132 are flush with surface 12A.

[0023] 7 , the method for fabricating the semiconductor rectifier device 1 includes forming a patterned layer 52 on the surface 12A of the epitaxial layer 12. The patterned layer 52 covers the first and second trench structures 151, 152 and exposes a portion of the epitaxial layer 12 located between the first trench structure 151 and the second trench structure 152. In some embodiments, the patterned layer 52 has an opening 521 that exposes a portion of the epitaxial layer 12 located between the first trench structure 151 and the second trench structure 152. The patterned layer 52 may be a material layer suitable for use as a mask for a subsequent etching process, such as a photomask, a hardening layer, or a dielectric layer (e.g., an oxide or nitride layer). In some embodiments, the patterned layer 52 includes an oxide (e.g., silicon oxide). In some embodiments, the entire oxide layer is formed to cover the surface 12A of the epitaxial layer 12, a patterning photomask is formed on the oxide layer, a portion of the oxide layer is removed using the patterning photomask, and then the patterning photomask is removed to form the patterned layer 52 of FIG. 7 . The opening 521 is located approximately midway between the first trench structure 151 and the second trench structure 152. In some embodiments, the distance L1 from the opening 521 to the first trench structure 151 is approximately equal to the distance L2 from the opening 521 to the second trench structure 152. In some embodiments, the distance L3 from the center of the opening 521 (indicated by the dashed line C1) to the first trench structure 151 is approximately equal to the distance L4 from the center of the opening 521 to the second trench structure 152. In some embodiments, the width W521 of the opening 521 is 0.3 to 0.6 μm.

[0024] 8 , the method for manufacturing the semiconductor rectifier device 1 includes performing ion implantation on the surface 12A of the epitaxial layer 12 using the patterning layer 52 as a mask to form a doped region 21 having a second conductivity type. The depth D21 of the doped region 21 is less than the depth of the first trench structure 151 or the second trench structure 152. Because the doped region 21 is defined by the opening 521 in the patterning layer 52, the width W21 of the doped region 21 at the surface 12A of the epitaxial layer 12 is approximately the same as the width W521 of the opening 521. In some embodiments, the width W21 of the doped region 21 is 0.3 to 0.6 μm. In some embodiments, the depth D21 of the doped region 21 is 0.2 to 0.8 μm. In some embodiments, the doping concentration of the doped ions of the second conductivity type in the doped region 21 is 1*10 16 ~1*10 18 cm -3 The ion implantation process is followed by a thermal annealing process to activate the doped ions in the doped region 21.

[0025] Subsequently, a Schottky metal is formed on the surface 12A of the epitaxial layer 12, and the interface between the epitaxial layer 12 and the Schottky metal forms a Schottky contact. This causes the electric field generated by the semiconductor rectifier 1 during operation to concentrate between the first trench structure 151 and the second trench structure 152, and to concentrate at a position between the first trench structure 151 and the second trench structure 152 adjacent to the surface 12A of the epitaxial layer 12. This electric field concentration region is likely to lead to the occurrence of current leakage. Forming a doped region 21 in the epitaxial layer 12 adjacent to the surface 12A between the first trench structure 151 and the second trench structure 152 effectively blocks the electric field, thereby avoiding the problem of current leakage in the semiconductor rectifier 1. Depending on the magnitude and distribution range of the electric field generated by various devices, the width W21 of the doped region 21 (or the lateral area located on the surface 12A) can be adjusted to block the electric field close to the surface 12A, but if the lateral area located on the surface 12A of the doped region 21 is too large, this may lead to an increase in VF.

[0026] Because electric fields can concentrate between the first trench structure 151 and the second trench structure 152 and in the epitaxial layer 12 between them, the depth D21 of the doped region 21 determines the range of electric field blocking on both sides along the vertical direction. The larger the blocking range, the less likely it is that concentrated electric fields will form near the surface 12A. Although the depth D21 of the doped region 21 does not significantly affect the VF, several tests have shown that the depth D21 of the doped region 21 contributes to improving the leakage current problem by improving the electric field blocking effect. However, because the leakage current problem is mainly concentrated near the surface 12A, it is unlikely that reaching a certain value for the depth D21 of the doped region 21 will significantly contribute to improving the leakage current. The aforementioned range of the depth D21 of the doped region 21 is based on the overall dimensions of the semiconductor rectifier device 1 and the limitations of conventional manufacturing methods and processes. The resulting preferred range is not intended to limit the inventive concept of the present disclosure.

[0027] 9 , the method for fabricating semiconductor rectifier device 1 includes conformally forming metal layer 18 on surface 12A of epitaxial layer 12. Metal layer 18 may be selected from Schottky metals such as titanium (Ti), nickel (Ni), molybdenum (Mo), platinum (Pt), nickel platinum (NiPt), or combinations thereof. In some embodiments, metal layer 18 contacts surface 12A of epitaxial layer 12, a top surface of first trench structure 151, and a top surface of second trench structure 152. In some embodiments, metal layer 18 is adjacent to doped region 21.

[0028] A typical Schottky barrier rectifier device can only achieve low reverse leakage current by selecting metals with high Schottky barrier heights, such as platinum and molybdenum, and avoids using metals with low Schottky barrier heights, such as titanium. This is because using metals with low Schottky barrier heights leads to low VF and relatively low power consumption, but the device is more susceptible to the influence of electric field strength, and leakage current will rise sharply when there is a relatively strong electric field strength in a certain area.

[0029] In the present disclosure, doped regions 21 are formed between the trench structures 151, 152 and in a portion of the epitaxial layer 12 where the electric field is concentrated, which can effectively block the electric field. Compared to a Schottky barrier rectifier without doped regions 21, this not only improves the original leakage current problem, but also significantly increases the options for usable Schottky metals, eliminating the limitation to using only metals with high Schottky barrier heights. Even when metals with low Schottky barrier heights are used, the same or better effects can be achieved as in conventional Schottky barrier rectifiers.

[0030] Referring to FIG. 10 , the method for manufacturing the semiconductor rectifier device 1 includes forming an upper electrode layer 16 on a metal layer 18. The upper electrode layer 16, serving as the anode electrode of the semiconductor rectifier device 1, may include a suitable metal material or alloy, such as, but not limited to, titanium tungsten (TiW), aluminum (Al), aluminum silicon alloy (AlSi), aluminum silicon copper alloy (AlSiCu), or a combination thereof. After the upper electrode layer 16 is formed, the upper electrode layer 16 and the contact metal 31 can be etched to form a desired pattern. Because the etching step is performed based on the desired circuit design, the etching step is not shown in the drawings. Those skilled in the art can adjust the etching step based on the above content of this disclosure to form the desired pattern of the upper electrode layer 16 and the metal layer 18.

[0031] 11 , the method for fabricating semiconductor rectifier device 1 includes forming bottom electrode layer 17 on substrate 11 below epitaxial layer 12. Bottom electrode layer 17 and top electrode layer 16 are located on opposite sides of epitaxial layer 12. Doped region 24 in substrate 11 serves as the cathode contact region for semiconductor rectifier device 1. The material of bottom electrode layer 17 may be the same as or, in some embodiments, different from top electrode layer 16, and bottom electrode layer 17 comprises titanium-nickel-silver alloy (TiNiAg). In some embodiments, bottom electrode layer 17 contacts doped region 24 in substrate 11. In some embodiments, before forming bottom electrode layer 17, substrate 11 is polished or etched to reduce the thickness of substrate 11 and expose doped region 24.

[0032] For convenience of description, spatially relative terms such as "below," "underside," "lower," "upper," "top," "left side," "right side," etc. may be used herein to describe the relationship of one assembly or feature to another assembly or feature as shown in the drawings. The spatially relative terms are intended to encompass various orientations of the device during use or operation in addition to the orientation depicted in the drawings. The device may be oriented in other manners (rotated 90 degrees or at other orientations) and similarly, the spatially relative terms used herein may be interpreted accordingly. When an assembly is referred to as "connected to" or "coupled to" another assembly, it should be understood that it may be directly connected or coupled to the other assembly or that intermediate assemblies may be present.

[0033] As used herein, the terms "substantially," "generally," "essentially," and "about" are used to describe and account for small variations. When used in connection with an event or circumstance, the term can refer to an instance in which the event or circumstance occurred exactly or near the occurrence of the event or circumstance. The term "about," when used in connection with a given value or range, generally refers to within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to the other endpoint, or as lying between two endpoints. All ranges disclosed herein include endpoints unless expressly stated otherwise. The term "substantially flush" can refer to two surfaces positioned along the same plane being within a few microns (μm) of each other, such as within 10 μm, 5 μm, 1 μm, or 0.5 μm of each other. When numerical values ​​or properties are referred to as being "about" the same, the term can refer to values ​​that are within ±10%, ±5%, ±1% or ±0.5% of the mean of said value.

[0034] The foregoing has outlined certain exemplary features and detailed aspects of the present disclosure. The exemplary embodiments described in this disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or facilitate achieving the same or similar advantages of the exemplary embodiments presented herein. Various modifications, substitutions, and alterations to such equivalent constructions may be made without departing from the spirit and scope of the present disclosure.

Claims

1. In a semiconductor rectifier device, an epitaxial layer having opposing top and bottom surfaces; a first doped region having a first conductivity type located in the epitaxial layer; a first trench structure located in the first doped region and extending from the top surface toward the bottom surface; a second trench structure located in the first doped region, extending from the top surface toward the bottom surface and adjacent to the first trench structure; a second doped region having a second conductivity type located in the epitaxial layer between the first trench structure and the second trench structure and extending from the top surface toward the bottom surface, the second doped region having a depth less than a depth of the first trench structure; a metal layer located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure, and the second doped region, the top surface of which contacts the epitaxial layer forming a Schottky contact; A semiconductor rectifier comprising:

2. 2. The semiconductor rectifier device of claim 1, wherein the doping concentration of said first doped region increases gradually from said top surface to said bottom surface.

3. The concentration of the first doped region adjacent to the top surface is 4*10 １５ ~7*10 １５ cm －３ and the concentration of the first doped region adjacent to the bottom surface is 1*10 １６ ~4*10 １６ cm －３ 2. The semiconductor rectifier device according to claim 1, wherein:

4. 2. The semiconductor rectifier device of claim 1, wherein a distance from a center of the second doped region to the first trench structure is approximately the same as a distance from the center of the second doped region to the second trench structure.

5. 2. The semiconductor rectifier device of claim 1, wherein the width of the second doped region is between 0.3 μm and 0.6 μm.

6. 2. The semiconductor rectifier device of claim 1, wherein the second doped region has a depth of 0.2 μm to 0.8 μm.

7. The concentration of the second doped region is 1*10 １６ ~1*10 １８ cm －３ 2. The semiconductor rectifier device according to claim 1, wherein:

8. 2. The semiconductor rectifier device according to claim 1, wherein a top surface of the first trench structure or the second trench structure is flush with a top surface of the epitaxial layer.

9. 2. The semiconductor rectifier device of claim 1, wherein the first trench structure comprises a first dielectric layer and a first electrode layer surrounded by the first dielectric layer, and the second trench structure comprises a second dielectric layer and a second electrode layer surrounded by the second dielectric layer.

10. an anode electrode located on the metal layer; a substrate overlying the bottom surface of the epitaxial layer; a cathode electrode in contact with the substrate layer; The semiconductor rectifier device of claim 1 further comprising:

11. 2. The semiconductor rectifier device of claim 1, wherein the depth of the first trench structure is 8 μm to 10 μm, and the depth of the second trench structure is approximately the same as the depth of the first trench structure.

12. 1. A method for manufacturing a semiconductor rectifier, comprising: forming an epitaxial layer having a first conductivity type on a substrate; forming a first trench structure and a second trench structure adjacent to the first trench in the epitaxial layer; forming a doped region having a second conductivity type in the epitaxial layer between the first trench structure and the second trench structure; forming a metal layer on the epitaxial layer, the metal layer covering the first trench structure, the second trench structure, and the doped region; A method for manufacturing a semiconductor rectifier, comprising:

13. forming the epitaxial layer having a first conductivity type; epitaxially introducing ions having a first conductivity type, wherein the concentration of the introduced ions decreases with time of epitaxial growth, and the concentration of the ions in the epitaxial layer gradually decreases upward from a top surface of the semiconductor material layer; The method of claim 12, comprising:

14. forming the first trench structure and the second trench structure; forming a patterning layer on a top surface of the epitaxial layer to define the location of the first trench structure and the second trench structure; forming a first trench and a second trench using the patterning layer as a mask; forming a dielectric layer conformally covering the epitaxial layer, the dielectric layer having a first portion disposed in the first trench and a second portion disposed in the second trench; forming a polysilicon layer on the dielectric layer, the polysilicon layer having a first portion filling the first trench and a second portion filling the second trench; removing the polycrystalline silicon layer and the dielectric layer located above a top surface of the epitaxial layer, the top surface of which is flush with a top surface of the first trench structure and a top surface of the second trench structure; The method of claim 12, comprising:

15. removing the polycrystalline silicon layer and the dielectric layer located above the top surface of the epitaxial layer; performing a first etching process on the polysilicon layer to remove a portion of the polysilicon layer; performing a second etching process on the dielectric layer to remove a portion of the dielectric layer; The method of claim 14, comprising:

16. The manufacturing method according to claim 12, wherein the thickness of the dielectric layer is 0.2 μm to 2 μm.

17. The manufacturing method of claim 12 , wherein the material of the metal layer comprises titanium, molybdenum, nickel, platinum, nickel platinum, alloys thereof, or combinations thereof.

18. forming an anode electrode on the metal layer; reducing the thickness of the semiconductor material layer from below the semiconductor material layer; forming a cathode electrode below the layer of semiconductor material; The method of claim 12 further comprising:

19. 20. The manufacturing method of claim 18, wherein the material of the anode electrode comprises aluminum, aluminum silicon alloy, aluminum silicon copper alloy, and the material of the cathode electrode comprises titanium nickel silver alloy.

20. The method of claim 18 , wherein the anode electrode has a flat bottom surface adjacent to the top surface of the epitaxial layer.

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