Pillar-based memory (MRAM) embedded within embedded power rails in the backside power distribution network

Abstract

The device comprises a backside power distribution network; a backside power rail coupled to the backside power distribution network; and a backside contact via connecting at least one front end of a line transistor to the backside power rail; wherein the backside contact via comprises a pillar-based memory device.

Description

[Background technology]

[0001] The exemplary embodiments described herein relate generally to semiconductor device and integrated circuit designs, and more specifically to pillar-based memory (MRAM) integrated within embedded power rails in backside power distribution networks.

[0002] In some systems, there may be integration of MRAM devices and TSVs, placing the MRAM significantly farther away from the respective transistors. However, placing MTJs close to the transistors is necessary to minimize RC delay in last-level cache applications, replacing eDRAM. Also, in some systems, the MRAM devices are not directly connected to the backside contacts connected to the transistors, whereas it may be advantageous to directly connect the MRAM to the backside contacts connected to the transistors, for example, to improve upon that described in U.S. Pat. No. 10,916,583 B2. Summary of the Invention

[0003] In one aspect, an apparatus comprises a backside power distribution network; a backside power rail coupled to the backside power distribution network; and a backside contact via coupling at least one front end of a line transistor to the backside power rail; wherein the backside contact via comprises a pillar-based memory device.

[0004] In another aspect, a method comprises forming a backside power distribution network; coupling a backside power rail to the backside power distribution network; and forming a contact via, the contact via coupling at least one front end of a line transistor to the backside power rail; wherein the contact via comprises a pillar-based memory device.

[0005] In another aspect, an apparatus comprises a transistor having a source or a drain; a backside contact coupled to the transistor; and a memory device formed on a backside of a wafer, the memory device having an electrode; wherein the electrode of the memory device is directly connected to the backside contact of the transistor.

[0006] In another aspect, a method comprises forming a first sacrificial placeholder in a first region of a wafer beneath a source or drain region of at least one transistor in the first region; forming a second sacrificial placeholder in a second region of the wafer beneath a source or drain region of at least one transistor in the second region, wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder; inverting the wafer; removing the first sacrificial placeholder to form a first free area; forming a first backside contact and electrode for a memory device at least partially in the first free area, the first backside contact contacting a source or drain of the at least one transistor in the first region; depositing and patterning the memory device at least partially in the first free area; removing the second sacrificial placeholder to form a second free area; and forming a second backside contact at least partially in the second free area, the second backside contact contacting a source or drain of the at least one transistor in the second region.

[0007] In another aspect, a semiconductor device includes: a first region having a first backside contact to couple at least one transistor in the first region to a memory device in the first region; and a second region having a second backside contact to couple at least one transistor in the second region to a backside power rail in the second region. [Brief explanation of the drawings]

[0008] The foregoing and other aspects of the exemplary embodiments will become more apparent in the following detailed description when read in conjunction with the accompanying drawing figures.

[0009] [Figure 1] Shows vias for buried power rails that are part of the backside power distribution network.

[0010] [Figure 2] A starting structure substrate with n blanket epitaxial SiGe / Si stacks is shown.

[0011] [Figure 3] Nanosheet patterning is shown.

[0012] [Figure 4] The STI layer and nanosheet stack fins are shown to form exposed.

[0013] [Figure 5] Indicates the continuation and completion of FEOL integration.

[0014] [Figure 6] 1 illustrates MOL processing including forming contacts to source drain and vias for buried power rail connection.

[0015] [Figure 7] 1 shows a cross-sectional view between gates in the source / drain area.

[0016] [Figure 8] Indicates that BEOL processing will continue.

[0017] [Figure 9] This shows the completion of BEOL processing and bonding to a carrier wafer.

[0018] [Figure 10] Flipping the wafer is shown.

[0019] [Figure 11] The starting substrate is shown thinning, stopping at the etch stop layer.

[0020] [Figure 12] The removal of the etch stop layer is shown.

[0021] [Figure 13] 10 shows etching and applying CMP to a portion of the silicon layer to expose the backside via contact.

[0022] [Figure 14] Shows recessed MRAM backside via contacts.

[0023] [Figure 15] 1 illustrates filling the backside via recess with one or more non-magnetic materials.

[0024] [Figure 16] 1 shows the application of CMP pedestal materials.

[0025] [Figure 17] Deposition of a hard mask is shown.

[0026] [Figure 18] MTJ patterning is shown.

[0027] [Figure 19] Shows encapsulation / etchback to protect MTJ sidewalls and expose block features.

[0028] [Figure 20] 1 shows selective peeling of strip block shapes.

[0029] [Figure 21] Filling with ILD followed by CMP is shown.

[0030] [Figure 22] Shown is backside ILD fill followed by buried power rail patterning and metallization.

[0031] [Figure 23] The backside power distribution network of the MRAM is shown.

[0032] [Figure 24] 1 shows a semiconductor device.

[0033] [Figure 25] The logic and MRAM regions are shown after nanosheet stack patterning, STI formation, gate patterning, BDI / spacer formation, nanosheet recess formation, and inner spacer formation.

[0034] [Figure 26] Placeholder patterning is shown.

[0035] [Figure 27] A block mask is used to open up the MRAM area and show the increased placeholder depth.

[0036] [Figure 28] Shown is a placeholder material fill.

[0037] [Figure 29] 1 shows the creation of a placeholder material recess.

[0038] [Figure 30] Source / drain epitaxy, ILD layer deposition and CMP are shown.

[0039] [Figure 31] Dummy gate removal, SiGe removal, replacement HKMG formation, MOL / BEOL interconnect formation, and carrier wafer bonding are shown.

[0040] [Figure 32] Shows wafer flip, substrate removal, and stopping on the etch stop layer.

[0041] [Figure 33] Etch stop layer and silicon removal are shown.

[0042] [Figure 34] Backside ILD deposition and CMP are shown.

[0043] [Figure 35] 10 shows exposed placeholder removal.

[0044] [Figure 36] Forming a contact including a silicide liner, an adhesion liner, and a metal fill is shown.

[0045] [Figure 37] 10 shows the fabrication of backside contact recesses.

[0046] [Figure 38] 1 shows filling of bottom electrode material for MRAM.

[0047] [Figure 39] 1 shows the MRAM stack deposition.

[0048] [Figure 40] MRAM patterning by IBE is shown.

[0049] [Figure 41] MRAM protective spacer deposition and RIE are shown.

[0050] [Figure 42] Indicates placeholder removal.

[0051] [Figure 43]1 shows backside contact filling and recessing.

[0052] [Figure 44] 1 shows backside rail formation and backside interconnect formation.

[0053] [Figure 45] 1 is a logical flow diagram illustrating a method for forming a pillar-based memory device with embedded power rails and a backside power distribution network.

[0054] [Figure 46] 1 is a logical flow diagram illustrating a method for forming a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0055] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are example embodiments provided to enable any person skilled in the art to make or use the invention and do not limit the scope of the invention, which is defined by the claims.

[0056] Described herein is a pillar-based memory (MRAM) embedded within a buried power rail in a backside power distribution network. In particular, described herein is a semiconductor structure having a buried power rail and a backside power distribution network. The structure includes a contact via connecting a FEOL transistor with the backside power rail. A pillar-based memory device is formed within the contact via. The via may include a magnetic material (such as Co). The memory may be an MRAM device. A portion of the magnetic contact via that forms the bottom contact for the MRAM device has a non-magnetic conductive spacer (e.g., TiN) between the MRAM device and the via. In other embodiments, the contact via may include a non-magnetic conductive material. Alternately, the memory may be PCM or ReRAM.

[0057] Also described herein is a method for forming pillar-based memory devices within a buried power rail and backside power distribution network.

[0058] Therefore, the examples described herein relate to MRAM integrated on the backside of the wafer, where the backside power distribution network / buried power rails reside. The non-magnetic bottom electrode contacts the MRAM device and avoids interfering with its operation.

[0059] The device described herein has high-value attributes and technical advantages. In particular, the structure forming the MRAM very close to each transistor minimizes RC delay. Possible applications are last-level cache, i.e., 14 nm, 7 nm, 5 nm, and 3 nm technology nodes. The structure can be integrated into existing unused space, so no additional space is required.

[0060] MRAM is an emerging memory technology that will be integrated into older, current, and future technology nodes (14nm and below). High-performance MRAM integration poses significant challenges at 14nm and below due to minimum vertical height. In some systems, heterogeneous integration of MRAM with TSVs allows the MRAM to be placed significantly farther away from the respective transistors, while placing MTJs closer to the transistors minimizes RC delay for last-level cache applications, making it necessary to replace eDRAM. Alternative schemes, such as skipping a level between M1 and M3, have significant integration issues and move the top contacts further away from the transistors.

[0061] The example described herein places MRAM pillars with buried power rail vias and a backside power distribution network. Some of the magnetic contact vias (e.g., Co) are replaced with non-magnetic conductive spacers (e.g., TiN), thus forming the bottom contacts of the MRAM pillars.

[0062] FIG. 1 illustrates an example of a semiconductor device 100. The semiconductor device 100 is a via to buried power rail backside power distribution network device. The BEOL 104 is bonded to the surface of a carrier wafer 102. The via 112 connects the contact 108 to the buried power rail 118. The STI 114 is formed in the initial substrate, and the buried power rail 118 is later formed. The backside via 112 is formed in the STI 114. The silicon 110 is remnant silicon from the initial silicon substrate. The backside power distribution network 120 is formed on the side of the buried power rail 118 and the ILD 116. The source / drain contact 106 is coupled to the source / drain 105, and the source / drain contact 108 is coupled to the source / drain 107.

[0063] 2 shows a starting structure substrate having n blanket epitaxial SiGe / Si stacks 216. A sacrificial etch-stop layer 204 is applied between the substrate 202 and the silicon layer 206. The sacrificial etch-stop layer 204 can include BOX, silicon germanium alloy (SiGe), or phosphorus-doped silicon (Si:P). In the example shown in FIG. 2, the silicon / SiGe nanosheet stack 216 includes four layers of SiGe (208, 210, 212, 214).

[0064] 3 shows nanosheet patterning. Several etches (302, 304, 306, 308, 310, 312) are made in a structure comprising silicon 206 and silicon / SiGe nanosheet stack 216. As shown, hard masks (314, 316, 318, 320, 322) are made on the sides of the etched silicon / SiGe nanosheet stack 216.

[0065] 4 shows the formation of an STI layer and fin exposure. An STI layer 402 is formed within the etching (302, 304, 306, 308, 310, 312) on the side of the silicon layer 206. The hard mask (314, 316, 318, 320, 322) is removed to reveal the fins (412, 414, 416, 418, 420).

[0066] 5 illustrates continuing and completing the FEOL integration: an ILD layer 502 is formed adjacent to (e.g., above) the STI layer 402 and between the epitaxy-based fins (504, 506, 508, 510, 512).

[0067] 6 illustrates the MOL process, including forming contacts to the source and drain and VBPR connections. Multiple source / drain contacts (604, 606, 608, 610, 612) are fabricated adjacent to (e.g., above) the epitaxy-based fins (504, 506, 508, 510, 512) in the ILD layer 502. Two vias (601, 602) connect the source / drain contacts (606, 610) to the silicon layer 206 through the ILD layer 502 and the STI layer 402.

[0068] 7 shows a cross-sectional view between the gates in the source / drain area. Shown is a dummy gate line 702 interrupted by a gate cut 704, as well as additional source / drain contacts (605, 607) and source / drain contact 606, and active device layers 706 across source / drain contact 604 and dummy gate line 702. Shown are cross-sectional views of source / drain contact 606, via 601, and source / drain contact 607.

[0069] 8 illustrates continuing BEOL processing. A BEOL layer 802 is formed adjacent to (e.g., above) the source / drain contacts (604, 606, 608, 610, 612). A plurality of vias (802, 804, 806, 808, 810, 812) are formed in the BEOL layer 802, where via 802 is formed on the side of source / drain contact 604, via 808 is formed on the side of source / drain contact 608, and via 812 is formed on the side of source / drain contact 612.

[0070] 9 illustrates the completion of BEOL processing and bonding to a carrier wafer. Another BEOL layer 902 is formed next to the BEOL layer 802, which is next to the vias (802, 804, 806, 808, 810, 812). The BEOL layer 902 is bonded to a carrier wafer 904.

[0071] FIG. 10 shows the flipping 1002 of wafer 1004 so that carrier wafer 900, which was previously on one side, is now on a different side and starting substrate 202, which was previously on a different side, is now on said one side.

[0072] Figure 11 shows thinning the starting substrate and stopping on the etch stop layer (buried oxide, SiGe, Si:P). The substrate 202 is thinned and removed. Figure 12 shows removing the etch stop layer 204.

[0073] FIG. 13 shows etching and applying CMP to portions of silicon layer 206 to expose via contacts (602, 601). FIG. 13 depicts an embodiment in which via contact 601 is not recessed and the pedestal / MTJ (2316 / 1802, see FIGS. 23 and 18) is located directly on via contact 601 (e.g., compare FIG. 13 without a μ-stud to FIG. 23 with a μ-stud 1504). A drawback to this embodiment is that if via contact 601 is made of a magnetic material (i.e., cobalt), the MTJ stack (2304, 2312, 1908, see FIG. 23) would need to be adjusted to compensate for the magnetic field coming from via 601. In FIG. 13, via 601 is a via for a buried power rail (2308, see FIG. 23).

[0074] 14 shows a recessed MRAM via contact 601 (e.g., a recess 1402 greater than 10 nm). Thus, the via contact 601 is recessed. In this embodiment, the recessed MRAM via contact 601 prevents magnetic field interference with possible co-connect metal (magnetic) from within the via 601 to the MTJ (1802, see FIG. 18). FIG. 14 also shows the creation of a wet-release pattern block shape 1404 (i.e., sacrificial SiN) created on the surface of the STI layer 402, a portion of the silicon layer 206, and the via contact 602.

[0075] 15 illustrates filling one or more non-magnetic materials (such as titanium (Ti), titanium nitride (TiN), titanium alloy (Ta), titanium aluminum nitride (TaN), etc.) 1502 in the via recess 1402. The one or more non-magnetic materials 1502 are also fabricated over the wet-release pattern block shape 1404, the STI layer 402, and the silicon layer 206. The one or more non-magnetic materials 1502 in the recess 1402 form μ-studs 1504.

[0076] 16 shows the application of CMP pedestal material 1602 to ensure a smooth surface coming into the MTJ deposition. This embodiment does not require the pedestal 2316 to be flush on the block shape (see, e.g., item 1604). An embodiment without recessed via contact 601 as shown in FIG. 13 would look similar, but without μ-stud 1504 formed of one or more non-magnetic materials 1502.

[0077] FIG. 17 illustrates depositing a hard mask 1702 , such as a patterned hard mask, and creating an RIE layer 1704 on top of the pedestal layer 1602 .

[0078] Figure 18 shows the patterning (IBE) to form MTJ 1802. The partially etched block shape 1404 prevents etching into the vias (e.g., 602), STI 402, and silicon 206, if desired. As shown in Figure 18, there are two etches (1804, 1806) created in the STI 402 and silicon 206.

[0079] 19 shows the encapsulation / etchback to protect the MTJ sidewalls (1904, 1906) and expose the block features 1404. The encapsulation spacers 1902 protect the sidewalls (1904, 1906) of the MTJ 1802. The MRAM 1908 is formed.

[0080] Figure 20 shows selective etching (2002) of the block features 1404 without etching the STI 402, silicon 206, at least a portion of the SiN encapsulation 1404, and via metal 602. Figure 21 shows fill with ILD 2102 followed by CMP. Figure 22 shows backside ILD fill (2102) followed by buried power rail patterning and metallization (2202, 2204, 2206). The spacers 1902 around the MTJ 1802 can be silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), or other high-quality silicon nitride (SiN) materials that can be selectively etched from the SiN blocks 1404. The block shape 1404 is a wet-removable sacrificial SiN (e.g., silicon carbonitride (SiCNH) or silicon nitride imide (SiNH) hydrogen). Wet removal is performed with diluted HF.

[0081] 23 shows an MRAM backside power distribution network 2300 including a backside power distribution network 2302 and an MRAM 2304. The MRAM backside power distribution network 2300 may be referred to as an MRAM embedded power rail, an embedded MRAM embedded power rail, or a memory embedded power rail. The embedded power rail 2308 is coupled to vias including via 601, μ-stud 1504, and pillar via 2312 including MRAM 1908. The embedded power rail 2308 is also coupled to the backside power distribution network 2302. The via 601 and μ-stud 1504 couple transistor 2314 to MRAM 1908. The pedestal 2316 is formed from the pedestal material / layer 1602.

[0082] Also described herein is MRAM integration with self-aligned backside contacts. There is great interest in forming MRAM close to the source / drain to increase speed. Backside direct contacts offer great opportunities to move MRAM very close to the device. However, there is a great risk that backsputtering of the backside contact metal will degrade MRAM yield.

[0083] In one embodiment, a method for forming a semiconductor device includes forming a sacrificial placeholder under the S / D of an MRAM transistor that is deeper than that of a logic transistor, flipping the wafer after MOL / BEOL fabrication, first removing the sacrificial placeholder in the MRAM region, forming a backside contact and a bottom electrode of the MRAM in the vacant placeholder region, depositing and patterning the MRAM stack, removing the sacrificial placeholder in the logic region, and forming the backside contact and backside interconnect. This method provides a promising solution for MRAM integration with self-aligned backside contacts.

[0084] Further described herein is a semiconductor device including an MRAM formed on the backside of a wafer, where the bottom electrode of the MRAM is directly connected to the backside contact of a transistor. The backside contact is substantially aligned with the bottom electrode of the MRAM. The backside contact is substantially aligned with the S / D of the transistor. The backside contact is separated from the gate metal by a BDI and an inner spacer. A backside contact also exists for the transistor in the logic region, where the backside contact in the logic region has a top surface that is lower than the bottom surface of the MRAM spacer.

[0085] FIG. 24 shows a semiconductor device. FIG. 24 provides a renumbering of FIG. 3C of U.S. Patent No. 10,916,583 B2. The first ("front") substrate includes front back-end layers 40 and device layer 4. The second ("back") substrate includes back-end layers 52. Front back-end layers 40 include interconnect layer 38, interconnect layer 36, and interconnect layer 32. Device layer 4 includes ILD 28 and substrate 99. Back-end layers 52 include substrate 50, interconnect layer 54, and interconnect layer 58.

[0086] The interconnect layer 38 includes interconnects 34 and interconnects (bit lines) 35 that connect to the reference layer of the interconnect layer 36. The interconnect layer 36 includes a SHE-MRAM 42, which includes a reference layer, a barrier layer, a free layer, and a spin filter. The spin filter of the interconnect layer 36 is coupled to an interconnect 34 of the interconnect layer 32. The interconnect 34 is shared by the interconnect layer 32 and the ILD 28 and is coupled to the gate 24 of the ILD 28. The gate 24 of the ILD 28 is coupled to a logic transistor 12 in the substrate 99, which includes a source 16 and a drain 20.

[0087] 24 , the MRAM device 60 is not directly connected to the backside contact 2. FIG. 24 contrasts with the semiconductor device shown in FIG. 44 , which is the result of the semiconductor fabrication method described herein. FIG. 44 shows that the MRAM device 4414 is directly connected to the backside contact 3602.

[0088] 25 shows logic region 2501 of wafer 2551 and MRAM region 2502 of wafer 2551 after nanosheet stack patterning, STI formation, gate patterning, BDI / spacer formation, nanosheet recess formation, and interior space formation. Logic region 2501 includes silicon substrate 2503, etch stop layer 2505 (such as BOX, SiO2, or SiGe), and silicon layer 2507. Logic region 2501 further includes BDI layer 2509 and silicon layer 2515 for bonding dummy gate 2517 to SiGe 2511, where the SiGe is contained within interior spacer 2513. Spacer 2521 encapsulates dummy gate 2517 and hard mask 2519. Structures 2525 and 2527 are constructed similarly (ie, contain similar components) to structure 2523, which includes SiGe 2511, inner spacer 2513, Si 2515, dummy gate 2517, hard mask 2519, and spacer 2521.

[0089] MRAM region 2502 includes a silicon substrate 2504, an etch stop layer 2506 (such as BOX, SiO2, or SiGe), and a silicon layer 2508. MRAM region 2502 further includes a BDI layer 2510 and a silicon layer 2516 for coupling a dummy gate 2518 to SiGe 2512, where the SiGe is contained within an interior spacer 2514. A spacer 2522 encapsulates dummy gate 2518 and hard mask 2520. Structures 2526 and 2528 are constructed similarly (i.e., include similar components) to structure 2524, which includes SiGe 2512, interior spacer 2514, Si 2516, dummy gate 2518, hard mask 2520, and spacer 2522.

[0090] FIG. 26 shows the application of OPL layer 2601 in logic region 2501 and OPL layer 2602 in MRAM region 2502, and placeholder patterning, including etching placeholder regions 2603 in BDI layer 2509 and possibly silicon layer 2507 in logic region 2501 and placeholder regions 2604 in BDI layer 2510 and possibly silicon layer 2508 in MRAM region 2502.

[0091] Figure 27 illustrates the use of a block mask to open MRAM region 2502 to increase the placeholder depth in region 2604. The depth of placeholder region 2604 relative to the MRAM is increased by the amount indicated generally by item 2702. Figure 27 also illustrates the application of OPL layer 2704 between structures 2523 and 2525 in placeholder region 2603 of logic region 2501. Figure 27 also illustrates the removal of OPL to create placeholder region 2706 in MRAM region 2502.

[0092] 28 shows placeholder material fillers (e.g., titanium oxide (TiOx) or aluminum oxide (AlOx)). Placeholder filler 2801 is applied to logic region 2501, and placeholder filler 2802 is applied to MRAM region 2502.

[0093] FIG. 29 illustrates the creation of placeholder material recesses by removing a portion of placeholder fill 2801 to create placeholder 2901 and a portion of placeholder fill 2802 to create placeholder 2902.

[0094] 30 shows S / D epitaxy formation, ILD layer deposition, and CMP. S / D epitaxy 3001 and S / D epitaxy 3003 are formed in logic region 2501, and S / D epitaxy 3002 and S / D epitaxy 3004 are formed in MRAM region 2502. S / D epitaxy 3001 is formed in S / D region 3011, and S / D epitaxy 3002 is formed in S / D region 3012. ILD 3005 is formed adjacent to (e.g., above) S / D epitaxy 3001, ILD 3007 is formed adjacent to (e.g., above) S / D epitaxy 3003, ILD 3006 is formed adjacent to (e.g., above) S / D epitaxy 3002, and ILD 3008 is formed adjacent to (e.g., above) S / D epitaxy 3004. Hard mask 2519 and hard mask 2520 are removed, as are the hard masks from structures 2525, 2526, 2527, and 2528.

[0095] 31 illustrates dummy gate removal, SiGe removal, replacement high-k / metal gate (HKMG) formation, MOL / BEOL interconnect formation, and carrier wafer bonding. In particular, dummy gates 2517 and 2518 are removed, as are dummy gates from structures 2525, 2526, 2527, and 2528. SiGe 2511 and SiGe 2512 are removed. HKMG3107, HKMG3109, HKMG3111, HKMG3108, HKMG3110, and HKMG3112 are formed to replace the removed dummy gates and SiGe. In logic region 2501, forming BEOL 3103 bonds carrier wafer 3101 to an additional ILD layer 3113 formed next to (e.g., above) HKMG 3107, HKMG 3109, and HKMG 3111. BEOL 3103 is also coupled to contacts 3105 coupled to S / D epitaxy 3003. Source / drain contacts 3105 are formed within ILD layer 3113 and ILD 3007. Similarly, in MRAM region 2502, forming BEOL 3104 bonds carrier wafer 3102 to an additional ILD layer 3114 formed next to (e.g., above) HKMG 3108, HKMG 3110, and HKMG 3112. BEOL 3104 is also coupled to source / drain contacts 3106 coupled to S / D epitaxy 3004. Source / drain contacts 3106 are formed within ILD layer 3114 and ILD 3008 .

[0096] 32 shows wafer flipping, substrate removal, and stopping on the etch stop layer. The logic area wafer is flipped (3201) and the MRAM area wafer is flipped (3202), resulting in inverted wafer 2551. Silicon substrate 2503 is removed from logic area 2501 (shown as item 3203), and silicon substrate 2504 is removed from MRAM area 2502 (shown as item 3204).

[0097] 33 illustrates the etch stop layer and Si removal. In particular, silicon layer 2507 is removed from logic region 2501 (shown as item 3301), and silicon layer 2508 is removed from MRAM region 2502 (shown as item 3302). Etch stop layer 2505 is removed from logic region 2501 (shown as item 3303), and etch stop layer 2506 is removed from MRAM region 2502 (shown as item 3304).

[0098] Figure 34 shows backside ILD deposition and CMP. ILD layer 3401 is formed on the backside of logic region 2501 next to BDI layer 2509, encapsulating placeholder 2901. ILD layer 3402 is formed on the backside of MRAM region 2502 next to BDI layer 2510, encapsulating placeholder 2902. Figure 35 shows the removal of the exposed placeholder to form region 3502.

[0099] Figure 36 shows forming contact 3602. Forming contact 3602 includes applying a silicide liner (3604, 3606) such as titanium and an adhesion liner titanium nitride (TiN), and a metal fill 3608 such as cobalt and CMP. Figure 37 shows creating a backside contact recess 3702. Figure 38 shows filling the MRAM in recess 3702 with bottom electrode material to create bottom electrode 3802. Figure 39 shows MRAM stack deposition 3901 in logic region 2501 and MRAM stack deposition 3902 in MRAM region 2502.

[0100] 40 shows MRAM patterning by IBE. In logic region 2501, MRAM stack deposition 3901 is removed and a portion of backside interlayer dielectric 3401 (indicated by 4001) is also removed. The benefit is that placeholder 2901 is embedded in backside interlayer dielectric 3401 so that there is no backsputtering. In MRAM region 2502, MRAM patterning involves creating regions 4002 and 4004 by removing portions of backside interlayer dielectric 3402 and MRAM stack deposition 3902. A hard mask 4006 is applied to the side of the remaining portion of MRAM stack deposition 3902.

[0101] Figure 41 shows MRAM protection spacer deposition and RIE. MRAM protection spacer 4102 is formed on the sides of hard mask 4006, MRAM stack deposition 3902, and backside interlayer dielectric 3402. Etching of backside interlayer dielectric 3402 creates regions 4104 and 4106. Figure 42 shows placeholder removal to remove placeholder 2901 from logic region 2501 to create region 4201. Figure 43 shows backside contact fill and recess to create backside contact 4301 and recess 4303.

[0102] 44 illustrates backside rail formation and backside interconnect formation. In logic region 2501, backside power rail 4401 is connected to backside contact 4301 and via 4403, which couples backside power rail 4401 to backside interconnect 4405. Backside interlayer dielectric layer 3401 is extended (4407), so that backside interlayer dielectric layers (3401, 4407) encapsulate backside power rail 4401 and via 4403. In MRAM region 2502, backside interlayer dielectric layer 3402 is extended (4408). In MRAM region 2502, via 4404 connects backside interconnect layer 4406 to MRAM stack stack 3902 through backside interlayer dielectric layer (3402, 4408) and hard mask 4006. A backside interlayer dielectric layer (3402, 4408) encapsulates at least a portion of via 4404, hard mask 4006, spacer 4102, MRAM stack stack 3902, bottom electrode 3802, and backside contact 3602. Also shown are S / D 4410 of transistor 4412, S / D 4409 of transistor 4411, and memory device 4414. In FIG. 44, MRAM device 4414 is not directly connected to backside contact 3602.

[0103] Figure 45 is a logic flow diagram 4500 illustrating a method for forming a pillar-based memory device having an embedded power rail and a backside power distribution network. At 4510, the method includes forming a backside power distribution network (2302). At 4520, the method includes coupling a backside power rail (2308) to the backside power distribution network (2302). At 4530, the method includes forming contact vias (601, 1504, 2312), the contact vias (601, 1504, 2312) coupling at least one front end of a line transistor (2314) to the backside power rail (2308). At 4540, the method includes including the contact vias (601, 1504, 2312) in the pillar-based memory device (1908).

[0104] Figure 46 is a logic flow diagram 4600 illustrating a method of forming a semiconductor device. At 4610, the method includes forming a first sacrificial placeholder (2902) in a first region (2502) of a wafer (2551) below a source or drain region (3012) of at least one transistor (4412) in the first region (2502). At 4620, the method includes forming a second sacrificial placeholder (2901) in a second region (2501) of the wafer (2551) below a source or drain region (3011) of at least one transistor (4411) in the second region (2501). At 4630, the method includes forming the first sacrificial placeholder (2902) deeper within the wafer (2551) than the second sacrificial placeholder (2901). At 4640, the method includes inverting (3201, 3202) the wafer (2551). At 4650, the method includes removing the first sacrificial placeholder (2902) to form a first free area (3502). At 4660, the method includes forming a first backside contact (3602) and electrode (3802) for a memory device (4414) at least partially within the first free area (3502), the first backside contact (3602) contacting a source (4410) or a drain (4410) of at least one transistor (4412) in the first region (2502). At 4670, the method includes depositing and patterning the memory device (4414) at least partially within the first free area (3502). At 4680, the method includes removing the second sacrificial placeholder (2901) to form a second open area (4201). At 4690, the method includes forming a second backside contact (4301) at least partially in the second open area (4201), the second backside contact (4301) contacting a source (4409) or a drain (4409) of at least one transistor (4411) in the second region (2501).

[0105] Referring now to all figures, in one exemplary embodiment, an apparatus comprises a backside power distribution network; a backside power rail coupled to the backside power distribution network; and a backside contact via coupling at least one front end of a line transistor to the backside power rail; wherein the backside contact via comprises a pillar-based memory device.

[0106] A portion of the backside contact via couples a source or drain to the memory device. The apparatus may further include a non-magnetic conductive spacer between the memory device and the portion of the backside contact via. The memory device may be directly connected to the portion of the backside contact via. The memory device may include at least one of: magnetoresistive memory; phase change memory; or resistive memory.

[0107] In another embodiment, a method comprises forming a backside power distribution network; coupling a backside power rail to the backside power distribution network; and forming a contact via, the contact via coupling at least one front end of a line transistor to the backside power rail; wherein the contact via comprises a pillar-based memory device.

[0108] The method may further include forming a recess in the contact via and filling the recess with at least one non-magnetic material to form a non-magnetic, electrically conductive spacer between the memory device and a non-recessed portion of the contact via. The method may further include forming the memory device, the memory device being formed by a method comprising: applying at least one non-magnetic pedestal material to a shallow trench isolation layer encapsulating at least a portion of the contact via; depositing a hard mask on the non-magnetic pedestal material; forming a magnetic tunnel junction between the non-magnetic pedestal material and the hard mask; and forming an encapsulation spacer along at least one wall of the magnetic tunnel junction. The method may further include applying a block shape to the shallow trench isolation layer, wherein the block shape prevents etching of the contact via, the shallow trench isolation layer, and a select portion of a silicon layer. The memory device may include at least one of: magnetoresistive memory; phase change memory; or resistive memory.

[0109] In another embodiment, an apparatus comprises a transistor having a source or a drain; a backside contact coupled to the transistor; and a memory device formed on a backside of a wafer, the memory device having an electrode; wherein the electrode of the memory device is directly connected to the backside contact of the transistor.

[0110] The memory device may include at least one of: magnetoresistive memory; phase change memory; or resistive memory. The backside contact may be substantially aligned with the electrode of the memory device, and the backside contact may be substantially aligned with the source or drain of the transistor. The backside contact may be separated from the gate metal of the transistor by a dielectric isolation layer and an internal spacer. The apparatus may further comprise a logic region of the wafer, the logic region being distinct from a region of the wafer having the memory device; a logic region transistor in the logic region, the logic region transistor being distinct from the transistor; and a logic region backside contact in the logic region, the logic region backside contact being distinct from the backside contact; wherein the logic region backside contact has a top surface that is lower than a bottom surface of a spacer in the region of the wafer having the memory device, and the spacer is configured to separate the backside contact from the gate metal of the transistor.

[0111] In one embodiment, a method comprises forming a first sacrificial placeholder in a first region of a wafer beneath a source or drain region of at least one transistor in the first region; forming a second sacrificial placeholder in a second region of the wafer beneath a source or drain region of at least one transistor in the second region, wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder; inverting the wafer; removing the first sacrificial placeholder to form a first free area; forming a first backside contact and electrode for a memory device at least partially in the first free area, the first backside contact contacting a source or drain of the at least one transistor in the first region; depositing and patterning the memory device at least partially in the first free area; removing the second sacrificial placeholder to form a second free area; and forming a second backside contact at least partially in the second free area, the second backside contact contacting a source or drain of the at least one transistor in the second region.

[0112] The method may further include coupling the at least one transistor in the first region to the memory device using the first backside contact; and coupling the memory device to a back end of a line interconnect using a via. The method may further include coupling the at least one transistor in the second region to a backside power rail using the second backside contact; and coupling the backside power rail to a back end of a line interconnect using a via. The first sacrificial placeholder may be formed deeper in the wafer than the second sacrificial placeholder such that a top surface of the second backside contact is lower than a bottom surface of a spacer in the first region of the wafer including the memory device, the spacer being configured to separate the first backside contact from a gate metal of the at least one transistor in the first region. The memory device may include at least one of: a magnetoresistive memory; a phase change memory; or a resistive memory.

[0113] In another embodiment, a semiconductor device comprises: a first region having a first backside contact to couple at least one transistor in the first region to a memory device in the first region; and a second region having a second backside contact to couple at least one transistor in the second region to a backside power rail in the second region.

[0114] The first backside contact may directly connect a source or drain of the at least one transistor to an electrode of the memory device. A top surface of the second backside contact may be lower than a bottom surface of a spacer in the first region including the memory device, the spacer configured to separate the first backside contact from a gate metal of the at least one transistor in the first region. The memory device may include at least one of: a magnetoresistive memory; a phase change memory; or a resistive memory. The semiconductor device may further include an electrode of the memory device, wherein the first backside contact is substantially aligned with the electrode of the memory device.

[0115] References to "computer," "processor," etc. should be understood to encompass not only computers having different architectures, such as single / multi-processor architectures and serial or parallel architectures, but also specialized circuitry, such as field programmable gate arrays (FPGAs), application specific circuits (ASICs), signal processing devices, and other processing circuitry. References to computer programs, instructions, code, etc. should be understood to encompass software or firmware for a programmable processor, e.g., the programmable contents of a hardware device, whether the instructions of a processor or the configuration settings for a fixed function device, gate array, programmable logic device, etc.

[0116] The memories described herein may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-transitory memory, transient memory, fixed memory and removable memory, etc. The memories may include databases for storing data.

[0117] As used herein, a circuit may refer to the following: (a) hardware circuit implementations, such as implementations in analog and / or digital circuitry; and (b) combinations of circuitry and software (and / or firmware), such as (where applicable) (i) a combination of a processor or (ii) a processor / software portion including a digital signal processor, software, and memory that work together to cause a device to perform various functions; and (c) a circuit such as a microprocessor or portion of a microprocessor that requires software or firmware for operation even when the software or firmware is not physically present. As a further example, as used herein, a circuit also encompasses simply an implementation of a processor (or processors) or portion of a processor and its (or their) accompanying software and / or firmware. A circuit also encompasses, for example, a baseband integrated circuit or an application processor integrated circuit for a mobile phone, or a similar integrated circuit in a server, cellular network device, or another network device, if applicable to the particular element.

[0118] A list of abbreviations, which may be joined to each other or to other characters using, for example, a dash or hyphen ("-"). ASIC application-specific integrated circuit BDI bottom dielectric isolation BEOL (back end of line) BOX Buried oxide CMP chemical mechanical planarization / polishing DHF diluted hydrofluoric acid eDRAM embedded dynamic random access memory FEOL Front End of Line FPGA: Field-programmable gate array HF hydrofluoric acid high-k high dielectric constant HKMG high-k metal gate IBE Ion beam etching ILD interlayer dielectric M metal layer, e.g., M1, M3 MOL Middle of line MRAM: magnetoresistive random access memory MTJ magnetic tunnel junction OPL organic planarization layer PCM Phase change memory RC resistance capacitance ReRAM Resistive random access memory RIE reactive-ion etching S / D source drain SHE-MRAM Spin-Hall effect MRAM Si silicon SiGe Silicon-germanium Si:P phosphorus doped epitaxial silicon sp spacer STI shallow trench isolation STT spin-transfer torque TSV (through silicon via) VBPR via to buried power rail

[0119] In the foregoing description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be understood by those skilled in the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may be omitted or not described to avoid obscuring the presented embodiments.

[0120] The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations that do not depart from the scope of the invention will be apparent to those skilled in the art. The embodiments have been chosen and described to best explain the principles and practical applications of the invention and to enable others skilled in the art to understand the invention in its various embodiments with various modifications as suited to the particular uses contemplated.

Claims

1. Backside distribution network; a backside power rail coupled to the backside power distribution network; and a backside contact via coupling at least one front end of a line transistor to the backside power rail; Provided with: wherein the backside contact via comprises a pillar-based memory device Device.

2. The apparatus of claim 1 , wherein some of the backside contact vias couple a source or a drain to the memory device.

3. The apparatus of claim 2 , further comprising a non-magnetic conductive spacer between the memory device and the portion of the backside contact via.

4. The apparatus of claim 2 , wherein the memory device is directly connected to the portion of the backside contact via.

5. The memory device: Magnetoresistive memory; Phase change memory; or Resistive memory The apparatus of claim 1 , comprising at least one of:

6. forming a rear distribution network; coupling a backside power rail to the backside power distribution network; and forming a contact via, the contact via connecting at least one front end of a line transistor to the backside power rail. Provided with: wherein the contact via comprises a pillar-based memory device. method.

7. forming a recess in the contact via; and filling the recess with at least one non-magnetic material to form a non-magnetic conductive spacer between the memory device and the non-recessed portion of the contact via. The method of claim 6 further comprising:

8. Further comprising forming the memory device, the memory device comprising: applying at least one non-magnetic pedestal material to a shallow trench isolation layer encapsulating at least a portion of the contact via; depositing a hard mask on the non-magnetic pedestal material; forming a magnetic tunnel junction between the non-magnetic pedestal material and the hard mask; and forming an encapsulation spacer along at least one wall of the magnetic tunnel junction; The method of claim 6 , wherein the method comprises:

9. 10. The method of claim 8, further comprising applying a block shape to a shallow trench isolation layer, wherein the block shape prevents etching into the contact via, the shallow trench isolation layer, and a select portion of a silicon layer.

10. The memory device: Magnetoresistive memory; Phase change memory; or Resistive memory The method of claim 6 , comprising at least one of:

11. a transistor having a source or a drain; a backside contact coupled to the transistor; and A memory device formed on the backside of the wafer, said memory device having electrodes Provided with: wherein the electrode of the memory device is directly connected to the backside contact of the transistor. Device.

12. The memory device: Magnetoresistive memory; Phase change memory; or Resistive memory The apparatus of claim 11 , comprising at least one of:

13. The apparatus of claim 11 , wherein the backside contact is substantially aligned with the electrode of the memory device, and the backside contact is substantially aligned with the source or drain of the transistor.

14. 12. The device of claim 11, wherein the backside contact is separated from the gate metal of the transistor by a dielectric isolation layer and an inner spacer.

15. a logic area of ​​the wafer, the logic area being different from an area of ​​the wafer having the memory devices; a logic region transistor within the logic region, the logic region transistor being different from the transistor; and a logic region backside contact within the logic region, the logic region backside contact being different from the backside contact; Furthermore, wherein the logic area backside contact has a top surface that is lower than a bottom surface of a spacer in the region of the wafer having the memory device, the spacer being configured to separate the backside contact from gate metal of the transistor.

12. The apparatus of claim 11.

16. forming a first sacrificial placeholder in a first region of the wafer beneath a source or drain region of at least one transistor in the first region; forming a second sacrificial placeholder in a second region of the wafer beneath a source or drain region of at least one transistor in the second region; wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder; inverting the wafer; removing the first sacrificial placeholder to form a first empty area; forming a first backside contact and electrode for a memory device at least partially within the first free area, the first backside contact contacting a source or drain of the at least one transistor in the first region; depositing and patterning the memory device at least partially within the first free area; removing the second sacrificial placeholder to form a second free space; and forming a second backside contact at least partially within the second space region, the second backside contact contacting a source or drain of the at least one transistor in the second region. A method comprising:

17. coupling the at least one transistor in the first region to the memory device using the first backside contact; and connecting the memory device to a back end of a line interconnect using vias; 17. The method of claim 16, further comprising:

18. coupling the at least one transistor in the second region to a backside power rail using the second backside contact; and connecting the backside power rail to a back end of a line-to-line interconnect using vias; 17. The method of claim 16, further comprising:

19. 17. The method of claim 16, wherein the first sacrificial placeholder is formed deeper in the wafer than the second sacrificial placeholder such that a top surface of the second backside contact is lower than a bottom surface of a spacer in the first region of the wafer including the memory device, the spacer being configured to separate the first backside contact from a gate metal of the at least one transistor in the first region.

20. The memory device: Magnetoresistive memory; Phase change memory; or Resistive memory 17. The method of claim 16, comprising at least one of:

21. a first region having a first backside contact for coupling at least one transistor in the first region to a memory device in the first region; and a second region having a second backside contact for coupling at least one transistor in the second region to a backside power rail in the second region; A semiconductor device comprising:

22. 22. The semiconductor device of claim 21, wherein the first backside contact directly connects a source or drain of the at least one transistor to an electrode of the memory device.

23. 22. The semiconductor device of claim 21, wherein a top surface of the second backside contact is lower than a bottom surface of a spacer in the first region including the memory device, the spacer being configured to separate the first backside contact from a gate metal of the at least one transistor in the first region.

24. The memory device: Magnetoresistive memory; Phase change memory; or Resistive memory 17. The method of claim 16, comprising at least one of:

25. 22. The semiconductor device of claim 21, further comprising an electrode of the memory device, wherein the first backside contact is substantially aligned with the electrode of the memory device.

Images