Video encoding method, encoder, and decoder

Abstract

A video encoding method, an encoder, and a decoder are disclosed, which are applied to a decoder and include the steps of: obtaining a bitstream corresponding to a current frame; analyzing the bitstream to obtain a current CTU of the current frame; determining availability of at least one neighboring CTU of the current CTU in the current frame based on a wavefront delay, where the wavefront delay is a row-wise delay in CTU units between the current CTU located in a current CTU row and the neighboring CTU located in an upper CTU row, where the current CTU and the neighboring CTU are decoded in parallel; determining a prediction block in at least one neighboring CTU for a current coding unit (CU) in the current CTU; and decoding the current CU using the prediction block.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. provisional patent application Ser. No. 63 / 375,031, filed Sep. 8, 2022, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD This disclosure relates generally to video coding. This disclosure relates to video coding methods, encoders, and decoders. [Background technology]

[0003] Digital video capabilities can be incorporated into a variety of devices, including digital televisions, digital live broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablets, e-readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite wireless telephones, video conferencing devices, video streaming devices, and the like.

[0004] Digital video devices implement video compression technologies developed by the Moving Picture Experts Group (MPEG)-2, MPEG-4, ITU-TH.263, ITU-TH.264, Advanced Video Coding (AVC), or High Efficiency Video Coding (HEVC), etc., to more efficiently transmit and receive digital video information. By implementing these video coding technologies, video devices can more efficiently transmit, receive, encode, decode, and / or store digital video information.

[0005] The popularity of Internet video has led to higher demands for video compression efficiency, despite the continuous evolution of digital video compression technology. Summary of the Invention

[0006] SUMMARY OF THE INVENTION Embodiments of the present application provide a video coding method, an encoder, and a decoder that are capable of decoding bitstreams in parallel using improved intra prediction.

[0007] In a first aspect, an embodiment of the present application provides a video encoding method applied to a decoder, the video encoding method including the steps of: obtaining a bitstream corresponding to a current frame, analyzing the bitstream to obtain a current coding tree unit (CTU) of the current frame, determining availability of at least one neighboring CTU of the current CTU in the current frame based on a wavefront delay, where the wavefront delay is a row-wise delay in CTU units between a current CTU located in a current CTU row and an neighboring CTU located in an upper CTU row, where the current CTU and the neighboring CTU are decoded in parallel, determining a prediction block in at least one neighboring CTU for a current coding unit (CU) in the current CTU, and decoding the current CU using the prediction block.

[0008] According to one embodiment, when decoding the first CTU in a current CTU row, the video encoding method further includes inheriting state information from a neighboring CTU that has completed decoding and is located in a CTU row above at least one row above if the wavefront delay is N CTUs, and the row-wise delay of the neighboring CTU is N-1 CTUs.

[0009] According to one embodiment, the step of determining the availability of at least one neighboring CTU of the current CTU in the current frame based on the wavefront delay includes determining the availability of at least one neighboring CTU of the current CTU located at the i-th CTU row and the j-th CTU column. i,jRegarding the case where the wavefront delay is N CTUs, when b - j ≧ (i - a) × N, it includes the step of determining that the adjacent CTU a,b located in the a-th CTU row and the b-th CTU column is unavailable.

[0010] According to one embodiment, the availability of at least one adjacent CTU of the current CTU in the current frame is determined based on the wavefront delay in response to the sequence parameter set (SPS) level syntax element being valid.

[0011] According to one embodiment, the step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on the wavefront delay is for the current CTU located in the i-th CTU row and the j-th CTU column i,j Regarding the step of determining the intra block copy (IBC) reference area, the IBC reference area includes a plurality of adjacent CTUs located within a fixed range from the current CTU i,j When the wavefront delay is N CTUs, when b - j ≧ (i - a) × N, the adjacent CTU located in the a-th CTU row and the b-th CTU column of the IBC reference area a,b is determined to be unavailable, and includes.

[0012] According to one embodiment, the IBC reference area includes adjacent CTUs satisfying (j - 2) ≦ k ≦ (j + 1) in the CTU row two rows above the i-th CTU row i-2,k and adjacent CTUs satisfying (j - 2) ≦ k ≦ (j + 1) in the CTU row one row above the i-th CTU row i-1,k and adjacent CTUs satisfying (j - 2) ≦ k ≦ (j - 1) i,k and includes.

[0013] According to one embodiment, the IBC reference area includes adjacent CTUs satisfying (j - 1) ≦ k in the CTU row one row above the i-th CTU row i-1,k and adjacent CTUs satisfying k < j i,k and includes.

[0014] According to one embodiment, the IBC reference region includes adjacent CTUs that satisfy (j - 2) ≤ k in the CTU row two rows above the i-th CTU row i-2,k and adjacent CTUs that satisfy any k in the CTU row one row above the ii-th CTU row i-1,k and adjacent CTUs that satisfy k < j i,k and.

[0015] According to one embodiment, for the current CU in the current CTU, the step of determining a prediction block in at least one adjacent CTU includes the step of decoding an IBC block vector from a bitstream and using the IBC block vector to determine a prediction block in at least one adjacent CTU within the IBC reference region for the current CU. If the IBC block vector points to a region outside the IBC reference region, or is modified to point to a region within the IBC reference region by a mapping function, or is binarized into a bounded codeword space within the limits of the IBC reference region, the IBC block vector is determined to be invalid.

[0016] In a second aspect, an embodiment of the present application provides a decoder, the decoder comprising: a communication interface, a storage device, and a processor, the communication interface configured to obtain a bitstream corresponding to a current frame, the storage device configured to store at least one computer-executable instruction, the processor coupled to the communication interface and the storage device and configured to execute the at least one computer-executable instruction to perform the following steps: analyzing the bitstream to obtain a current coding tree unit (CTU) of the current frame; determining availability of at least one neighboring CTU of the current CTU in the current frame based on a wavefront delay, the wavefront delay being a row-wise delay in CTU units between a current CTU located in a current CTU row and an neighboring CTU located in an upper CTU row, the current CTU and the neighboring CTU being decoded in parallel; determining a prediction block in the at least one neighboring CTU for a current coding unit (CU) in the current CTU; and decoding the current CU using the prediction block.

[0017] According to one embodiment, the processor is configured to, when decoding the first CTU in a current CTU row, inherit state information from a neighboring CTU located in a CTU row above at the latest after decoding has completed, if the wavefront delay is N CTUs, and the row-wise delay of the neighboring CTU is N-1 CTUs.

[0018] According to one embodiment, the current CTU located at the i-th CTU row and the j-th CTU column i,j For (a), the processor is configured to determine that adjacent CTUs a, b located in the a-th CTU row and b-th CTU column are unusable if bj≧(i a)×N when the wavefront delay is N CTUs.

[0019] According to one embodiment, the current CTU located at the i-th CTU row and the j-th CTU columni,j The processor determines an IBC reference region, the IBC reference region being the current CTU. i,j and bj≧(ia)×N when the wavefront delay is N CTUs. a,b is unavailable.

[0020] According to one embodiment, the processor is configured to: decode an IBC block vector from a bitstream; and determine, for a current CU, a prediction block in at least one neighboring CTU within an IBC reference region using the IBC block vector. The IBC block vector is determined to be invalid if it points to a region outside the IBC reference region, or if it is modified by a mapping function to point to a region within the IBC reference region, or if it is binarized to a bounded codeword space within the limits of the IBC reference region.

[0021] In a third aspect, an embodiment of the present application provides a video encoding method applied to an encoder, the video encoding method including: obtaining a current frame of a video; dividing the current frame into a plurality of CTUs; determining availability of at least one neighboring CTU of the current CTU in the current frame based on a wavefront delay, where the wavefront delay is a row-wise delay in units of CTUs between a current CTU located in a current CTU row and an neighboring CTU located in an upper CTU row, and the current CTU and the neighboring CTU are coded in parallel; performing intra prediction on a current CU of the current CTU to obtain a prediction block from the at least one neighboring CTU; and encoding a block vector pointing to the prediction block into a bitstream corresponding to the current frame.

[0022] According to one embodiment, the step of determining the availability of at least one neighboring CTU of the current CTU in the current frame based on the wavefront delay includes determining the availability of at least one neighboring CTU of the current CTU located at the i-th CTU row and the j-th CTU column. i,j For example, if bj≧(i a)×N when the wavefront delay is N CTUs, determining that adjacent CTUs a and b located in the a-th CTU row and b-th CTU column are unusable.

[0023] According to one embodiment, the step of determining the availability of at least one neighboring CTU of the current CTU in the current frame based on the wavefront delay includes determining the availability of at least one neighboring CTU of the current CTU located at the i-th CTU row and the j-th CTU column. i,j determining an IBC reference region for the current CTU; i,j and bj≧(ia)×N when the wavefront delay is N CTUs. a,b and determining that the is unavailable.

[0024] In a fourth aspect, an embodiment of the present application provides an encoder, the encoder comprising: a communication interface, a storage device, and a processor. The communication interface is configured to obtain a current frame of a video. The storage device is configured to store at least one computer-executable instruction. The processor is coupled to the communication interface and the storage device and executes the at least one computer-executable instruction to include: dividing the current frame into a plurality of CTUs; determining availability of at least one neighboring CTU of the current CTU in the current frame based on a wavefront delay, the wavefront delay being a row-wise delay in CTU units between a current CTU located in a current CTU row and an neighboring CTU located in an upper CTU row, the current CTU and the neighboring CTU being coded in parallel; performing intra prediction on a current CU of the current CTU to obtain a prediction block from the at least one neighboring CTU; and encoding a block vector pointing to the prediction block into a bitstream corresponding to the current frame.

[0025] According to one embodiment, the current CTU located at the i-th CTU row and the j-th CTU column i,j For (a), the processor is configured to determine that adjacent CTUs a, b located in the a-th CTU row and b-th CTU column are unusable if bj≧(i a)×N when the wavefront delay is N CTUs.

[0026] According to one embodiment, the current CTU located at the i-th CTU row and the j-th CTU column i,j The processor determines an IBC reference region, the IBC reference region being the current CTU. i,j and bj≧(ia)×N when the wavefront delay is N CTUs. a,b is unavailable.

[0027] According to one embodiment, the residual reconstruction unit reconstructs the residual level of each color component of the plurality of points by calculating the product of the decoded symbol multiplied by the absolute level of the decoded level of the residual level of the color component. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a schematic diagram of a video encoding system according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of a video decoding system according to an embodiment of the present disclosure. [Figure 3A] FIG. 1 is a schematic diagram of dividing an image into blocks called CTUs according to an embodiment of the present disclosure. [Figure 3B] FIG. 1 is a schematic diagram of dividing a CTU into CUs according to an embodiment of the present disclosure. [Figure 4A] FIG. 1 is a schematic diagram illustrating the propagation of CABAC and toning board predictors according to an embodiment of the present disclosure. [Figure 4B] FIG. 1 is a schematic diagram illustrating a wavefront of a WPP according to an embodiment of the present disclosure. [Figure 5A] FIG. 1 is a schematic diagram illustrating an extended IBC reference region according to an embodiment of the present disclosure. [Figure 5B] FIG. 1 is a schematic diagram illustrating an extended IBC reference region according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic diagram of a hardware structure of a decoder provided in an embodiment of the present application according to an embodiment of the present disclosure. [Figure 7] 1 is a flowchart of an encoding method applied to a decoder according to an embodiment of the present disclosure. [Figure 8] FIG. 10 is a schematic diagram illustrating availability of adjacent blocks of wavefront delay according to an embodiment of the present disclosure. [Figure 9] 1 is a flowchart of an encoding method applied to a decoder according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram illustrating availability of adjacent blocks of wavefront delay according to an embodiment of the present disclosure. [Figure 11] FIG. 10 is a schematic diagram illustrating availability of adjacent blocks of wavefront delay according to an embodiment of the present disclosure. [Figure 12] 1 is a flowchart of an encoding method applied to a decoder according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a schematic diagram of a hardware structure of an encoder according to an embodiment of the present disclosure. [Figure 14] 1 is a flowchart of a video encoding method applied to a decoder according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] Aspects of the present disclosure can be best understood from the foregoing detailed description with reference to the drawings. It should be understood that, according to industry practice, features are not drawn to scale. In fact, the dimensions of features may be arbitrarily increased or decreased for clarity of discussion.

[0030] In order to understand the features and technical contents of the embodiments of the present application in more detail, the following detailed description of the embodiments of the present application will be given with reference to the drawings, which are for reference and explanation only and are not intended to limit the embodiments of the present application.

[0031] This disclosure proposes several aspects of a method for modifying the reference regions of the Intra Block Copy (IBC) tool and regular intra prediction tools to support the Wavefront Parallel Processing (WPP) feature. These aspects include enabling WPP through state propagation and CTU availability restrictions, modifying the reference region for intra prediction, and processing IBC block vectors. The proposed method can be used in future video coding standards.

[0032] Encoding a video involves encoding each frame of the video into a bitstream, frame by frame. Similarly, decoding a video bitstream after the video has been encoded and compressed involves decoding the bitstream, frame by frame. Each frame may also be called an image, and the video may be called an image sequence. To efficiently compress the video, the bitstream order may differ from the order in which the images are displayed, and therefore the decoding order of the images may differ from the display order of the images. Typically, the images are reordered into a hierarchy suitable for compression, such as for groups of 8, 16, or 32 images.

[0033] Modern international video coding standards typically describe a block-based hybrid scheme for decoding a bitstream. For example, the High Efficiency Video Coding (HEVC) standard and the Versatile Video Coding (VVC) standard are block-based hybrid spatial and temporal predictive coding schemes. That is, to generate such a bitstream when encoding each image, the image must be divided into multiple blocks and each of these blocks must be coded one by one. For hardware implementation reasons, an image is typically first divided into largest coding units (LCUs) or coding tree units (CTUs) with the same size of N×N pixels, and these units are arranged in raster scan order from one side of the image to the other. Next, each CTU is further divided into multiple blocks called coding units (CUs), which do not necessarily have the same size. Therefore, encoding a video image sequence involves sequentially encoding each CU of each image, and decoding the bitstream of a video image sequence involves sequentially decoding each CU of each picture, ultimately reconstructing the entire video image sequence.

[0034] In order to adapt to the different image contents and attributes of each part in the image, the most effective coding can be performed accordingly. The size of the CU in the image can be different, such as 8x8 pixels, 64x64 pixels, etc. The shape of the CU can be rectangular, and in one image, each CU can have a different shape and size.

[0035] For example, first, an image is divided into CTUs of the same size of 64x64 pixels, i.e., N=64. Here, one CTU consists of three CUs of 32x32 pixels and four CUs of 16x16 pixels, and another CTU consists of two CUs of 32x32 pixels, three CUs of 16x16 pixels, and 20 CUs of 8x8 pixels. One CU can be further divided into several sub-regions. The sub-regions include, but are not limited to, prediction units (PUs) and transform units (TUs). As described above, a coding block or a decoding block refers to a region in an image to be coded or decoded.

[0036] 1 is a schematic block diagram of a video encoding system according to an embodiment of the present disclosure. As shown in FIG. 1, the video encoding system 100 includes a transform and quantization unit 101, an intra estimation unit 102, an intra prediction unit 103, a motion compensation unit 104, a motion estimation unit 105, an inverse transform and inverse quantization unit 106, a filter control analysis unit 107, a filtering unit 108, an entropy coding unit 109, and a decoded image buffer unit 110. The filtering unit 108 may perform one or more in-loop filtering operations, such as deblocking, sample adaptive offset (SAO), adaptive loop filtering (ALF) based on Wiener filter estimation, bilateral filtering, and neural network loop filtering (NNLF). The entropy coding unit 109 may perform header information coding and context-based adaptive binary arithmetic coding (CABAC).

[0037] For an input video, coding tree units (CTUs) can be obtained through a first-stage partitioning, and a CU can be obtained by applying content adaptive partitioning to one CTU. A CU is composed of one or more coding blocks (CBs), where each coding block corresponds to one color component of the video. Next, for residual pixel information obtained after intra-prediction or inter-prediction, the video coding block is transformed by a transform and quantization unit 101. This transformation includes converting the residual information from the pixel domain to the transform domain and quantizing the resulting transform coefficients to further reduce the bit rate.

[0038] The intra estimation unit 102 and the intra prediction unit 103 are configured to perform intra prediction coding on the coding block. In one example, the intra estimation unit 102 and the intra prediction unit 103 are configured to determine an intra prediction mode to be used for coding the coding block. The motion compensation unit 104 and the motion estimation unit 105 are configured to perform inter prediction coding of the received coding block according to one or more blocks in one or more reference frames to provide temporal prediction information. The motion estimation performed by the motion estimation unit 105 is a process of generating motion vectors, which can estimate the motion of the coding block. The motion compensation unit 104 is configured to perform motion compensation based on the motion vectors determined by the motion estimation unit 105. After determining the intra prediction mode, the intra prediction unit 103 is further configured to provide the selected intra prediction data to the entropy coding unit 109, and the motion estimation unit 105 is configured to send the calculated motion vector data to the entropy coding unit 109.

[0039] The inverse transform and inverse quantization unit 106 is configured to reconstruct the coding block. After reconstructing the residual block in the pixel domain and removing the blocking effect of the reconstructed residual block by the filter control analysis unit 107 and the filtering unit 108, the reconstructed residual block is added to the prediction of the image in the decoded image buffer unit 110 to generate a reconstructed video coding block. The entropy coding unit 109 is configured to encode various coding parameters and quantized transform coefficients. In a CABAC-based coding algorithm, the context may be based on neighboring coding blocks, and the entropy coding unit 109 is configured to encode information indicating the determined intra-prediction mode and output a bitstream of the video signal. The decoded image buffer unit 110 is configured to store the reconstructed coding block for reference in the prediction. As the image coding progresses, reconstructed coding blocks are continuously generated and stored in the decoded image buffer unit 110.

[0040] 2 is a schematic block diagram of a video decoding system according to an embodiment of the present disclosure. As shown in FIG. 2, the video decoding system 200 includes, but is not limited to, an entropy decoding unit 201, an inverse transform and inverse quantization unit 202, an intra prediction unit 203, a motion compensation unit 204, a filtering unit 205, and a decoded image buffer unit 206. The entropy decoding unit 201 can perform header information decoding and CABAC. The filtering unit 205 can perform one or more in-loop filtering operations, such as deblocking, sample adaptive offset (SAO), adaptive loop filtering (ALF) based on Wiener filter estimation, bilateral filtering, and neural network loop filtering (NNLF).

[0041] After the input video signal is coded, a bitstream of the video signal is output. This bitstream is input to a video decoding system 200. First, decoded transform coefficients are obtained by an entropy decoding unit 201. The decoded transform coefficients are processed by an inverse transform and inverse quantization unit 202 to generate a residual block in the pixel domain. An intra prediction unit 203 may be configured to generate prediction data for a currently coded block based on a determined intra prediction mode and data from a previously decoded block of a current frame or image.

[0042] The motion compensation unit 204 is configured to determine prediction information for a decoded block by analyzing the motion vectors and other related syntax elements, and to use this prediction information to generate a prediction for the coded block being decoded. The decoded block is formed by summing the residual block from the inverse transform and inverse quantization unit 202 with the corresponding prediction generated by the intra prediction unit 203 or the motion compensation unit 204. The filtering unit 205 can remove blocking effects in the decoded video signal and improve video quality. The decoded block is then stored in a decoded image buffer unit 206. The decoded image buffer unit 206 is configured to store reference images for subsequent intra prediction or motion compensation, and to output a video signal, i.e., a reconstructed original video signal is obtained.

[0043] 3A is a schematic diagram of dividing an image into blocks called CTUs according to an embodiment of the present disclosure. As shown in FIG. 3A, an image of one frame is divided into multiple regions of the same size according to rows and columns, and each region is called a CTU, where the length of a side of a CTU may be 128 pixels, 64 pixels, etc. The division is strictly performed in the horizontal and vertical directions, so there is no overlap between CTUs.

[0044] For example, the CTU 300 is a block of 128 x 128 pixels. Each CTU 300 in an image may be divided into one or more CUs (coding units) and used for prediction and transformation.

[0045] 3B is a schematic diagram of dividing a CTU into CUs according to an embodiment of the present disclosure. As shown in FIG. 3B, unlike HEVC, in VVC, CUs 302 may be rectangular or square and can be coded without further division into prediction units or transform units. Each CU 302 may be the same size as the root CTU 300 or may be subdivided into 4x4 blocks of the root CTU 300.

[0046] VVC employs many new coding tools, which are described in detail below.

[0047] In this disclosure, encoding is intended to mean encoding and decoding methods and systems.

[0048] The CTUs in each image are arranged in a regular grid, and in this disclosure, CTUs are referred to by their position within the grid, so that i,j represents the CTU located at the i-th CTU row and the j-th CTU column. In this disclosure, the index of the CTU grid starts from 0, so for example, the CTU at the top left corner of the image is CTU 0,0 In the example of Figure 3A, the CTUs of the entire image are decoded in raster scan order. As each CTU is decoded, the CABAC arithmetic decoder decodes syntax elements from the bitstream and correspondingly updates the context that models the probability distributions of these syntax elements. The updated context is then used to decode the next CTU in raster scan decoding order.

[0049] One advantage of this context update policy is that with each decoded CTU, the context modeling gradually adapts and learns to the video signal statistics. However, this also introduces an order dependency on the raster scan decoding order. As a result of this dependency, all CABAC decoding must be performed sequentially, and the speed of the decoding process is practically limited by the performance of the decoder core. High data rates, e.g., high resolution, high frame rate video sequences, place high demands on decoder throughput.

[0050] An image may be divided into independent decoded units, such as slices or tiles. In such cases, a decoder with relatively low throughput can decode a single slice / tile in parallel, however, at the expense of significant compression loss.

[0051] [Wavefront Parallel Processing] VVC provides an alternative mechanism called Wavefront Parallel Processing (WPP) to achieve parallel decoding at the cost of lower compression efficiency.

[0052] When the SPS level syntax element sps_entropy_coding_sync_enabled_flag is enabled, the relationship between CTUs is modified in two ways.

[0053] 4A is a schematic diagram illustrating the propagation of CABAC and a toning plate predictor according to an embodiment of the present disclosure. As shown in FIG. 4A, first, the inheritance of state information between CTUs, which is normally performed in raster scan order, is modified. At the beginning of each CTU row, instead of inheriting state information from the CTU row immediately above that has completed decoding, the state information is inherited from the first CTU in the CTU row immediately above that has completed decoding. The state information may consist of the CABAC context and the toning plate predictor when the toning plate encoding tool is enabled, as described above, but the present disclosure is not limited thereto.

[0054] Second, when you enable the syntax element sps_entropy_coding_sync_enabled_flag, you modify the availability of neighboring CTUs for prediction. Typically, the current CTU is i,j adjacent CTUs are determined to be unavailable.

[0055] a. This neighboring CTU is located outside the image boundary. For example, CTU -1,0 is not available.

[0056] b. This adjacent CTU is currently a CTU i,j and located in different slices or tiles.

[0057] c. This neighboring CTU is the current CTU in the raster scan decoding order. i,j It is located after the CTU. i,j+1 is not available.

[0058] When the syntax element sps_entropy_coding_sync_enabled_flag is enabled, the availability of CTUs for prediction is further restricted in another case: neighboring CTUs a,b If the column position of the CTU in is greater than the current CTU, i.e., b>j, then the CTU a,b is not available.

[0059] The restriction of the syntax element sps_entropy_coding_sync_enabled_flag allows decoding of the bitstream in a parallel structure called Wavefront Parallel Processing (WPP).

[0060] 4B is a schematic diagram illustrating a wavefront of a WPP according to an embodiment of the present disclosure. i,j , CTU i-1,j+1 , CTU i-2,j+2 , and CTU i-3,j+3 The diagonal cascade set of CTUs can be decoded in parallel.i,j Decryption is CTU i-1,j+1 This means that this neighboring CTU is marked as unavailable for prediction and the state information (such as the CABAC context) is not available for the CTU. i-1,j This is because it is inherited from

[0061] In the example of Figure 4B, the maximum number of decoder cores capable of parallel processing is min(X,Y), where X is the number of CTU columns in the image and Y is the number of CTU rows in the image. Compared to slicing or tiling, WPP has less impact on compression efficiency because prediction and state propagation can still be performed in a limited way across CTU rows.

[0062] [Intra-block duplication] One of the intra prediction tools available in the VVC standard is Intra Block Copy (IBC). When predicting a CU using IBC, the corresponding block vector is used to determine the location of the predicted block. In VVC, the predicted block is obtained from a virtual IBC buffer whose size is 256x128 in luma samples. For a typical CTU whose size is 128x128 pixels, the virtual IBC buffer is two CTUs. Because a CU coded with IBC cannot be predicted from blocks other than the IBC buffer, this IBC buffer can also be called a "reference region" or "search region."

[0063] In an exploratory effort to enhance compression beyond VVC, it has been proposed to extend the reference region of the IBC to the current CTU row and the two CTU rows above.

[0064] 5A is a schematic diagram illustrating an extended IBC reference area according to an embodiment of the present disclosure. As shown in FIG. 5A, the extended reference area 52 is indicated by a shaded area. That is, the current CTU i,j If block CU1 in is predicted by IBC, any CTU from the CTU row two rows above that satisfies k≧j−2 i-2,k You can also refer to any CTU from the CTU line above. i-1,kmay refer to any CTU from the current CTU row that satisfies k≦j-1. i,k In this embodiment, the CTU i-2,j+1 The predicted block PB1 is used as a predictor for decoding the block CU1.

[0065] Although any block in the extended IBC reference region can be referenced by an IBC block vector, it is not practical for the encoder to determine the block vector by exhaustive search. For example, in the Enhanced Compression Software Model (ECM), the encoder performs a full sample-by-sample search only in the "local search region 52a" indicated by the solid-line CTU. The local search region 52a is the region of any CTU in the CTU row two rows above that satisfies (j-2) ≤ k ≤ (j+1). i-2,k , any CTU in the CTU row one row above that satisfies (j-2)≦k≦(j+1) i-1,k , and any CTU that satisfies (j-2)≦k≦(j-1). i,k Equivalently, the local search region 52a is composed of CTU i-2,j-2 , CTU i-2,j-1 , CTU i-2,j , CTU i-2,j+1 , CTU i-1,j-2 , CTU i-1,j-1 , CTU i-1,j , CTU i-1,j+1 , CTU i,j-2 , and CTU i,j-1 It consists of:

[0066] To limit the memory buffering load, we propose to extend the IBC reference region to only the current CTU row and the CTU row one above as a special case when the CTU size is 256x256 pixels.

[0067] 5B is a schematic diagram illustrating an extended IBC reference area according to an embodiment of the present disclosure. As shown in FIG. 5B, the extended reference area 54 is indicated by the hatched area. i,jIf a block in is predicted by IBC, any CTU from the CTU row above that satisfies k ≥ j-1 i-1,k may refer to any CTU from the current CTU row that satisfies k≦j-1. i,k In this embodiment, the CTU i-1,j+1 The predicted block PB2 is used as a predictor for decoding the block CU2.

[0068] Similar to the general situation described above with reference to Fig. 5A, the ECM encoder performs a full search of IBC block vectors only in the local search region 54a indicated by the CTU drawn with solid lines in Fig. 5B. That is, if the CTU size is 256x256, the local search region 54a is i-1,j-1 , CTU i-1,j , and CTU i,j-1 It consists of:

[0069] [decoder] 6 is a schematic diagram of a hardware structure of a decoder provided in an embodiment of the present application according to an embodiment of the present disclosure. Referring to FIG. 6, the decoder 60 includes a communication interface 62, a storage device 64, and a processor 66 coupled to the communication interface 62 and the storage device 64 via a bus system 68.

[0070] The communication interface 62 may be, but is not limited to, a network card supporting a wired network connection such as Ethernet, a wireless network card supporting wireless communication standards such as IEEE (Institute of Electrical and Electronics Engineers) 802.11n / b / g / ac / ax / be, or other network connection device. The communication interface 62 is configured to obtain a bitstream corresponding to a current frame.

[0071] Storage device 64 may be volatile or nonvolatile memory, or may include both volatile and nonvolatile memory. Nonvolatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. Storage device 64, as described herein, is configured to store at least one computer-executable instruction.

[0072] The processor 66 is coupled to the communication interface 62 and the storage device 64 via a bus system 68. It can be appreciated that the bus system 68 is used as a data bus to realize the connection and communication between these components. In addition to a data bus, the bus system 68 can also be a power bus, a control bus, and a status signal bus, or a combination thereof, but this embodiment is not limited to these.

[0073] As can be understood, each component in this embodiment may be integrated into one processing unit, or each component may exist physically separately, or two or more components may be integrated into one component.

[0074] Figure 7 is a flowchart of an encoding method applied to a decoder according to an embodiment of the present disclosure. Referring to Figures 6 and 7, the method of this embodiment is applied to the decoder 60 of Figure 6. In the following, detailed steps of the exemplary encoding method of the present disclosure as well as components of the decoder 60 are described.

[0075] In step S702, the processor 66 uses the communication interface 62 to obtain the bitstream corresponding to the current frame.

[0076] In step S704, processor 66 parses the bitstream to obtain the current coding tree unit (CTU) of the current frame.

[0077] In step S706, processor 66 determines the availability of at least one adjacent CTU of the current CTU in the current frame based on a wavefront delay, where the wavefront delay is a delay in CTU units in the row direction between the current CTU located in the current CTU row and the adjacent CTU located in the CTU row one row above, and the current CTU and the adjacent CTU are decoded in parallel.

[0078] In some embodiments, when decoding the first CTU in a current CTU row, if the wavefront delay is N CTUs, processor 66 can inherit state information from a decoded neighboring CTU located at least one row above, where the row delay of the neighboring CTU is N-1 CTUs, thereby enabling wavefront parallel processing (WPP). Examples of state information include, but are not limited to, CABAC context, a toning plate predictor, and persistent Rice parameters.

[0079] It should be noted that in this disclosure, a first aspect of the disclosure proposes a general implementation of the WPP feature. Define the wavefront delay as N, where N is the delay in CTUs between the decoding "wavefront" in CTU row i and the decoding wavefront in the next CTU row i+1. Then, when enabling a high-level syntax element (such as sps_entropy_coding_sync_enabled_flag), the video encoding and resulting bitstream are modified in two ways.

[0080] a. At the beginning of each CTU row i, instead of inheriting state information from the last CTU in the CTU row immediately above, the CTU immediately after the decoding of the CTU row immediately above is completed is used. i-1,N-1 Inherits state information from

[0081] b. The availability of neighboring CTUs for prediction is further restricted in another situation: if bj ≥ (i a) × N, then the neighboring CTUs a,b is currently CTU i,j are marked as not usable as predictors for

[0082] 8 is a schematic diagram illustrating the availability of adjacent blocks of wavefront delay according to an embodiment of the present disclosure. Referring to FIG. 8, since the wavefront delay is defined as N, the available area (including area A and area B, where area B is the IBC reference area) is delimited by a solid line, and the unavailable area (i.e., area C) is delimited by a dashed line.

[0083] It should be noted that when N = 1, the above restrictions allow the WPP feature of VVC. The availability restriction of CTU (disabled when bj ≥ ia) is less restrictive than VVC (disabled when b > j), but the implementation of the WPP feature is still allowed.

[0084] By setting the wavefront delay N to different values, a trade-off can be made between compression efficiency and parallelism. A higher N value results in higher compression efficiency because more CTUs can be accommodated before state information propagates to the next CTU row, and a larger area in the image is marked as available for prediction. However, a higher N value can also reduce the number of parallel decoder cores that can be used to decode the image. If X is the number of CTU columns in the image and Y is the number of CTU rows in the image, then the maximum number of decoder cores that can operate in parallel is

number

[0085] Return to the flow of FIG. 7. At step S708, the processor 66 determines a prediction block in at least one adjacent CTU for the current coding unit (CU) within the current CTU.

[0086] Finally, at step S710, the processor 66 decodes the current CU using the prediction block.

[0087] Based on the above, the present disclosure provides a modification of wavefront parallel processing (WPP) by restricting adjacent CTUs for prediction, whereby a bitstream can be decoded by a plurality of low-cost decoder cores, improving the decoding throughput.

[0088] In a second aspect of the present disclosure, when the syntax element sps_entropy_coding_sync_enabled_flag is enabled, the intra prediction tool is restricted to match the area available for prediction, and this area needs to permit WPP. When combined with the first aspect, the IBC reference area of the CTU i,j is modified to the common set of the extended reference area as shown in FIG. 5A and the area available for the CTU as shown in FIG. 8, thereby obtaining the IBC reference area B shown in FIG. 8. More generally, when the syntax element sps_entropy_coding_sync_enabled_flag is enabled, the intra prediction tools are all restricted to the area available for prediction. For example, the IBC reference area can be further extended to more CTU rows or the shape can be modified, but still must be masked to the common set with the area available for prediction.

[0089] For example, when the wavefront delay N = 1, the IBC reference area of the block within the current CTU i,j is any CTU satisfying j - 2 ≦ k < j + 2 in the CTU row two rows above, i-2,k any CTU satisfying k < j + 1 in the CTU row one row above​​i-1,k and any CTU in the current CTU row that satisfies k < j i,k Modify it to. When the wavefront delay N = 3, the current CTU i,j The IBC reference area of the blocks within is any CTU that satisfies j - 2 ≤ k < j + 6 in the CTU two rows above the i-th CTU row i-2,k Any CTU that satisfies k < j + 4 in the CTU row one row above the i-th CTU row i-1,k and any CTU that satisfies k < j i,k Modify it to.

[0090] FIG. 9 is a flowchart of an encoding method applied to a decoder according to an embodiment of the present disclosure. Referring to FIGS. 6 and 9, the method of this embodiment is applied to the decoder 60 of FIG. 6. Below, the detailed steps of an exemplary encoding method of the present disclosure will be described together with the components of the decoder 60.

[0091] In step S902, the processor 66 uses the communication interface 62 to obtain the bitstream corresponding to the current frame.

[0092] In step S904, the processor 66 analyzes the bitstream to obtain the current coding tree unit (CTU) of the current frame.

[0093] In step S906, the processor 66 determines the IBC reference area, and the IBC reference area includes a plurality of adjacent CTUs located within a fixed range from the current CTU i,j For example, the local search area in FIG. 5 is determined as the IBC reference area.

[0094] In step S908, when the wavefront delay is N CTUs, if b - j ≥ (i - a) × N, the adjacent CTU located at the a-th CTU row and the b-th CTU column of the IBC reference area of the processor 66 a,bDetermine that it is unusable. In some embodiments, the IBC reference region is modified by removing the unusable determined CTU. For example, determine the region B in FIG. 8 as the modified IBC reference region.

[0095] In step S910, the processor 66 determines a prediction block in the modified IBC reference region of the current coding unit (CU) within the current CTU.

[0096] Finally, in step S912, the processor 66 decodes the current CU using the prediction block.

[0097] Based on the above, the present disclosure provides a modification of the IBC reference region and WPP. This enables compatibility between the IBC reference region and WPP, and extends the IBC reference region to enable improved intra prediction.

[0098] For the special case where the CTU size is 256×256 pixels, modify the IBC reference region to the common set of the extended reference region as shown in FIG. 5B and the region available for prediction as shown in FIG. 8. For example, when the wavefront delay N = 1, the IBC reference region of the blocks within the current CTU i,j is modified to any CTU in the CTU row one row above that satisfies j - 1 ≦ k < j + 1, i-1,k and any CTU in the current CTU row that satisfies k < j. i,k

[0099] In some embodiments, by combining the second aspect with the limitation by the syntax element sps_entropy_coding_sync_enabled_flag in VVC, the IBC reference region of the CTU i,j is obtained.

[0100] In another embodiment, step S908 is modified to make the unusable rule the same as the VVC standard. That is, when b > j, the adjacent CTU located in the a-th CTU row and the b-th CTU column a,b ​is not available. FIG. 10 is a schematic diagram showing the availability of adjacent blocks of wavefront delay according to this embodiment of the present disclosure. Referring to FIG. 10, when the wavefront delay N = 1, the IBC reference area of the block within the current CTU i,j is modified to any CTU satisfying j - 2 ≦ k ≦ j in the CTU row two rows above, i-2,k any CTU satisfying k ≦ j in the CTU row one row above, i-1,k and any CTU satisfying k < j in the current CTU row. i,k Since the IBC reference area is smaller than that shown in FIG. 8, the compression performance may decrease. However, in order to facilitate implementation and buffer management, it may be desirable to use an IBC reference area having a regular shape as shown in FIG. 10.

[0101] In some embodiments, when disabling the syntax element sps_entropy_coding_sync_enabled_flag, first, the IBC reference area can be reduced to the local search area shown in FIGS. 5A and 5B. When reducing the IBC reference area, generally the compression performance of the IBC tool may decrease. Nevertheless, there are several reasons why this arrangement is desirable.

[0102] First, the degradation of compression performance can be reduced because the local search region is composed of spatially close CTUs, and these CTUs are more likely to provide the best predictor for the current block. Second, because the local search region has a fixed size in CTU units, the IBC buffer needs depend only on the CTU size. This may be more important than the IBC reference region for requirements design and hardware implementation because the IBC reference region depends not only on the CTU size but also on the width of a CTU row. Third, when the syntax element sps_entropy_coding_sync_enabled_flag is enabled, the WPP feature can be preserved without further restricting the IBC reference region. For example, when the first embodiment is implemented with delay N=2, further restriction of the IBC reference region is not necessary. When the first embodiment is implemented with delay N=1, when the syntax element sps_entropy_coding_sync_enabled_flag is enabled, the IBC reference region is similarly modified to the intersection with the available region for prediction.

[0103] 11 is a schematic diagram showing an embodiment of reducing the original IBC reference region to the local search region 52a described in FIG. 5A. When the syntax element sps_entropy_coding_sync_enabled_flag is disabled, the IBC reference region is set equal to the local search region 52a, and the IBC reference region is i-2,j-2 , CTU i-2,j-1 , CTU i-2,j , CTU i-2,j+1 , CTU i-1,j-2 , CTU i-1,j-1 , CTU i-1,j , CTU i-1,j+1 , CTU i,j-2 , and CTU i,j-1 When the syntax element sps_entropy_coding_sync_enabled_flag is enabled and the wavefront delay N=1, the availability of neighboring CTUs for prediction is limited by the unavailable area (i.e., area C') delimited by the dashed line and the available area (i.e., area A') delimited by the solid line. The IBC reference area is modified to area B', which includes neighboring CTUs. Area B' is the area of ​​the CTU.i-2,j-2 , CTU i-2,j-1 , CTU i-2,j , CTU i-2,j+1 , CTU i-1,j-2 , CTU i-1,j-1 , CTU i-1,j , CTU i,j-2 and CTU i,j-1 It consists of:

[0104] In some embodiments of the second aspect, when the syntax element sps_entropy_coding_sync_enabled_flag is enabled, the reference region of the IBC tool is reduced to match the region available for prediction, regardless of the value of the syntax element sps_entropy_coding_sync_enabled_flag. For example, the reduced IBC reference region in FIG. 8 or FIG. 10 is always available for the IBC tool. While this reduces the potential compression efficiency of the IBC tool, this restriction may be more desirable for encoder implementations. When enabling or disabling the syntax element sps_entropy_coding_sync_enabled_flag, the change in reference region means that the encoder needs to implement two independent IBC search algorithms to maximize coding gain. In practice, it may be more desirable to optimize a single search algorithm for the reduced IBC reference region.

[0105] In a third aspect of the present disclosure, the binarization of an IBC block vector written to a bitstream is not constrained to coincide with the IBC reference region described in the second aspect, but a value of the block vector that points outside the IBC reference region is invalid. For example, the binarization of an IBC block vector may be located in an unbounded codeword space, or in a bounded codeword space whose maximum value exceeds the range of the IBC reference region. A codeword in which the IBC vector has a value that points outside the IBC reference region is invalid in the bitstream.

[0106] In some embodiments, to determine the IBC block vectors, the values ​​written to the bitstream can be passed to a mapping function, where the function can generate only block vectors that point inside the IBC reference region. For example, the function can clip the codeword values ​​or apply a modulo operation to force the block vectors to be legal.

[0107] In some embodiments, IBC block vectors can be binarized into a bounded codeword space that does not allow transmission of block vectors that point outside the IBC reference region.

[0108] Figure 12 is a flowchart of an encoding method applied to a decoder according to an embodiment of the present disclosure. With reference to Figures 6 and 12, the method of this embodiment is applied to the decoder 60 of Figure 6. In the following, detailed steps of the exemplary encoding method of the present disclosure as well as components of the decoder 60 are described.

[0109] In step S1202, the processor 66 uses the communication interface 62 to obtain the bitstream corresponding to the current frame.

[0110] In step S1204, processor 66 parses the bitstream to obtain the current coding tree unit (CTU) of the current frame.

[0111] In step S1206, processor 66 determines the IBC reference region, which is the current CTU. i,j It includes multiple adjacent CTUs located within a fixed range of

[0112] In step S1208, if bj≧(i a)×N when the wavefront delay is N CTUs, processor 66 selects the adjacent CTU located in the a-th CTU row and the b-th CTU column of the IBC reference region. a,b determines that the

[0113] In step S1210 of this embodiment, processor 66 decodes IBC block vectors from the bitstream rather than determining the prediction block using samples in the modified IBC reference region.

[0114] In step S1212, processor 66 uses the IBC block vector to determine a prediction block in a neighboring CTU in the IBC reference region relative to the current CU.

[0115] In some embodiments, if an IBC block vector points to an area outside the IBC reference area, the IBC block vector is determined to be invalid. For example, the horizontal component of the IBC block vector is transmitted in 3 bits, with values ​​0 to 5 indicating an area within the IBC reference area and values ​​6 and 7 indicating an area outside the IBC reference area. In this case, the horizontal components {110, 111} of the binarized IBC block vector with values ​​6 and 7 are determined to be invalid.

[0116] In some embodiments, a mapping function modifies an IBC block vector to point to a region within the IBC reference region. For example, assuming that the horizontal components of an IBC block vector are transmitted using 3 bits, the decoded values ​​can be clipped to max(x, 5), thereby maintaining the original values ​​of the binarized horizontal components {000, 001, 010, 011, 100, 101} and clipping the value of the binarized horizontal component {110, 111} to 5. In another example, assuming that the horizontal components of an IBC block vector are transmitted using 3 bits, a modulo operator x%6 can be applied, thereby maintaining the original values ​​of the binarized horizontal components {000, 001, 010, 011, 100, 101} and modifying the value of the binarized horizontal component {110} to 0 and modifying the value of the binarized horizontal component {110} to 1.

[0117] In some embodiments, IBC block vectors are binarized into a codeword space, which is bounded within the limits of the IBC reference region. For example, assume that the horizontal component of an IBC block vector can take values ​​between 0 and 5, and values ​​6 or 7 refer to a region outside the IBC reference region. Binary codewords truncated as follows are used to create a codeword space bounded by the allowed values ​​of the horizontal component: {000=0, 001=1, 010=2, 011=3, 10=4, 11=5}.

[0118] [Encoder] 13 is a schematic diagram of a hardware structure of an encoder according to an embodiment of the present disclosure. Referring to FIG. 13, an encoder 130 includes a communication interface 132, a storage device 134, and a processor 136 coupled to the communication interface 132 and the storage device 134 via a bus system 138.

[0119] As can be understood, the hardware configuration of the communication interface 132, the storage device 134, the processor 136, and the bus system 138 is similar to the hardware configuration of the communication interface 62, the storage device 64, the processor 66, and the bus system 68 in FIG. 6, and therefore will not be described again here.

[0120] In this embodiment, the communication interface 132 is configured to obtain a current frame of video, and the processor 136 is configured to perform the following video encoding method by executing computer-executable instructions stored in the storage device 134:

[0121] Figure 14 is a flowchart of a video encoding method applied to a decoder according to an embodiment of the present disclosure. Referring to Figures 13 and 14, the method of this embodiment is applied to the encoder 130 shown in Figure 13. In the following, detailed steps of the exemplary encoding method of the present disclosure, along with the components of the encoder 120, are described.

[0122] In step S1402, the processor 136 uses the communication interface 132 to obtain the current frame of the video.

[0123] In step S1404, the processor 136 divides the current frame into a plurality of CTUs.

[0124] In step S1406, processor 136 determines the availability of at least one adjacent CTU of the current CTU in the current frame based on a wavefront delay, where the wavefront delay is a row-wise delay in CTU units between the current CTU located in the current CTU row and the adjacent CTU located in the CTU row one row above, and the current CTU and the adjacent CTU are coded in parallel.

[0125] In step S1408, the processor 136 performs intra prediction on the current CU of the current CTU to obtain a prediction block from at least one neighboring CTU.

[0126] In step S1410, the processor 136 encodes the block vector pointing to the prediction block into the bitstream corresponding to the current frame.

[0127] As described above, in the video coding method, encoder, and decoder of the present disclosure, modifications are described to maintain compatibility with WPP features by intra prediction of reference domains, especially by IBC prediction, so that the bitstream can be decoded by multiple low-cost decoder cores, and the decoding throughput can be improved.

[0128] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover all modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A video encoding method applied to a decoder, The steps include obtaining the bitstream corresponding to the current frame, analyzing the bitstream to obtain the current coded tree unit (CTU) of the current frame, A step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on wavefront delay, wherein the wavefront delay is a row-direction CTU-unit delay between the current CTU located in the current CTU row and an adjacent CTU located in the CTU row one row above, and the current CTU and the adjacent CTU are decoded in parallel. The steps include determining a prediction block in at least one adjacent CTU for the current coding unit (CU) within the current CTU, A video encoding method comprising the step of decoding the current CU using the prediction block.

2. The aforementioned video encoding method is When decoding the first CTU in the current CTU row, if the wavefront delay is N CTUs, the process further includes inheriting state information from an adjacent CTU located at the latest one row above, after decoding is complete, wherein the row-direction delay of the adjacent CTU is N-1 CTUs. The video encoding method according to claim 1.

3. The step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on the wavefront delay is: The current CTU located in the i-th CTU row and j-th CTU column ｉ，ｊ Regarding When the wavefront delay consists of N CTUs, and b - j ≥ (i - a) × N, the step includes determining that adjacent CTUs a and b located in the a-th CTU row and b-th CTU column are unavailable. The video encoding method according to claim 1.

4. The availability of at least one adjacent CTU of the current CTU in the current frame is determined based on the wavefront delay in response to the activation of a Sequence Parameter Set (SPS) level syntax element. The video encoding method according to claim 1.

5. The step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on the wavefront delay is: The current CTU located in the i-th CTU row and j-th CTU column ｉ，ｊ Regarding A step of determining an intrablock replication (IBC) reference region, wherein the IBC reference region is the current CTU ｉ，ｊ A step including multiple adjacent CTUs located within a fixed range, When the wavefront delay is N CTUs, if b - j ≥ (i - a) × N, then adjacent CTUs located in the a-th CTU row and b-th CTU column of the IBC reference region ａ，ｂ The step of determining that it is unavailable, The video encoding method according to claim 1.

6. The IBC reference region is the adjacent CTU row two rows above the i-th CTU row where (j-2) ≤ k ≤ (j+1) ｉ－２，ｋ And, in the CTU row one row above the i-th CTU row, the adjacent CTU row where (j-2) ≤ k ≤ (j+1) ｉ－１，ｋ And, adjacent CTUs such that (j-2) ≤ k ≤ (j-1) ｉ，ｋ and, including The video encoding method according to claim 5.

7. The IBC reference area is an adjacent CTU satisfying (j−1)≦k in the CTU row that is one row above the i-th CTU row ｉ－１，ｋ and an adjacent CTU satisfying k<j ｉ，ｋ comprising the above. The video encoding method according to claim 5.

8. The IBC reference region is the adjacent CTU in the CTU row two rows above the i-th CTU row where (j-2) ≤ k. ｉ－２，ｋ And, in the CTU row one row above the i-th CTU row, adjacent CTUs satisfying any k ｉ－１，ｋ And, adjacent CTUs where k < j ｉ，ｋ and, including The video encoding method according to claim 5.

9. The step of determining a prediction block in at least one adjacent CTU for the current CU within the current CTU is: The steps include decoding an IBC block vector from the bitstream, The step of determining a predicted block in at least one adjacent CTU within the IBC reference region for the current CU using the IBC block vector, If the IBC block vector points to a region other than the IBC reference region, or is modified by a mapping function to point to a region within the IBC reference region, or is binarized into a bounded codeword space within the limits of the IBC reference region, the IBC block vector is determined to be invalid. The video encoding method according to claim 5.

10. It is a decoder, It comprises a communication interface, a storage device, and a processor. The aforementioned communication interface is configured to acquire the bitstream corresponding to the current frame. The memory device is configured to store at least one computer-executable instruction. The processor is configured to perform the video encoding method described in any one of claims 1 to 9. decoder.

11. A video encoding method applied to an encoder, Steps to get the current frame of the video, The steps include dividing the current frame into multiple coding tree units (CTUs), A step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on wavefront delay, wherein the wavefront delay is a row-direction CTU-unit delay between the current CTU located in the current CTU row and an adjacent CTU located in the CTU row one row above, and the current CTU and the adjacent CTU are encoded in parallel. The steps include performing intraprediction on the current coding unit (CU) of the current CTU and obtaining a prediction block from at least one adjacent CTU, A video encoding method comprising the step of encoding a block vector pointing to the prediction block into a bitstream corresponding to the current frame.

12. The step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on the wavefront delay is: The current CTU located in the i-th CTU row and j-th CTU column ｉ，ｊ Regarding When the wavefront delay consists of N CTUs, and b - j ≥ (i - a) × N, the step includes determining that adjacent CTUs a and b located in the a-th CTU row and b-th CTU column are unavailable. The video encoding method according to claim 11.

13. The step of determining the availability of at least one adjacent CTU of the current CTU in the current frame based on the wavefront delay is: The current CTU located in the i-th CTU row and j-th CTU column ｉ，ｊ Regarding A step of determining an intrablock replication (IBC) reference region, wherein the IBC reference region is the current CTU ｉ，ｊ A step including multiple adjacent CTUs located within a fixed range, When the wavefront delay is N CTUs, if b - j ≥ (i - a) × N, then adjacent CTUs located in the a-th CTU row and b-th CTU column of the IBC reference region ａ，ｂ The step of determining that it is unavailable, The video encoding method according to claim 11.

14. It is an encoder, It comprises a communication interface, a storage device, and a processor. The aforementioned communication interface is configured to acquire the current frame of the video. The storage device is configured to store at least one computer-executable instruction, The processor is configured to perform the video encoding method according to any one of claims 11 to 13. Encoder.

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