Resistance change memory with a resistance spreading layer

Abstract

To limit resistance variations across a resistive memory (RRAM) cell, the present disclosure includes an RRAM cell having a resistance spreading layer within the RRAM cell between the top and bottom electrodes of the RRAM cell. The resistance spreading layer is in series with the filament-forming layer of the RRAM cell and has no impedance therewith. The resistance spreading layer may be below the filament-forming layer or above the filament-forming layer. The resistance spreading layer may also be in series with the bottom electrode or the top electrode and has no impedance therewith.

Description

[Background technology]

[0001] The present disclosure relates generally to the field of semiconductor device technology, and more particularly to a resistive random-access memory (RRAM) cell that includes a resistive spreading layer located between a top electrode and a bottom electrode.

[0002] Metal-insulator-metal (MIM) devices can be utilized within integrated circuits. MIM devices include a MIM dielectric positioned between metal plates that form the electrodes of the MIM device. MIM devices are used in a variety of applications, such as dynamic random-access memory (DRAM) capacitors and decoupling capacitors, and RRAM devices.

[0003] A typical RRAM device includes a typical RRAM cell with a filament-forming layer in series and no impedance to both electrodes. The filament-forming layer is usually insulating, but can be made conductive by the formation of filaments or conductive paths after a sufficiently high voltage is applied. The conductive paths can result from various mechanisms, including the movement of vacancies or metal defects. Once a filament is formed, it can be reset (broken, becoming highly resistive) or set (reformed, becoming less resistive) by another voltage. Thus, in one operating state, there is at least one current path through the filament-forming layer.

[0004] As conventional RRAM cells are utilized in conventional high-voltage applications, such high voltages are typically reduced at the input electrode of the RRAM cell. A solution to this problem is exemplarily illustrated in the prior art RRAM cell 100 of FIG. 1A and the prior art circuit of FIG. 1B, in which the voltage at the RRAM cell 100 is stepped down or reduced by a large compliance resistor (e.g., a transistor). The compliance resistor is typically placed in series with the RRAM cell 100 to relatively reduce the voltage seen by the RRAM cell 100. The compliance resistor is traditionally placed external to the RRAM cell 100 (i.e., not internally between the top electrode 106 and the bottom electrode 110). The RRAM cell 100 and circuitry can result in relatively narrow filaments 104 (e.g., relatively few oxygen vacancies during their formation), which can result in relatively large resistance variations between filaments 104 within the same or different RRAM cells 100. This resistance variation can make these known techniques and structures unsuitable or otherwise undesirable for high voltage applications. Summary of the Invention

[0005] In some embodiments of the present disclosure, a resistive random access memory (RRAM) cell is presented. The RRAM cell includes a bottom electrode underlying and in direct contact with a resistance spreading layer. The RRAM cell further includes a top electrode overlying and in direct contact with a filament-forming layer. A current passes through the top electrode, generating a filament in the filament-forming layer that electrically connects a bottom portion of the top electrode to a top portion of the resistance spreading layer. In the resistance spreading layer, the current propagates radially from the top portion of the resistance spreading layer to the bottom portion of the resistance spreading layer and flows into the bottom electrode.

[0006] In some implementations, there is no impedance between the entire top surface of the filament-forming layer and the entire bottom surface of the upper electrode. Similarly, there may be no impedance between the entire bottom surface of the filament-forming layer and the entire top surface of the resistance spreading layer. Similarly, there may be no impedance between the entire bottom surface of the resistance spreading layer and the entire top surface of the lower electrode.

[0007] The sidewalls of the bottom electrode, the resistance spreading layer, the filament-forming layer, and the top electrode may be coplanar. The resistance spreading layer may be between the top electrode and the bottom electrode. In some implementations, the top electrode may be a titanium nitride (TiN) top electrode, the bottom electrode may be a TiN bottom electrode, the filament-forming layer may be a transition metal oxide filament-forming layer, and the resistance spreading layer may be an aluminum carbide (AlC) resistance spreading layer.

[0008] In some embodiments of the present disclosure, another resistive random access memory (RRAM) cell is presented. The RRAM cell includes a top electrode overlying and in direct contact with a resistance spreading layer. The RRAM cell further includes a bottom electrode underlying and in direct contact with a filament-forming layer. A current passes through the bottom electrode, generating a filament in the filament-forming layer that electrically connects the top of the bottom electrode to the bottom of the resistance spreading layer. In the resistance spreading layer, the current propagates radially from the bottom of the resistance spreading layer to the top of the resistance spreading layer and flows into the top electrode.

[0009] In some implementations, there is no impedance between the entire lower surface of the filament-forming layer and the entire upper surface of the bottom electrode. Similarly, there is no impedance between the entire upper surface of the filament-forming layer and the entire lower surface of the resistance spreading layer. Similarly, there is no impedance between the entire upper surface of the resistance spreading layer and the entire lower surface of the top electrode.

[0010] In some implementations, the sidewalls of the bottom electrode, the resistance spreading layer, the filament-forming layer, and the top electrode are coplanar. The resistance spreading layer is between the top electrode and the bottom electrode. In some implementations, the top electrode is a titanium nitride (TiN) top electrode, the bottom electrode is a TiN bottom electrode, the filament-forming layer is a transition metal oxide filament-forming layer, and the resistance spreading layer is an aluminum carbide (AlC) resistance spreading layer.

[0011] In another embodiment of the present disclosure, a method for fabricating a resistive random access memory (RRAM) cell is presented. The method includes forming a bottom electrode over and vertically aligned with a bottom interconnect. The method further includes forming a filament-forming layer directly over the bottom interconnect. The method further includes forming a resistance spreading layer directly over the filament-forming layer. The method further includes forming a top electrode directly over the filament-forming layer.

[0012] In some implementations, the method further includes forming a sacrificial cap directly above the top electrode and / or forming encapsulation spacers on sidewalls of the bottom electrode, on sidewalls of the resistance spreading layer, on sidewalls of the filament-forming layer, and on sidewalls of the top electrode.

[0013] In some implementations, the method further includes forming an interlayer dielectric (ILD) over a top surface of the sacrificial cap and / or etching an upper interconnect trench in the ILD, the etching removing the sacrificial cap and exposing at least a portion of the upper electrode, and forming an upper interconnect in the upper interconnect trench over the exposed portion of the upper electrode.

[0014] These embodiments provide methods and structures for increasing the resistance between and through the top and bottom electrodes of an RRAM cell. Such high-resistance-enabled RRAM cells may be candidates for future random-access memory implementations and memory-in-logic applications such as artificial synapses. Artificial resistive synapse arrays in the form of analog resistive processing units (RPUs) have been shown to have great potential for accelerating the learning process in artificial neural networks compared to any digital solution. Resistors at each crosspoint of an RPU array constitute neuromorphic weights and are naturally programmable over a nearly linear range of conductances. For large arrays of RPUs required for high processing throughput, the required resistance at the crosspoints can be large, on the order of megaohms.

[0015] Therefore, to limit resistance variations, embodiments of the present disclosure recognize that the RRAM cell may include a resistance spreading layer in the RRAM cell between the top and bottom electrodes of the RRAM cell, in series with and without impedance to the filament-forming layer. In one embodiment, the resistance spreading layer may be below the filament-forming layer, such that the resistance spreading layer is closer to the bottom electrode than the filament-forming layer. In another embodiment, the resistance spreading layer may be above the filament-forming layer, such that the resistance spreading layer is closer to the top electrode than the filament-forming layer.

[0016] Thus, according to embodiments of the present disclosure, the current through the filament is forced to spread radially through the resistance spreading layer rather than spreading uniformly as it does through the conductive electrodes of the RRAM cell 100. As a result, a high spreading resistance exists in series with the filament, but the resistance of the filament is inversely proportional to the filament's diameter. If the resistance of the filament is much lower than the resistance of the resistance spreading layer, the total resistance between the top and bottom electrodes can be controlled by controlling the radial distance of the filaments (e.g., by controlling the number of filaments in a particular filament group) and by varying the geometry of the resistance spreading layer. In this way, the variation in the total resistance between the top electrode 206 and the bottom electrode 210 can be reduced.

[0017] According to embodiments of the present disclosure, when a current flows through a resistance spreading layer, the potential drop across it is localized, so that most of the potential drop occurs within a radial distance of a few filament diameters. As a result, by forming multiple filaments independently, spaced a few filament diameters apart, no path can steal voltage from its neighbors. In this multi-filament operating mode, the total conductance between the top and bottom electrodes is proportional to the number of filaments. Note that a large number of filaments helps reduce the variation in the total resistance between the top and bottom electrodes, which can be further controlled primarily by selecting a predetermined shape for the resistance spreading layer.

[0018] These and other aspects, features, and advantages of various embodiments of the present disclosure will become more apparent from the following description read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0019] These and other aspects, features, and advantages of various embodiments of the present disclosure will become more apparent from the following description read in conjunction with the accompanying drawings.

[0020] [Figure 1A]1 shows a cross-sectional view of a prior art RRAM cell.

[0021] [Figure 1B] 1B shows a schematic diagram of a prior art circuit including the RRAM cell of FIG. 1A.

[0022] [Figure 2] 1 illustrates a cross-sectional view of an RRAM cell including a resistance spreading layer located between a top electrode and a bottom electrode, according to an embodiment of the present disclosure.

[0023] [Figure 3] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 4] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 5] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 6] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 7] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 8] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 9] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 10] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. [Figure 11] 1A-1C are cross-sectional fabrication views of a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure.

[0024] [Figure 12]1 illustrates a cross-sectional view of an RRAM cell including a resistance spreading layer located between a top electrode and a bottom electrode, according to an embodiment of the present disclosure.

[0025] [Figure 13] 1 illustrates a method for fabricating a semiconductor device including an RRAM cell with a resistance spreading layer according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] 2-13, in which like components are labeled with like reference numerals, exemplary embodiments including semiconductor carriers, semiconductor devices, e.g., wafers, chips, integrated circuits, microdevices, etc., according to embodiments of the present disclosure are shown and will now be described in more detail below. Note that while this description refers to one component, more than one component may be shown in FIGS. 2-13. The specific number of components shown in FIGS. 2-13, and applicable structural diagram orientations or cross-sectional views, have been selected to best illustrate the various embodiments described herein.

[0027] FIG. 2 illustrates a cross-sectional view of an RRAM cell 200 including a resistance spreading layer 212 located between a top electrode 206 and a bottom electrode 210 according to an embodiment of the present disclosure.

[0028] The RRAM cell 200 is an exemplary non-volatile solid-state memory that utilizes a change in resistance across a filament-forming layer 202 upon application of an electric field. The RRAM cell 200 is programmable into two or more different states or levels that exhibit different resistance characteristics. The programmable cell states can be used to represent different data values, enabling the storage of information.

[0029] The RRAM cell 200 may include a metal-insulator-memory (MIM) structure, which includes an insulating layer (I) sandwiched between two metal (M) electrodes. A voltage pulse applied across the RRAM cell 200 can transition the device from an OFF state, generally referred to as a insulating state (HRS) or logic "0," to an ON state, generally referred to as a low-resistance state (LRS) or logic "1," and vice versa.

[0030] Typically, immediately after preparation, the RRAM cell 200 is initially in the HRS state. To switch the device from the HRS to the LRS state, applying a voltage (e.g., a high-voltage pulse) enables the formation of a conductive path, which may be called a filament 204, in the filament-forming layer 202, switching the RRAM cell 200 to the LRS state. This process, which occurs due to soft breakdown of the metal-insulator-metal (MIM) structure, is typically called "electroforming," and the voltage at which this process occurs is called the forming voltage. To switch the RRAM cell 200 from the LRS to the HRS state, a voltage pulse, called a reset voltage, may be applied.

[0031] To read data from RRAM cell 200, a read voltage that does not disturb the current state of RRAM cell 200 is applied to determine whether the cell is in a logic 0 (HRS) or logic 1 (LRS) state. Because both the LRS and HRS retain their respective values ​​even after the applied voltage is removed, RRAM cell 200 is a non-volatile memory.

[0032] The switching of the RRAM cell 200 is based on the growth of a conductive filament 204 inside the filament-forming layer 202. The conductive filament 204 can also be referred to as a channel having a diameter on the order of nanometers, which connects the top electrode 206 or the bottom electrode 210, respectively, to the resistance spreading layer 212 of the RRAM cell 200. When the conductive filament 204 is formed throughout the thickness of the filament-forming layer 202 (as shown in the figure), a low LRS with high conductivity is obtained, and when the conductive filament 204 is cut by a gap in the conductive filament 204 between both ends of the filament-forming layer 202, a high RRS is obtained.

[0033] In some implementations, the RRAM cell 200 may have more than two programmable states, allowing for the storage of more than one bit per RRAM cell 200. The different programmable states correspond to different proportions of the conductive filaments 204 across the filament-forming layer 202. In particular, the RRAM cell 200 may have intermediate states in which the RRAM cell contains different volumes of conductive filaments 204 or different numbers of conductive filaments 204. Because the LRS and HRS exhibit a large resistance contrast, varying the size of the conductive filaments 204 or increasing the number of conductive filaments 204 throughout the RRAM cell 200 correspondingly varies the resistance of the RRAM cell 200.

[0034] The RRAM cell 200 includes a bottom electrode 210, a top electrode 206, and a dual RRAM layer between the bottom electrode 210 and the top electrode 206. The dual RRAM layers are a resistance spreading layer 212 and a filament-forming layer 202. The resistance spreading layer 212 may be below the filament-forming layer 202 as shown. In this embodiment, the resistance spreading layer 212 is directly below, in series with, and in direct contact with the filament-forming layer 202. Therefore, there is substantially no electrical impedance between the resistance spreading layer 212 and the filament-forming layer 202.

[0035] In the illustrated implementation, the RRAM cell 200 may be a column, pillar, or the like. One or more sidewalls of the RRAM cell 200 may be coplanar. For example, the filament-forming layer 202 may include a side surface 203, a side surface 205, a front surface 207, and a rear surface 209. The resistance-spreading layer 212 may include a side surface 213, a side surface 215, a front surface 217, and a rear surface 219. The side surfaces 203 and 213 may be coplanar, the side surfaces 205 and 215 may be coplanar, the front surfaces 207 and 217 may be coplanar, and the rear surfaces 209 and 219 may be coplanar. The top electrode 206 and the bottom electrode 210 may have similar side surfaces, front surfaces, and rear surfaces, which may also be coplanar with the associated surfaces of the resistance-spreading layer 212 and the filament-forming layer 202, respectively. In this way, the sidewalls of the RRAM cells 200 in the shape of a pillar or column may be flush with each other.

[0036] To limit resistance variations across the RRAM cell 200, a resistance spreading layer 212 is located in the RRAM cell 200 in series between the top electrode 206 and the bottom electrode 210 without any impedance to the filament-forming layer 202. For example, there is no impedance between the entire top surface of the filament-forming layer and the entire bottom surface of the top electrode. In one example, therefore, the entire top surface of the filament-forming layer is in direct mechanical and electrical contact with the entire bottom surface of the top electrode.

[0037] Therefore, according to an embodiment of the present disclosure, the current 220 passing through the filament 204 is forced to spread radially through the resistance spreading layer 212 rather than spreading uniformly. Due to the conductive properties of the conductive electrodes 210 and 206, the current 220 spreads uniformly through each of the conductive electrodes 210 and 206. As a result, a high spreading resistance exists in series with the filament 204, but the resistance of the filament 204 is inversely proportional to the diameter of the filament 204. If the resistance of the filament 204 is much lower than the resistance of the resistance spreading layer 212, the total resistance between the top electrode 206 and the bottom electrode 210 can be controlled by varying the shape or material (e.g., thickness, etc.) of the resistance spreading layer 212 as well as controlling the diameter of the filament 204. In this way, the variation in the total resistance between the top electrode 206 and the bottom electrode 210 can be reduced.

[0038] Therefore, according to embodiments of the present disclosure, the potential drop across the resistance spreading layer 212 is localized, with most of the potential drop occurring within a radial distance of a few filament diameters. As a result, by forming multiple filaments 204 independently in the filament-forming layer 202, spaced a few filament diameters apart, no path can rob its neighbors of voltage. In this multiple filament 204 operating mode, the total conductance between the top electrode 206 and the bottom electrode 210 is proportional to the number of filaments 204. Having a large number of filaments 204 helps reduce the variation in the total resistance between the top electrode 206 and the bottom electrode 210, which can be further controlled primarily by selecting a predetermined shape or material for the resistance spreading layer 212.

[0039] 3-7 illustrate manufacturing stages for forming a semiconductor device 300. Specifically, the methods discussed with respect to FIGS. 3-7 relate to a semiconductor device 300 being fabricated to include the RRAM cell 200 shown in FIG. 2 or FIG. 12.

[0040] For purposes of the following description, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives refer to the structures and methods described as oriented in the drawing figures. The terms “overlying,” “above,” “on,” “positioned on,” or “positioned on” mean that a first element, such as a first structure, is present on a second element, such as a second structure, where an intervening element, such as an interface structure, may be present between the first and second elements. The term “direct contact” or similar terms means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements. Note that the term “selective to,” e.g., “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.

[0041] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measuring quantities based on equipment available at the time of filing. For example, substantial coplanarity between various materials can include appropriate manufacturing tolerances of ±8%, ±5%, or ±2% difference between coplanar materials.

[0042] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Furthermore, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. The various steps in the manufacturing of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or omitted entirely without providing details of the well-known processes.

[0043] Generally, the various processes used to form microchips that are packaged into ICs fall into four broad categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material on a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from the wafer. Examples include etching processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, typically by diffusion and / or ion implantation. These doping processes are followed by a furnace anneal or rapid thermal anneal (RTA). The anneal serves to activate the implanted dopants. Both conductor (e.g., polysilicon, aluminum, copper, etc.) and insulator (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used to connect and isolate transistors and their components. By selectively doping various regions of a semiconductor substrate, the conductivity of the substrate can be altered by applying a voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography creates three-dimensional relief images or patterns on semiconductor substrates so that the patterns can subsequently be transferred to the substrate. In semiconductor lithography, the patterns are formed by a photosensitive polymer called a photoresist.To build the complex structures that make up the transistors and the numerous wires that connect the circuit's millions of transistors, the lithography and etching pattern transfer steps are repeated multiple times. Each pattern printed on the wafer is aligned with a pre-formed pattern, slowly building up conductors, insulators, and selectively doped regions to form the final device.

[0044] 3 shows a cross-sectional fabrication view of a semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, underlying interconnects 350 may be formed on or within the substrate 310.

[0045] Semiconductor device 300 may be an integrated circuit (IC) chip. IC chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the IC chip may be mounted in a single-chip package (e.g., in a plastic carrier with leads secured to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., in a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the IC chip may be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product can be any product containing IC chips, ranging from toys and other low-cost applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0046] In one or more embodiments, the substrate 310 can be a semiconductor or an insulator having an active surface semiconductor layer. The substrate 310 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 310 can be essentially (i.e., excluding contaminants) a single element (e.g., silicon), predominantly (i.e., by doping) a single element, such as silicon (Si) or germanium (Ge), or the substrate 310 can include a compound, such as GaAs, SiC, or SiGe. The substrate 310 can also have multiple material layers.

[0047] In some implementations, the substrate 310 can be an inter-layer dielectric (ILD) layer beneath which additional layers and / or structures or components of the semiconductor device 300 can be prefabricated. The ILD can have a composition selected from the group consisting of silicon-containing materials such as SiO, SiN, SiON, SiC, SiCO, SiCOH, and SiCH compounds, in which Ge is substituted for some or all of the Si in these silicon-containing materials, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-containing materials, organic-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H.

[0048] The lower interconnect 350 may be formed from one or more materials, material layers, or the like utilized as IC device interconnects, such as, for example, copper, tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, or the like.

[0049] The underlying interconnect 350 may be formed in the substrate 310 using conductive interconnect fabrication techniques. For example, trenches may be formed in the substrate 310 using known photolithography techniques and then filled with the conductive material of the underlying interconnect 350. Chemical mechanical planarization or other known methods may be used to remove excess underlying interconnect 350 material from the top surface of the substrate 310 so that the top surfaces of the substrate 310 and the underlying interconnect 350 are coplanar.

[0050] The lower interconnect 350 may be electrically connected to other components of the semiconductor device 300 by one or more electrical paths. For example, one or more electrical paths (e.g., vias, wires, or the like) may connect the lower interconnect 350 to a memory controller or the like. In this manner, components of the semiconductor device 300 or components connected to the semiconductor device 300 may be electrically connected to the RRAM cell 200 via the lower interconnect 350 and / or the upper interconnect 410, as shown in FIG. 11 .

[0051] 4 shows a cross-sectional fabrication view of a semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, an encapsulation layer 320 may be formed over the substrate 310 and over the bottom interconnect 350, and a bottom electrode 330 may be formed within the encapsulation layer 320.

[0052] The encapsulation layer 320 may be a silicon-based layer, such as a silicon layer or a silicon nitride layer, and may be formed on the substrate 310 by one or more deposition processes. The bottom electrode 330 is formed in the encapsulation layer 320 by a conductive material deposition technique. For example, a trench may be formed in the encapsulation layer 320 using known photolithography techniques to expose a portion of the associated underlying wiring 350. The trench may be filled with a conductive bottom electrode 330 material. CMP or polishing may be used to remove excess bottom electrode 330 material from the top surface of the encapsulation layer 320. The bottom electrode 330 material may be any generally conductive material used as an electrode, such as tungsten, platinum, titanium nitride, tantalum nitride, titanium aluminum nitride, or the like.

[0053] In certain implementations, the trench in the bottom electrode 330 is formed through the encapsulation layer 320 to expose a portion of the top surface of the bottom interconnect 350 previously formed in the substrate 310. The bottom electrode 330 can then contact the bottom interconnect 350, thereby substantially eliminating or minimizing electrical impedance between the bottom interconnect 350 and the bottom electrode 330.

[0054] 5 shows a cross-sectional fabrication view of a semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, the build-up layers of the RRAM cell 200 are fabricated.

[0055] For example, to fabricate the RRAM cell 200 shown in FIG. 2 , a bottom electrode material layer 360 is formed on the encapsulation layer 320, a resistance spreading layer 362 is formed on the bottom electrode material layer 360, a filament forming layer 364 is formed on the resistance spreading layer 362, a top electrode material layer 366 is formed on the filament forming layer 364, and / or a capping layer 368 is formed on the top electrode material layer 366.

[0056] For example, to fabricate the RRAM cell 200 shown in FIG. 12 , a bottom electrode material layer 360 is formed on the encapsulation layer 320, a filament-forming layer 364 is formed on the bottom electrode material layer 360, a resistance spreading layer 362 is formed on the filament-forming layer 364, a top electrode material layer 366 is formed on the resistance spreading layer 362, and / or a capping layer 368 is formed on the top electrode material layer 366.

[0057] The bottom electrode material layer 360 may be formed by depositing an electrically conductive electrode material, such as titanium nitride, on the encapsulation layer 320 and / or on the electrode 330. The bottom electrode material layer 360 may be formed to a thickness of 5 to 75 nm. In a particular embodiment, the bottom electrode material layer 360 may be formed to a thickness of 20 to 30 nm.

[0058] The resistor spreading layer 362 may be formed by depositing a dielectric material such as aluminum carbide (AlC). The resistor spreading layer 362 may be formed to a thickness of 2 to 50 nm. In a particular embodiment, the resistor spreading layer 362 may be formed to a thickness of 5 to 10 nm.

[0059] The resistance spreading layer 362 should support high electric fields and current densities. For example, a 1-megaohm resistor with a 10-nm diameter filament 204 biased at 1 V experiences a current density of 1.3×10 A / cm and a maximum electric field of 2.6 MV / cm. An advantageous material is one that can withstand many programming cycles and has a very short mean free path (MFP). The short MFP ensures that resistive behavior is maintained over distances both very short and longer than the MFP, and that electrons do not gain inappropriately high energy from the electric field. A suitable material for the resistance spreading layer 362 should be highly disordered, such as an amorphous semiconductor material.

[0060] The filament-forming layer 364 is made of hafnium oxide (HfO x ), tantalum oxide (TaOx ), or titanium dioxide (TiO x The filament-forming layer 364 may be formed by depositing a filament-forming metal oxide material, such as an oxygen-deficient metal oxide layer (Oxygen Deficient Metal Oxide Layer). The filament-forming layer 364 may also be referred to as an RRAM cell insulating layer. In other embodiments, the filament-forming layer 364 may also be referred to as an oxygen-deficient metal oxide layer, a transition metal oxide layer, or the like. The filament-forming layer 364 may be formed to a thickness of 2 to 50 nm. In a particular embodiment, the filament-forming layer 364 may be formed to a thickness of 4 to 8 nm.

[0061] The top electrode material layer 366 may be formed by depositing an electrically conductive electrode material, such as titanium nitride. The top electrode material layer 366 is generally, but not necessarily, formed of the same material as the bottom electrode material layer 360. The top electrode material layer 366 may be formed to a thickness of 5 to 75 nm. In certain embodiments, the top electrode material layer 366 may be formed to a thickness of 15 to 25 nm.

[0062] The capping layer 368 may be formed by depositing a dielectric material, such as silicon nitride or the like, on the top electrode material layer 366. The capping layer 368 may be a mask layer and may be formed to a thickness of 10 to 80 nm. In a particular embodiment, the capping layer 368 may be formed to a thickness of 30 to 40 nm.

[0063] 6 shows a cross-sectional fabrication view of a semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, the RRAM cells 200 are formed by patterning the RRAM cell build-up layers, for example, by etching techniques to remove unwanted or exposed portions of the RRAM cell build-up layers and retain desired portions of the RRAM cell build-up layers to form one or more RRAM cells 200.

[0064] Photolithography techniques can be used to develop or pattern the capping layer 368 to leave a portion of the capping layer 368 on the top layer of the cell build-up layer, thereby defining the RRAM cell 200 layer underneath and protecting it from the etchants of a chemical etch or the high-energy kinetic energy beam (ions, electrons, or photons) of a dry etch. In this way, the desired underlying RRAM cell 200 layer is preserved protected, effectively forming the RRAM cell 200. The etching technique generally removes the unwanted portion of the RRAM cell 200 layer, generally exposing the field encapsulation layer 320 generally outside the formed RRAM cell 200.

[0065] The etching technique may be a physical or dry etching technique, or a chemical wet etching technique. In a preferred implementation, the etching technique is a physical dry etching technique, which reduces the risk of damaging the material of the formed RRAM cell 200 (e.g., the absence of chemical etchants allows for limited lateral etching of the layer material of the RRAM cell 200).

[0066] As shown, the formed RRAM cell 200 includes a bottom electrode 210 formed from a retention portion of a bottom electrode material layer 360, a resistance spreading layer 212 formed from a retention portion of a resistance spreading layer 362, a filament-forming layer 202 formed from a retention portion of a filament-forming layer 364, and a top electrode 206 formed from a retention portion of a top electrode material layer 366. At this stage of fabrication, the RRAM cell 200 may further include a sacrificial cap 370 formed from a retention portion of a capping layer 368.

[0067] 7 shows a cross-sectional fabrication view of semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, encapsulation layer 380 is formed on encapsulation layer 320 and on and around one or more RRAM cells 200.

[0068] The encapsulation layer 380 is a layer of dielectric material that helps prevent or limit short circuits between various layers of the RRAM cell 200. For example, the spacer 383 shown in FIG. 8 formed from the encapsulation layer 380 prevents contact between the bottom electrode 210 and the top electrode 206 through the sides of the RRAM cell 200.

[0069] The encapsulation layer 380 may be formed by depositing a dielectric, conformal, insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, amorphous carbon, aluminum nitride, or the like, over the exposed encapsulation layer 320 and over and around the RRAM cell 200. For example, the encapsulation layer 380 may be formed by depositing a blanket dielectric material layer over the previously exposed encapsulation layer 320, the sidewalls or sides of the RRAM cell 200, and over the top surface of the RRAM cell 200.

[0070] The thickness of the encapsulation layer 380 may be sufficient to protect the cell stack 380 during subsequent etching of the unwanted portions of the encapsulation spacer layer 380, thereby allowing the unwanted encapsulation spacer layer 380 to be removed from the field while remaining on the sidewalls or lateral surfaces of the RRAM cell 200. For example, the encapsulation layer 380 may be formed to a thickness of 2 to 100 nm. In particular embodiments, the encapsulation layer 380 may be formed to a thickness of 10 to 20 nm.

[0071] 8 shows a cross-sectional fabrication view of a semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, an encapsulation spacer 382 is formed from the encapsulation layer 380 around the RRAM cell 200.

[0072] The encapsulation spacer 382 can be formed by removing unwanted portions of the encapsulation layer 380 and retaining desired portions of the encapsulation layer 380 on the sidewalls of the RRAM cell 200 .

[0073] Known directional etching techniques may be used to etch or otherwise remove unwanted portions of encapsulation layer 380. These unwanted portions of encapsulation layer 380 may be generally horizontal (i.e., portions of encapsulation layer 380 that are wider than they are tall). The directional etching process may preserve desired portions of encapsulation layer 380 on the sidewalls of encapsulation layer 380. These desired portions of encapsulation layer 380 may be generally vertical (i.e., portions of the layer that are taller than they are tall), as shown in the cross-sectional view of FIG.

[0074] The etching technique may be a physical or dry etching technique, or a chemical wet etching. In a preferred implementation, the etching technique is a chemical wet etching. As such, the encapsulation layer 320 may be configured to be an etch stop. For clarity, this fabrication step may be omitted if it is desired that the ILD 390 surround the sides and top of the RRAM cell 200, as shown in FIG. 9, for example.

[0075] 9 shows a cross-sectional fabrication view of a semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, an ILD 390 is formed on the encapsulation layer 320 and around the RRAM cell 200.

[0076] The ILDs 390 may be formed, as appropriate or desired, by depositing a blanket layer of a dielectric material, such as a low-k dielectric material, over the encapsulation layer 320, the encapsulation spacers 382, ​​and the sacrificial cap 370. The ILDs 390 may be formed to a thickness that is generally greater than the height of the sacrificial cap 370 or to a thickness that is generally above the top surface of the sacrificial cap 370.

[0077] 10 shows a cross-sectional fabrication view of semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, wiring trench 404 and wiring trench 406 are formed in ILD 390.

[0078] The interconnect trenches 406, 404 may be formed by known selective removal techniques to remove unwanted portions of the ILD 390 generally above the underlying interconnect 350 and / or generally above the RRAM cell 200.

[0079] The wiring trenches 404 generally each expose at least a portion of an underlying conductive structure, such as a respective lower wiring 350. The wiring trench(es) 406 generally expose at least a portion of the top surface of the RRAM cell 200 (e.g., at least a portion of the top surface of the top electrode 206) and planarize the top surface of the encapsulation spacer 382 with the top surface of the RRAM cell 200.

[0080] In a preferred implementation, as shown, the wiring trench 406 exposes the entire top surface of the RRAM cell 200 (e.g., the top surface of the encapsulation spacer 382 and the top surface of the top electrode 206). Similarly, the wiring trench 404 exposes at least a portion of the top surface of the associated underlying wiring 350.

[0081] Etching techniques may be used to form wiring trenches 404, 406 with orthogonal sidewalls (i.e., parallel to the sidewalls of the RRAM cell 200), or may be used to form wiring trenches 404, 406 with sloped sidewalls, as shown.

[0082] According to an embodiment of the present disclosure, the top surface of the top electrode 206 can be used as an etch stop layer against which the etch that forms the wiring trench 406 stops. In this manner, the wiring trench 406 is formed using an etch stop that is embedded or otherwise included in the RRAM cell 200.

[0083] The etching technique utilized to form the wiring trench 406 may be a physical or dry etching technique, or a chemical wet etching technique. In a preferred implementation, the etching technique for forming the wiring trench 406 is a chemical wet etching technique, and the top electrode 206 is set as a wet etchant stop.

[0084] 11 shows a cross-sectional fabrication view of semiconductor device 300 according to an embodiment of the present disclosure. At this stage of fabrication, wiring 408 has been formed in wiring trench 404, and top wiring 410 has been formed in wiring trench 406.

[0085] The interconnect 408 and the upper interconnect 410 may be formed by depositing an electrically conductive material in the interconnect trenches 404 and 406, respectively.

[0086] The top wiring 410 may be directly connected to the top electrode 206, i.e., the RRAM cell 200. For example, there may be no electrical impedance between the top wiring 410 and the top electrode 206, or if any, it may be minimized. For example, the top wiring 410 may contact a portion or the entire top surface of the top electrode 206. In some implementations, the top wiring 410 contacts the entire top surface of the top electrode 206 and also contacts at least a portion of the top surface of the nearby encapsulation spacer 382.

[0087] The upper wiring 410 and 408 may be electrically connected to other components of the IC device by one or more electrical paths within the IC device. For example, one or more electrical paths may connect the upper wiring 410 to a memory controller or the like. In this manner, components of the semiconductor device 300 may be electrically connected to the RRAM cell 200.

[0088] 12 illustrates a cross-sectional view of an RRAM cell 200 including a resistance spreading layer 212 positioned between a top electrode 206 and a bottom electrode 210, according to an embodiment of the present disclosure. The RRAM cell 200 of FIG. 12 differs from that of FIG. 2 in that the relative orientations of the dual RRAM (i.e., the resistance spreading layer 212 and the filament-forming layer 202) are reversed. Furthermore, the direction of current flow through the RRAM cell 200 of FIG. 12 (e.g., from the bottom electrode 210 to the top electrode 206) may be reversed from the direction of FIG. 2 (e.g., from the top electrode 206 to the bottom electrode 210). The description of the RRAM cell 200 of FIG. 12 is similar to the description of the RRAM cell 200 of FIG. 2 and will not be repeated herein.

[0089] 13 illustrates a method 500 for fabricating a semiconductor device 300 including an RRAM cell 200 according to an embodiment of the present disclosure. The method 500 may include forming one or more RRAM cells 200 (block 502). The RRAM cells 200 may be formed on an encapsulation layer 320 and / or on a bottom electrode 330 located within the encapsulation layer 320. The RRAM cells 200 may be formed to be vertically aligned with the bottom electrode 330. For example, the associated aligned RRAM cells 200 and bottom electrodes 330 may share the same perpendicular bisector.

[0090] Forming the RRAM cell 200 may include forming a bottom electrode material layer 360 on the encapsulation layer 320 above the bottom electrode 330 (block 504). Forming the RRAM cell 200 may include forming a resistance spreading layer 362 and a filament forming layer 364 on the bottom electrode material layer 360 (block 506). The relative orientations of the resistance spreading layer 362 and the filament forming layer 364 can be selected as needed. Forming the RRAM cell 200 may further include forming a top electrode material layer 366 on the filament forming layer 364 (block 508). In some implementations, a capping layer 368 may also be formed on the top electrode material layer 366. Forming the RRAM cell 200 may further include removing portions of the bottom electrode material layer 360, the resistance spreading layer 362, the filament forming layer 364, and the top electrode material layer 366 while retaining other portions to form one or more RRAM cells 200 (block 510).

[0091] The method 500 may further include forming an encapsulation spacer 382 on the sidewalls of the RRAM cell 200 (block 512). The encapsulation spacer 382 may be formed by forming an encapsulation layer on the substrate encapsulation layer 320 and on and around the RRAM cell 200 (block 514).

[0092] The encapsulation spacer 382 may further be formed by removing unwanted portions of the encapsulation layer (block 516). For example, the unwanted portions of the encapsulation layer are etched away by chemical or physical etching. The encapsulation spacer 382 can be formed substantially by desired or retained portions of the encapsulation layer located on the sidewalls or lateral surfaces of one or more RRAM cells 200 (block 518).

[0093] The method 500 may continue with forming an upper interconnect in the RRAM cell 200 and / or on the encapsulation spacer 382 (block 520). For example, an upper interconnect 410 is formed in the ILD 390 located above the top surface of the RRAM cell 200 and above the top surface of the encapsulation spacer 382. Using the top surface of the top electrode 206 as an etch stop, an interconnect trench 406 may be formed in the ILD 390 (block 522), thereby exposing the top surface of the top electrode 206. The etching may further expose at least a portion of the top surface of the encapsulation spacer 382. The upper interconnect 410 may be formed by depositing a conductive material in the interconnect trench 406 such that the conductive material contacts the top surface of the top electrode 206 (block 524). The conductive material may further contact a portion of the encapsulation spacer 382. CMP may be used to planarize the top surfaces of the upper interconnect 410 and the ILD 390.

[0094] The descriptions of various embodiments of the present disclosure have been presented for illustrative purposes, but are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements to commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a bottom electrode underlying and in direct contact with the resistance spreading layer; an upper electrode overlying and in direct contact with the filament-forming layer; Equipped with passing a current through the top electrode to generate a filament in the filament-forming layer electrically connecting a bottom portion of the top electrode to a top portion of the resistance spreading layer; In the resistance spreading layer, the current propagates radially from the upper portion of the resistance spreading layer to the lower portion of the resistance spreading layer and flows into the lower electrode. Resistive random access memory (RRAM) cells.

2. The RRAM cell of claim 1 , wherein there is no impedance between the entire top surface of the filament-forming layer and the entire bottom surface of the top electrode.

3. 3. The RRAM cell of claim 2, wherein there is no impedance between the entire lower surface of the filament-forming layer and the entire upper surface of the resistance-spreading layer.

4. 4. The RRAM cell of claim 3, wherein there is no impedance between the entire lower surface of the resistance spreading layer and the entire upper surface of the bottom electrode.

5. The RRAM cell of claim 4 , wherein the sidewalls of the bottom electrode, the resistance spreading layer, the filament forming layer, and the top electrode are coplanar.

6. The RRAM cell of claim 1 , wherein the resistance spreading layer is between the top electrode and the bottom electrode.

7. 2. The RRAM cell of claim 1, wherein the top electrode is a titanium nitride (TiN) top electrode, the bottom electrode is a TiN bottom electrode, the filament-forming layer is a transition metal oxide filament-forming layer, and the resistance spreading layer is an aluminum carbide (AlC) resistance spreading layer.

8. a top electrode overlying and in direct contact with the resistance spreading layer; a bottom electrode below and in direct contact with the filament-forming layer; Equipped with passing a current through the bottom electrode to generate a filament in the filament-forming layer electrically connecting an upper portion of the bottom electrode to a lower portion of the resistance spreading layer; In the resistance spreading layer, the current propagates radially from the lower part of the resistance spreading layer to the upper part of the resistance spreading layer and flows into the upper electrode. Resistive random access memory (RRAM) cells.

9. The RRAM cell of claim 8 , wherein there is no impedance between the entire lower surface of the filament-forming layer and the entire upper surface of the bottom electrode.

10. 10. The RRAM cell of claim 9, wherein there is no impedance between the entire top surface of the filament-forming layer and the entire bottom surface of the resistance-spreading layer.

11. The RRAM cell of claim 10 , wherein there is no impedance between the entire top surface of the resistance spreading layer and the entire bottom surface of the top electrode.

12. The RRAM cell of claim 11 , wherein the sidewalls of the bottom electrode, the resistance spreading layer, the filament forming layer, and the top electrode are coplanar.

13. The RRAM cell of claim 8 , wherein the resistance spreading layer is between the top electrode and the bottom electrode.

14. 9. The RRAM cell of claim 8, wherein the top electrode is a titanium nitride (TiN) top electrode, the bottom electrode is a TiN bottom electrode, the filament-forming layer is a transition metal oxide filament-forming layer, and the resistance spreading layer is an aluminum carbide (AlC) resistance spreading layer.

15. forming a lower electrode on the lower wiring so as to be vertically aligned therewith; forming a filament-forming layer directly on the lower electrode; forming a resistance spreading layer directly over the filament forming layer; and forming an upper electrode directly above the filament-forming layer; A method for manufacturing a resistive random access memory (RRAM) cell, comprising:

16. forming a sacrificial cap directly above the upper electrode; The method of claim 15 further comprising:

17. forming encapsulation spacers on the sidewalls of the bottom electrode, on the sidewalls of the resistance spreading layer, on the sidewalls of the filament-forming layer, and on the sidewalls of the top electrode; The method of claim 16 further comprising:

18. forming an interlayer dielectric (ILD) on the top surface of the sacrificial cap; The method of claim 17 further comprising:

19. etching an upper interconnect trench in the ILD to remove the sacrificial cap and expose at least a portion of the upper electrode; The method of claim 18 further comprising:

20. forming an upper interconnection in the upper interconnection trench on the exposed portion of the upper electrode; The method of claim 19 further comprising:

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