MRAM structure with chiral spin-orbit torque metal electrodes

Abstract

A magnetoresistive random access memory (MRAM) structure is provided that includes a chiral spin-orbit torque (SOT) metal bottom electrode beneath a lower magnetic free layer, surrounded by a via dielectric. The chiral SOT metal bottom electrode enables charge current, spin current, and spin polarization to be in the same direction, perpendicular to the surface of the chiral SOT via structure (Figure 1).

Description

[Background technology]

[0001] This application relates to memory structures, and more particularly to magnetoresistive random access memory (MRAM) structures that include chiral spin-orbit torque (SOT) metal bottom electrodes (i.e., chiral SOT via structures).

[0002] MRAM is a nonvolatile random-access memory technology that stores data using magnetic memory elements. These elements are typically formed from two ferromagnetic plates, each capable of retaining magnetization, separated by a thin dielectric layer (i.e., a tunnel barrier layer). One of the two plates (i.e., the magnetic reference layer or pinned layer) is a magnet with its magnetic moment oriented in a specific direction, while the magnetization of the other plate (i.e., the magnetic free layer) can be changed to at least two different directions, representing different digital states such as 0 and 1 for memory applications. In MRAM, such elements are sometimes called magnetic tunnel junction (MTJ) structures. In a typical MTJ structure, the magnetization of the magnetic reference layer is fixed in one direction (e.g., upward), and the direction of the magnetic free layer can be "switched" by some external force, such as a magnetic field or a spin-spin transfer torque that generates a charge current. A smaller current (of either polarity) can be used to read the device's resistance, which depends on the relative orientations of the magnetizations of the magnetic free and magnetic reference layers. Resistance is usually higher when the magnetizations are antiparallel and lower when they are parallel (although the opposite may be true for some materials).

[0003] One type of MRAM that can use MTJ structures is spin-transfer torque (STT) MRAM. STT MRAM offers the advantages of lower power consumption and greater scalability compared to traditional MRAM, which uses magnetic fields to flip active elements. In STT MRAM, spin-transfer torque is used to flip (switch) the orientation of the magnetic free layer. In STT MRAM devices, current passing through the MTJ structure is used to switch, or "write," the bit state of the MTJ memory element. Current passing downward through the MTJ structure aligns the magnetic free layer parallel to the magnetic reference layer, while current passing upward through the MTJ structure aligns the magnetic free layer antiparallel to the magnetic reference layer. Summary of the Invention

[0004] An MRAM structure is provided that contains a chiral SOT metal bottom electrode (i.e., a chiral SOT via structure) under the lower magnetic free layer, surrounded by a via dielectric. The chiral SOT metal bottom electrode allows the charge current, spin current, and spin polarization direction to be in the same direction, perpendicular to the surface of the chiral SOT via structure. This makes SOT assistance more efficient than prior art MRAMs that contain SOT metals in which the spin current is polarized perpendicular to its transmission direction.

[0005] In one aspect of the present application, a memory structure is provided. In one embodiment, the memory structure includes a chiral SOT metal bottom electrode, a via dielectric material structure disposed laterally adjacent to the chiral SOT metal bottom electrode, and an MTJ structure disposed on top of the chiral SOT metal bottom electrode, where a magnetic free layer of the MTJ structure is disposed below a magnetic reference layer of the MTJ. The memory structure further includes a top electrode disposed on top of the MTJ structure.

[0006] In an embodiment of the present application, the chiral SOT metal bottom electrode allows the charge current direction, spin current direction, and spin polarization direction to be perpendicular to the horizontal surface of the chiral SOT metal bottom electrode. Such a chiral SOT underlayer structure can generate a spin current with a non-zero perpendicular spin polarization (due to the increased tilted interface orientation associated with the helical growth). This results in a net spin accumulation with a polarization perpendicular to the surface of the chiral SOT metal bottom electrode, which in turn couples to the free layer perpendicularly magnetized nanomagnet, initiating or assisting spin current-induced switching. This makes the SOT assistance more efficient than prior art techniques, in which the spin current is polarized perpendicular to its propagation direction.

[0007] In the embodiment of the present application, the chiral SOT metal bottom electrode is a via structure. This via structure can form the necessary tilted interface for the chiral SOT metal structure, enabling efficient conversion of charge current into spin current with large perpendicular polarization. Furthermore, the via structure under the MTJ can help eliminate any possibility of partial shunting of the MTJ tunnel barrier during the patterning process.

[0008] In an embodiment of the present application, each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode may have a cylindrical shape.

[0009] In embodiments of the present application, the magnetic free layer of the MTJ structure has a width different from the width of the chiral SOT metal bottom electrode, while in other embodiments, the magnetic free layer of the MTJ structure has a width substantially equal to the width of the chiral SOT metal bottom electrode.

[0010] In an embodiment of the present application, the memory structure further comprises an interconnect level including an interconnect dielectric material layer and a conductive structure disposed below the chiral SOT metal bottom electrode, the chiral SOT metal bottom electrode being disposed on a surface of the conductive structure. In such an embodiment, the interconnect dielectric material layer has a notch surface disposed adjacent to the conductive structure, and the via dielectric material structure is disposed on the notch surface of the interconnect dielectric material layer.

[0011] In embodiments of the present application, the chiral SOT metal bottom electrode is constructed as a bilayer or multilayer thin film structure and deposited in a pre-opened via recess to allow for a graded interface. The layer materials are selected to provide strong SOT charge-spin conversion at the interface, with at least one layer having very high spin current conductivity to propagate the spin current generated at the interface toward the free layer of the switching nanomagnet. In embodiments of the present application, examples of such chiral SOT metal bottom electrode bilayer or multilayer structures can be constructed using the form A / B or A / I / B, where A=β-Ta, β-W, Cu, x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x , Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2, TaS2, Pt x Rh 1-x or any material known to produce a large SOT charge-spin conversion efficiency, x is between 0 and 1, and B = a known good spin conductor such as Cu, Ag, or Au, and simultaneously "I" is a poor charge conductor but a good spin conductor such as NiO, FeOx, and other ferromagnetic, supermagnetic, or antiferromagnetic materials that have magnon-mediated spin conductivity but are charge insulating. The I layer in this case is used as an interface layer between A and B, facilitating spin transport but preventing charge current shunting.

[0012] In embodiments of the present application, the structure further comprises a passivation layer disposed on each sidewall of the top electrode, the MTJ structure, and the chiral SOT metal bottom electrode, and a dielectric fill material disposed on the passivation layer, the dielectric fill material having a top surface coplanar with a top surface of the top electrode.

[0013] In an embodiment of the present application, the structure further comprises an interconnect dielectric material layer disposed above the top electrode, the conductive structure being embedded in the interconnect dielectric material layer, and the conductive structure contacting a surface of the top electrode. In such an embodiment, the conductive structure has a width different from a width of the top electrode, or the conductive structure has a width equal to a width of the top electrode.

[0014] In another embodiment of the present application, a memory structure comprises an interconnect level including at least one first conductive structure embedded in a first interconnect dielectric material layer, wherein the first interconnect dielectric material has a notch surface adjacent to the at least one first conductive structure. The memory structure further comprises a chiral SOT metal bottom electrode disposed on a surface of the at least one first conductive structure, a via dielectric material structure disposed laterally adjacent to the chiral SOT metal bottom electrode and contacting the notch surface of the first interconnect dielectric material layer, and an MTJ structure disposed on top of the chiral SOT metal bottom electrode, wherein a magnetic free layer of the MTJ structure is disposed below a magnetic reference layer of the MTJ. The memory structure further comprises a top electrode disposed on top of the MTJ structure and at least one second conductive structure embedded in a second interconnect dielectric material layer disposed on top of the top electrode, wherein the at least one second conductive structure contacts the top electrode.

[0015] In this alternative embodiment, the chiral SOT metal bottom electrode allows the charge current direction, spin current direction and spin polarization direction to each be perpendicular to the horizontal surface of the chiral SOT metal bottom electrode.

[0016] In this alternative embodiment, the chiral SOT metal bottom electrode is a via structure.

[0017] In this alternative embodiment, each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode is cylindrical.

[0018] In this alternative embodiment, the magnetic free layer of the MTJ structure has a width different from the width of the chiral SOT metal bottom electrode, or the magnetic free layer of the MTJ structure has a width substantially equal to the width of the chiral SOT metal bottom electrode.

[0019] In another aspect of the present application, a method for forming a memory structure is provided. In one embodiment of the present application, the method includes the steps of forming an interconnect level including at least one conductive structure embedded in an interconnect dielectric material layer; forming at least one sacrificial dielectric material layer via structure in the interconnect dielectric material layer while physically exposing the at least one conductive structure; and forming a layer of chiral SOT metal on the physically exposed at least one conductive structure, wherein forming the layer of chiral SOT metal comprises depositing the chiral SOT metal by physical vapor deposition, and the depositing is performed while rotating the interconnect level and the at least one sacrificial dielectric material layer via structure in the same rotational direction.

[0020] The method of the present application may further comprise the steps of planarizing the layer of chiral SOT metal to provide a precursor chiral SOT metal bottom electrode, and patterning the layer of precursor chiral SOT metal bottom electrode to provide a chiral SOT metal bottom electrode, wherein the patterning step forms a notch surface in the interconnect dielectric material layer, which removes at least one sacrificial dielectric material layer via structure from the structure.

[0021] The method of the present application may further comprise forming a via dielectric material structure at a notch surface of the interconnect dielectric material layer and laterally adjacent to the chiral SOT bottom electrode.

[0022] The method of the present application may further comprise forming an MTJ structure and a top electrode on top of the chiral SOT metal bottom electrode, the MTJ structure being disposed between the chiral SOT metal bottom electrode and the top electrode, and the magnetic free layer of the MTJ structure being disposed below the magnetic reference layer of the MTJ structure. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a cross-sectional view of an exemplary structure that can be used in accordance with an embodiment of the present application, the exemplary structure including an interconnect level including at least one first conductive structure embedded in a first interconnect dielectric material layer.

[0024] [Figure 2] 2 is a cross-sectional view of the exemplary structure shown in FIG. 1 after forming a sacrificial dielectric material layer on the interconnect level.

[0025] [Figure 3A] 3A and 3B are different views of the exemplary structure shown in FIG. 2 after patterning the sacrificial dielectric material layer into at least one sacrificial dielectric material via structure, where FIG. 3A is a top view and FIG. 3B is a cross-sectional view along XX shown in FIG. 3A. [Figure 3B] 3A and 3B are different views of the exemplary structure shown in FIG. 2 after patterning the sacrificial dielectric material layer into at least one sacrificial dielectric material via structure, where FIG. 3A is a top view and FIG. 3B is a cross-sectional view along XX shown in FIG. 3A.

[0026] [Figure 4A] FIG. 3C is a cross-sectional view of the exemplary structure shown in FIG. 3B after forming a layer of chiral SOT metal on the physically exposed surface of at least one first conductive structure utilizing at least one sacrificial dielectric material layer via structure as a deposition shadow mask.

[0027] [Figure 4B] 4B is a diagram depicting the process of forming the layer of chiral SOT metal shown in FIG. 4A.

[0028] [Figure 5] FIG. 4B is a cross-sectional view of the exemplary structure shown in FIG. 4A after performing a planarization process to convert the layer of chiral SOT metal into a precursor chiral SOT metal bottom electrode.

[0029] [Figure 6] FIG. 6 is a cross-sectional view of the exemplary structure shown in FIG. 5 after forming a patterned masking stack with a patterned via in the precursor chiral SOT metal bottom electrode.

[0030] [Figure 7] FIG. 7 is a cross-sectional view of the exemplary structure shown in FIG. 6 after patterning the precursor chiral SOT metal bottom electrode to provide a chiral SOT metal bottom electrode utilizing the patterned masking stack as an etch mask, wherein the patterning removes at least one sacrificial dielectric material via structure and a portion of the precursor chiral SOT metal bottom electrode, and the patterning forms a notch surface in the first interconnect dielectric material layer.

[0031] [Figure 8] 8 is a cross-sectional view of the exemplary structure shown in FIG. 7 after forming a via dielectric material structure in the notch face of the first interconnect dielectric material layer laterally adjacent to the chiral SOT metal bottom electrode.

[0032] [Figure 9] 9 is a cross-sectional view of the exemplary structure shown in FIG. 8 after forming a magnetic material-containing stack including a blanket layer of magnetic free material, a blanket layer of tunnel barrier material, a blanket layer of magnetic reference material, and a blanket layer of top electrode material.

[0033] [Figure 10]FIG. 10 is a cross-sectional view of the exemplary structure shown in FIG. 9 after patterning the magnetic material-containing stack to provide a patterned stack consisting of an unetched remaining portion of a blanket layer of magnetic free material (hereinafter referred to as the magnetic free layer), an unetched remaining portion of a blanket layer of tunnel barrier material (hereinafter referred to as the tunnel barrier layer), an unetched remaining portion of a blanket layer of magnetic reference material (hereinafter referred to as the magnetic reference layer), and an unetched remaining portion of a blanket layer of top electrode material (hereinafter referred to as the top electrode); in this embodiment, the magnetic free layer has a width that is smaller than the width of the chiral SOT metal bottom electrode.

[0034] [Figure 11] FIG. 11 is a cross-sectional view of another exemplary structure processed according to the steps illustrated in FIGS. 1-10, where the magnetic free layer has a width greater than the width of the chiral SOT metal bottom electrode.

[0035] [Figure 12] FIG. 11 is a cross-sectional view of yet another exemplary structure processed according to the steps illustrated in FIGS. 1-10, where the magnetic free layer has a width substantially equal to the width of the chiral SOT metal bottom electrode.

[0036] [Figure 13] 11 is a cross-sectional view of the example structure shown in FIG. 10 after further MRAM device processing. DETAILED DESCRIPTION OF THE INVENTION

[0037] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings of the present application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0038] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0039] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0040] In complementary metal-oxide-semiconductor (CMOS) integration, it is desirable to have a simple two-terminal memory bit that can be driven by a field-effect transistor (FET) with limited current (<<100 μA). One category of methods proposed to improve MTJ-based memory bits is to use a SOT to generate more spin current to assist the MTJ switching under the limited charge current supply. A key challenge for the spin current generated by the SOT is to provide it with spin polarization along the perpendicularly magnetized magnetic free layer. However, conventional SOTs generate spin currents polarized perpendicular to the direction of their propagation, resulting in low SOT-assisted efficiency.

[0041] The present application solves the aforementioned problems of MTJ-containing SOTs by providing a chiral via SOT structure as the bottom metal electrode. The chiral via SOT structure of the present application generates a spin current whose spin polarization direction is significantly aligned with the current propagation direction, resulting in a high conversion efficiency of charge-spin current conversion. Therefore, a spin current with axially polarized spins along the via axis can be efficiently generated. This is achieved by a multilayer transport structure that forms a helical pattern for both charge conduction and spin current conduction. The chiral-via structure is configured as a bilayer or multilayer structure in the form of A / B or A / I / B, where A=β-Ta, β-W, Cu, x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x , Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2, TaS2, Pt x Rh 1-x A is any material known to produce large SOT charge-spin conversion efficiencies, where x is between 0 and 1; and B is a known good spin conductor, such as Cu, Ag, or Au. At the same time, "I" is a ferromagnetic, supermagnetic, or antiferromagnetic material that is a poor charge conductor but a good spin conductor, such as NiO or FeOx, and other magnon-mediated spin conductive but charge insulating materials. The I layer in this case is used as an interface layer between A and B to promote spin conduction but prevent charge current shunting. Gradually increasing the tilt of the normal to the A / B or A / I / B interface creates a gradient for the spin current that accumulates a significant component with axial (toward the helix) spin polarization, thus achieving high-efficiency conversion of charge current to axially polarized spin current, which is crucial for efficient switching of perpendicularly magnetized nanomagnets constructed above the chiral-via structure.

[0042] Referring first to Figure 1, an exemplary structure that can be used in accordance with one embodiment of the present application is shown; note that all cross-sectional views, including the one shown in Figure 1, are taken along the line XX shown in Figure 3A. The exemplary structure includes an interconnect level that includes at least one first conductive structure 12 (three are shown as an example in the drawings of the present application) embedded in a first interconnect dielectric material layer 10.

[0043] The interconnect level shown in FIG. 1 can be disposed above at least one underlying metal level (not shown) and a front-end-of-the-level (FEOL) level, also not shown. In some embodiments, the metal level can be a mid-level interconnect (MOL) level. In other embodiments, the metal level can be at least one lower interconnect level of a multi-level interconnect structure. In still further embodiments, the metal level can be a combination of a MOL level and at least one lower interconnect level of a multi-level interconnect structure. The metal level can include underlying conductive structures embedded in a layer of dielectric material. The FEOL can include a semiconductor substrate having one or more semiconductor devices (e.g., transistors, etc.) formed thereon. The metal level and the FEOL can be formed using materials and techniques known to those skilled in the art. In order not to obscure the memory structures of the present application, the materials and techniques used in providing the metal level and the FEOL will not be described herein.

[0044] The first interconnect dielectric material layer 10 can be composed of any interconnect dielectric material including, for example, silicon oxide (SiOx), silsesquioxane, C-doped oxides (i.e., organosilicates) containing atoms of Si, C, O, and H, thermosetting polyarylene ethers, or multilayers thereof. The term "polyarylene" is used in this application to refer to aryl or inertly substituted aryl moieties linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like.

[0045] The first interconnect dielectric material layer 10 may have a dielectric constant of about 4.0 or less (all dielectric constants referred to herein are measured relative to a vacuum unless otherwise specified). In one embodiment, the first interconnect dielectric material layer 10 has a dielectric constant of 2.8 or less. These dielectrics generally have lower parasitic crosstalk compared to dielectric materials with a dielectric constant greater than 4.0. The first interconnect dielectric material layer 10 may be formed by a deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or spin-on coating. The first interconnect dielectric material layer 10 may have a thickness of 50 nm to 250 nm. Other thicknesses less than 50 nm and greater than 250 nm may also be employed in the present application.

[0046] The at least one first conductive structure 12 can be composed of a conductive metal or a conductive metal alloy. Illustrative examples of conductive materials that can be used in the present application to provide the at least one first conductive structure 12 include, but are not limited to, Cu, Al, Cu-Al alloys, W, Ru, or Rh. The at least one first conductive structure 12 generally has a cylindrical shape, as evident from the top view shown in FIG. 3A . While the at least one first conductive structure 12 is shown as having a cylindrical shape, the shape of the at least one first conductive structure 12 is not limited to a cylindrical shape.

[0047] In some embodiments, a diffusion barrier liner (not shown) may be present along at least the sidewalls (and in some embodiments, along the bottom wall) of at least one conductive structure 12. If present, the diffusion barrier liner may be composed of any well-known diffusion barrier material, such as, for example, Ta, TaN, Ti, TiN, W, or WN. In some embodiments, the diffusion barrier liner may include a material stack of two or more diffusion barrier materials. In one example, the diffusion barrier liner may be composed of a Ta / TaN stack or a Ti / TiN stack.

[0048] The exemplary structure shown in FIG. 1 may be formed by first depositing a first interconnect dielectric material layer 10. Then, at least one opening is formed in the first interconnect dielectric material layer 10 by lithography and etching. Lithography involves forming a photoresist material on the surface of the material layer or structure that needs to be patterned, exposing the deposited photoresist material to a radiation pattern, and then developing the exposed photoresist material. The etching used to provide the at least one opening in the first interconnect dielectric material layer 10 may include a dry etching process (i.e., reactive ion etching, plasma etching, or ion beam etching) or a chemical wet etching. Next, if present, a layer of diffusion barrier material may be formed over at least the opening and the first interconnect dielectric material layer 10. Forming the layer of diffusion barrier material may include a deposition process such as, for example, CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). The layer of diffusion barrier material does not entirely fill the at least one opening. Next, one of the above-mentioned conductive materials (e.g., Cu) is deposited on the layer of diffusion barrier material. The deposition of the conductive material can include CVD, PECVD, PVD, ALD, sputtering, or plating. Next, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove the layer of diffusion barrier material (if present) and the conductive material formed on top of the first interconnect dielectric material layer 10 outside the at least one opening. The conductive material and, if present, the layer of diffusion barrier material remain in the opening after the planarization process. The conductive material remaining in the opening provides the first conductive structure 12, and the diffusion barrier material layer, if present, remaining in the opening provides a diffusion barrier liner (not shown in FIG. 1).In an embodiment of the present application, the at least one first conductive structure 12 has a top surface that is coplanar with the top surface of at least the first interconnect dielectric material layer 10; if a diffusion barrier liner is present, the top surface of the at least one first conductive structure 12 can be coplanar with both the top surface of the diffusion barrier layer and the top surface of the first interconnect dielectric material layer 10.

[0049] Referring now to FIG. 2, the exemplary structure shown in FIG. 1 is illustrated after forming a sacrificial dielectric material layer 14L at the interconnect level. As shown, the sacrificial dielectric material layer 14L is formed on the first interconnect dielectric material layer 10 and at least one first conductive structure 12. The sacrificial dielectric material layer 14L comprises a dielectric material that is compositionally different from the dielectric material that provides the first interconnect dielectric material layer 10. In one example, the sacrificial dielectric material layer 14L is composed of silicon nitride (SiN) or silicon oxynitride (SiON). The sacrificial dielectric material layer 14L may be formed by a deposition process such as, for example, CVD, PECVD, PVD, or ALD. The sacrificial dielectric material layer 14L may have a thickness between 20 nm and 200 nm, although other thicknesses are contemplated and may be used as the thickness of the sacrificial dielectric material layer 14L.

[0050] 3A-3B, the exemplary structure shown in FIG. 2 is shown after patterning the sacrificial dielectric material layer 14L into at least one sacrificial dielectric material via structure 14. The at least one sacrificial dielectric material via structure 14 is present in a portion of the first interconnect dielectric material layer 10 but is not present in any portion of the at least one first conductive structure 12. Therefore, the at least one first conductive structure 12 is physically exposed. The patterning includes lithography and etching, as described above. In cross section, the at least one sacrificial dielectric material via structure 14 has a width between 5 nm and 100 nm. The at least one sacrificial dielectric material via structure 14 has a vertical height between 20 nm and 500 nm. The at least one sacrificial dielectric material via structure 14 is configured to enable efficient shadow deposition of a layer of chiral SOT metal, as described in detail herein below.

[0051] Referring now to FIG. 4A, the exemplary structure shown in FIG. 3B is shown after forming a layer of chiral SOT metal 18L on the physically exposed surface of at least one first conductive structure 12; the layer of chiral SOT metal 18L may also extend into portions of the first interconnect dielectric material layer 10 that are not protected by the at least one sacrificial dielectric material via structure 14. In the drawing, element 16 represents an unwanted region of the structure where chiral SOT metal formation is undesirable. The unwanted region contains a similar composition to the layer of chiral SOT metal 18L but lacks the orientation (i.e., chirality) of the layer of chiral SOT metal 18L. Note that the area not protected by the at least one sacrificial dielectric material via structure 14 defines a via, and the layer of chiral SOT metal 18L is formed within the via. During this deposition stage, the at least one sacrificial dielectric material layer via structure 14 acts as a deposition shadow mask, blocking some areas of the structure from unwanted SOT metal deposition.

[0052] The chiral SOT metal layer 18L is composed of a conductor that can generate a spin current that assists in the switching of the subsequently formed MTJ under a limited charge current supply. The chiral via SOT structure of the present application generates a spin current whose spin polarization direction is significantly aligned with the current propagation direction, resulting in a high conversion efficiency of charge-to-spin current conversion. Therefore, a spin current with axially polarized spins along the via axis can be efficiently generated. This is achieved by a multilayer transport structure that forms a helical pattern for both charge conduction and spin current conduction. The chiral-via structure can be configured as a bilayer or multilayer structure in the form of A / B or A / I / B, where A=β-Ta, β-W, Cu. x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x , Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2, TaS2, Pt x Rh 1-xA is any material known to produce large SOT charge-spin conversion efficiencies, where x is between 0 and 1; and B is a known good spin conductor, such as Cu, Ag, or Au. At the same time, "I" is a ferromagnetic, supermagnetic, or antiferromagnetic material that is a poor charge conductor but a good spin conductor, such as NiO or FeOx, and other magnon-mediated spin conductive but charge insulating materials. The I layer in this case is used as an interface layer between A and B to promote spin conduction but prevent charge current shunting. Gradually increasing the tilt of the normal to the A / B or A / I / B interface creates a gradient for the spin current that accumulates a significant component with axial (toward the helix) spin polarization, thus achieving high efficiency from charge current to axially polarized spin current, which is crucial for efficient switching of perpendicularly magnetized nanomagnets built above the chiral-via structure. The chiral SOT metal layer 18L can be formed by PVD using at least two targets while rotating a substrate having an exemplary structure; this embodiment of the present application is shown, for example, in FIG. 4B. Rotation can be performed in a clockwise or counterclockwise direction. Rotation is performed around a central axis perpendicular to the horizontal surface of the structure shown in FIGS. 3A-3B. The two or more targets can include one or more of the elements described above to form the desired A / B or A / I / B type layered spiral growth structure. The chirality of the chiral SOT metal layer 18L is determined by the direction of rotation of the structure during the deposition process. In the present application, the chiral SOT metal layer 18L can be optimized to provide maximum vertically polarized spin accumulation at the top surface. This can be achieved, for example, by controlling the incidence angles and deposition rates of various sources to adjust the slope change rate of the multilayer interface that changes during spiral growth. The relative thickness of the A / B or A / I / B film can also be optimized by adjusting the deposition rates of the associated sources. All of these aim to optimize the charge-spin current conversion efficiency and maximize the spin current polarized along the helix axis.

[0053] The chiral SOT metal layer 18L has a vertical height greater than about 20 nm. The chiral SOT metal layer 18L, at this point in the application, typically has a top surface disposed above the top surface of the at least one sacrificial dielectric material via structure 14. In embodiments, and after deposition, a recess etch can be used to reduce the vertical height of the chiral SOT metal layer 18L and adjust the vertical height of the chiral SOT metal layer 18L.

[0054] 5, the exemplary structure shown in FIG. 4A is shown after performing a planarization process, such as, for example, CMP, to convert the layer of chiral SOT metal 18L into a precursor chiral SOT metal bottom electrode 18P. The planarization process removes a portion of the layer of chiral SOT metal 18L, as well as an upper portion of the unwanted region 16 and an upper portion of the at least one sacrificial dielectric material via structure 14. The net result of the planarization is that each formed precursor chiral SOT metal bottom electrode 18P has a top surface that is coplanar with the remaining portion of the at least one sacrificial dielectric material via structure 14.

[0055] Referring now to Figure 6, the exemplary structure shown in Figure 5 is shown after forming a patterned masking stack 20 / 22 with patterned vias in the precursor chiral SOT metal bottom electrode 18P. The patterned masking stack 20 / 22 protects some, but not all, of the precursor chiral SOT metal bottom electrode 18P. Therefore, as shown in Figure 6, a portion of the precursor chiral SOT metal bottom electrode 18P is unprotected. However, the patterned masking stack 20 / 22 does not cover the unwanted region 16.

[0056] The patterned masking stack 20 / 22 includes a lower hardmask material layer 20 and an upper softmask material layer 22. In some embodiments, the lower hardmask material layer 20 is composed of a dielectric hardmask material, such as, for example, silicon nitride or silicon oxynitride. In other embodiments, the lower hardmask material layer 20 is composed of a dielectric hardmask material, such as, for example, AlO xThe lower hard mask material layer 20 may be composed of a metal hard mask material such as a metal oxide or a metal nitride. The hard mask material providing the lower hard mask material layer 20 may be compositionally the same as or different from the dielectric material providing the at least one sacrificial dielectric via structure 14. The upper soft mask material layer 22 may be composed of an organic planarization layer (OPL) or any other similar organic masking material. The patterned masking stack 20 / 22 may be formed by blanket depositing a hard mask material followed by a soft mask material, and then subjecting the deposited hard mask material / soft mask material to lithographic patterning. Deposition may include, but is not limited to, CVD, PECVD, spin-on, or coating. These blanket layers of hard mask material and soft mask material may be deposited using the same or different deposition processes. The lower hard mask material layer 20 may have a thickness of 20 nm to 150 nm, and the upper soft mask material layer 22 may have a thickness of 50 nm to 500 nm. However, other thicknesses of the lower hardmask material layer 20 and the upper softmask material layer 22 are contemplated and may be used in the present application.

[0057] 7 , the exemplary structure shown in FIG. 6 is shown after patterning the precursor chiral SOT metal bottom electrode 18P to provide a chiral SOT metal bottom electrode 18 utilizing the patterned masking stack 20 / 22 as an etch mask, where the patterning removes at least one sacrificial dielectric material via structure 14 and a portion of the precursor chiral SOT metal bottom electrode 18P, and the patterning forms a notch surface S1 in the first interconnect dielectric material layer 10. During this patterning step, the remaining unwanted region 16 is also removed from the structure. Note that the notch surface S1 is formed in an area of ​​the first interconnect dielectric material layer 10 laterally adjacent to the first conductive structure 12 that includes the chiral SOT metal bottom electrode 18 on its upper surface. As shown in FIG. 7 , this patterning step can also form a notch surface S2 at an upper corner of at least one first conductive structure. This notching occurs due to the difference in etch rates between the metal and the dielectric.

[0058] The patterning may include reactive ion etching or ion beam etching. During this patterning step, the soft mask material layer 22 and the upper portion of the hard mask material layer 20 may be removed. The resulting chiral SOT metal bottom electrode 18 has a sidewall surface that is generally perpendicular to the top surface of the at least one first conductive structure 12. However, a slight taper may occur in the sidewall of the chiral SOT metal bottom electrode 18. The chiral SOT metal bottom electrode 18 is typically a via structure with a cylindrical shape.

[0059] Referring now to FIG. 8 , the exemplary structure shown in FIG. 7 is shown after forming a via dielectric material structure 24 laterally adjacent to the chiral SOT metal bottom electrode 18 on the notched surface S1 of the first interconnect dielectric material layer 10; note that the via dielectric material structure 24 is also formed on the unnotched surface of the first interconnect dielectric material layer 10. The via dielectric material structure 24 may be composed of one of the dielectric materials described above for the first interconnect dielectric material layer 10, or another dielectric material, such as silicon nitride, may be used to provide the via dielectric material structure 24. The dielectric material providing the via dielectric material structure 24 may be compositionally the same as or a compositionally different dielectric material from the material providing the first interconnect dielectric material layer. The via dielectric material structure 24 may be formed by deposition of a dielectric material followed by a planarization process. The deposition of the dielectric material providing the via dielectric 24 may include CVD, PECVD, PVD, or spin-on coating. After planarization, the via dielectric material structure 24 has a top surface that is coplanar with the top surface of the chiral SOT metal bottom electrode 18, as shown in FIG.

[0060] Referring now to FIG. 9 , the exemplary structure shown in FIG. 8 is shown after forming a magnetic material-containing stack including a blanket layer of magnetic free material 26L, a blanket layer of tunnel barrier material 28L, a blanket layer of magnetic reference material 30L, and a blanket layer of top electrode material 32L; the blanket layer of top electrode material 32L is then patterned to act as an etch mask for the remaining blanket layers in the magnetic material-containing stack. Note that other magnetic and non-magnetic materials typically present in MTJ structures can be formed in the magnetic material-containing stack shown in FIG. 9 . As shown in FIG. 9 , the magnetic material-containing stack is disposed in both the via dielectric material structure 24 and each chiral SOT metal bottom electrode 18. In an embodiment of the present application, the blanket layer of magnetic free material 26L forms a direct interface with the chiral SOT metal bottom electrode 18.

[0061] The blanket layer of magnetically free material 26L of the magnetic-material-containing stack is composed of at least one magnetic material with a magnetization that can change orientation relative to the magnetization orientation of the magnetic reference material; note that the term "magnetically free material" indicates that this magnetic layer does not have a fixed magnetization, but this term does not mean that this layer does not contain magnetic material. Exemplary materials for the blanket layer of magnetically free material 26L include, but are not limited to, alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys. The blanket layer of magnetically free material 26L can have a thickness of 0.3 nm to 3 nm, although other thicknesses are possible and can be used for the blanket layer of magnetically free material 26L.

[0062] The blanket layer of tunnel barrier material 28L in the magnetic-material-containing stack is composed of an insulating material and is formed to a thickness that provides adequate tunneling resistance. Exemplary materials for the blanket layer of tunnel barrier material 28L include magnesium oxide, aluminum oxide, and titanium oxide, or materials with higher electrical tunneling conductivity, such as semiconductors or low-bandgap insulators. The thickness of the blanket layer of tunnel barrier material 28L depends on the material selected. In one example, the blanket layer of tunnel barrier material 28L may have a thickness of 0.5 nm to 1.5 nm, although other thicknesses are possible as long as the blanket layer of tunnel barrier material 28L provides adequate tunneling resistance.

[0063] The blanket layer of magnetic reference material 30L has a fixed magnetization. The blanket layer of magnetic reference material 30L is composed of a metal or metal alloy containing one or more metals that exhibit high spin polarization. In an alternative embodiment, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, and manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic reference layer may be a multilayer arrangement having (1) high spin polarization regions formed using metals and / or metal alloys using the metals described above, and (2) regions composed of a material or materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be arranged as alternating layers. The strong PMA region can also include an alloy exhibiting a strong PMA; exemplary alloys include cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be employed. The blanket layer of magnetic reference material 30L may have a thickness of 0.3 nm to 3 nm, although other thicknesses are possible and may be used for the blanket layer of magnetic reference material 30L.

[0064] The blanket layer of top electrode material 32L may be comprised of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The blanket layer of top electrode material 32L may have a thickness between 5 nm and 100 nm; other thicknesses are possible and may be used herein as the thickness of the blanket layer of top electrode material 32L.

[0065] The above-described magnetic material-containing stacks 26L / 28L / 30L / 32L can be formed using one or more deposition processes, including but not limited to, CVD, PECVD, PVD, ALD (including plasma-enhanced ALD), or sputtering, as shown in FIG.

[0066] 10 , the exemplary structure shown in FIG. 9 is shown after patterning the magnetic-material-containing stack to provide a patterned stack comprised of an unetched remainder of a blanket layer of magnetic free material 26L (hereinafter referred to as magnetic free layer 26), an unetched remainder of a blanket layer of tunnel barrier material 28L (hereinafter referred to as tunnel barrier layer 28), an unetched remainder of a blanket layer of magnetic reference material 30L (hereinafter referred to as magnetic reference layer 30), and an unetched remainder of a blanket layer of top electrode material 32L (hereinafter referred to as top electrode 32). In this embodiment, the magnetic free layer 26L has a width that is smaller than the width of the chiral SOT metal bottom electrode 18; it should be noted that the width of the chiral SOT metal bottom electrode 18 is the average width of that electrode. The combination of the magnetic free layer 26, the tunnel barrier layer 28, and the magnetic reference layer 30 provides an MTJ structure disposed between the top electrode 32 and the chiral SOT metal bottom electrode 18.

[0067] This patterning involves a lithography process in which a patterned resist (not shown) is formed on the surface of the blanket layer of top electrode material 32L. The patterned resist may be formed by depositing a photoresist material, exposing the photoresist material to a desired radiation pattern, and developing the exposed photoresist material. The patterned resist protects portions of the blanket layer of top electrode material 32L while leaving other portions of the blanket layer of top electrode material 32L physically exposed. The physically exposed portions of the blanket layer of top electrode material 32L are removed in an initial transfer etch. After the initial transfer etch, the patterned resist is removed using a conventional resist removal process, such as ashing. Patterning continues using another etch in which the top electrode 32L serves as an etch mask for the remainder of the patterning process. This other etch stops on a sub-surface of the via dielectric material structure 24. The term "sub-surface" refers to the surface of a material disposed between the top and bottom surfaces of the material. This other etch removes the remaining portions of the magnetic material-containing stack not covered by the top electrode 32 and the upper portion of the via dielectric material structure 24. In some embodiments, this etch may also remove the portion of the chiral SOT metal bottom electrode 18 not protected by the top electrode 32. The transfer etch and any subsequent etches may include ion beam etching, reactive ion beam etching, or any combination thereof. The transfer etch can be the same as or different from the other etches used in this patterning step. For example, the transfer etch may include reactive ion etching and the other etches may include ion beam etching.

[0068] In some embodiments of the present application, the exemplary structure shown in FIG. 10 can be subjected to an oxygen treatment process or any other gas treatment process to remove any unwanted metal particles that may have redeposited on the sidewalls of the MTJ structure during this patterning.

[0069] The top electrode 32 and the underlying MTJ structure 26 / 28 / 30 typically have a cylindrical shape. In some embodiments of the present application, the top electrode 32 and the underlying MTJ structure 26 / 28 / 30 typically have the same width. Therefore, the outermost walls of the top electrode 32 and the underlying MTJ structure 26 / 28 / 30 are typically vertically aligned with each other. In other embodiments of the present application, the top electrode 32 and the underlying MTJ structure 26 / 28 / 30 may have different widths to provide some degree of taper to the outermost walls of the stack containing the top electrode 32 and the underlying MTJ structure 26 / 28 / 30.

[0070] 1-10, where the magnetic free layer 26 has a width greater than the width of the chiral SOT metal bottom electrode 18; and the width of the chiral SOT metal bottom electrode 18 is an average width. In this embodiment, the magnetic free layer 26 overhangs the outermost wall of the chiral SOT metal bottom electrode 18, and a via dielectric material structure 24 resides below the overhanging portion of the magnetic free layer 26. This structure can be formed by ion beam etching, reactive ion etching, or a combination of both etching processes.

[0071] 12, there is shown a cross-sectional view of yet another exemplary structure processed according to the steps shown in FIGS. 1-10, where the magnetic free layer has a width (i.e., average width) substantially equal to (i.e., ±5%) the width of the chiral SOT metal bottom electrode 18. This structure can be formed by ion beam etching, reactive ion etching, or a combination of both etching processes.

[0072] Referring now to FIG. 13 , a cross-sectional view of the exemplary structure shown in FIG. 10 is shown after further MRAM device processing. Further MRAM device processing may also be performed on the exemplary structure shown in FIGS. 11 and 12 . The further MRAM device processing includes forming an encapsulation layer 34. The encapsulation layer 34 laterally surrounds the top electrode 32, the MTJ structures 26 / 28 / 30, and any exposed upper portions of the chiral SOT metal bottom electrode 18, and resides on top of the via dielectric material structure 24. The encapsulation layer 34 is formed by deposition (e.g., CVD, PECVD, PVD, ALD, or spin-on coating) of an encapsulant (typically a dielectric material), followed by a planarization process that removes the deposited encapsulant formed on top of the top electrode 32. In one embodiment, the encapsulant is silicon nitride. In another embodiment, the encapsulant is a dielectric material containing atoms of silicon, carbon, and hydrogen. In some embodiments, in addition to atoms of carbon and hydrogen, the encapsulant may include at least one of nitrogen and oxygen atoms. In other embodiments, in addition to atoms of silicon, nitrogen, carbon, and hydrogen, the encapsulant may include atoms of boron. In one example, encapsulation layer 34 may be comprised of an nBLOK dielectric material containing atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, encapsulation layer 34 may be comprised of a SiBCN dielectric material containing atoms of silicon, boron, carbon, hydrogen, and nitrogen. Encapsulation layer 34 may have a thickness between 10 nm and 200 nm. Other thicknesses are possible and may be utilized for encapsulation layer 34.

[0073] After forming the encapsulation layer 34, an MTJ dielectric fill material 36 is formed on the encapsulation layer 34 and laterally adjacent to the top electrode 32 and the MTJ structures 26 / 28 / 30. The dielectric MTJ dielectric fill material 36 may include one of the dielectric materials described above for the via dielectric material structure 24. The dielectric material providing the MTJ dielectric fill material 36 can be compositionally the same as or different from the dielectric material providing the via dielectric material structure 24. The MTJ dielectric fill material 36 may be formed by deposition of a dielectric material followed by a planarization process. Note that in embodiments of the present application, this planarization process is used to remove both the encapsulant and the dielectric material from above the top electrode 32. The MTJ dielectric fill material 36 has a top surface that is coplanar with the top surface of the top electrode 32.

[0074] Further MRAM device processing also includes forming a second interconnect dielectric material layer 38 contacting the surface of the top electrode 32 and having at least one second conductive structure 40 embedded therein, and then forming a third interconnect dielectric material 42 on top of the second interconnect dielectric material 38 and the at least one second conductive structure 40, although the step of forming the third interconnect dielectric material 42 may be omitted in some embodiments of the present application. The second interconnect dielectric material layer 38 may include one of the dielectric materials described above for the first interconnect dielectric material layer 10. The dielectric material providing the second interconnect dielectric material layer 38 can be compositionally the same as or compositionally different from the dielectric material providing the first interconnect dielectric material layer 10. The second interconnect dielectric material layer 38 may be formed using one of the deposition processes described above for forming the first interconnect dielectric material layer 10.

[0075] The at least one second conductive structure 40 is composed of one of the conductive materials described above for the at least one first conductive structure 12. In some embodiments, a diffusion barrier liner (not shown) may be formed along the sidewalls and bottom wall of the second conductive structure 40. In some embodiments, a diffusion barrier liner is not present. The diffusion barrier liner is composed of a diffusion barrier material as defined above. The at least one second conductive structure 40, and if present, the diffusion barrier liner, may be formed by providing the exemplary structure shown in FIG. 1 as described above. The at least one second conductive structure 40 may have a width greater than, less than, or equal to the width of the top electrode 32. In some embodiments, as shown in FIG. 13, individual second conductive structures 40 (three in the illustrated embodiment) are formed, with each individual second conductive structure 40 contacting a single top electrode 32. In other embodiments, the second conductive structures 40 may be formed to contact two or more top electrodes 32.

[0076] If present, the third interconnect dielectric material layer 42 may comprise one of the dielectric materials described above for the first interconnect dielectric material layer 10. The dielectric material providing the third interconnect dielectric material layer 42 may be compositionally the same as or different from the dielectric material providing the first interconnect dielectric material layer 10 and / or the dielectric material providing the second interconnect dielectric material layer. The third interconnect dielectric material layer 42 may be formed utilizing one of the deposition processes described above for forming the first interconnect dielectric material layer 10. A third conductive structure (not shown) may be formed in the third interconnect dielectric material and in contact with at least one of the second conductive structures.

[0077] While the present application has been particularly shown and described in connection with its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. Chiral spin-orbit torque (SOT) metal bottom electrode; a via dielectric material structure disposed laterally adjacent to said chiral SOT metal bottom electrode; a magnetic tunnel junction (MTJ) structure disposed on top of the chiral SOT metal bottom electrode, wherein a magnetic free layer of the MTJ structure is disposed below a magnetic reference layer of the MTJ; and an upper electrode disposed on top of the MTJ structure; A memory structure comprising:

2. 2. The memory structure of claim 1, wherein the chiral SOT metal bottom electrode enables each of a charge current direction, a spin current direction, and a spin polarization direction to be perpendicular to a horizontal surface of the chiral SOT metal bottom electrode.

3. The memory structure of claim 1 , wherein the chiral SOT metal bottom electrode is a via structure.

4. The memory structure of claim 1 , wherein each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode is cylindrical.

5. The memory structure of claim 1 , wherein the magnetic free layer of the MTJ structure has a width different from a width of the chiral SOT metal bottom electrode.

6. The memory structure of claim 1 , wherein the magnetic free layer of the MTJ structure has a width substantially equal to a width of the chiral SOT metal bottom electrode.

7. 10. The memory structure of claim 1, further comprising an interconnect level including an interconnect dielectric material layer and a conductive structure disposed below said chiral SOT metal bottom electrode, said chiral SOT metal bottom electrode being disposed on a surface of said conductive structure.

8. 8. The memory structure of claim 7, wherein the interconnect dielectric material layer has a notched surface disposed adjacent to the conductive structure, and the via dielectric material structure is disposed on the notched surface of the interconnect dielectric material layer.

9. 10. The memory structure of claim 1, wherein the chiral SOT metal bottom electrode is composed of a conductor that generates a spin current that assists in switching the MTJ.

10. The chiral SOT metal bottom electrode is composed of a bilayer or multilayer structure in the form of A / B or A / I / B, where A=β-Ta, β-W, Cu ｘ Pt １－ｘ , Cu １－ｘ Ta ｘ , Pd ｘ Pt １－ｘ , Au ｘ Pt １－ｘ , Pt, Bi ２ Se ３ , WTe ２ , PtTe ２ or TaS ２ , Pt ｘ Rh １－ｘ 10. The memory structure of claim 9, wherein B=Cu, Ag, or Au, and I comprises NiO, FeOx, or other spin-conducting but charge-insulating ferromagnetic, supermagnetic, or antiferromagnetic material.

11. The memory structure of claim 1 , further comprising a passivation layer disposed on each sidewall of the top electrode, the MTJ structure, and the chiral SOT metal bottom electrode.

12. 12. The memory structure of claim 11, further comprising a dielectric fill material disposed in said passivation layer, said dielectric fill material having a top surface coplanar with a top surface of said top electrode.

13. 10. The memory structure of claim 1, further comprising an interconnect dielectric material layer disposed above said top electrode, said conductive structure being embedded in said interconnect dielectric material layer, said conductive structure contacting a surface of said top electrode.

14. 14. The memory structure of claim 13, wherein the conductive structure has a width different from a width of the top electrode.

15. 14. The memory structure of claim 13, wherein the conductive structure has a width equal to a width of the top electrode.

16. an interconnect level including at least one first conductive structure embedded in a first interconnect dielectric material layer, said first interconnect dielectric material having a notched surface adjacent said at least one first conductive structure; a chiral spin-orbit torque (SOT) metal bottom electrode disposed on a surface of the at least one first conductive structure; a via dielectric material structure disposed laterally adjacent to the chiral SOT metal bottom electrode and contacting the notch face of the first interconnect dielectric material layer; a magnetic tunnel junction (MTJ) structure disposed on top of the chiral SOT metal bottom electrode, wherein a magnetic free layer of the MTJ structure is disposed below a magnetic reference layer of the MTJ; a top electrode disposed on top of the MTJ structure; and at least one second conductive structure embedded in a second interconnect dielectric material layer disposed above the top electrode, wherein the at least one second conductive structure contacts the top electrode; A memory structure comprising:

17. 17. The memory structure of claim 16, wherein the chiral SOT metal bottom electrode enables each of a charge current direction, a spin current direction, and a spin polarization direction to be perpendicular to a horizontal surface of the chiral SOT metal bottom electrode.

18. 17. The memory structure of claim 16, wherein the chiral SOT metal bottom electrode is a via structure.

19. 17. The memory structure of claim 16, wherein each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode is cylindrical.

20. 17. The memory structure of claim 16, wherein the magnetic free layer of the MTJ structure has a width different from a width of the chiral SOT metal bottom electrode.

21. 17. The memory structure of claim 16, wherein the magnetic free layer of the MTJ structure has a width substantially equal to a width of the chiral SOT metal bottom electrode.

22. 1. A method of forming a memory structure, the method comprising: forming an interconnect level including at least one conductive structure embedded in an interconnect dielectric material layer; forming at least one sacrificial dielectric material layer via structure in the interconnect dielectric material layer while physically exposing the at least one conductive structure; and forming a layer of chiral spin-orbit torque (SOT) metal on the physically exposed at least one conductive structure, wherein forming the layer of chiral SOT metal comprises depositing the chiral SOT metal by physical vapor deposition, the depositing being performed while rotating the interconnect level and the at least one sacrificial dielectric material layer via structure in the same rotational direction. A method for providing the above.

23. 23. The method of claim 22, further comprising planarizing the layer of chiral SOT metal to provide a precursor chiral SOT metal bottom electrode, and patterning the layer of precursor chiral SOT metal bottom electrode to provide a chiral SOT metal bottom electrode, wherein the patterning step forms a notched surface in the interconnect dielectric material layer.

24. 24. The method of claim 23, further comprising forming a via dielectric material structure at a notch surface of the interconnect dielectric material layer and laterally adjacent to the chiral SOT bottom electrode.

25. 25. The method of claim 24, further comprising forming a magnetic tunnel junction (MTJ) structure and a top electrode on top of the chiral SOT metal bottom electrode, the MTJ structure being disposed between the chiral SOT metal bottom electrode and the top electrode, and a magnetic free layer of the MTJ structure being disposed below a magnetic reference layer of the MTJ structure.

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