Phase change memory cell sidewall heater

Abstract

A phase change memory structure having an improved sidewall heater and its formation may be presented. The phase change material may be switchable between a first structural state in which the material is entirely in an amorphous solid phase in the active region of the cell and a second structural state in which the material is entirely in a crystalline solid phase. Presented herein may be a sidewall heater, where an upper section extends through a bilayer dielectric to contact the phase change material layer, and a lower section of the sidewall heater has a conductive layer in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape that reduces the current requirement to reset the phase change material.

Description

[Background technology]

[0001] The present invention relates generally to the field of integrated circuits, and more particularly to phase change memory cell structures.

[0002] Phase change materials can be switched between a first structural state in which the material is entirely in an amorphous solid phase and a second structural state in which the material is entirely in a crystalline solid phase in the active region of the cell. The term amorphous is used to refer to a structure that is less ordered than a single crystal and has a detectable property, such as higher electrical resistance, than the crystalline phase. The term crystalline is used to refer to a structure that is more ordered than an amorphous structure and has a detectable property, such as lower electrical resistance, than the amorphous phase. Other material properties affected by the change between the amorphous and crystalline phases include atomic arrangement, free electron density, and activation energy. The material can be switched between either different solid phases or a mixture of two or more solid phases, providing a grayscale between fully amorphous and fully crystalline states.

[0003] The transition from the amorphous to the crystalline state is generally a lower current operation, requiring sufficient current to raise the phase change material to a level between the phase transition temperature and the melting temperature. The transition from the crystalline to the amorphous state, referred to herein as reset, is generally a higher current operation involving a short, high current density pulse to melt or destroy the crystalline structure, after which the phase change material quickly cools to inhibit the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to induce the transition of the phase change material from the crystalline state to the amorphous state. The magnitude of the required reset current can be reduced by reducing the volume of the active region within the phase change material element in the cell. Techniques used to reduce the volume of the active region include reducing the contact area between the electrodes and the phase change material so that a higher current density within the active volume is achieved, resulting in a smaller absolute current value through the phase change material element. Summary of the Invention

[0004] According to one embodiment of the present invention, a phase change memory structure with an improved sidewall heater is provided. The phase change memory element structure includes a bottom electrode, a phase change material layer, a bilayer dielectric, and a sidewall heater having upper and lower sections. The upper section of the sidewall heater extends vertically through the bilayer dielectric and contacts the phase change material layer, and the lower section of the sidewall heater includes multiple conductive layers in contact with the bottom electrode, wherein the dimensions of the upper section of the sidewall heater in contact with the phase change material layer are substantially smaller than the dimensions of the lower section of the sidewall heater in contact with the bottom electrode, resulting in an inverted T shape.

[0005] According to another embodiment of the present invention, a method for forming an improved phase change memory cell sidewall is disclosed. The method includes forming a plurality of bottom electrodes on a semiconductor substrate. The method further includes depositing a dual-layer dielectric, where the dual-layer dielectric is in contact with at least two of the plurality of bottom electrodes, the dual-layer dielectric being composed of at least one top oxide layer. Additionally, the method includes depositing a conformal multi-stack layer of sidewall heater metal. Further, the method includes depositing a conformal dielectric liner layer on the conformal multi-stack layer of sidewall heater metal. The method may also include removing horizontal surfaces of the conformal dielectric liner layer of sidewall heater metal and the conformal multi-stack layer. Further, the method may include removing a portion of the top oxide layer into two or more segments. Additionally, the method may include removing horizontally exposed multi-stack layers of sidewall heater metal to be level with their respective contacting dual-layer dielectrics. The method may also include removing the top oxide layer. Further, the method may include depositing an upper dielectric layer. The method may also include exposing horizontal surfaces of the multi-stack sidewall heater metal. The method may include depositing a phase change material. Additionally, the method may include depositing a top electrode material. The method may also include forming two or more phase change material elements. [Brief explanation of the drawings]

[0006] The following detailed description, given by way of example and not intended to limit the disclosure thereto, will be best understood in conjunction with the accompanying drawings, in which:

[0007] [Figure 1A] 1A shows a cross-sectional view of phase change memory cell 102 of FIG. 1A, generally designated 100A, taken along the YY' plane of FIG. 1B, in accordance with at least one embodiment of the present invention. [Figure 1B]1A through the XX' plane, in accordance with at least one embodiment of the present invention.

[0008] [Figure 2] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 3] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 4] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 5] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 6] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 7] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 8] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 9] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 10] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 11] 1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention. [Figure 12]1A-1D illustrate stages in a fabrication sequence for producing a dual cell phase change memory structure in accordance with at least one embodiment of the present invention.

[0009] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like reference numerals represent like elements. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention relates generally to the field of integrated circuits, and more particularly to phase change memory cell sidewall heaters.

[0011] Phase change memory (PCM) is an emerging nonvolatile random access memory with advantages over existing nonvolatile memory technologies. PCM offers numerous advantages for both classical memory and neuromorphic computing applications. Briefly, PCM has two basic forms: a crystalline structure with low electrical resistance and an amorphous structure with high electrical resistance. PCM achieves the amorphous state when heated for a short period of time and cooled quickly. To achieve the crystalline state, PCM is heated at a lower temperature for a longer period of time and cooled slowly relative to the amorphous state.

[0012] Current PCM devices achieve a programmable state through a reset procedure that utilizes sidewall heaters. The sidewall heaters have sublithographic dimensions that make them relatively thinner at the contact than the PCM material. However, the sidewall heater dimensions parallel to the contact are generally the same dimensions as the top electrode of the memory cell. This provides a large contact area between the sidewall heaters and the PCM.

[0013] Embodiments of the present invention improve upon the deficiencies of the current PCM reset step and the resulting structure by forming a sidewall heater that has a reduced area above the sidewall heater that contacts the PCM and a reduced thermal conductivity between the sidewall heater and the PCM due to the large area of ​​the bottom of the sidewall heater that contacts the dielectric layer.

[0014] Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the present invention. However, it should be understood that embodiments of the present invention may be practiced without these specific details. Thus, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0015] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," and "bottom," and their derivatives, refer to the disclosed structures and methods as oriented in the drawing figures. Terms such as "above," "on," "above," "overlying," or "located on" mean that a first element, such as a first structure, resides on a second element, such as a second structure, where an intervening element, such as an interfacial structure, may reside between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0016] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses on distinctive features or elements of various embodiments of the present invention.

[0017] As used herein, terms such as "depositing" and "forming" may refer to the placement of a layer or portion of material according to a given embodiment. Such processes may or may not differ from those used in standard practice in the field of phase change memory structure fabrication. Such processes include, but are not limited to, atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), limited reaction processing CVD (LRPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition, sputtering, plating, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination of these methods.

[0018] As used herein, terms such as "forming" may refer to a process that alters the structure and / or composition of one or more layers of material or portions of material, according to a given embodiment. For example, such forming processes may include, but are not limited to, exposure to a particular frequency or range of frequencies of electromagnetic radiation, ion implantation techniques, and / or chemical / mechanical polishing (CMP). As used herein, terms such as "forming" may refer to a process that alters the structure of one or more layers of material or portions of material by removing an amount of material, according to a given embodiment. For example, such forming processes may include, but are not limited to, micromachining, microetching, wet and / or dry etching processes, plasma etching processes, or any of the known etching processes in which material is removed.

[0019] Those skilled in the art will appreciate that many different techniques may be used to add, remove, and / or modify various materials and portions thereof, and that embodiments of the present invention may utilize a combination of such processes to produce the structures disclosed herein without departing from the scope of the present invention.

[0020] The following description, which refers to the accompanying drawings, is provided to facilitate a comprehensive understanding of exemplary embodiments of the present invention, as defined by the claims and their equivalents. The description includes numerous specific details to facilitate understanding, but these are considered to be merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications to the embodiments described herein may be made without departing from the scope of the present invention. Some of the process steps shown may be combined into an integrated process step. Additionally, for clarity and conciseness, descriptions of well-known functions and structures may be omitted.

[0021] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits on semiconductor chips. The presented embodiments can be implemented in conjunction with integrated circuit fabrication techniques for semiconductor chips and devices currently used in the art, and only equivalent commonly implemented process steps are included to the extent necessary for understanding the described embodiments. The figures represent cross-sectional portions of various semiconductor structures and subassembly structures and are not drawn to scale, but instead are drawn to illustrate features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to variously use the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0022] The present invention will now be described in detail with reference to the drawings, in which like reference numerals refer to like elements throughout. Figures 1 through 12 include various cross-sectional views illustrating exemplary steps in a method for fabricating a semiconductor device, particularly a phase change memory structure with improved sidewall heaters, and their resulting structures, in accordance with selected embodiments of the present invention. Those skilled in the art will understand that there are many options available for forming the structures described herein, and that the following description does not limit embodiments to only the techniques described herein.

[0023] 1A and 1B, structures 100A and 100B show various views of a PCM structure comprising a PCM cell 102 having an improved sidewall heater 110 in contact with a phase change element (PCE) 118 in accordance with at least one embodiment of the present invention. It should be understood that Figures 1A and 1B, taken in conjunction with each other, are non-limiting examples of at least one embodiment of the present invention. Figure 1A is a cross-sectional view taken along line Y-Y' in Figure 1B, and Figure 1B is a cross-sectional view taken along line X-X' in Figure 1A.

[0024] As shown by the cross-sectional view of structure 100A in Figure 1A, PCM cell 102 includes a semiconductor substrate 104, an interlayer dielectric 106, a bottom electrode 108, a sidewall heater 110, a base layer dielectric 112, a PCE layer dielectric 114, a heater layer dielectric 116, a PCE 118, and a top electrode 120. For ease of understanding, Figure 1A is described in a bottom-up manner, describing the components of PCM cell 102 in relation to each other.

[0025] The semiconductor substrate 104 may be a base upon which the PCM structure is fabricated. The semiconductor substrate 104 may be any suitable material, such as, for example, silicon, metal oxides, and gallium arsenide. In one embodiment, the semiconductor substrate 104 may have pre-built devices integrated onto the substrate itself. Examples of pre-built devices may include, but are not limited to, transistors (e.g., field effect transistors), resistors, capacitors, etc.

[0026] Overlying the semiconductor substrate 104 is a bottom electrode 108 surrounded by an interlayer dielectric 106. The bottom electrode 104 and the top electrode 120 are electrically conductive and may be made from metals such as titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), and alloys such as tungsten nitride (WN), tungsten carbide (WC), or multilayer stacks thereof. Additionally, the bottom electrode 104 and the top electrode 120 may be wires, vias, or a combination of the two.

[0027] 1A, the base layer dielectric 112 overlies the interlayer dielectric 106 and the bottom electrode 108. The base layer dielectric 112 is intermediate the sidewall heater elements 110. The sidewall heaters 110 overlie the bottom electrode 108 and are in contact with the PCE layer dielectric 114 on their outer sides. The sidewall heater elements 110 are also in electrical contact with the bottom electrode 108.

[0028] Overlying the PCE layer dielectric 114 is the PCE 118. The PCE 118 may be constructed from germanium-antimony-tellurium (GeSbTe, also known as GST) or a germanium-telluride material (GeTe). Alternatively, other suitable materials for the PCE 118 may include a Si—Sb—Te (silicon-antimony-tellurium) alloy, a Ga—Sb—Te (gallium-antimony-tellurium) alloy, a Ge—Bi—Te (germanium-bismuth-tellurium) alloy, an In—Se (indium-tellurium) alloy, an As—Sb—Te (arsenic-antimony-tellurium) alloy, an Ag—In—Sb—Te (silver-indium-antimony-tellurium) alloy, a Ge—In—Sb—Te alloy, a Ge—Sb alloy, an Sb—Te alloy, a Si—Sb alloy, a combination of the Ge—Te alloys, or another other phase-change material suitable for use in a PCM device. The PCE 118 may be undoped or doped (e.g., doped with one or more of O, N, Si, or Ti). The PCE 118 also overlies and is in contact with the sidewall heater 110 and the heater dielectric 116. Overlying the PCE 118 is a top electrode 120.

[0029] The dimensions of the sidewall heater 110 in contact with the PCE 118 can be controlled by the thickness (e.g., 3 nm, 4 nm, 5 nm, etc.) of the film used to deposit the sidewall heater metal during fabrication. In one embodiment, the sidewall heater 110 can be one or more layers of a metallic material suitable for thermal and electrical conductance. In one embodiment, the sidewall heater 110 can be two or more alternating layers made of TiN and TaN.

[0030] Referring to FIG. 1B, structure 100B, generally designated as PCE 102, is a view of PCE 102 taken along the X-X' axis of FIG. 1A. FIG. 1B shows a bottom electrode 108 overlying a semiconductor substrate 104. Overlying the bottom electrode 108 is a sidewall heater 110. As shown in FIG. 1B, the sidewall heater 110 has a column-forming portion having a dimension substantially thinner than a base. The column portion extends upward, and a PCE dielectric layer 114 contacts either side of the column portion. The column portion terminates at a PCE 118, which overlies the termination point of the column section of the sidewall heater 118 and the PCE dielectric 114. As such, the PCE 118 is in contact with the PCE dielectric 114 and the sidewall heater 110. Overlying the PCE 118 is a top electrode 120.

[0031] 2-12, which illustrate stages in a fabrication sequence for a dual-cell phase-change memory structure in accordance with at least one embodiment of the present invention. While a dual-cell PCM structure is shown, it should be noted that the stages illustrated in these figures may be scaled to fabricate a memory structure having any number of PCM cells (e.g., 3, 4, n...n+1). FIG. 2 illustrates that structure 200 results from forming a bottom electrode 108 in a strip on a semiconductor substrate 104 and depositing an interlayer dielectric 106 around the strip of bottom electrode 108 surrounding both sides of the bottom electrode 108 while leaving an upper horizontal portion of the bottom electrode 108 exposed. Alternatively, bottom electrode 108 may be formed, for example, by a conventional complementary metal-oxide-semiconductor (CMOS) back-end (BEOL) damascene process (e.g., tungsten, cobalt, or copper surrounded by interlayer dielectric 106).

[0032] 3 shows the structure 300 after a dual-layer dielectric 302 constructed from a base layer dielectric 112 and an etched oxide dielectric layer 304 has been deposited (e.g., patterned) on the central portion of the interlayer dielectric 106, covering approximately half of the middle portion of the bottom electrode 108 in the previous structure. The dual-layer dielectric 302 is a dielectric material that may be constructed from two substances, including a nitride underlayer (SiN) and an oxide layer (SiO2). The etched oxide layer 304 is a dielectric material that provides footing and protection for the sidewall heater 110 during the fabrication process. The etched oxide layer 304 may be constructed from a suitable dielectric oxide material (e.g., SiO2).

[0033] FIG. 4 shows a structure 400 including a conformal metal layer of sidewall heater material 110 deposited on the previous structure 300. In one embodiment, the conformal metal layer of sidewall heater material (e.g., TiN, TaN, TiAlN, TiSiN, TaAlN, TaSiN) can be deposited in multiple layers forming a multilayer stack. The multilayer stack can be two or more alternating layers of variable thickness (e.g., 3 nm TaN / 5 nm TiN, 3 nm TaN / 3 nm TiN). The thickness of the multistack layer can depend on the thickness of the conformal layer during the fabrication process. In another embodiment, the conformal multistack layer of alternating sidewall heater material can be five layers thick, including 3 nm TaN, 5 nm TiN, 3 nm TaN, 3 nm TiN, 3 nm TaN. Note that the number of layers and layer thicknesses are not limited to the above example. This deposition of conformal multi-stack sidewall heater material provides three layers of multi-stack heater material in contact with the PCE 118 in the final phase change material structure.

[0034] 5 shows a structure 500 including the result of depositing a conformal layer of sidewall heater dielectric 116 on the previous structure 400. The sidewall heater dielectric 116 may be constructed from a nitride dielectric material (e.g., SiN) and may protect the underlying multi-stack sidewall heater material previously deposited on the structure 400.

[0035] 6 shows a structure 600 including removal of portions of the conformal layer of the conformal sidewall heater material 110 and sidewall heater dielectric 116 on the horizontal surfaces of the structure 500. In one embodiment, an etching process (e.g., reactive ion etching) may be performed to remove material (e.g., sidewall heater dielectric 116) along the structure 500 on the horizontal surfaces. Approximately equal amounts of material may be removed on the horizontal surfaces to expose the upper portion of the interlayer dielectric 106, portions of the horizontal and vertical surfaces of the sidewall heater 110, horizontal portions of the etched oxide layer 304, and the outer vertical and horizontal upper portions of the sidewall heater dielectric 116.

[0036] 7 shows a structure 700 that includes etched oxide layer 304 cut into multiple segments. In one embodiment, structure 700 is achieved by utilizing a pattern mask to cut etched oxide layer 304 into two separate segments, exposing the upper horizontal surface of bottom layer dielectric 112 and the inner vertical surface of sidewall heater 110. In one embodiment, trimming of etched oxide dielectric 304 can be performed via an isotropic etch to further narrow the two separate segments.

[0037] 8 shows a structure 800. Structure 800 is achieved by removing the sidewall heater material level with the oxide etch dielectric 304 block structure and the upper portion of the bottom layer dielectric 112, respectively, while exposing the inner vertical surfaces of the oxide etch dielectric 304 and the sidewall dielectric 116 above the base layer dielectric 112. In one embodiment, the removal of the sidewall heater material can be achieved by an isotropic etch (e.g., atomic layer etch).

[0038] FIG. 9 shows structure 900. Structure 900 is achieved by removing both blocks of oxide etch dielectric 304 shown in FIG. 800. In one embodiment, the blocks of oxide etch dielectric 304 may be removed by performing a layer-by-layer isotropic etch. In one embodiment, this exposes the inner intermediate surface of the sidewall heater 110. In one embodiment, a multi-layer sidewall heater 110 is used with alternating materials. In such an embodiment, one or more layers of the vertical columnar portion of sidewall heater material may be removed. For example, if the sidewall heater 110 is comprised of a four-layer multilayer (i.e., TaN / TiN / TaN / TiN composition), two of these layers may be removed. A two-layer columnar vertical portion remains, where one of the layers has an exposed intermediate inner surface (e.g., the TiN layer), while the other layer is sandwiched between the sidewall heater dielectric 110 and the exposed remaining layer of sidewall heater material. The exposed horizontal surface of this sandwiched layer may form the top of the sidewall heater 110 .

[0039] FIG. 10 shows a structure 1000. Structure 1000 is realized by depositing a dielectric layer 114 on the exposed horizontal surfaces of structure 900 of FIG. 9 and performing CMP to remove material from the horizontal surfaces of structure 1000 to expose the sidewall heaters 110. In one embodiment, dielectric layer 114 can be a SiO2 or SiN material. In one embodiment, a layer of base layer dielectric 112 can be deposited on the horizontal and vertical surfaces of structure 900 before dielectric layer 114 to prevent possible oxidation of the bottom electrode 108 and sidewall heaters 110. In one embodiment, a thin base layer dielectric 112 can be deposited, followed by layer deposition of dielectric layer 114, and then portions of base layer dielectric 112 and dielectric layer 114 can be removed via CMP to expose the top horizontal surfaces of sidewall heaters 110 that will be in contact with the phase change material.

[0040] FIG. 11 shows a structure 1100. The structure 1100 is realized by first depositing a phase change element 118 (e.g., GST) followed by a top electrode material. The phase change element 118 is deposited on the structure 1000. The phase change element 118 is deposited on the top horizontal planar surface of the PCE layer dielectric 114, the top horizontal surface of the heater layer dielectric, and the top portion of the horizontal surface of the sidewall heater 110. In one embodiment, the top surface of the phase change element 118 can be planarized to be parallel to its bottom horizontal surface. A top electrode 120 can be deposited on the top horizontal surface of the phase change element 118 to form the top electrode 120. The top electrode 120 can be constructed of one or more materials capable of conducting electrical current (e.g., TiN, W, Cu, Al, etc.).

[0041] 12 illustrates structure 1200 after structure 1100 of FIG. 11 has been divided or sectioned into two separate phase change memory cells. Structure 1200 is achieved by patterning top electrode 120 and phase change memory element 118 into two separate blocks. Additionally, in one embodiment, an etching process is performed to remove any remaining material previously covered by interlayer dielectric layer 106 and bottom electrode 108 from phase change memory element 118, resulting in two separate phase change memory cells 122A and 122B. In one embodiment, a dielectric material (not shown) may be deposited around phase change memory cells 122A and 122B and over the now exposed interlayer dielectric 106 and bottom electrode 108 to further ensure separation between phase change memory cells 122A and 122B and insulate them from stray currents. It should be noted that while only two phase change memory cells 122A and 122B are shown in Figure 12, many more memory cells (e.g., 2, 3, n... n+1) may be fabricated via the methods illustrated in Figures 2 through 12. Phase change memory cells may be arranged in any array known in the art and used as a form of memory (e.g., volatile or non-volatile) in a computing device.

[0042] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, their practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0043] Additionally, any specified materials or any specified dimensions of any structures described herein are by way of example only. Further, as will be understood by those skilled in the art, the structures described herein can be made or used in the same manner regardless of their location and orientation. Thus, as used herein, it should be understood that terms and phrases such as "side," "top," "vertical," "inclined," etc. refer to the relative locations and orientations of various portions of the structures with respect to one another and are not intended to suggest that any particular absolute orientation with respect to an external object is necessary or required.

[0044] The foregoing specification also describes process steps. Some of these steps may be in an ordered sequence, while others may be in a different embodiment from the order detailed in the foregoing specification. The ordering of steps, where it occurs, is explicitly indicated by adjectives such as "ordered," "before," "after," "then," and other adjectives of similar meaning.

[0045] Benefits, other advantages, and solutions to problems have been described above with respect to particular embodiments. However, these benefits, advantages, solutions, and any elements that may give rise to or make more apparent any benefit, advantage, or solution should not be construed as critical, necessary, or essential features or elements of any or all of the claims. Many modifications and variations of the present invention are possible in light of the above teachings and will be apparent to those skilled in the art.

Claims

1. bottom electrode; a phase change material layer; a dual layer dielectric; and a sidewall heater having an upper section and a lower section, wherein the upper section extends vertically through the dual-layer dielectric and contacts the phase change material layer, and the lower section of the sidewall heater includes a plurality of conductive layers in contact with the bottom electrode, wherein a dimension of the upper section of the sidewall heater in contact with the phase change material layer is substantially smaller than a dimension of the lower section of the sidewall heater in contact with the bottom electrode, resulting in an inverted T-shape; A phase change memory element structure comprising:

2. The phase change memory element structure of claim 1 , wherein the phase change memory element structure is formed on a semiconductor substrate.

3. The phase change memory element structure of claim 1 , wherein the sidewall heater is constructed from multi-stack metals.

4. 3. The phase change memory element structure of claim 2, wherein the multi-stack metal is comprised of at least one of a 3 nm TaN / 5 nm TiN configuration or a 3 nm TaN / 3 nm TiN configuration.

5. 3. The phase change memory element structure of claim 2, wherein the multi-stack metals can be composed of at least two of TiN, TaN, TaAlN, TiSiN, TiAlN, or TaSiN.

6. The dual layer dielectric has a bottom layer of SiN dielectric and a top layer of SiO ２ 10. The phase change memory element structure of claim 1, comprising:

7. 10. The phase change memory element structure of claim 1, wherein the phase change memory layer is composed of chalcogenide glass.

8. 8. The phase change memory element structure of claim 7, wherein the chalcogenide glass is germanium-antimony-tellurium ("GST").

9. bottom electrode; a phase change material layer; a dual layer dielectric; and a sidewall heater having an upper section and a lower section, wherein the upper section extends vertically through the dual-layer dielectric and contacts the phase change material layer, and the lower section of the sidewall heater includes a plurality of conductive layers in contact with the bottom electrode, wherein a width of the upper section of the sidewall heater in contact with the phase change material layer is substantially similar to the width of the lower section of the sidewall heater in contact with the bottom electrode. A phase change memory element structure comprising:

10. 10. The phase change memory element structure of claim 9, wherein the upper section of the sidewall heater is comprised of a single layer of conductive material.

11. 10. The phase change memory element structure of claim 9, further comprising a SiN liner surrounding the sidewall heater except for the portion in contact with the phase change material layer.

12. 1. A method of forming a phase change memory element structure, comprising: forming a plurality of bottom electrodes on a semiconductor substrate; depositing a dual-layer dielectric, wherein the dual-layer dielectric is in contact with at least two of the plurality of bottom electrodes, the dual-layer dielectric being comprised of at least one top oxide layer; depositing a conformal multi-stack layer of sidewall heater metal; depositing a conformal dielectric liner layer over the conformal multi-stack layer of sidewall heater metallurgy; removing the conformal dielectric liner layer of the sidewall heater metallization and horizontal surfaces of the conformal multi-stack layer; removing a portion of said top oxide layer into two or more segments; removing the horizontally exposed multi-stack layers of sidewall heater metallization to be level with each contacting dual-layer dielectric; removing the top oxide layer; depositing an upper dielectric layer; exposing a horizontal surface of the multi-stack sidewall heater metal; depositing a phase change material; depositing a top electrode material; and Forming two or more phase change material elements A method comprising:

13. 13. The method of claim 12, wherein forming the plurality of bottom electrodes further comprises patterning the plurality of bottom electrodes into intermediate strips of an interlayer dielectric.

14. 13. The method of claim 12, wherein removing the conformal dielectric liner layer and the horizontal surfaces of the conformal multi-stack layer of the sidewall heater comprises directional reactive ion etching.

15. The method of claim 12 , wherein removing horizontal surfaces of the conformal dielectric liner layer of the sidewall heater material further comprises pattern masking.

16. The method of claim 12 , wherein the interconnect structure is at least one of an interposer or a bridge.

17. The method of claim 12 , wherein the horizontal surfaces of the multi-stack sidewall heater metal are exposed using chemical mechanical planarization.

18. The method of claim 12 , wherein removing the exposed multi-stack layers comprises performing an atomic layer etch.

19. 13. The method of claim 12, wherein forming the two or more phase change material elements comprises patterning the top electrode material, the phase change material, and etching into an interlayer dielectric.

20. The method of claim 12 , wherein the multi-stack metal can be composed of at least two of TiN, TaN, TaAlN, TiSiN, TiAlN, or TaSiN.

21. 21. A computer program comprising program code adapted to perform the steps of the method according to any of claims 12 to 20 when the program is run on a computer.

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