Barrier structure to reduce dispersion in transistor devices

Abstract

A transistor device is provided. In one example, the transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite the channel layer. The first Group III nitride layer has a thickness greater than a thickness of the second Group III nitride layer. The aluminum concentration of the first Group III nitride layer is at least two times higher than the aluminum concentration of the second Group III nitride layer.

Description

Detailed Description of the Invention

[0001] [Priority claim] This application is based on and claims the benefit of priority to U.S. Patent Application No. 2017 / 951708, filed September 23, 2022. This application claims priority to and the benefit of the entire contents of this cited application, which is incorporated by reference in its entirety. [Field]

[0002] TECHNICAL FIELD This disclosure relates generally to semiconductor devices, and more particularly to transistor devices. [background]

[0003] Power semiconductor devices are widely used to carry large currents, handle high voltages, and / or operate at high frequencies such as radio frequencies. A wide variety of power semiconductor devices are available for a variety of applications, including, for example, power switching devices and power amplifiers. Many power semiconductor devices are realized using various types of field-effect transistor (FET) devices, including MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (double-diffused metal-oxide-semiconductor) transistors, HEMTs (high-electron-mobility transistors), MESFETs (metal-semiconductor field-effect transistors), LDMOS (latently diffused metal-oxide-semiconductor) transistors, etc.

[0004] Power semiconductor devices can be fabricated from wide-bandgap semiconductor materials (e.g., having a bandgap of 1.40 eV or greater). For example, HEMT power devices can be fabricated from gallium nitride (GaN) or other Group III-nitride-based material systems formed on, for example, silicon carbide (SiC) substrates or other substrates. As used herein, the term "Group III nitride" refers to semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, often aluminum (Al), gallium (Ga), and / or indium (In). These compounds have an empirical formula in which one mole of nitrogen combines with one mole of total Group III elements. For high-power, high-temperature, and / or high-frequency applications, devices formed from wide-bandgap semiconductor materials, such as silicon carbide (e.g., the bandgap of alpha silicon carbide at room temperature is 2.996 eV) and Group III nitrides (e.g., the bandgap of gallium nitride at room temperature is 3.36 eV), can offer higher electric field breakdown strengths and higher electron saturation velocities compared to gallium arsenide (GaAs) and silicon (Si)-based devices. [overview]

[0005] Aspects and advantages of each embodiment of the present disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned through practice of the embodiments.

[0006] An exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite the channel layer. The first Group III nitride layer has a thickness greater than a thickness of the second Group III nitride layer. The first Group III nitride layer has an aluminum concentration at least two times higher than the aluminum concentration of the second Group III nitride layer.

[0007] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite the channel layer. The first Group III nitride layer has a thickness at least four times greater than the thickness of the second Group III nitride layer. The first Group III nitride layer has a higher aluminum concentration than the second Group III nitride layer.

[0008] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer. The first layer is Al x Ga 1-x The second layer is an N layer, where x≧0.5. y Ga 1-y The N layer is 0.2≦y<1. The third layer is Al z Ga 1-z N layers, 0 <z≦0.1である。

[0009] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer III-nitride based barrier structure on the channel layer. The multi-layer III-nitride based barrier structure includes a first layer and a second layer on the first layer. The thickness or aluminum concentration of the second layer is such that the current collapse of the transistor device after a stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, where the stress condition includes a 10-millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0010] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer III-nitride based barrier structure on the channel layer. The multi-layer III-nitride based barrier structure includes a first layer and a second layer on the first layer. The thickness or aluminum concentration of the second layer is such that a pinch-off voltage shift of the transistor device after a stress condition is about 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, where the stress condition includes a 10 ms pulse of a drain voltage of 100 V and a gate voltage of −8 V.

[0011] These and other features, aspects, and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, explain associated principles.

[0012] Detailed descriptions of embodiments directed to those skilled in the art are provided herein and refer to the accompanying drawings, in which: [Brief explanation of the drawings]

[0013] [Figure 1] 1 illustrates a cross-sectional view of an example transistor device according to an exemplary embodiment of the present disclosure. [Figure 2] 1 illustrates a multi-layer barrier structure according to an exemplary embodiment of the present disclosure. [Figure 3] 1 illustrates a multi-layer barrier structure according to an exemplary embodiment of the present disclosure. [Figure 4] 1 illustrates a multi-layer barrier structure according to an exemplary embodiment of the present disclosure. [Figure 5] 1 illustrates a multi-layer barrier structure according to an exemplary embodiment of the present disclosure. [Figure 6] 1 shows a graphical representation of the dispersion of a transistor device under stress conditions. [Figure 7] FIG. 6 shows a conventional barrier structure of a transistor device in which dispersion occurs. [Figure 8] 1 illustrates a graphical representation of the distribution of a transistor device according to an exemplary embodiment of the present disclosure. [Figure 9A] 1 shows the electric field of a transistor device with a conventional barrier structure. [Figure 9B] 1 illustrates an electric field in a transistor device having a barrier structure according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] [Detailed explanation] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the various drawings. Each example is provided by way of explanation of an embodiment, not to limit the disclosure. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the spirit and scope of the disclosure. For example, features illustrated or described as part of one embodiment can be used with another embodiment to yield a still further embodiment. Accordingly, it is intended that aspects of the disclosure cover such modifications and variations.

[0015] Transistor devices, such as high electron mobility transistors (HEMTs), can be used in power electronics applications. HEMTs fabricated in III-nitride material systems have the potential to generate significant radio frequency (RF) power because of their combination of material properties, such as high breakdown field, wide bandgap, large conduction band offset, and / or high saturated electron drift velocity. III-nitride HEMTs may therefore be promising candidates for high frequency and / or high power RF applications and low frequency high power switching applications, either as discrete transistors or as transistors interfaced with other circuit elements, for example, in monolithic microwave integrated circuit (MMIC) devices.

[0016] Field-effect transistors, such as HEMT devices, are sometimes classified as depletion-mode or enhancement-mode, corresponding to whether the transistor is in an on or off state when the gate-source voltage is zero. In enhancement-mode devices, the device is in an off state when the gate-source voltage is zero, while in depletion-mode devices, the device is in an on state when the gate-source voltage is zero. In many cases, high-performance III-nitride HEMT devices can be implemented as depletion-mode (normally on) devices because they are conductive at zero gate-source bias due to polarization-induced charges at the interface between the barrier and channel layers of the device.

[0017] When a HEMT device is in the on-state, a two-dimensional electron gas (2DEG) is created at the heterojunction of two semiconductor materials with different bandgap energies, with the material with the smaller bandgap having a higher electron affinity. The 2DEG is an accumulation layer in the material with the smaller bandgap, which can have a very high sheet electron concentration. Furthermore, electrons generated in the semiconductor material with the wider bandgap migrate to the 2DEG layer, allowing for high electron mobility due to reduced ionized impurity scattering. The combination of high carrier concentration and high carrier mobility gives HEMT devices very large transconductance (which can also refer to the relationship between output current and input voltage), which can provide a strong performance advantage over MOSFETs in high-frequency applications.

[0018] A HEMT device may have a channel layer made of a III-nitride material (e.g., GaN). The HEMT device may have a barrier layer disposed on the channel layer. The barrier layer may include, for example, a III-nitride material having a different bandgap than the channel layer. For example, the barrier layer may include an AlGaN layer and / or an AlN layer. Disposing the barrier layer on the channel layer may result in very high electric fields under the gate region of the HEMT device. Under high stress conditions (e.g., high power switching conditions), the HEMT device may experience dissipation, such as pinch-off voltage or current collapse. Pinch-off voltage refers to the change in gate voltage at which the HEMT device transitions to an off-state. Current collapse refers to the decrease in the drain current of the HEMT device when the HEMT device is in a fully on-state.

[0019] In high frequency and / or high power RF applications, switching of transistor devices can place them under high stress conditions. Transistor devices subject to strong dispersion under stress conditions can lead to performance degradation. For example, dispersion within a transistor device can lead to gain variations over time and / or power gain degradation in RF amplifiers (e.g., power amplifiers and low noise amplifiers). The amplifiers can also lose linearization.

[0020] An exemplary embodiment of the present disclosure relates to a transistor device (e.g., a HEMT device) that reduces dispersion under stress conditions. The transistor device may have a multi-layer barrier structure. The multi-layer barrier structure may be disposed on a channel layer of the transistor device. The multi-layer barrier structure may include a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer. The first Group III nitride layer may have a thickness greater than that of the second Group III nitride layer. For example, the ratio of the thickness of the first Group III nitride layer to the thickness of the second Group III nitride layer may be about 4:1 or greater. The aluminum concentration of the first Group III nitride layer may be higher than that of the second Group III nitride layer. For example, the aluminum concentration of the first Group III nitride layer may be at least two times higher than the aluminum concentration of the second Group III nitride layer, e.g., at least five times higher, e.g., at least eight times higher, e.g., in a range from at least two times to about ten times higher.

[0021] Examples of the present disclosure provide technical effects and advantages. For example, without being bound by any theory of operation, the inventors have discovered that a multi-layer barrier structure according to example embodiments of the present disclosure can significantly reduce the electric field around the gate region of a transistor device. The reduced electric field around the gate region reduces dispersion (e.g., current collapse and pinch-off voltage shift) of the transistor device under stress conditions, leading to more stable operation of the transistor device in a variety of applications, either as a discrete device or in combination with other circuit elements (e.g., as an MMIC device). The reduced dispersion can make the transistor device useful in many high-stress applications, such as high-power and / or high-frequency RF applications.

[0022] Although the terms "first," "second," etc. may be used herein to describe various elements, it should be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the words "comprises," "comprising," and / or "includes," when used herein, specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, it will be understood that terms used herein should be interpreted as having a meaning consistent with the meaning in the context of this specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

[0025] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it is understood that the element can be directly on or extending directly onto the other element, and that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it is understood that the element can be directly connected or coupled to the other element, and there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0026] Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation of the device depicted in the figures.

[0027] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the figures are expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein, but are intended to include deviations in shapes that result, for example, from manufacturing. Similarly, it is understood that variations in dimensions due to standard deviations in manufacturing procedures are expected. As used herein, "approximately" or "about" includes values ​​within 10% of the nominal value.

[0028] Like numbers refer to like elements throughout, and thus, the same or similar numbers may be described with reference to other drawings even if not illustrated or described in the corresponding drawing, and elements not labeled with a reference number may be described with reference to other drawings.

[0029] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, and p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated by a "+" or "-" (e.g., n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively high ("+") or low ("-") concentration of majority carriers compared to other layers or regions. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in a given layer or region.

[0030] Aspects of the present disclosure are described with reference to HEMT transistor devices for purposes of illustration and explanation, and it will be apparent to those skilled in the art, using the disclosure provided herein, that certain aspects of the present disclosure may be applicable to other transistor devices without departing from the scope of the present disclosure.

[0031] The drawings and specification disclose exemplary embodiments, and although specific terms are employed, they are used in a generic and descriptive sense only and are not intended to limit the scope of the invention as set forth in the following claims.

[0032] Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0033] 1 illustrates a cross-sectional view of an example HEMT device 100 according to an exemplary embodiment of the present disclosure. FIG. 1 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 100 may include a semiconductor structure 102. The semiconductor structure 102 may be a III-nitride semiconductor structure.

[0034] As used herein, the term "III-nitrides" refers to semiconductor compounds formed between nitrogen (N) and elements from Group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary (or higher) compounds, such as AlGaN and AlInGaN. As will be appreciated by those skilled in the art, Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. All of these compounds have an empirical formula where one mole of nitrogen combines with one mole of total Group III elements.

[0035] The semiconductor structure 102 may be on a substrate 104. The substrate 104 may be a semiconductor material. For example, the substrate 104 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or other suitable substrate. In some embodiments, the substrate 104 may be a semi-insulating SiC substrate, which may be, for example, a 4H polytype of silicon carbide. Other candidate SiC polytypes may include the 3C, 6H, and 15R polytypes. The substrate may be a high-purity semi-insulating (HPSI) substrate, available from Wolfspeed. The term "semi-insulating" is used herein descriptively, rather than in an absolute sense.

[0036] In some embodiments, the SiC bulk crystal of the substrate 104 has a crystallinity of about 1×10 at room temperature. 5 The substrate 104 may have a resistivity of ohm-cm or greater. Exemplary SiC substrates that may be used in some embodiments are manufactured, for example, by Wolfspeed, Inc., and methods for manufacturing such substrates are described, for example, in U.S. Reissue Patent Nos. 34,861, 4,946,547, 5,200,022, and 6,218,680, the disclosures of which are incorporated herein by reference. While SiC may be used as the substrate material, any suitable substrate may be used in embodiments of the present disclosure, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The substrate 104 may be a SiC wafer, and the HEMT device 100 may be formed, at least in part, through wafer-level processing, after which the wafer may be diced to obtain a plurality of individual HEMT devices 100.

[0037] The substrate 104 may have a bottom surface 104A and a top surface 104B. In some embodiments, the substrate 104 of the HEMT device 100 may be a thin substrate 104. In some embodiments, the thickness of the substrate 104 (e.g., in the vertical Z direction in FIG. 1 ) may be about 100 μm or less, such as about 75 μm or less, or for example, about 50 μm or less.

[0038] The HEMT device 100 may include a channel layer 106 on the top surface 104B of the substrate 104 (or on any layer described further herein, such as any buffer layer or nucleation layer). The HEMT device 100 may include a barrier structure 108 on the top surface of the channel layer 106. In some embodiments, the channel layer 106 and the barrier structure 108 may each be formed by epitaxial growth. Techniques for epitaxial growth of Group III nitrides are described, for example, in U.S. Patent Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are incorporated herein by reference. The channel layer 106 may have a bandgap smaller than that of the barrier structure 108. The channel layer 106 may have a greater electron affinity than the barrier structure 108. The channel layer 106 and the barrier structure 108 may comprise Group III nitride-based materials.

[0039] In some embodiments, if the energy of the conduction band edge of the channel layer 106 is less than the energy of the conduction band edge of the barrier structure 108 at the interface between the channel layer 106 and the barrier structure 108, the channel layer 106 may be made of a group III nitride, such as Al. w Ga 1-wN (where 0≦w<1). In some embodiments, the aluminum mole fraction w is about 0, indicating that the channel layer 106 is GaN. The channel layer 106 may be or include other III-nitrides, such as InGaN or AlInGaN. The channel layer 106 may be undoped (or "unintentionally doped") and may be grown to a thickness ranging from about 0.5 μm to about 5 μm, e.g., about 2 μm. The channel layer 106 may also have a multilayer structure, such as a superlattice or combination of GaN, AlGaN, etc. In some embodiments, the channel layer 106 may be compressively strained.

[0040] The barrier structure 108 may be a multi-layer barrier structure 108. Details regarding an exemplary barrier structure 108 are described with reference to Figures 2-5. The channel layer 106 and / or the barrier layer 108 may be deposited by, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). A 2DEG 110 may be induced in the channel layer 106 at the interface between the channel layer 106 and the barrier structure 108. The 2DEG 110 is highly conductive and provides conduction between the source and drain regions of the HEMT device 100.

[0041] For purposes of illustration, HEMT device 100 is shown with substrate 104, channel layer 106, and barrier layer 108, however, HEMT device 100 may include additional layers / structures / elements. For example, HEMT device 100 may include a buffer layer and / or one or more nucleation layers between substrate 104 and channel layer 106. For example, there may be an AlN buffer layer on top surface 104B of substrate 104 to provide a suitable crystal structure transition between SiC substrate 104 and channel layer 106. Optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HYPE.

[0042] The HEMT device 100 may include a cap layer on the barrier structure 108. HEMT structures, including substrates, channel layers, barrier layers, and other layers, are described, by way of example, in U.S. Patent Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,709,269, 7,709,859, and 10,971,612, the disclosures of which are incorporated herein by reference. Furthermore, one or more strain-compensating transition layers may additionally and / or alternatively be provided, for example, as described in U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference.

[0043] The HEMT device 100 may include a source contact 112 on or in contact with the top surface 108A of the barrier structure 108. The HEMT device 100 may include a drain contact 114 on or in contact with the top surface 108A of the barrier structure 108. The source contact 112 and the drain contact 114 may be laterally spaced apart from one another. In some embodiments, the source contact 112 and the drain contact 114 may comprise a metal capable of making ohmic contact with a III-nitride semiconductor material. Suitable metals include refractory metals such as titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), nickel (Ni), gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), nickel silicide (NiSi), and the like. x), titanium silicide (TiSi), titanium nitride (TiN), tungsten silicide nitride (WSiN), platinum (Pt), etc. In some embodiments, the source contact 112 may be an ohmic source contact 112. The drain contact 114 may be an ohmic drain contact 114. Thus, the source contact 112 and / or the drain contact 114 may include an ohmic contact portion that is in direct contact with the barrier structure 108. In some embodiments, the source contact 112 and / or the drain contact 114 may include multiple layers that constitute an ohmic contact, which may be provided as described, for example, in U.S. Pat. Nos. 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference.

[0044] The HEMT device 100 may include a gate contact 116 on or in contact with (e.g., embedded in) the upper surface 108A of the barrier structure 108. The gate contact 116 has a gate length L G The gate length L G may be the length of the gate contact 116 at the portion of the gate contact 116 that is over the semiconductor structure 102, as shown in FIG. 1. In some embodiments, the gate length L G In some embodiments, the gate length L may be in the range of about 100 nm to about 200 nm, for example about 150 nm. G In some embodiments, the gate length L G may be in the range of about 40 nm to about 90 nm.

[0045] The material of the gate contact 116 may be selected based on the composition of the barrier structure 108 and may be a Schottky contact in some embodiments. For example, nickel (Ni), platinum (Pt), nickel silicide (NiSi xAlternatively, a material capable of making a Schottky contact with a Group III nitride-based semiconductor material, such as tungsten (W), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W), and / or tungsten silicide nitride (WSiN), may be used.

[0046] The source contact 112 may be coupled to a reference signal, such as a ground voltage, or other reference signal. The coupling to the reference signal may be provided by a via 118 extending from the lower surface 104A of the substrate 104 through the substrate 104 and the channel layer 106 to the upper surface 108A of the barrier structure 108. The via 118 may expose a bottom surface of the ohmic portion 112A of the source contact 112. A backside metal layer 120 may be on the lower surface 104A of the substrate 104 and on the sidewalls of the via 118. The backside metal layer 120 may be in direct contact with the ohmic portion 112A of the source contact 112. In some embodiments, the contact area between the backside metal layer 120 and the bottom surface of the ohmic portion 112A of the source contact 112 may be 50 percent or more of the area of ​​the bottom surface of the ohmic portion 112A of the source contact 112. Thus, the backside metal layer 120, and thus the coupled signal, may be electrically connected to the source contact 112.

[0047] In some embodiments, the via 118 may have an oval or circular cross-section when viewed in plan. However, the disclosure is not limited to this shape. In some embodiments, the cross-section of the via 118 may be polygonal or other shapes, as would be understood by one of ordinary skill in the art using the disclosure provided herein. In some embodiments, the dimensions (e.g., length and / or width) of the via are such that the maximum cross-sectional area A1 of the via 118 is about 1000 μm 2The cross-sectional area A1 may be measured in a direction parallel to the lower surface 104A of the substrate 104 (e.g., the XY plane in FIG. 1 ). In some embodiments, the maximum cross-sectional area A1 of the via 118 may be the cross-sectional area of ​​the portion of the via 118 adjacent to the lower surface 104A of the substrate 104 (e.g., the opening of the via 118). For example, in some embodiments, the maximum width (e.g., in the X direction in FIG. 1 ) may be about 16 μm and the maximum length (e.g., in the Y direction in FIG. 1 ) may be about 40 μm, although the disclosure is not limited thereto. In some embodiments, the sidewalls of the via 118 may be inclined and / or oblique with respect to the lower surface 104A of the substrate 104. In some embodiments, the sidewalls of the via 118 may be approximately perpendicular to the lower surface 104A of the substrate 104.

[0048] In some embodiments, the drain contact 114 may be formed on, in, and / or through the barrier structure 108, and ion implantation may be performed into the material surrounding the drain contact 114 to reduce resistivity and improve ohmic contact to the semiconductor material. In yet other embodiments, the source via 118 is not present, and the source contact 112 is formed on, in, and / or through the barrier structure 108, and ion implantation may be performed into the material surrounding the source contact 112 to reduce resistivity and improve ohmic contact to the semiconductor material. If the source via 118 is not present, electrical connection to the source contact 112 may be made on the same side as the gate contact 116 and the drain contact 114. In some examples, connections to the source contact 112, the drain contact 114, and / or the gate contact 116 may be made from the top and / or the bottom, providing a flip-chip configuration of the HEMT device 100. In some examples, thermal paths may be provided from the top and / or bottom to provide for flip-chip configuration of the HEMT device 100.

[0049] The HEMT device 100 may include a first insulating layer 122. The first insulating layer 122 may be in direct contact with the top surface of the semiconductor structure 102 (e.g., in contact with the top surface 108A of the barrier structure 108). The HEMT device 100 may also include a second insulating layer 124. The second insulating layer 124 may be on the first insulating layer 122. It will be appreciated that in some embodiments, more than two insulating layers may be included. The first insulating layer 122 and / or the second insulating layer 124 may provide a protective layer for the HEMT device 100. The first insulating layer 122 and / or the second insulating layer 124 may be a dielectric layer. Various dielectric materials may be used, such as SiN, SiO2, Si, Ge, MgOx, MgNx, ZnO, SiNx, SiOx, alloys or stacks thereof, or epitaxial materials.

[0050] The source contact 112, the drain contact 114, and the gate contact 116 may be within the first insulating layer 122. In some embodiments, at least a portion of the gate contact 116 may be within the first insulating layer 122. In some embodiments, the gate contact 116 may be a T-gate and / or a gamma-gate, configurations of which are described, by way of example, in U.S. Patent Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated herein by reference. A second insulating layer 124 may be on the first insulating layer 122 and on portions of each of the source contact 112, the drain contact 114, and the gate contact 116. The protrusion from the gate may also be referred to as a field plate integrated with the gate.

[0051] The field plate 126 may be on the second insulating layer 124, as shown in FIG. 1, or on a separate insulating layer, depending on the number of insulating layers included in the HEMT device. At least a portion of the field plate 126 may be on the gate contact 116. At least a portion of the field plate 126 may be on a portion of the second insulating layer 124 between the gate contact 116 and the drain contact 114. The field plate 126 can reduce the peak electric field in the HEMT device 100, thereby increasing the breakdown voltage and reducing charge trapping. The reduced electric field also provides other benefits, such as reduced leakage current and improved reliability. Field plates and techniques for forming them are described, by way of example, in U.S. Pat. No. 8,120,064, the disclosure of which is incorporated herein by reference.

[0052] 1 , or on another insulating layer, depending on the number of insulating layers included in the HEMT device. The metal contacts 128 may provide interconnections between the source contacts 112, the drain contacts 114, the gate contacts 116, and other portions of the HEMT device 100. Each of the metal contacts 128 may directly contact a corresponding one of the drain contacts 114 and / or the source contacts 112. The metal contacts 128 may comprise a metal or highly conductive material, such as copper, cobalt, gold, and / or composite metals.

[0053] A HEMT transistor may be formed by an active region between a source contact 112 and a drain contact 114, controlled by a gate contact 116 that is between the source contact 112 and the drain contact 114. For purposes of illustration, Figure 1 shows a cross-sectional view of one unit of a HEMT device 100. The HEMT device 100 may be formed adjacent to another HEMT device unit and may share, for example, a source contact 112 with the adjacent HEMT device unit.

[0054] FIG. 2 illustrates an exemplary semiconductor structure 102 according to an exemplary embodiment of the present disclosure, which may be used, for example, in the HEMT device 100 of FIG. 1. FIG. 2 is intended to depict the structure for purposes of identification and explanation, and is not intended to depict the structure to physical scale. The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a first III-nitride layer 132 having a first surface 132A disposed on a surface 106A of the channel layer 106. The multilayer barrier structure 108 includes a second III-nitride layer 134 on the first III-nitride layer 132, the second III-nitride layer 134 configured such that its first surface 134A is disposed on a second surface 132B of the first III-nitride layer 132 opposite the channel layer 106. The multilayer barrier structure 108 including the first III-nitride layer 132 and the second III-nitride layer 134 may also be referred to as a multilayer III-nitride based barrier structure.

[0055] The multilayer barrier structure 108 may have a thickness T1. The thickness T1 may be, for example, in the range of about 150 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 300 angstroms, for example, in the range of about 200 angstroms to about 250 angstroms. In some embodiments, the thickness T1 may be about 310 angstroms. In some embodiments, the thickness T1 may be about 280 angstroms. In some embodiments, the thickness T1 may be about 250 angstroms. The thickness T1 of the channel layer 106 may be, for example, in the range of about 150 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 300 angstroms, for example, in the range of about 200 angstroms to about 250 angstroms. In some embodiments, the thickness T1 may be about 310 angstroms. In some embodiments, the thickness T1 may be about 280 angstroms. In some embodiments, the thickness T1 may be about 250 angstroms. B The ratio of the thickness T1 of the multi-layer barrier structure 108 to the channel layer 106 may be, for example, in a range from about 1:12 to about 1:250, such as in a range from about 1:50 to about 1:90. The multi-layer barrier structure 108 may be sufficiently thick and have a sufficiently high aluminum (Al) composition and doping to induce a significant carrier concentration at the interface between the channel layer 106 and the multi-layer barrier structure 108 through polarization effects.

[0056] In some embodiments, the multi-layer barrier structure 108 may have a thickness T1 of about 150 angstroms or less. For example, in higher frequency applications, the gate length L of the gate contact 116 of the HEMT device 100 G In these applications, the thickness T1 of the multi-layer barrier structure 108 may be about 100 nm or less, e.g., about 90 nm or less, e.g., about 60 nm or less, or in the range of about 40 nm to about 90 nm. In these applications, the thickness T1 of the multi-layer barrier structure 108 may be the ratio of the gate length L of the gate contact 116 to the thickness T1 of the multi-layer barrier structure 108. G may be reduced such that the ratio is in the range of 8: 1 to 16: 1. For example, the multi-layer barrier structure 108 may have a thickness T1 of about 50 Angstroms to about 120 Angstroms.

[0057] The first III-nitride layer 132 is made of a III-nitride, such as Al y Ga 1-y N, where y is the aluminum mole fraction of the first III-nitride layer 132. At the interface between the channel layer 106 and the multilayer barrier structure 108, the conduction band edge energy of the first III-nitride layer 132 is greater than the conduction band edge energy of the channel layer 106. In some embodiments, the aluminum mole fraction y is such that 0.2≦y<1 (e.g., the aluminum mole fraction is in the range of about 20% to about 100%), indicating that the first III-nitride layer 132 is an AlGaN layer. However, the first III-nitride layer 132 may include other group III elements (e.g., In) without departing from the scope of the present disclosure.

[0058] The second III-nitride layer 134 is made of a III-nitride, such as Al z Ga 1-zIt may also be N, where z is the aluminum molar fraction of the second group-III nitride layer 134. The aluminum concentration of the second group-III nitride layer 134 may be lower than the aluminum concentration of the first group-III nitride layer 132. For example, in some embodiments, the aluminum concentration of the first group-III nitride layer 132 may be at least about 2 times, such as at least 5 times, such as at least 8 times, such as in the range of at least 2 times to 10 times higher than the aluminum concentration of the second group-III nitride layer 134. In some embodiments, the aluminum molar fraction z is a value where 0 < z ≦ 0.1 (for example, the aluminum molar fraction is in the range of about 1% to about 10%), indicating that the second group-III nitride layer 134 is an AlGaN layer. However, the second group-III nitride layer 134 may contain other group-III elements (such as In) without departing from the scope of the present disclosure.

[0059] In some embodiments, the second group-III nitride layer 134 may have a stepwise concentration of aluminum that increases in the direction from the second surface 134B to the first surface 134A of the second group-III nitride layer 134. For example, the second group-III nitride layer 134 may have a stepwise concentration of aluminum such that the aluminum concentration is higher at the first surface 134A, which is at the interface between the first group-III nitride layer 132 and the second group-III nitride layer 134, than at the second surface 134B of the second group-III nitride layer 134 on the opposite side of the first group-III nitride layer 132. The stepwise concentration of aluminum can increase with a constant concentration change, a varying concentration change, or a combination of changes from the second surface 134B to the first surface 134A. For example, the stepwise concentration of aluminum can increase from an aluminum molar fraction of about 0% at the second surface 134B to an aluminum molar fraction of about 10% at the first surface 134A.

[0060] In some embodiments, there may be an aluminum concentration difference between the first III-nitride layer 132 and the second III-nitride layer 134 at the interface between the first III-nitride layer 132 and the second III-nitride layer 134. For example, in some embodiments, the aluminum concentration of the first III-nitride layer 132 may be at least two times, such as at least five times, such as at least eight times, such as in the range of at least two times to about ten times, higher than the aluminum concentration of the second III-nitride layer 134 at the interface between the first III-nitride layer 132 and the second III-nitride layer 134.

[0061] The first III-nitride layer 132 may have a thickness T2, and the second III-nitride layer 134 may have a thickness T3. In some embodiments, the ratio of the thickness T2 of the first III-nitride layer 132 to the thickness T3 of the second III-nitride layer 134 may be in a range of about 3:1 or more, such as about 4:1 or more, for example, in a range of about 3:1 to about 15:1. In some embodiments, the thickness T2 of the first III-nitride layer 132 may be four times greater than the thickness T3 of the second III-nitride layer 134. In some embodiments, the thickness T2 may be in a range of about 200 angstroms to about 250 angstroms, for example, about 230 angstroms. The thickness T3 of the second III-nitride layer 134 may be about 50 angstroms or less, such as about 30 angstroms or less, for example, about 30 angstroms.

[0062] Gate length L G In embodiments where the total thickness T1 of the multi-layer barrier structure 108 is 100 nm or less, the total thickness T1 of the multi-layer barrier structure 108 may range from about 50 angstroms to about 120 angstroms. In these embodiments, the thickness T2 of the first III-nitride layer 132 and the thickness T3 of the second III-nitride layer 134 may be correspondingly reduced to maintain a ratio of the thickness T2 of the first III-nitride layer 132 to the thickness T3 of the second III-nitride layer 134 of about 3:1 or more, such as in the range of about 4:1 or more, such as in the range of about 3:1 to about 15:1.

[0063] 3 illustrates another exemplary semiconductor structure 102 according to an exemplary embodiment of the present disclosure, which may be used, for example, in the HEMT device 100 of FIG. 1. FIG. 3 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a first III-nitride layer 132 and a second III-nitride layer 134 having a configuration similar to that of FIG. 2.

[0064] The multilayer barrier structure 108 further includes a spacer layer or interfacial layer 136 (referred to herein as an "interfacial layer") (e.g., a third layer, such as a third III-nitride layer) disposed between the channel layer 106 and the first III-nitride layer 132. The interfacial layer 136 has a first surface 136A disposed on the surface 106A of the channel layer 106. The first III-nitride layer 132 is disposed on the interfacial layer 136 such that the first surface 132A of the first III-nitride layer 132 is on a second surface 136B of the interfacial layer 136 opposite the channel layer 106.

[0065] The interface layer 136 is a group III nitride, such as Al x Ga 1-x In some embodiments, the aluminum mole fraction x is greater than or equal to 0.5 (e.g., the aluminum mole fraction is greater than 50%), indicating that the interfacial layer 136 is an AlGaN layer. In some embodiments, the aluminum mole fraction x is greater than or equal to 0.75 (e.g., the aluminum mole fraction is greater than 75%), indicating that the interfacial layer 136 is an AlGaN layer. In some embodiments, the aluminum mole fraction is 1 (e.g., the aluminum mole fraction is 100%), indicating that the interfacial layer 136 is an AlN layer. However, the interfacial layer 136 may include other Group III elements (e.g., In) without departing from the scope of the present disclosure.

[0066] The interfacial layer 136 may have a thickness T4, which may be about 50 angstroms or less, such as about 30 angstroms or less, for example, in the range of about 3 angstroms to about 50 angstroms, for example, in the range of about 3 angstroms to about 30 angstroms.

[0067] The multilayer barrier structure 108 may have a thickness T1 including a thickness T2 of the first III-nitride layer 132, a thickness T3 of the second III-nitride layer 134, and a thickness T4 of the interfacial layer 136. The thickness T1 may be, for example, in the range of about 150 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 300 angstroms, for example, in the range of about 200 angstroms to about 250 angstroms. In some embodiments, the thickness T1 may be about 310 angstroms. In some embodiments, the thickness T1 may be about 280 angstroms. In some embodiments, the thickness T1 may be about 250 angstroms. The thickness T1 of the channel layer 106 may be, for example, in the range of about 150 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 350 angstroms, for example, in the range of about 200 angstroms to about 300 angstroms, for example, in the range of about 200 angstroms to about 250 angstroms. In some embodiments, the thickness T1 may be about 310 angstroms. In some embodiments, the thickness T1 may be about 280 angstroms. In some embodiments, the thickness T1 may be about 250 angstroms. B The ratio of the thickness T1 of the multi-layer barrier structure 108 to the thickness T1 of the channel layer 106 may be, for example, in a range from about 1:12 to about 1:250, such as in a range from about 1:50 to about 1:90. The multi-layer barrier structure 108 may be sufficiently thick and have a sufficiently high aluminum (Al) composition and doping to induce a significant carrier concentration at the interface between the channel layer 106 and the multi-layer barrier structure 108 through polarization effects.

[0068] In some embodiments, the multi-layer barrier structure 108 may have a thickness T1 of about 150 angstroms or less. For example, in higher frequency applications, the gate length L of the gate contact 116 of the HEMT device 100 G In these applications, the thickness T1 of the multi-layer barrier structure 108 may be about 100 nm or less, e.g., about 90 nm or less, e.g., about 60 nm or less, e.g., in the range of about 40 nm to about 90 nm. In these applications, the thickness T1 of the multi-layer barrier structure 108 is determined by the gate length L of the gate contact relative to the thickness T1 of the multi-layer barrier structure 108. Gmay be reduced such that the ratio is in the range of 8:1 to 16:1. For example, the multi-layer barrier structure 108 may have a thickness T1 of about 50 Angstroms to about 120 Angstroms.

[0069] Gate length L G In embodiments where the total thickness T1 of the multi-layer barrier structure 108 is 100 nm or less, the total thickness T1 of the multi-layer barrier structure 108 may range from about 50 angstroms to about 120 angstroms. In these embodiments, the thickness T2 of the first Group III-nitride layer 132 and the thickness T3 of the second Group III-nitride layer 134 may be reduced accordingly to maintain a ratio of the thickness T2 of the first Group III-nitride layer 132 to the thickness T3 of the second Group III-nitride layer 134 of about 3:1 or more, such as in the range of about 4:1 or more, such as in the range of about 3:1 to about 15:1.

[0070] 4 illustrates another exemplary semiconductor structure 102 according to an exemplary embodiment of the present disclosure, which may be used, for example, in the HEMT device 100 of FIG. 1. FIG. 4 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The semiconductor structure 102 includes a multi-layer barrier structure 108 on a channel layer 106. The multi-layer barrier structure 108 includes a first III-nitride layer 132 and a second III-nitride layer 134 having a configuration similar to that of FIG. 2.

[0071] The semiconductor structure 102 further includes a cap layer T1 when disposed between the multi-layer barrier structure 108 and the gate contact 116. The cap layer 138 may be a single layer or may include multiple layers. The cap layer 138 may have a thickness, for example, in the range of about 20 angstroms to about 50 angstroms. The cap layer 138 may be a III-nitride, such as Al c Ga 1-cN, where c is the aluminum mole fraction of cap layer 138. In some embodiments, the aluminum mole fraction c is a value such that 0≦c≦0.15. In some embodiments, cap layer 138 is a GaN layer. In some embodiments, cap layer 138 is an AlGaN layer. In some embodiments, cap layer 138 is an AlN layer. Cap layer 138 may include other Group III elements (e.g., In) without departing from the scope of the present disclosure.

[0072] In some embodiments, the cap layer 138 may have a graded or varying concentration of aluminum. For example, the cap layer 138 may have a different aluminum concentration at a first surface 138A of the cap layer 138, which is at the interface between the cap layer 138 and the multi-layer barrier structure 108, than at a second surface 138B of the cap layer 138, which is opposite the multi-layer barrier structure 108.

[0073] 4 shows the gate contact 116 disposed on the cap layer 138. The gate contact 116 may be embedded in the cap layer 138 without departing from the scope of the present disclosure. The cap layer 138 may be deposited by MOCVD, MBE, or HVPE, for example.

[0074] 5 illustrates another exemplary semiconductor structure 102 according to an exemplary embodiment of the present disclosure, which may be used, for example, in the HEMT device 100 of FIG. 1. FIG. 5 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The semiconductor structure 102 includes a multilayer barrier structure 108 on a channel layer 106. The multilayer barrier structure 108 includes a first III-nitride layer 132, a second III-nitride layer 134, and an interface layer 136 having a configuration similar to that of FIG. 3.

[0075] 5, the semiconductor structure 102 further includes a cap layer 138 disposed between the multi-layer barrier structure 108 and the gate contact 116. The cap layer 138 may be a single layer or may have multiple layers. The cap layer 138 may have a thickness T5, for example, in the range of about 20 angstroms to about 50 angstroms. The cap layer 138 may be made of a III-nitride, such as Al. c Ga 1-c N, where c is the aluminum mole fraction of cap layer 138. In some embodiments, the aluminum mole fraction c is a value such that 0≦c≦0.15. In some embodiments, cap layer 138 is a GaN layer. In some embodiments, cap layer 138 is an AlGaN layer. In some embodiments, cap layer 138 is an AlN layer. Cap layer 138 may include other Group III elements (e.g., In) without departing from the scope of the present disclosure.

[0076] In some embodiments, the cap layer 138 may have a graded or varying concentration of aluminum. For example, the cap layer 138 may have a different aluminum concentration at a first surface 136A of the cap layer 138, which is at the interface between the cap layer 138 and the multi-layer barrier structure 108, than at a second surface 138B of the cap layer 138, which is opposite the multi-layer barrier structure 108.

[0077] 5 shows the gate contact 116 disposed on the cap layer 138. The gate contact 116 may be embedded in the cap layer 138 without departing from the scope of the present disclosure. The cap layer 138 may be deposited by MOCVD, MBE, or HVPE, for example.

[0078] 2-5 may demonstrate reduced dispersion under stress conditions. In this regard, transistor devices implementing multi-layer barrier structures 108 according to exemplary embodiments of the present disclosure may provide improved performance in applications involving high stress conditions, such as high frequency and / or high power RF switching applications.

[0079] More specifically, Figure 6 shows an example dispersion graph 140 of a conventional HEMT device having a conventional barrier structure after exposure to stress conditions. Figure 7 shows an example conventional barrier structure 208 associated with graph 140 of Figure 6. Barrier structure 208 of Figure 7 overlies channel layer 206. Barrier structure 208 includes an AlGaN layer 232 disposed on an AlN interfacial layer 236. AlGaN layer 232 has a thickness T6 of approximately 250 angstroms and an aluminum mole fraction of approximately 22%. AlN interfacial layer 236 has a thickness T7 of approximately 50 angstroms or less.

[0080] FIG. 6 plots gate voltage Vg (V) along the horizontal axis and drain current density Id (A / mm) along the vertical axis. Curve 142 relates to the no-stress condition. Curve 142 is obtained by applying a drain voltage of 50 V to the drain contact of the HEMT device and sweeping the gate voltage applied to the gate contact of the HEMT device from 0 V to −6 V. Curve 142 plots the drain current density at each gate voltage.

[0081] Curve 144 relates to a stress condition in which a drain voltage of 100 V is applied to the drain contact of the HEMT device in a 10 ms pulse and a gate voltage of −8 V is applied to the gate contact of the HEMT device. After the stress condition, a drain voltage of 50 V is applied to the drain contact of the HEMT device and the gate voltage applied to the gate contact of the HEMT device is swept from 0 V to −6 V, resulting in curve 144. Curve 144 plots the drain current density at each gate voltage.

[0082] 7 experiences dispersion after stress conditions, as shown by the difference between curves 142 and 144. More specifically, the HEMT device experiences a pinch-off voltage shift 146 of approximately 0.8 V. The HEMT device also experiences a current collapse 148 of approximately 34% (e.g., a decrease in drain current density from approximately 0.6 A / mm to approximately 0.4 A / mm).

[0083] 8 shows an example dispersion graph 150 for a HEMT device according to an exemplary embodiment of the present disclosure. Graph 150 may relate to a HEMT device having the barrier structure 108 shown in FIG. 3. More specifically, barrier structure 108 may include a first III-nitride layer 132, a second III-nitride layer 134, and an interfacial layer 136. First III-nitride layer 132 may have a thickness T2 of approximately 220 angstroms and an aluminum mole fraction of approximately 25%. Second III-nitride layer 134 may have a thickness T3 of approximately 30 angstroms and an aluminum mole fraction of approximately 5%. Interfacial layer 136 may be an AlN layer having a thickness T4 of approximately 50 angstroms or less.

[0084] FIG. 8 plots gate voltage Vg (V) along the horizontal axis and drain current density Id (A / mm) along the vertical axis. Curve 152 relates to the no-stress condition. Curve 152 is obtained by applying a drain voltage of 50 V to the drain contact of the HEMT device and sweeping the gate voltage applied to the gate contact of the HEMT device from 0 V to −6 V. Curve 152 plots the drain current density at each gate voltage.

[0085] Curve 154 relates to a stress condition in which a drain voltage of 100 V is applied to the drain contact of the HEMT device in a 10-millisecond pulse and a gate voltage of −8 V is applied to the gate contact of the HEMT device. After the stress condition, a drain voltage of 50 V is applied to the drain contact of the HEMT device and the gate voltage applied to the gate contact of the HEMT device is swept from 0 V to −6 V, resulting in curve 154. Curve 154 plots the drain current density at each gate voltage.

[0086] As shown by the difference between curves 152 and 154, the HEMT device according to the exemplary embodiment of the present disclosure experiences dispersion after the stress condition. More specifically, the HEMT device experiences a pinch-off voltage shift 156 of about 0.4 V or less at a drain voltage of 50 V after the stress condition relative to the operation of the HEMT device before the stress condition. The HEMT device experiences a current collapse 158 of about 30% or less (e.g., 26%) at a gate voltage of 0 V after the stress condition relative to the operation of the HEMT device before the stress condition.

[0087] As demonstrated in Figure 8, HEMT devices implementing barrier structures according to exemplary embodiments of the present disclosure experience reduced dispersion after stress conditions. For example, the pinch-off voltage shift is reduced from approximately 0.8 V in the example of Figure 7 to approximately 0.4 V in the example of Figure 8. The current collapse is reduced from approximately 34% in the example of Figure 7 to less than 30%, e.g., approximately 26%, in the example of Figure 8.

[0088] Without being bound by any particular theory, the inventors have discovered that the multi-layer barrier structure according to exemplary embodiments of the present disclosure can result in a reduced electric field near the gate region of a HEMT device, which in turn leads to reduced dispersion of the HEMT device after stress conditions.

[0089] 9A illustrates the electric field in an example HEMT device having a barrier structure similar to the conventional barrier structure 208 shown in FIG. 9A shows a strong electric field 162 in the gate region 160 near the gate region 160. Field lines representing the electric field 162 have been added to the gate region 160 for ease of illustration. The electric field 162 in the gate region 160 penetrates into the channel layer 106.

[0090] 9B illustrates the electric field in an example HEMT device having a barrier structure similar to the conventional barrier structure 108 shown in FIG. 3 according to an example embodiment of the present disclosure. As shown in FIG. 9B, the electric field 164 has been reduced in the same gate region 160. For ease of illustration, field lines representing the electric field 164 have been added to the gate region 160. Relative to the electric field 162, the electric field 164 has a reduced strength and does not penetrate as deeply into the channel layer 106.

[0091] Exemplary aspects of the present disclosure are described in the following paragraphs.

[0092] An exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite the channel layer. The first Group III nitride layer has a thickness greater than a thickness of the second Group III nitride layer. The first Group III nitride layer has an aluminum concentration at least two times higher than the aluminum concentration of the second Group III nitride layer.

[0093] In some examples, the thickness of the second III-nitride layer or the aluminum concentration of the second III-nitride layer is such that the current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, where the stress condition comprises a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0094] In some examples, the thickness of the second III-nitride layer or the aluminum concentration of the second III-nitride layer is such that the pinch-off voltage shift of the transistor device after the stress condition is about 0.4 V or less at a drain voltage of 50 V relative to the operation of the transistor device before the stress condition, where the stress condition includes a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of −8 V.

[0095] In some examples, the aluminum concentration of the first Group III-nitride layer is at least five times higher than the aluminum concentration of the second Group III-nitride layer.

[0096] In some examples, the aluminum mole fraction of the first III-nitride layer ranges from about 20% to about 100%, and the aluminum mole fraction of the second III-nitride layer ranges from about 1% to about 10%.

[0097] In some examples, the ratio of the thickness of the first Group III-nitride layer to the thickness of the second Group III-nitride layer is 4:1 or greater.

[0098] In some examples, the first III-nitride layer has a thickness of about 200 Angstroms to about 250 Angstroms, and the second III-nitride layer has a thickness of about 50 Angstroms or less.

[0099] In some examples, the multi-layer barrier structure includes an interfacial layer. The first III-nitride layer is disposed on the interfacial layer opposite the channel layer. The interfacial layer has a higher aluminum concentration than the first III-nitride layer and the second III-nitride layer. In some examples, the interfacial layer has a thickness in the range of about 50 angstroms or less.

[0100] In some examples, the transistor device includes a source contact and a drain contact on the multi-layer barrier structure.

[0101] In some examples, the second III-nitride layer has a graded concentration of aluminum that increases such that the aluminum concentration at the interface between the first and second III-nitride layers is higher than at a surface of the second III-nitride layer opposite the first III-nitride layer.

[0102] In some examples, the transistor device has a cap layer on the multi-layer barrier structure.

[0103] In some examples, the transistor device is a high electron mobility transistor. In some examples, the first III-nitride layer and the second III-nitride layer each comprise AlGaN. In some examples, the channel layer is disposed on a silicon carbide substrate.

[0104] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first Group III nitride layer and a second Group III nitride layer on the first Group III nitride layer and opposite the channel layer. The first Group III nitride layer has a thickness at least four times thicker than the second Group III nitride layer. The first Group III nitride layer has a higher aluminum concentration than the second Group III nitride layer.

[0105] In some examples, the thickness of the second III-nitride layer or the aluminum concentration of the second III-nitride layer is such that the current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, where the stress condition comprises a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0106] In some examples, the thickness of the second III-nitride layer or the aluminum concentration of the second III-nitride layer is such that the pinch-off voltage shift of the transistor device after the stress condition is about 0.4 V or less at a drain voltage of 50 V relative to the operation of the transistor device before the stress condition, where the stress condition includes a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of −8 V.

[0107] In some examples, the aluminum concentration of the first Group III-nitride layer is at least five times higher than the aluminum concentration of the second Group III-nitride layer.

[0108] In some examples, the aluminum mole fraction of the first III-nitride layer ranges from about 20% to about 100%, and the aluminum mole fraction of the second III-nitride layer ranges from about 1% to about 10%.

[0109] In some examples, the first III-nitride layer has a thickness of about 200 Angstroms to about 250 Angstroms, and the second III-nitride layer has a thickness of about 50 Angstroms or less.

[0110] In some examples, the multi-layer barrier structure includes an interfacial layer. The first III-nitride layer is disposed on the interfacial layer opposite the channel layer. The interfacial layer has a higher aluminum concentration than the first III-nitride layer and the second III-nitride layer. In some examples, the interfacial layer has a thickness in the range of about 50 angstroms or less.

[0111] In some examples, the transistor device includes a source contact and a drain contact on the multi-layer barrier structure.

[0112] In some examples, the second III-nitride layer has a graded concentration of aluminum such that the aluminum concentration is higher at the interface between the first and second III-nitride layers than at a surface of the second III-nitride layer opposite the first III-nitride layer.

[0113] In some examples, the transistor device includes a cap layer on the multi-layer barrier structure.

[0114] In some examples, the transistor device is a high electron mobility transistor. In some examples, the first III-nitride layer and the second III-nitride layer each comprise AlGaN. In some examples, the channel layer is disposed on a silicon carbide substrate.

[0115] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer barrier structure on the channel layer. The multi-layer barrier structure includes a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer. The first layer is Al x Ga 1-x The second layer is an N layer, where x≧0.5. y Ga 1-y The N layer is 0.2≦y<1. The third layer is Al z Ga 1-z N layers, 0 <z≦0.1である。

[0116] In some instances, the ratio of the thickness of the second layer to the thickness of the third layer is 4:1 or greater.

[0117] In some examples, the second layer has a thickness of about 200 Angstroms to about 250 Angstroms, and the third layer has a thickness of about 50 Angstroms or less.

[0118] In some examples, the transistor device includes a source contact and a drain contact on the multi-layer barrier structure.

[0119] In some examples, x≧0.7.

[0120] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer III-nitride based barrier structure on the channel layer. The multi-layer III-nitride based barrier structure includes a first layer and a second layer on the first layer. The thickness or aluminum concentration of the second layer is such that the current collapse of the transistor device after a stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, where the stress condition includes a 10-millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

[0121] In some examples, the thickness of the second layer or the aluminum concentration of the second layer is such that the pinch-off voltage shift of the transistor device after the stress condition is about 0.4 V or less at a drain voltage of 50 V relative to the operation of the transistor device before the stress condition.

[0122] In some instances, the ratio of the thickness of the first layer to the thickness of the second layer is about 4:1.

[0123] In some examples, the aluminum concentration of the first layer is at least two times higher than the aluminum concentration of the second layer at the interface between the first and second layers.

[0124] Another exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a channel layer. The transistor device includes a multi-layer III-nitride based barrier structure on the channel layer. The multi-layer III-nitride based barrier structure includes a first layer and a second layer on the first layer. The thickness or aluminum concentration of the second layer is such that a pinch-off voltage shift of the transistor device after a stress condition is about 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, where the stress condition includes a 10 ms pulse of a drain voltage of 100 V and a gate voltage of −8 V.

[0125] In some instances, the ratio of the thickness of the first layer to the thickness of the second layer is about 4:1.

[0126] In some examples, the aluminum concentration of the first layer is at least two times higher than the aluminum concentration of the second layer at the interface between the first and second layers.

[0127] While the present subject matter has been described in detail with reference to specific exemplary embodiments thereof, it will be appreciated that those skilled in the art, upon attaining the foregoing understanding, may readily make alterations, variations, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is intended to be illustrative rather than limiting, and the disclosure of the present subject matter is not intended to exclude the inclusion of such modifications, variations, and / or additions to the present subject matter that would be readily apparent to those skilled in the art.

Claims

1. 1. A transistor device comprising: a channel layer; a multi-layer barrier structure overlying the channel layer, the multi-layer barrier structure comprising a first Group III nitride layer and a second Group III nitride layer over the first Group III nitride layer opposite the channel layer, the first Group III nitride layer having a thickness greater than a thickness of the second Group III nitride layer; Equipped with A transistor device wherein the aluminum concentration of the first Group III-nitride layer is at least two times higher than the aluminum concentration of the second Group III-nitride layer.

2. 10. The transistor device of claim 1, a thickness of the second Group III-nitride layer or an aluminum concentration of the second Group III-nitride layer such that a current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0V relative to operation of the transistor device before the stress condition, the stress condition comprising a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

3. 10. The transistor device of claim 1, a thickness of the second Group III-nitride layer or an aluminum concentration of the second Group III-nitride layer such that a pinch-off voltage shift of the transistor device after the stress condition is about 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, the stress condition comprising a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of −8 V.

4. 10. The transistor device of claim 1, A transistor device, wherein the aluminum concentration of the first Group III-nitride layer is at least five times higher than the aluminum concentration of the second Group III-nitride layer.

5. 10. The transistor device of claim 1, The transistor device, wherein the aluminum mole fraction of the first Group III nitride layer ranges from about 20% to about 100%.

6. 6. The transistor device of claim 5, The aluminum mole fraction of the second III-nitride layer ranges from about 1% to about 10%.

7. 10. The transistor device of claim 1, a ratio of the thickness of the first Group III-nitride layer to the thickness of the second Group III-nitride layer is 4:1 or greater.

8. 10. The transistor device of claim 1, a first Group III-nitride layer having a thickness of about 200 Angstroms to about 250 Angstroms and a second Group III-nitride layer having a thickness of about 50 Angstroms or less;

9. 10. The transistor device of claim 1, the multi-layer barrier structure comprises an interfacial layer, the first Group III nitride layer being disposed on the interfacial layer opposite the channel layer; A transistor device, wherein the aluminum concentration of the interfacial layer is greater than the aluminum concentration of the first Group III-nitride layer and the aluminum concentration of the second Group III-nitride layer.

10. 10. The transistor device of claim 9, The transistor device, wherein the thickness of the interfacial layer is in the range of about 50 angstroms or less.

11. 10. The transistor device of claim 1, The transistor device further comprises a source contact and a drain contact on the multi-layer barrier structure.

12. 10. The transistor device of claim 1, the second Group III nitride layer has a graded concentration of aluminum that increases such that the second Group III nitride layer has a higher aluminum concentration at the interface between the first Group III nitride layer and the second Group III nitride layer relative to a surface of the second Group III nitride layer opposite the first Group III nitride layer.

13. 10. The transistor device of claim 1, The transistor device further comprises a cap layer on the multi-layer barrier structure.

14. 10. The transistor device of claim 1, The transistor device is a high electron mobility transistor.

15. 10. The transistor device of claim 1, The transistor device, wherein the channel layer is disposed on a silicon carbide substrate.

16. 1. A transistor device comprising: a channel layer; a multi-layer barrier structure overlying the channel layer, the multi-layer barrier structure comprising a first Group III nitride layer and a second Group III nitride layer over the first Group III nitride layer opposite the channel layer, the first Group III nitride layer having a thickness at least four times greater than a thickness of the second Group III nitride layer; Equipped with A transistor device, wherein the first Group III nitride layer has a higher aluminum concentration than the second Group III nitride layer.

17. 17. The transistor device of claim 16, the thickness of the second III-nitride layer or the aluminum concentration of the second III-nitride layer is such that a current collapse of the transistor device after the stress condition is about 30% or less at a gate voltage of 0V relative to operation of the transistor device before the stress condition, the stress condition comprising a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

18. 17. The transistor device of claim 16, wherein the thickness of the second Group III-nitride layer or the aluminum concentration of the second Group III-nitride layer is such that a pinch-off voltage shift of the transistor device after the stress condition is about 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, the stress condition comprising a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of −8 V.

19. 17. The transistor device of claim 16, the multi-layer barrier structure comprises an interfacial layer, the first Group III nitride layer being disposed on the interfacial layer opposite the channel layer; A transistor device, wherein the aluminum concentration of the interfacial layer is greater than the aluminum concentration of the first Group III-nitride layer and the aluminum concentration of the second Group III-nitride layer.

20. 20. The transistor device of claim 19, The transistor device, wherein the thickness of the interfacial layer is in the range of about 50 angstroms or less.

21. 17. The transistor device of claim 16, A transistor device, wherein the aluminum concentration of the first Group III-nitride layer is at least two times higher than the aluminum concentration of the second Group III-nitride layer.

22. 1. A transistor device comprising: a channel layer; a multi-layer barrier structure on the channel layer, the multi-layer barrier structure comprising a first layer on the channel layer, a second layer on the first layer, and a third layer on the second layer; Equipped with The first layer is Al ｘ Ga １－ｘ N layers, x≧0.5; The second layer is Al ｙ Ga １－ｙ N layers, 0.2≦y<1; The third layer is Al ｚ Ga １－ｚ A transistor device having N layers, where 0<z≦0.

1.

23. 23. The transistor device of claim 22, A transistor device, wherein the ratio of the thickness of the second layer to the thickness of the third layer is 4:1 or greater.

24. 23. The transistor device of claim 22, Further, the transistor device comprises a silicon carbide substrate.

25. 1. A transistor device comprising: a channel layer; a multi-layer III-nitride based barrier structure on the channel layer, the multi-layer III-nitride based barrier structure comprising a first layer and a second layer on the first layer; Equipped with The thickness of the second layer or the aluminum concentration of the second layer is such that a current collapse of the transistor device after a stress condition is about 30% or less at a gate voltage of 0V relative to the operation of the transistor device before the stress condition, the stress condition comprising a 10 millisecond pulse of a drain voltage of 100V and a gate voltage of -8V.

26. 26. The transistor device of claim 25, A transistor device, wherein the ratio of the thickness of the first layer to the thickness of the second layer is about 4:

1.

27. 26. The transistor device of claim 25, A transistor device, wherein the aluminum concentration of the first layer is at least two times higher than the aluminum concentration of the second layer at the interface between the first layer and the second layer.

28. 1. A transistor device comprising: a channel layer; a multi-layer III-nitride based barrier structure on the channel layer, the multi-layer III-nitride based barrier structure comprising a first layer and a second layer on the first layer; Equipped with a thickness of the second layer or an aluminum concentration of the second layer such that a pinch-off voltage shift of the transistor device after the stress condition is about 0.4 V or less at a drain voltage of 50 V relative to operation of the transistor device before the stress condition, the stress condition comprising a 10 millisecond pulse of a drain voltage of 100 V and a gate voltage of −8 V.

29. 30. The transistor device of claim 28, A transistor device, wherein the ratio of the thickness of the first layer to the thickness of the second layer is about 4:

1.

30. 30. The transistor device of claim 28, A transistor device, wherein the aluminum concentration of the first layer is at least two times higher than the aluminum concentration of the second layer at the interface between the first layer and the second layer.

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