Fluorine-doped silicon-containing materials

Abstract

An exemplary semiconductor processing method may include delivering one or more deposition precursors to a processing region of a semiconductor processing chamber. The method may include contacting a substrate contained in the processing region with the one or more deposition precursors. The method may include forming a silicon-containing material on the substrate. The method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The method may include contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material. The method may include contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 941,347, filed Sep. 9, 2022, entitled "FLUORINE-DOPED SILICON-CONTAINING MATERIALS," the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology relates to deposition processes and chambers, and more particularly to methods for producing fluorine-doped silicon-containing materials. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on the surface of a substrate. Creating patterned materials on a substrate requires controlled methods for forming and removing materials. The properties of the materials can affect the operation of the device and can also affect how films are removed relative to each other. Plasma deposition can create films with specific properties. Many of the films formed require additional processing to adjust or enhance the material properties of the film to provide the appropriate properties.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technique. Summary of the Invention

[0005] An exemplary semiconductor processing method may include delivering one or more deposition precursors to a processing region of a semiconductor processing chamber. The method may include contacting a substrate contained in the processing region with the one or more deposition precursors. The method may include forming a silicon-containing material on the substrate. The method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The method may include contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material. The method may include contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen.

[0006] In some embodiments, the one or more deposition precursors include a silicon-containing precursor and a boron-containing precursor. During the semiconductor processing method, a temperature within the semiconductor processing chamber may be maintained at or below about 550° C. The substrate may include features characterized by an aspect ratio of about 3:1 or greater. The method may include stopping the flow of the one or more deposition precursors after formation of the silicon-containing material on the substrate. The method may include reducing the pressure within the semiconductor processing chamber before delivering a fluorine-containing precursor to a processing region of the semiconductor processing chamber. While contacting the silicon-containing material on the substrate with the fluorine-containing precursor, the pressure within the semiconductor processing chamber may be maintained at or below about 15 Torr. The method may include forming an argon or diatomic nitrogen plasma effluent before contacting the fluorine-treated silicon-containing material with the argon or diatomic nitrogen plasma effluent. The argon or diatomic nitrogen plasma effluent may be formed at a plasma power of about 750 W or less. The method may include contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen to form a fluorine-doped silicon-boron-nitrogen-containing material. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by a conformality of about 90% or greater. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by a thickness of about 750 Å or less. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by a dielectric constant of about 4.6 or less.

[0007] Some embodiments of the present technology include a semiconductor processing method. The method may include: i) forming a silicon-containing material on a substrate; ii) contacting the silicon-containing material on the substrate with a fluorine-containing precursor to form a fluorine-treated silicon-containing material; iii) contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen to form a fluorine-doped silicon-boron-nitrogen-containing material; and iv) repeating steps i) through iii) for at least five cycles.

[0008] In some embodiments, steps i) and ii) are performed plasma-free. The substrate may include features characterized by an aspect ratio of about 3:1 or greater. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by a conformality of about 90% or greater. During the semiconductor processing method, a temperature may be maintained at about 550° C. or less. During the semiconductor processing method, a pressure may be maintained at about 40 Torr or less. The method may include v) annealing the substrate and the fluorine-doped silicon-boron-nitrogen-containing material.

[0009] Some embodiments of the present technique include a semiconductor processing method. The method may include delivering one or more deposition precursors to a processing region of a semiconductor processing chamber. The one or more deposition precursors may include a silicon-containing precursor. The method may include contacting a substrate contained in the processing region with the one or more deposition precursors. The method may include thermally forming a layer of silicon-containing material on the substrate. The method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The method may include thermally contacting the layer of silicon-containing material on the substrate with the fluorine-containing precursor to form a layer of fluorine-doped silicon-containing material. The method may include delivering argon, diatomic nitrogen, or both to the processing region of the semiconductor processing chamber. The method may include forming plasma effluents of argon, diatomic nitrogen, or both. The method may include contacting the layer of fluorine-doped silicon-containing material with plasma effluents of argon, diatomic nitrogen, or both to form the fluorine-doped silicon-containing material.

[0010] In some embodiments, the layer of fluorine-doped silicon-containing material is characterized by a conformality of about 90% or greater. The plasma effluent of argon, diatomic nitrogen, or both may be formed at a plasma power of about 750 W or less. The layer of fluorine-doped silicon-containing material has a dielectric constant of about 4.6 or less and a dielectric constant of about 5.0E-08 A / cm. 2and leakage current:

[0011] The above techniques can provide many advantages over conventional systems and techniques. For example, fluorine and plasma treatments can be performed to improve deposition characteristics. For example, fluorine treatments can be performed to improve the conformality of the deposited material, reduce the dielectric constant of the deposited material, and / or reduce leakage current of the deposited material. Additionally, plasma treatments can densify the material, further improving conformality and / or reducing the dielectric constant. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2] 1 is a schematic cross-sectional view illustrating an exemplary plasma system according to some embodiments of the present technique; [Figure 3] 1A-1D illustrate steps of an exemplary semiconductor processing method in accordance with some embodiments of the present technique. [Figure 4A] 1A-1D illustrate cross-sectional views of a substrate being processed in accordance with some embodiments of the present technique. [Figure 4B] 1A-1D illustrate cross-sectional views of a substrate being processed in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0017] Some of the figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless scale is specifically stated. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0015]

[0018] In the accompanying figures, similar components and / or features may be labeled with the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a letter that distinguishes between the similar components. When only a first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016]

[0019] In the formation of integrated circuits, many layers of material are formed and then partially or completely removed. Some integrated circuits require the formation of spacer or liner materials to at least partially isolate other materials formed on either side of the spacer. Conventional techniques may use purely thermal processes or deposition and etch loop processes to form spacer or liner materials with the desired conformality. These conventional approaches cannot simultaneously achieve both a low dielectric constant and high conformality. As integrated circuits continue to shrink, there is an increasing desire for material layers that serve multiple purposes, such as low dielectric constant and high conformality. Furthermore, these conventional approaches may result in the formation of spacer or liner materials that do not meet leakage current or voltage resistance requirements. Furthermore, these conventional techniques are prone to shrinkage during post-formation processing, such as annealing, which may result in the material not maintaining its desired properties.

[0017]

[0020] The present technology overcomes these problems by performing a fluorine treatment and / or plasma treatment after the deposition of the silicon-containing material. The fluorine treatment can introduce a fluorine-containing precursor to thermally treat the formed silicon-containing material, thereby doping the silicon-containing material with fluorine. When doping the silicon-containing material, the fluorine can replace hydrogen bonds in the material with fluorine bonds. This replacement smooths the surface of the silicon-containing material and improves its conformality. Plasma treatment bombards the film with heavy inert precursors to densify the film and further improve conformality. The fluorine treatment and / or plasma treatment can also favorably affect the electrical properties of the silicon-containing material, such as the dielectric constant, leakage current, and breakdown voltage. Conventional techniques cannot address all of these properties of the deposited film, thereby sacrificing one or more desirable properties.

[0018]

[0021] While the remainder of the disclosure will always identify specific deposition processes using the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition chambers and processes that may be performed in the described chambers. Accordingly, the present technology should not be considered limited to use with only these specific deposition processes or chambers. This disclosure will describe one possible system and chamber that may be used to perform deposition processes according to embodiments of the present technology, before describing additional details according to embodiments of the present technology.

[0019]

[0022] FIG. 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100 according to an embodiment. In the figure, a pair of front-opening unified pods 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f positioned in tandem sections 109a-c. Substrate wafers can be transported from the holding area 106 to and from the substrate processing chambers 108a-f using a second robotic arm 110. Each substrate processing chamber 108a-f can be equipped to perform multiple substrate processing steps, including the formation of stacks of semiconductor materials described herein, in addition to other substrate processes including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and annealing, ashing, etc.

[0020]

[0023] The substrate processing chambers 108a-f can include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, can be used to deposit a dielectric material on a substrate, and a third pair of processing chambers, e.g., 108a-b, can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, can be configured to deposit a stack of alternating dielectric films on a substrate. Any one or more of the described processes can be performed in chambers separate from the manufacturing system shown in different embodiments. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100.

[0021]

[0024] 2 is a schematic cross-sectional view illustrating an exemplary plasma system 200 according to some embodiments of the present technique. The plasma system 200 may be equipped in one or more of the tandem sections 109 described above and may include a pair of processing chambers 108 that may include lid stack components according to embodiments of the present technique, which may be further described below. The plasma system 200 may generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an interior sidewall 201 that defines a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include identical components.

[0022]

[0025] For example, processing region 220B (components of which may also be included in processing region 220A) may include a pedestal 228 disposed within the processing region through a passageway 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, to heat and control the substrate temperature to a desired process temperature. The pedestal 228 may also be heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0023]

[0026] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 may electrically couple the pedestal 228 to a power outlet or power box 203. The power box 203 may include a drive system that controls the elevation and movement of the pedestal 228 within the processing region 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include an interface for power and a temperature indicator, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to detachably couple with the power box 203. A perimeter ring 235 is illustrated above the power box 203. In some embodiments, the perimeter ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0024]

[0027] A rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing region 220B and may be utilized to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively space the substrate 229 from the pedestal to facilitate exchange of the substrate 229 by a robot utilized to transfer the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0025]

[0028] A chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may house one or more precursor delivery systems 208 coupled thereto. The precursor delivery system 208 may include a precursor inlet passage 240 that may deliver reactant and cleaning precursors into the processing region 220B through a dual channel showerhead 218. The dual channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 disposed intermediate a faceplate 246. A radio frequency (“RF”) source 265 may be coupled to the dual channel showerhead 218, which may provide power to the dual channel showerhead 218 to facilitate generation of a plasma region between the faceplate 246 and the pedestal 228 of the dual channel showerhead 218. In some embodiments, the RF source may be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the dual channel showerhead 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 may be disposed around the periphery of the pedestal 228 to engage the pedestal 228.

[0026]

[0029] Optional cooling channels 247 may be formed in the annular base plate 248 of the precursor delivery system 208 for cooling the annular base plate 248 during processing. A heat transfer fluid, such as water, ethylene glycol, or gas, may be circulated through the cooling channels 247 so that the base plate 248 may be maintained at a predetermined temperature. A liner assembly 227 may be positioned in the processing region 220B adjacent to the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment in the processing region 220B. The liner assembly 227 may include an ambient pumping cavity 225 that may be coupled to a pumping system 264 configured to evacuate gases and byproducts from the processing region 220B and control the pressure in the processing region 220B. A plurality of exhaust ports 231 may be formed on the liner assembly 227. The exhaust port 231 can be configured to allow gas flow from the processing region 220B to the ambient pumping cavity 225 in a manner that facilitates processing within the system 200.

[0027]

[0030] FIG. 3 illustrates steps in an exemplary method 300 of semiconductor processing according to some embodiments of the present technology. The method can be performed in a variety of processing chambers, including the processing system 200 described above, as well as any other chamber in which plasma deposition can be performed. Method 400 can include one or more steps prior to the start of the method, including front-end processing, polishing, cleaning, deposition, etching, or any other steps that can be performed before the described steps. Method 300 can include numerous optional steps that may or may not be particularly relevant to some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader range of structure formation, but are not critical to the present technology or may be performed by alternative methodologies, as described further below. Method 300 illustrates steps shown generally in FIGS. 4A-4B, which will be discussed in conjunction with the steps of method 300. It should be understood that FIGS. 4A-4B are partial schematic views only, and that a substrate can include any number of transistor features having the configurations illustrated in the figures.

[0028]

[0031] 4A, the structure 400 can include a substrate 405. The substrate 405 can be made of or can include silicon or other semiconductor substrate materials. One or more material layers 410 can be formed on the substrate 405. The one or more material layers 410 can include or define a recess 415. The aspect ratio of the recess 415, or the ratio of the hole length to the hole diameter, can be about 2:1 or greater, and can be about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, or greater.

[0029]

[0032] In step 305, the method 300 may include supplying one or more deposition precursors into a processing chamber that may deliver the precursors into a processing region of the chamber that may house the substrate 405, such as region 220. The deposition precursors may include, for example, a silicon-containing precursor, a boron-containing precursor, a nitrogen-containing precursor, or any other deposition precursor used to form a silicon-containing material.

[0030]

[0033] In embodiments, one or more deposition precursors may include a silicon-containing precursor. The silicon-containing precursor may include an organosilane, which may include silane, disilane, and other materials. Additional silicon-containing precursors may include silicon, carbon, oxygen, or nitrogen, such as trisilylamine. In embodiments, one or more deposition precursors may include a boron-containing precursor. The boron-containing precursor may include boron, such as borane, diborane, or other multi-core boron materials, as well as any other boron-containing material that can be used to produce silicon-boron-containing materials. In some embodiments, deposition may use a single deposition precursor, such as a silicon- and boron-containing precursor. The precursor may or may not include delivery of additional precursors, such as a carrier gas or one or more oxygen-containing precursors for depositing an oxide layer.

[0031]

[0034] In step 310, the method 300 may include contacting the substrate 405 with one or more deposition precursors. As shown in FIG. 4B, in step 315, the method 300 may include forming a silicon-containing material 420. The silicon-containing material may be formed on one or more material layers 410 formed on the substrate 405.

[0032]

[0035] Process conditions can dictate the steps performed in method 300. While each step of method 300 can be performed at a constant temperature in some embodiments, in some embodiments, the temperature can be adjusted during different steps. In some embodiments of the present technology, method 300 can be performed when the substrate, pedestal, and / or chamber temperature is below about 550°C, which can be due to thermal balance issues, and can be performed at temperatures below about 525°C, below about 500°C, below about 475°C, below about 450°C, below about 425°C, below about 400°C, below about 375°C, below about 350°C, below about 325°C, below about 300°C, or below. Temperatures can also be maintained within these ranges, within smaller ranges encompassed by these ranges, or anywhere between any of these ranges. Forming materials at higher temperatures can reduce deposition rates and therefore improve conformality. Thus, in some embodiments, pressure can be maintained between about 400°C and about 500°C.

[0033]

[0036] The pressure within the semiconductor processing chamber can also affect the processes performed. In embodiments, the pressure may be maintained below about 40 Torr. Thus, the pressure may be maintained at about 35 Torr or less, about 30 Torr or less, about 25 Torr or less, about 20 Torr or less, about 18 Torr or less, about 16 Torr or less, about 14 Torr or less, about 12 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, about 4 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. The pressure may also be maintained at any pressure within these ranges, within smaller ranges encompassed within these ranges, or between these ranges. Furthermore, the pressure may be adjusted during method 300, as described below. Conformity may increase as the pressure increases, as the precursors scatter more before reaching the substrate, thereby arriving at the substrate surface at more random angles, resulting in more conformal film growth. Thus, in some embodiments, the pressure may be maintained at about 10 Torr to about 20 Torr.

[0034]

[0037] In step 320, the method 300 may include supplying a fluorine-containing precursor into a processing chamber that may deliver the precursor into a processing region of the chamber where the substrate 405 may be housed. An exemplary fluorine-containing precursor may be nitrogen trifluoride (NF). Other sources of fluorine may be used in combination with or as a replacement for nitrogen trifluoride. In some embodiments, the fluorine-containing precursor may be or include atomic fluorine, diatomic fluorine, hydrogen fluoride, nitrogen trifluoride, carbon tetrafluoride, xenon difluoride, and various other fluorine-containing precursors used or available in semiconductor processing.

[0035]

[0038] In step 325, the method 300 may include contacting the silicon-containing material 420 with a fluorine-containing precursor. The fluorine-containing precursor may dope the silicon-containing material 420 to form a silicon-doped fluorine-containing material. Specifically, the fluorine-containing precursor may rearrange bonds in the silicon-containing material, replacing at least some Si-H and B-H bonds with Si-F and BF, respectively. Fluorine bonds, which are less polarizable compared to the previous hydrogen bonds, may decrease the dielectric constant of the silicon-containing material 420. Fluorine bonds may reduce leakage current of the silicon-containing material 420. Furthermore, contacting the silicon-containing material 420 with the fluorine-containing precursor may result in the formation of Si-F bonds from dangling silicon bonds on the surface of the silicon-containing material 420. The formation of Si-F bonds from dangling silicon bonds and the increased polarization stability of fluorine may stabilize the surface of the silicon-containing material 420, thereby relaxing strained portions on the surface. Relaxing strained portions on the surface of the silicon-containing material 420 may improve conformality. After contact with the fluorine-containing precursor, the silicon-containing material 420 may be characterized by a fluorine concentration of about 30 atomic % or less, and may be characterized by a fluorine concentration of about 28 atomic % or less, about 26 atomic % or less, about 24 atomic % or less, about 22 atomic % or less, about 20 atomic % or less, about 18 atomic % or less, about 16 atomic % or less, about 14 atomic % or less, about 12 atomic % or less, about 10 atomic % or less, or less.

[0036]

[0039] In embodiments, method 300 may include reducing the pressure between steps 320 and 325. For example, the pressure may be reduced to about 15 Torr or less, about 14 Torr or less, about 13 Torr or less, about 12 Torr or less, about 11 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. Lower pressures may result in shorter residence times for the fluorine-containing precursor compared to steps 305-315. Lower pressures may increase the mean free path, which may increase interaction between the fluorine-containing precursor and the silicon-containing material 420.

[0037]

[0040] The fluorine treatment in steps 320 and 325 may continue for a period of time sufficient for the fluorine-containing precursor to interact with the silicon-containing material 420. For example, the fluorine treatment in steps 320 and 325 may continue for a period of time from about 2 seconds to about 60 seconds. However, it is contemplated that steps 320 and 325 may continue for a period of time less than about 2 seconds and / or more than about 60 seconds, depending on various conditions such as temperature, pressure, flow rate of the fluorine-containing precursor, and properties and characteristics of the silicon-containing material 420.

[0038]

[0041] In embodiments, method 300 may include stopping the flow of one or more deposition precursors prior to delivering the fluorine-containing precursor in step 320. Stopping the flow of one or more deposition precursors may reduce or stop the deposition of material and allow the fluorine-containing precursor to dope into the formed silicon-containing material 420. However, it is contemplated that the flow of one or more deposition precursors may alternatively be reduced and / or maintained during step 320.

[0039]

[0042] In step 330, method 300 may include contacting the fluorine-treated silicon-containing material with plasma effluents. Note that prior to step 330, the semiconductor processing chamber may be maintained plasma-free, e.g., during any or all of steps 305-325. Method 300 may include supplying one or more plasma processing precursors into the processing chamber, which may deliver the precursors into a processing region of the chamber where the substrate 405 may be housed. The plasma processing precursors may include a nitrogen-containing precursor, such as diatomic nitrogen, which may add nitrogen to the silicon-containing material 420. After treatment with the fluorine-containing precursor, plasma processing in step 330 may form a fluorine-doped silicon-nitrogen-containing material, such as a fluorine-doped silicon-boron-nitrogen-containing material. The plasma processing precursors may also include one or more inert species, such as argon, neon, xenon, or hydrogen.

[0040]

[0043] The plasma effluent of the one or more plasma treatment precursors may be generated at a plasma power of about 750 W or less. Plasma powers greater than 750 W may increase the likelihood of arcing, which may be detrimental to the plasma treatment and the formation of the fluorine-doped silicon-containing material. Thus, the plasma effluent of the one or more plasma treatment precursors may be generated at a plasma power of about 700 W or less, and may be generated at about 650 W or less, about 600 W or less, about 550 W or less, about 500 W or less, about 450 W or less, about 400 W or less, about 350 W or less, about 300 W or less, about 250 W or less, about 200 W or less, about 150 W or less, or less.

[0041]

[0044] The plasma treatment in step 330 can add material to the silicon-containing material 420, such as through plasma effluents of a nitrogen-containing precursor. Additionally, plasma effluents of an inert precursor can bombard the film and densify the silicon-containing material 420. As the silicon-containing material 420 densifies, conformality can be further improved. The use of a heavier inert precursor, such as argon, can bombard the film and densify the silicon-containing material 420. The plasma treatment in step 330 can be performed at reduced pressures in steps 320 and 325, which can increase the plasma density and help densify the film more uniformly, also improving the conformality of the silicon-containing material 420.

[0042]

[0045] The plasma treatment in step 330 may continue for a period of time sufficient for the plasma to interact with the silicon-containing material 420. For example, the plasma treatment in step 330 may continue for a period of time from about 2 seconds to about 60 seconds. However, it is contemplated that step 330 may continue for a period of time less than about 2 seconds and / or greater than about 60 seconds, depending on various conditions, such as temperature, pressure, flow rate of the plasma treatment precursor, and properties and characteristics of the silicon-containing material 420.

[0043]

[0046] After the plasma treatment in step 330, the fluorine-doped silicon-containing material 420 may be characterized by a thickness of about 40 Å or less. If the silicon-containing material 420 is formed to a thickness greater than 40 Å, the fluorine treatments in steps 320 and 325 and the plasma treatment in step 330 may not be as effective. Thus, the silicon-containing material 420 may be formed to a thickness of about 35 Å or less, about 30 Å or less, about 25 Å or less, about 20 Å or less, about 15 Å or less, about 10 Å or less, about 5 Å or less, or less.

[0044]

[0047] 3, method 300 may include repeating steps 300-330 multiple times in step 335. Repeating steps 300-330 may form a silicon-containing material 420 with an increased thickness. In embodiments, the steps of method 300 may be repeated at least 2 cycles, at least 3 cycles, at least 4 cycles, at least 5 cycles, at least 10 cycles, at least 15 cycles, at least 20 cycles, at least 30 cycles, at least 40 cycles, at least 50 cycles, or more. Thus, after several cycles of the process, the silicon-containing material may be characterized by a thickness of up to about 750 Å or about 500 Å, for example, about 100 Å or more, about 125 Å or more, about 150 Å or more, about 175 Å or more, about 200 Å or more, about 250 Å or more, about 300 Å or more, about 350 Å or more, about 400 Å or more, about 450 Å or more, about 500 Å or more, about 550 Å or more, about 600 Å or more, about 650 Å or more, about 700 Å or more, or more.

[0045]

[0048] As previously mentioned, the present techniques can form silicon-containing materials characterized by low dielectric constants and improved electrical performance. For example, silicon-containing materials formed according to the present techniques can be characterized by conformality of about 90% or greater, e.g., about 91% or greater, about 92% or greater, about 93% or greater, about 94% or greater, about 95% or greater, or more. Furthermore, silicon-containing materials formed according to the present techniques can be characterized by a dielectric constant of about 4.6 or less, e.g., about 4.5 or less, about 4.4 or less, about 4.3 or less, about 4.2 or less, about 4.1 or less, about 4.0 or less, about 3.9 or less, or less. Silicon-containing materials formed according to the present techniques can have a dielectric constant of about 5.0E-08 A / cm 2 For example, about 4.8E-08A / cm 2 Below, about 4.6E-08A / cm 2 Below, about 4.4E-08A / cm 2 Below, about 4.2E-08A / cm 2 Below, about 4.0E-08A / cm 2 Below, about 3.9E-08A / cm 2 Below, about 3.8E-08A / cm 2Conventional techniques may be characterized by conformality of about 90% or greater, a dielectric constant of about 4.6 or less, and / or a leakage current of about 5.0E-08 A / cm. 2 It may be impossible to produce silicon-containing films characterized by leakage currents below: The fluorine and plasma treatments of the present technique can sufficiently modify the formed silicon-containing materials to tailor the film properties as described.

[0046]

[0049] In an embodiment, after silicon-containing material 420 is formed to a desired thickness, an anneal or other rapid thermal process may be performed in optional step 340. The anneal or other process may not substantially change the properties of the silicon-containing material, indicating the thermal stability of silicon-containing material 420.

[0047]

[0050] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0048]

[0051] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. Moreover, in order to avoid unnecessarily obscuring the technology, some well-known processes and elements have not been described. Therefore, the above description should not be taken as limiting the scope of the technology.

[0049]

[0052] Where a range of values ​​is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limit of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value in that stated range is also included. The upper and lower limits of these smaller ranges may independently be included or excluded, and each range in which either or both limits are included in the smaller ranges is also included within the technology, subject to any specifically excluded limits in the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0050]

[0053] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a silicon-containing precursor" includes a plurality of such silicon-containing precursors; a reference to "the layer of material" includes a reference to one or more layers of material and equivalents thereof known to those skilled in the art, and so forth.

[0051]

[0054] Also, as used in this specification and the claims that follow, the terms "comprise," "comprising," "contain," "containing," "include," and "including" specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A semiconductor processing method comprising: delivering one or more deposition precursors to a processing region of a semiconductor processing chamber; contacting a substrate contained in the processing region with the one or more deposition precursors; forming a silicon-containing material on the substrate; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; contacting a silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorinated silicon-containing material; contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen; A method comprising:

2. 10. The semiconductor processing method of claim 1, wherein the one or more deposition precursors include a silicon-containing precursor and a boron-containing precursor.

3. 10. The semiconductor processing method of claim 1, wherein the temperature within said semiconductor processing chamber is maintained at or below about 550[deg.] C. during said semiconductor processing method.

4. 10. The semiconductor processing method of claim 1, wherein the substrate includes features characterized by an aspect ratio of about 3:1 or greater.

5. stopping the flow of the one or more deposition precursors after formation of the silicon-containing material on the substrate; reducing the pressure in the semiconductor processing chamber prior to delivering the fluorine-containing precursor to the processing region of the semiconductor processing chamber; The semiconductor processing method of claim 1 further comprising:

6. 6. The semiconductor processing method of claim 5, wherein the pressure in the semiconductor processing chamber is maintained at about 15 Torr or less while contacting the silicon-containing material on the substrate with the fluorine-containing precursor.

7. 10. The semiconductor processing method of claim 1, further comprising forming argon or diatomic nitrogen plasma effluents prior to contacting the fluorine-treated silicon-containing material with argon or diatomic nitrogen plasma effluents, wherein the argon or diatomic nitrogen plasma effluents are formed at a plasma power of about 750 W or less.

8. contacting the fluorine-treated silicon-containing material with the argon or diatomic nitrogen plasma effluents to form a fluorine-doped silicon-boron-nitrogen-containing material; The fluorine-doped silicon-boron-nitrogen containing material has a conformality of about 90% or greater. characterized by, 10. The semiconductor processing method of claim 1.

9. 9. The semiconductor processing method of claim 8, wherein the fluorine doped silicon-boron-nitrogen containing material is characterized by a thickness of about 750 Å or less.

10. 9. The semiconductor processing method of claim 8, wherein said fluorine doped silicon-boron-nitrogen containing material is characterized by a dielectric constant of about 4.6 or less.

11. 1. A semiconductor processing method comprising: i) forming a silicon-containing material on a substrate; ii) contacting the silicon-containing material on the substrate with a fluorine-containing precursor to form a fluorinated silicon-containing material; iii) contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen to form a fluorine-doped silicon-boron-nitrogen-containing material; iv) repeating steps i) to iii) for at least five cycles; A method comprising:

12. 12. The semiconductor processing method of claim 11, wherein steps i) and ii) are performed plasma-free.

13. 12. The semiconductor processing method of claim 11, wherein the substrate includes features characterized by an aspect ratio of about 3:1 or greater.

14. 12. The semiconductor processing method of claim 11, wherein the fluorine doped silicon-boron-nitrogen containing material is characterized by a conformality of about 90% or greater.

15. maintaining a temperature below about 550° C. during the semiconductor processing method; the pressure is maintained at or below about 40 Torr during the semiconductor processing method; 12. The semiconductor processing method of claim 11.

16. v) annealing the substrate and the fluorine-doped silicon-boron-nitrogen containing material. The semiconductor processing method of claim 11 further comprising:

17. 1. A semiconductor processing method comprising: delivering one or more deposition precursors to a processing region of a semiconductor processing chamber, the one or more deposition precursors comprising a silicon-containing precursor; contacting a substrate contained in the processing region with the one or more deposition precursors; thermally forming a layer of silicon-containing material on the substrate; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; bringing a layer of silicon-containing material on the substrate into thermal contact with the fluorine-containing precursor to form a layer of silicon-containing material doped with fluorine; providing argon, diatomic nitrogen, or both to the processing region of the semiconductor processing chamber; forming a plasma effluent of argon, diatomic nitrogen, or both; contacting the layer of fluorine-doped silicon-containing material with the plasma effluents of argon, diatomic nitrogen, or both to form a fluorine-doped silicon-containing material; A method comprising:

18. 20. The semiconductor processing method of claim 17, wherein the layer of fluorine-doped silicon-containing material is characterized by a conformality of about 90% or greater.

19. 20. The semiconductor processing method of claim 17, wherein the argon, diatomic nitrogen, or both plasma effluents are formed at a plasma power of about 750 W or less.

20. The layer of fluorine-doped silicon-containing material comprises: a dielectric constant of about 4.6 or less; Approximately 5.0E-08 A / cm ２ The following leakage current and 20. The semiconductor processing method of claim 17, characterized by:

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