Back contact with shallow brace holder and easy back semiconductor removal

Abstract

The semiconductor structure includes a first source-drain region, a second source-drain region, at least one channel region connecting the first and second source-drain regions, and a gate adjacent to the at least one channel region. A bottom dielectric isolation region is located within the gate. First and second bottom silicon regions are located within the first and second source-drain regions, respectively. A backside contact protrudes through the second bottom silicon region to the second source-drain region.

Description

[Technical Field]

[0001] The present invention relates generally to electrical, electronic, and computer technologies, and more particularly to backside contacts for use with backside power distribution networks (BSPDNs). [Background technology]

[0002] A power distribution network provides power and reference voltages to active devices on a semiconductor chip; this power distribution network is essentially a network of interconnects distinct from the signal network. Traditionally, both power and signal networks have been formed on the front side of the wafer by back-end interconnect (BEOL) processing. More recently, BSPDNs have been developed, which distribute power from the back side of the wafer, typically formed during backside wafer processing. Summary of the Invention

[0003] In accordance with the principles of the present invention, techniques are provided for backside contacts with shallow trace holders and facilitating backside semiconductor removal. In one embodiment, an exemplary semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region connecting the first and second source-drain regions; a gate adjacent to the at least one channel region; a bottom dielectric isolation region inside the gate; first and second bottom silicon regions located inside the first and second source-drain regions, respectively; and a backside contact protruding through the second bottom silicon region to the second source-drain region.

[0004] In another aspect, an exemplary semiconductor array structure includes a plurality of field effect transistors, each having a first source-drain region, a second source-drain region, at least one channel region connecting the first and second source-drain regions, a gate adjacent to the at least one channel, a bottom dielectric isolation region inside the gate, and first and second bottom silicon regions located inside the first and second source-drain regions, respectively, and also including a backside power distribution network; a surface wiring network; a plurality of contacts interconnecting the surface wiring network and the plurality of first source-drain regions; and a plurality of backside contacts each protruding through a corresponding one of the second bottom silicon regions into a corresponding one of the second source-drain regions, the backside contacts each connected to the backside power distribution network.

[0005] In yet another aspect, an exemplary method for forming a semiconductor structure includes providing a precursor structure having a nanosheet stack outside a high-Ge SiGe epitaxial growth layer and a low-Ge SiGe epitaxial growth layer on an underlying substrate; removing the high-Ge SiGe layer and forming a bottom dielectric isolation (BDI) in the area vacated by the high-Ge SiGe layer; forming two sacrificial placeholders at least partially in the low-Ge SiGe epitaxial growth layer and forming source-drain regions outside the two sacrificial placeholders; and forming a middle-of-line (MOL) structure and a back-of-line (BEOL) structure outside the precursor structure and bonding a carrier wafer to the outside of the (BEOL) structure. The method further includes flipping the carrier wafer to remove the substrate, stopping on the Ge-low SiGe layer; removing the Ge-low SiGe layer selectively to the BDI and the sacrificial placeholders; forming a backside interlayer dielectric (ILD) inside the BDI; forming a backside contact opening in at least the backside ILD to reveal one of the sacrificial placeholders; and forming a backside contact in the backside contact opening.

[0006] As used herein, "facilitating" an activity includes performing an activity, making an activity easier, assisting in the performance of an activity, or having an activity performed. Thus, by way of example and not limitation, instructions executing on a processor may facilitate an activity performed by a semiconductor manufacturing facility by sending appropriate data or commands to cause or assist in the performance of an activity. When an actor facilitates an activity by something other than performing the activity, the activity is still performed by some entity or combination of entities.

[0007] The techniques disclosed herein can provide substantial beneficial technical advantages. Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments. By way of example only and not by way of limitation, one or more embodiments can provide one or more of the following features: · Ability to form relatively large backside contacts without shorting; Backside contacts can be formed without the need for difficult, deep reactive ion etching processes; Including a backside dielectric insulator layer to suppress sub-channel leakage and / or enhance the output performance of the field-effect transistor; Easier removal of the substrate from the backside; Currently, source / drain (S / D) epitaxy is easier to grow from shallow Si placeholders because S / D epitaxy not only grows from Si nanosheets but also from the top surface of the Si placeholder.

[0008] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention when read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0009] The following drawings are presented by way of example only and not limitation, and like reference numbers (where used) indicate corresponding elements throughout the several views.

[0010] [Figure 1A] 14D is a cross-sectional view of a semiconductor structure according to one embodiment of the present invention taken along line X in FIG. 14D. [Figure 1B] 14D is a cross-sectional view of a semiconductor structure taken along line Y1 of FIG. 14D according to an embodiment of the present invention. [Figure 1C] 14D is a cross-sectional view of a semiconductor structure taken along line Y2 of FIG. 14D according to an embodiment of the present invention.

[0011] [Figure 2A] 2D along line X of FIG. 2D, a cross-sectional view of a precursor for forming a semiconductor structure according to one embodiment of the present invention. [Figure 2B] 2D along line Y1 of FIG. 2D, a cross-sectional view of a precursor for forming a semiconductor structure according to one embodiment of the present invention. [Figure 2C] 2D along line Y2 of FIG. 2D, a cross-sectional view of a precursor for forming a semiconductor structure according to one embodiment of the present invention. [Figure 2D] FIG. 1 shows a top view of a semiconductor structure with the addition of a polycrystalline silicon dummy gate and patterned nanosheets.

[0012] [Figure 3A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 3B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 3C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 4A]2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 4B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 4C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 5A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 5B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 5C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 6A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 6B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 6C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 7A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 7B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 7C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 8A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 8B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 8C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 9A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 9B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 9C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 10A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 10B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 10C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 11A]2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 11B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 11C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D. [Figure 12A] 2D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 2D. [Figure 12B] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 2D. [Figure 12C] 2D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 2D.

[0013] [Figure 13A] 13D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 13D. [Figure 13B] 13D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 13D. [Figure 13C] 13D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 13D. [Figure 13D] 1 shows a top view of a semiconductor structure with an added gate cut.

[0014] [Figure 14A]14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 14B] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 14C] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D. [Figure 14D] 1 shows a top view of a semiconductor structure with the addition of MOL contacts. [Figure 15A] 14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 15B] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 15C] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D. [Figure 16A] 14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 16B] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 16C] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D. [Figure 17A] 14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 17B]14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 17C] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D. [Figure 18A] 14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 18B] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 18C] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D. [Figure 19A] 14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 19B] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 19C] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D. [Figure 20A] 14D, showing exemplary subsequent stages for forming a semiconductor structure according to one embodiment of the present invention, where view "A" is taken along line X of FIG. 14D. [Figure 20B] 14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "B" is taken along line Y1 of FIG. 14D. [Figure 20C]14D, showing an exemplary subsequent stage for forming a semiconductor structure according to one embodiment of the present invention, where view "C" is taken along line Y2 of FIG. 14D.

[0015] [Figure 21] 1 illustrates exemplary signal and power connections in accordance with an aspect of the present invention.

[0016] It should be understood that elements in the figures are shown for simplicity and clarity: common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown to enhance visibility of the illustrated embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] The principles of the invention are described herein in the context of exemplary embodiments. Moreover, in light of the teachings herein, it should be apparent to one skilled in the art that numerous modifications to the illustrated embodiments may be made that are within the scope of the claims. Thus, no limitations are intended or should be inferred with respect to the embodiments shown and described herein.

[0018] In modern semiconductor structures, self-aligned backside contacts are desirable to mitigate poor overlay margins at the backside of the wafer. However, self-aligned backside contacts require challenging processing modules such as placeholder formation, backside Si removal selective to the placeholder, and the like. One or more embodiments are advantageous for self-aligned direct backside contact (DBC) implementations of BSPDNs.

[0019] 20A, 20B, and 20C are cross-sectional views of a semiconductor structure according to one embodiment of the present invention, taken along lines X, Y1, and Y2, respectively, of FIG. 14D. Line "X" indicates a view across the gate, line "Y1" indicates a view along the gate, and line "Y2" indicates a view across the source / drain (S / D) regions. Beneath the gate 243 is a bottom dielectric isolation (BDI) 229. Beneath the epitaxially grown source / drain (S / D) regions 239 is an epitaxially grown Si layer 237 (also commonly referred to as a sacrificial placeholder, Si epitaxy / epi, and first and second bottom silicon regions). The bottom surface of the epitaxially grown Si layer 237 is lower than the bottom surface of the BDI 229. The backside contact 265 has an asymmetric shape, with a bottom 265A (also referred to herein as a "thin protruding trench region") that "digs into" the overlying epitaxially grown Si layer 237 and S / D epitaxy 239 (also referred to herein as "epitaxially grown source / drain (S / D) regions"). In one or more cases, the top of the STI 223 under the gate 243 is above the bottom surface of the BDI 229 (see FIG. 1B). In some cases, the top of the STI 223 under the S / D epitaxy 239 is below the bottom surface of the BDI 229 (compare FIG. 1C with FIG. 1B). In some embodiments, some backside interlayer dielectric (ILD) 255 remains between the backside contact 265 and the BDI 229 (see FIG. 1A).

[0020] An exemplary process flow of the invention will now be described. In one or more embodiments, a method of forming a semiconductor structure includes forming nanosheet stacks 207, 209, 211, 213, 215, 217 (also referred to herein as "nanosheets") on epitaxially grown layers of high Ge concentration SiGe 205 and low Ge concentration SiGe 203 (also referred to herein as SiGe 55 layer and low Ge concentration SiGe layer / SiGe 30, respectively) (see, e.g., FIG. 2A); removing the high Ge concentration SiGe layer (see, e.g., FIG. 2B); 6A), forming BDI 229 (see, e.g., FIG. 7A); forming sacrificial placeholders 237 in the low-Ge SiGe layer 203 below the S / D regions (see, e.g., FIG. 9A); forming middle-of-line (MOL) structures and back-of-line (BEOL) structures and bonding a carrier wafer 251 (see, e.g., FIG. 14A); and flipping the wafer to remove the substrate 201 and stop on the low-Ge SiGe layer 203 (see, e.g., FIG. 15A). The method further includes removing the low Ge concentration SiGe layer 203 selectively to the BDI 229 and the sacrificial placeholder 237 (see, e.g., Figure 16A); forming a backside ILD 255 (see, e.g., Figure 17A); forming a backside contact opening (also referred to herein as a "trench") 257 to reveal the sacrificial placeholder 237 (see, e.g., Figures 18A and 18C); removing the sacrificial placeholder (see, e.g., Figures 19A and 19C); and forming a backside contact 265 (see, e.g., Figures 20A and 20C).

[0021] Referring now to Figures 2A-2D, note the starting structure, which includes a silicon wafer / substrate 201. Outer of the silicon wafer 201 is a SiGe30 (30% Ge) layer 203. Outer of the SiGe30 layer 203 is a SiGe55 layer 205. Outer of the SiGe55 (55% Ge) layer 205 are alternating layers of SiGe30 207, 211, 215, and Si 209, 213, 217. Figures 2A, 2B, and 2C are views taken along lines X, Y1, and Y2, respectively, in Figure 2D. Figure 2D, in top view, shows a polysilicon dummy gate 219 (see Figures 4A and 4B) and patterned nanosheets 225 (see Figures 3B and 3C). It should be noted that with respect to layer 203, known selective etching processes (e.g., wet etching processes) can be used to remove Si thicknesses greater than 2 μm (i.e., thickness variations or differentials) with less than 5 nm of SiGe 30 reduction. The Ge concentrations in all SiGe layers are exemplary. Generally, layer 205 can include SiGe with a Ge concentration ranging from 40 to 75%, and layers 203, 207, 211, and 215 can include SiGe with a Ge concentration ranging from 15 to 35%. Those skilled in the art will be familiar with fabricating nanosheet transistors, including preferential / selective etching of SiGe with different Ge concentrations, and, in light of the teachings herein, can form precursor structures such as those shown in FIGS. 2A-2C. Generally, layers 203, 207, 211, and 215 have a sufficiently lower Ge concentration than layer 205 to allow for preferential / selective etching.

[0022] FIGS. 3A, 3B, and 3C are views taken along lines X, Y1, and Y2, respectively, of FIG. 2D, showing the structure of FIGS. 2A-2C after patterning the nanosheets (NS) and forming shallow trench isolations (STIs). Note the patterned nanosheets 225 and STIs 223. Those skilled in the art will be familiar with the use of lithography and etching and, given the teachings herein, will be able to perform the desired patterning. Suitable materials for STIs 223 include, for example, silicon oxide (SiO x ) are listed.

[0023] 4A, 4B, and 4C are views taken along lines X, Y1, and Y2, respectively, of FIG. 2D, showing the structure of FIGS. 3A-3C after forming the dummy gate. Note the dummy gate 219 and hard mask 227. For example, deposit amorphous Si (a-Si) material for the dummy gate 219 and perform planarization; deposit hard mask material 227 (which can be a multilayer dielectric) for the gate; pattern the hard mask 227 and etch the a-Si to form the dummy gate 219.

[0024] 5A, 5B, and 5C are views taken along lines X, Y1, and Y2, respectively, of FIG. 2D, and show the structure of FIGS. 4A-4C after an oxide etch (e.g., using reactive ion etching (RIE)) to reduce the height of the exposed STI (as seen in FIG. 5C).

[0025] Figures 6A, 6B, and 6C are views taken along lines X, Y1, and Y2, respectively, in Figure 2D, showing the structure of Figures 5A-5C after selective removal of the SiGe 55 205. For example, selective removal of the SiGe 55 205 is performed selectively to the SiGe 30 203, 207, 211, and 215; the Si 201, 209, 213, and 217; the dummy gate 219; and the hard mask 227. This can be achieved, for example, using a vapor-phase HCl process. At this stage, no gate is present yet; the structure is not floating; i.e., all of the nanosheets 207, 209, 211, 213, 215, and 217 are stable due to their attachment to the polysilicon dummy gate 219 located above the STI 223.

[0026] Figures 7A, 7B, and 7C are views taken along lines X, Y1, and Y2, respectively, of Figure 2D and show the structure of Figures 6A-6C after spacer / BDI formation, nanosheet (NS) recessing, SiGe indentation, and formation of inner spacer 231. Specifically, the area vacated by the selective removal of SiGe 55 205 has been filled with BDI 229; nanosheets 207, 209, 211, 213, 215, and 217 have been recessed; SiGe 30 layers 207, 211, and 215 have been indented; and inner spacer liner 231 has been applied to the indented areas of SiGe 30 layers 207, 211, and 215, forming gate spacer 233. Note trench 235. Note the "hat" shape of the BDI 229 atop the SiGe 30 layer 203, as seen in FIG. 7C. Non-limiting examples of suitable materials for elements 229, 231, and 233 include SiBCN, SiN, SiBCN, SiOCN, SiOC, SiON, and the like. Those skilled in the art are familiar with the fabrication of nanosheet transistors and, given the teachings herein, can process the structure shown in FIG. 6 to obtain the structure shown in FIG. 7 using known techniques. See, for example, commonly assigned U.S. Patent No. 10,903,315 to Nicolas Loubet et al., entitled "FORMATION OF DIELECTRIC LAYER AS ETCH-STOP FOR SOURCE AND DRAIN EPITAXY DISCONNECTION."

[0027] 8A, 8B, and 8C are views taken along lines X, Y1, and Y2, respectively, of FIG. 2D and show the structure of FIGS. 7A-7C after etching through trench 235 of FIGS. 7A-7C to form deeper trench 235A by opening BDI 229 and recessing SiGe 30 203. For example, RIE using a chemistry appropriate to etch BDI selectively to elements 231, 233, followed by a selective wet etch, is used to etch SiGe 30.

[0028] Figures 9A, 9B, and 9C are views taken along lines X, Y1, and Y2, respectively, of Figure 2D, and show the structure of Figures 8A-8C after epitaxial growth (with or without doping) of Si 237 from bottom to top. Those skilled in the art will be familiar with techniques for epitaxially growing silicon on SiGe 30 and with doping silicon.

[0029] Figures 10A, 10B, and 10C are views taken along lines X, Y1, and Y2, respectively, of Figure 2D and show the structure of Figures 9A-9C after epitaxial growth of source-drain regions 239. Those skilled in the art will be familiar with techniques for epitaxially growing source / drain regions on epitaxially grown Si, and will also be familiar with techniques for doping silicon.

[0030] 11A, 11B, and 11C are views taken along lines X, Y1, and Y2, respectively, of FIG. 2D and show the structure of FIGS. 10A-10C after depositing an interlayer dielectric (ILD) 241 and performing chemical mechanical polishing (CMP) or other suitable planarization. A non-limiting example of a suitable material for the ILD is silicon oxide.

[0031] 12A, 12B, and 12C are views taken along lines X, Y1, and Y2, respectively, of FIG. 2D, showing the structure of FIGS. 11A-11C after removing the dummy gate and stripping away the SiGe 30 layers 207, 211, and 215. Those skilled in the art will be familiar with the removal of the dummy (e.g., a-Si) gate and sacrificial SiGe layers 207, 211, and 215. The Si nanosheets 209, 213, and 217 are not "floating" but are supported by the inner spacer liner 231, gate spacer 233, and S / D 239, as seen in FIG. 12A.

[0032] 13A, 13B, and 13C are views taken along lines X, Y1, and Y2, respectively, of FIG. 13D, showing the structure of FIGS. 12A-12C after forming a high-k metal gate stack (HKMG) 243 and forming a gate cut 245. FIG. 13D is similar to FIG. 2D with the addition of the gate cut 245. Those skilled in the art will be familiar with the "dummy gate" process for forming the HKMG 243. The gate cut 245 can be formed by lithography, etching, and implantation. Suitable materials for the gate cut 245 include SiN, SiO, SiBCN, SiOCN, SiOC, SiC, or a combination thereof.

[0033] FIGS. 14A, 14B, and 14C are views taken along lines X, Y1, and Y2, respectively, of FIG. 14D, illustrating the structure of FIGS. 13A-13C after forming mid-level (MOL) contacts 247 and 248; forming back-end (BEOL) layers 249; and bonding a carrier wafer 251. FIG. 14D is similar to FIG. 13D with the addition of MOL contacts 247 and 248. Those skilled in the art will be familiar with forming BEOL layers, including metal wiring layers, vias, and dielectric materials. Those skilled in the art will be familiar with forming MOL contacts using lithography, etching, and filling; metals such as copper or the like are suitable. Those skilled in the art will be familiar with tools and techniques for bonding a carrier wafer 251 (e.g., silicon, glass) to BEOL layers 249, such as oxide-to-oxide bonding.

[0034] 15A, 15B, and 15C are views taken along lines X, Y1, and Y2, respectively, of FIG. 14D, showing the structure of FIGS. 14A-14C after flipping the wafer and removing the Si substrate 201, stopping the latter operation above the STI 223 and SiGe 30 203. For ease of illustration, the structures of FIGS. 15A-15C are shown in the same orientation as FIGS. 14A-14C, but flipped 180 degrees, as indicated by arrow 253; that is, in a typical process, the structures of FIGS. 14A-14C have the carrier wafer 251 above the Si substrate 201 relative to Earth's gravity, whereas the structures of FIGS. 15A-15C have the carrier wafer 251 below the other elements relative to Earth's gravity, even though the wafer 251 is shown at the top of the figures. Those skilled in the art are familiar with the tools and techniques for "flipping" the wafer and removing all of the silicon material of the substrate 201. Advantageously, at this stage, all source / drain regions or gates are well protected by SiGe, which is a good etch stop layer for the Si removal (this avoids any damage to the S / D epitaxy or gates during the Si removal).

[0035] Figures 16A, 16B, and 16C are views taken along lines X, Y1, and Y2, respectively, of Figure 14D and show the structure of Figures 15A-15C after selective removal of SiGe 30 203 relative to STI 223, BDI 229, and Si epitaxy 237. Selective removal of SiGe 30 relative to Si can be achieved using known techniques.

[0036] Figures 17A, 17B, and 17C are views taken along lines X, Y1, and Y2, respectively, of Figure 14D and show the structure of Figures 16A-16C after depositing a backside ILD (BILD) 255 and planarizing it, such as with CMP. A non-limiting example of a suitable material for BILD is silicon oxide.

[0037] 18A, 18B, and 18C are views taken along lines X, Y1, and Y2, respectively, of FIG. 14D, illustrating the structure of FIGS. 17A-17C after patterning the backside contact, with trenches 257 formed in the BILD 255 and STI 223. This can be done, for example, using appropriate lithography and etching (such as reactive ion etching (RIE)). Advantageously, the minimum dimension (e.g., diameter) of the backside contact formed in trench 257 can be large (e.g., larger than the bottom dimension of the Si epitaxy 237; as a non-limiting example, the size of the backside contact can be approximately half the gate pitch). In one or more embodiments, the backside contact formed in trench 257 does not short with the adjacent Si epitaxy 237, so long as the overlay accuracy is less than 15 nm. Further in this regard, lithographic overlay is the ability of a lithography apparatus to accurately transfer precise features to their intended locations in the respective layers. In one or more embodiments, this should be acceptable as long as trench 257 does not open into adjacent Si epi, and therefore does not create shorts between adjacent FETs. Additionally, in one or more embodiments, the RIE for the back contact does not need to be deep enough to reach BDI 229, as BDI is not a sufficient etch stop for the contact.

[0038] 19A, 19B, and 19C are views taken along lines X, Y1, and Y2, respectively, of FIG. 14D, showing the structure of FIGS. 18A-18C after optionally recessing the Si epi 237 adjacent to trench 257 (e.g., if the Si epi is not heavily doped) to form additional recesses 261 and 263 within trench 257. Suitable processing includes, for example, wet etching of Si. This recessing process can enlarge the silicide area (i.e., the area of ​​trench 257 that is covered with silicide prior to contact formation). Note that without this optional recessing step, no "gouge" is formed. However, even without the "gouge," the back contact's critical dimension (CD) is advantageously enlarged and the back contact does not contact the BDI.

[0039] 20A, 20B, and 20C are views taken along lines X, Y1, and Y2, respectively, of FIG. 14D and show the structure of FIGS. 19A-19C after backside contact metallization to form backside contact 265. In one or more embodiments, contact 265 includes a silicide liner, such as Ti, Nit, NiPt, or the like; a thin metal adhesion liner, such as TiN; and a low-resistivity metal fill material, such as W, Co, Ru, or the like.

[0040] 1A, 1B, and 1C are views taken along lines X, Y1, and Y2, respectively, of FIG. 14D, illustrating the structure of FIGS. 20A-20C after forming BSPDN layer 267. In one or more embodiments, BSPDN layer 267 includes more than one layer of metal lines and vias therebetween. The metal lines and vias are filled with a metal such as Co, Cu, Al, or the like, along with an adhesion liner such as TaN or TiN. One skilled in the art would be familiar with forming BSPDN layers, including metal wiring layers, vias, and dielectric materials.

[0041] In non-limiting examples, the conductive / metal feature can include a silicide liner such as Ni, Ti, NiPt, etc.; a thin metal adhesion layer such as TiN or TaN; and a conductive metal fill material such as Ru, W, Co, or Cu. Suitable materials for the STI liner herein include, for example, SiCO, SiOCN, and silicon nitride (SiN). Suitable materials for the STI herein include, for example, silicon oxide (SiOx); the STI can be deposited, for example, by high-density plasma (HDP) deposition, chemical vapor deposition (CVD), etc.

[0042] For example, referring to Figure 1A, a field effect transistor (FET) includes a first source-drain region (239 at the left end), a second source-drain region (239 at the right end), one or more channel regions (e.g., Si nanosheets 209, 213, 217), and a gate 243 surrounding the channel region. The FET can be a nanosheet FET and can be n-type (with n-type S / D regions) or p-type (with p-type S / D regions). Arrays of FETs can be provided; for example, with both n-type and p-type (complementary metal-oxide semiconductor, or CMOS).

[0043] For clarity, it should be noted that each source / drain region 239 shown in FIG. 1C corresponds to a separate device extending vertically (into or out of the page). Accordingly, aspects of the present invention include a semiconductor array structure including a plurality of field-effect transistors; for example, arranged in rows. In a non-limiting example, a CMOS array is provided having n-type and p-type FETs adjacent to one another, as just described. Inverters or other types of CMOS logic gates can be formed. Those skilled in the art will be familiar with CMOS inverters and other CMOS logic gates. In such inverters, the p-type FET has its source connected to the power supply rail VDD and its drain connected to the drain of the n-type FET. The source of the n-type FET is connected to ground / VSS. The gates of the n-type FET and the p-type FET are tied together to form an input for receiving a signal. The tied drains of the n-type FET and the p-type FET form an output node. One or more embodiments further include a signal source coupled to the front wiring network and a power supply coupled to the backside power distribution network. As a non-limiting specific example, referring to FIG. 21 , in one or more embodiments, the array structure further includes a first signal source (e.g., clock signal 2406); a logic signal source 2408; and a power supply (e.g., power supply 2402 (VDD) and ground terminal 2404 (VSS)). According to any of the disclosed embodiments, element 2400 generally represents an individual device or an array of devices. Power connections are generally provided to the source / drain terminals via appropriate contact structures, and signal connections are generally provided to the gates via appropriate contact structures. Power may be provided, for example, from BSPDN layer 267. Signals may be provided, for example, from surface wiring network 249, which may also include power wiring. VDD refers, for example, to power pins connected to p-type FETs, and VSS refers, for example, to power pins connected to n-type FETs.

[0044] In one or more embodiments, the metal features on the front surface are tapered with an increasing cross section toward the front surface, and the metal features on the back surface are tapered with an increasing cross section toward the back surface.

[0045] As mentioned above, in one or more embodiments, the presence of the Si epi layer 237 allows for a larger CD of the back contact, and as long as the overlay accuracy is less than 15 nm, the back contact will not short to adjacent Si epi. Furthermore, the RIE process for forming the back contact does not need to be deep enough to reach the BDI 229, as the BDI does not provide a sufficient etch stop for the contact. Advantageously, the BDI 229 is provided to improve semiconductor operation by suppressing subchannel leakage and increasing output performance. Furthermore, the presence of the SiGe layer 203 below the NS and SiGe55 layers allows for a more controlled removal process of the backside Si substrate, reducing the likelihood of damaging the source / drain and gate even if there is a pinhole in the BDI. In fact, the SiGe layer 203 below the BDI 229 acts as a buffer layer during Si substrate removal, preventing potential damage to the source / drain and gate even if there is a pinhole in the BDI. Advantageously, the recessed backside contact geometry allows for an expanded silicide area.

[0046] 1A-1C , it should be understood that, in one embodiment, an exemplary semiconductor structure includes a first source-drain region (239 on the left), a second source-drain region (239 on the right), and at least one channel region 209, 213, 217 connecting the first and second source-drain regions. Also included is a gate 243 adjacent to the at least one channel region, a bottom dielectric isolation region 229 inside the gate, and first and second bottom silicon regions 237 located inside the first and second source-drain regions, respectively. The structure further includes a backside contact 265 that protrudes through the second bottom silicon region to the second source-drain region.

[0047] In one or more embodiments, the back contact 265 has an asymmetric shape when viewed in cross section (FIGS. 1A and 1C).

[0048] In one or more embodiments, the semiconductor structure further includes a backside power distribution network 267 inside the backside contact, which is connected to the backside power distribution network.

[0049] In at least some cases, the semiconductor structure further includes a surface wiring network 249 (which may be formed, for example, using BEOL processing, and therefore has the same reference number as the BEOL layer) at the surface of the semiconductor structure, and contacts 247 interconnecting the surface wiring network and the first source-drain regions.

[0050] In one or more embodiments, the bottom surface of the Si epi layer 237 is lower than the BDI 229. In other words, the innermost surface of each of the first and second bottom silicon regions extends further inward than the innermost surface of the bottom dielectric isolation region.

[0051] Note that in this context, "inside" means towards the bottom of the figure, and "outside" means towards the top of the figure.

[0052] In one or more embodiments, a shallow trench isolation region 223 is further included inside the gate and the first and second source-drain regions. In at least some cases, the height of the STI below the gate 243 is above the bottom surface of the BDI 229. In other words, the outermost surface of the shallow trench isolation region 223 inside the gate 243 extends further outward than the innermost surface of the bottom dielectric isolation region.

[0053] In at least some cases, the STI height below the S / D epi is below the bottom surface of the BDI. In other words, the outermost surface of the shallow trench isolation region 223 inside the first and second source-drain regions 239 is further inside than the innermost surface of the bottom dielectric isolation region 229.

[0054] In one or more embodiments, a portion of the backside ILD 255 remains between the backside contact and the BDI. In one or more embodiments, a region of backside interlayer dielectric 255 is further included inside the bottom dielectric isolation region 229. In one or more embodiments, the backside contact has an innermost wide region and a narrow protruding trench region 265A that protrudes through the second bottom silicon region into the second source-drain region. A portion of the backside interlayer dielectric region 255 is located between the outermost surface of the innermost wide region and the innermost surface of the bottom dielectric isolation region, as best seen in FIG. 1A. As seen in FIGS. 1A and 1C, this trench region is offset from the centerline of the innermost wide region when viewed in cross section.

[0055] In some cases, the first and second bottom silicon regions 237 extend inwardly into a backside inter-layer dielectric region 255 .

[0056] The gate 243 can be, for example, a high-dielectric constant metal gate in a gate-all-around (GAA) structure that surrounds at least one channel region formed by the nanosheets 209, 213, 217 (the channel region acts as a conductive channel when a voltage is applied to the gate).

[0057] In one or more embodiments, the back contact 265 does not contact the bottom dielectric isolation region 229 .

[0058] In one or more embodiments, the maximum diameter of the backside contact 265 is greater than the maximum diameter of the second bottom silicon region 237 .

[0059] In another aspect, an exemplary semiconductor array structure includes a plurality of field effect transistors, each including, as just described, a first source-drain region, a second source-drain region, at least one channel region connecting the first and second source-drain regions, a gate adjacent to the at least one channel, a bottom dielectric isolation region inside the gate, and first and second bottom silicon regions located inside the first and second source-drain regions, respectively. The plurality of field effect transistors are arranged, for example, in rows, and the array further includes a backside power distribution network 267; a surface wiring network 249; a plurality of contacts 247 interconnecting the surface wiring network and the plurality of first source-drain regions; and a plurality of backside contacts 265 each protruding through a corresponding one of the second bottom silicon regions 237 into a corresponding one of the second source-drain regions 239 and each connected to the backside power distribution network 267. In one or more embodiments, a signal source coupled to the surface wiring network and a power source coupled to the backside power distribution network are further included. Please refer to Figure 21.

[0060] In one or more embodiments, each back contact has an asymmetric shape when viewed in cross section.

[0061] In one or more embodiments, the plurality of backside contacts 265 do not contact the bottom dielectric isolation region 229 and / or the maximum diameter of each of the plurality of backside contacts 265 is greater than the maximum diameter of the second bottom silicon region 237.

[0062] In one or more embodiments, the maximum diameter of the back contacts is approximately half the distance between adjacent gates of the gates (as discussed above, the size of the back contacts can be approximately half the gate pitch).

[0063] In another embodiment, an exemplary method for forming a semiconductor structure includes providing a precursor structure including nanosheet stacks 207, 209, 211, 213, 215, and 217 outside a high-Ge SiGe epitaxial growth layer 205 and a low-Ge SiGe epitaxial growth layer 203 on an underlying substrate 201 (see, e.g., FIG. 2A). Further steps include removing the high-Ge SiGe layer (see, e.g., FIG. 6A) and forming a bottom dielectric isolation (BDI) 229 in the area vacated by the high-Ge SiGe layer (see, e.g., FIG. 7A). Further steps include forming two sacrificial placeholders 237 at least partially in the low-Ge SiGe epitaxial growth layer 203 and forming source-drain regions 239 outside the two sacrificial placeholders 237 (see, e.g., FIGS. 9A and 10A).

[0064] More advanced steps include forming middle-of-line (MOL) structures (e.g., 247) and back-end-of-line (BEOL) structures 249 outside the preceding structures, and bonding a carrier wafer 251 to the outside of the BEOL structures (see, e.g., FIG. 14A). Referring to FIGS. 15A-15C, the carrier wafer is flipped to remove the substrate 201, terminating in the Ge-low SiGe layer 203. The Ge-low SiGe layer 203 is removed selectively to the BDI 229 and sacrificial placeholder 237 (see, e.g., FIG. 16A). A backside interlayer dielectric (ILD) 255 is formed inside the BDI 229 (see, e.g., FIG. 17A).

[0065] Further steps include forming a backside contact opening 257 in at least the backside ILD to reveal one of the sacrificial placeholders 237 (see, e.g., Figures 18A and 18C). Optionally, removing at least a portion of the revealed one of the sacrificial placeholders (see, e.g., Figures 19A and 19C). Forming a backside contact 265 in the backside contact opening (see, e.g., Figures 20A and 20C).

[0066] In one or more embodiments, during the steps of forming the back contact opening and removing at least a portion of the exposed one of the sacrificial placeholders, a centerline of at least a portion of the exposed one of the sacrificial placeholders is offset from a centerline of the back contact opening. See Figures 1A and 1C.

[0067] In one or more embodiments, the method further includes forming a gate 243 between the source-drain regions to surround the channel portion of the nanosheet stack. See Figures 13A-13C.

[0068] The fabrication of semiconductor devices involves various stages of a device patterning process. For example, the fabrication of semiconductor chips may begin with multiple device patterns, e.g., generated by computer-aided design (CAD), followed by replicating these device patterns within a substrate. The replication process may involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures. For example, in a photolithography process, a layer of photoresist material may first be coated onto a substrate and then selectively exposed according to a predetermined device pattern or patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beam, X-rays, etc.) may undergo some changes in solubility in certain solutions. The photoresist may then be developed in a developer to remove unirradiated (in the case of a negative resist) or irradiated (in the case of a positive resist) portions of the resist layer, forming a photoresist pattern or photomask. The photoresist pattern or photomask may then be copied or transferred to the substrate underlying the photoresist pattern.

[0069] At various stages in forming semiconductor structures, there are numerous techniques employed by those skilled in the art to remove material. As used herein, these processes are collectively referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, all of which are known techniques for removing selective materials when forming semiconductor structures. Standard Clean 1 (SC1) includes a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 includes a strong acid, such as hydrochloric acid, and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore, a more detailed description of such processes will not be presented herein.

[0070] While the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to carry out the method can utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication equipment. These techniques and equipment should already be familiar to those skilled in the relevant art in light of the teachings herein. For example, those skilled in the art should be familiar with epitaxial growth, the formation of self-aligned contacts, the formation of high-k metal gates, etc. The term "high-k" has a clear meaning to those skilled in the art in the context of high-k metal gate (HKMG) stacks and is not merely a relative term. Furthermore, one or more of the processing steps and equipment used to fabricate semiconductor devices are described in numerous readily available published documents. These include, for example, "Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition" by James D. Plummer et al. (Prentice Hall, 2001) and "Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices" by P.H. Holloway et al. (Cambridge University Press, 2008), both of which are incorporated herein by reference. While several individual process steps are described herein, it is emphasized that these steps are merely exemplary, and that one of ordinary skill in the art may be familiar with several equally suitable alternatives that may be applicable.

[0071] It should be understood that the various layers and / or regions illustrated in the accompanying figures may not be drawn to scale. However, in Figures 1A, 1B, and 1C, for example, the relative heights / thicknesses of the various layers are representative throughout these figures. Additionally, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of illustration. This is not to suggest that the semiconductor layers not explicitly shown are omitted in an actual integrated circuit device.

[0072] Those skilled in the art will appreciate that the exemplary structures described above may be provided in raw form, such as bare die (i.e., a single wafer having multiple unpackaged chips), in packaged form, or incorporated as part of an intermediate or final product.

[0073] Integrated circuits consistent with aspects of the present invention can be utilized in essentially any application and / or electronic system. Given the teachings of the disclosure provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the embodiments disclosed herein.

[0074] The illustrations of the embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to serve as a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art in light of the teachings herein; other embodiments may be utilized and derived therefrom, thereby allowing structural and logical substitutions and changes to be made without departing from the scope of the present disclosure. It should also be noted that in some alternative implementations, some of the steps of the exemplary method may occur out of the order shown in the figures. For example, two steps shown in succession may, in fact, be performed substantially simultaneously, or certain steps may, in some cases, be performed in the reverse order, depending on the functionality involved. The drawings are also merely representational and not drawn to scale. Accordingly, the specification and drawings are to be interpreted in an illustrative and not a restrictive sense.

[0075] Although multiple embodiments may be individually and / or collectively referred to herein as "embodiments," this is done merely for convenience and is not intended to limit the scope of the present application to any one embodiment or inventive concept, even if more than one embodiment is actually shown. Thus, while specific embodiments are shown and described herein, it should be understood that configurations which achieve the same purpose may be substituted for the specific embodiment shown; that is, the present disclosure is intended to apply to any adaptations or variations of the various embodiments. Combinations of the above embodiments, as well as other embodiments not specifically described herein, should be apparent to those skilled in the art in light of the teachings herein.

[0076] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as "bottom," "top," "above," "over," "under," and "below" are used to indicate the relative position, rather than the relative height, of elements or structures relative to one another. When a layer of a structure is described herein as being "over" another layer, it is understood that there may or may not be intermediate elements or layers between the two specified layers. When a layer is described as being "directly on" another layer, it indicates that the two layers are in direct contact. When "about" is used in this specification and the appended claims, it means within plus or minus 10 percent.

[0077] Structure, material, acts, and equivalents corresponding to any means-plus-function or step-plus-function elements in the following claims are intended to include any structure, material, or acts for performing that function in combination with other specifically claimed claim elements. While the description of various embodiments has been presented for purposes of illustration and description, it is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments. These embodiments were chosen and described to best explain the principles and practical applications and to enable others skilled in the art to understand the various embodiments, along with various modifications suitable for particular uses contemplated.

[0078] The Abstract is provided to comply with 37 CFR Section 1.76(b), requiring a summary that will allow the reader to quickly grasp the content of the technical disclosure. The Abstract has been submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above Detailed Description, various features may be grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, claimed subject matter may not include all features of a single embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

[0079] In light of the teachings provided herein, those skilled in the art will be able to conceive other implementations and applications of these techniques and the disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the exemplary embodiments are not limited to those precise embodiments, and that various other changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. a first source-drain region; a second source-drain region; at least one channel region connecting the first source-drain region and the second source-drain region; a gate adjacent to the at least one channel region; a bottom dielectric isolation region inside said gate; a first bottom silicon region and a second bottom silicon region located inside the first source-drain region and the second source-drain region, respectively; and a backside contact extending through the second bottom silicon region to the second source-drain region; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1 wherein said back contact has an asymmetric shape when viewed in cross section.

3. 3. The semiconductor structure of claim 2 further comprising a backside power distribution network inside said backside contact, said backside contact being connected to said backside power distribution network.

4. a surface wiring network on the surface of the semiconductor structure; and contacts interconnecting the surface wiring network and the first source-drain regions; 4. The semiconductor structure of claim 3 further comprising:

5. 5. The semiconductor structure of claim 4 wherein an innermost surface of each of said first bottom silicon region and said second bottom silicon region extends further inward than an innermost surface of said bottom dielectric isolation region.

6. 6. The semiconductor structure of claim 5 further comprising a shallow trench isolation region interior to said gate and said first and second source-drain regions, an outermost surface of said shallow trench isolation region interior to said gate extending further outward than said innermost surface of said bottom dielectric isolation region.

7. 6. The semiconductor structure of claim 5 further comprising a shallow trench isolation region inside said gate and said first and second source-drain regions, wherein an outermost surface of said shallow trench isolation region inside said first and second source-drain regions is further inboard than said innermost surface of said bottom dielectric isolation region.

8. 6. The semiconductor structure of claim 5, further comprising a backside interlayer dielectric region inside said bottom dielectric isolation region, said backside contact having an innermost wide region and a narrow protruding trench region that protrudes through said second bottom silicon region into said second source-drain region, a portion of said backside interlayer dielectric region being located between an outermost surface of said innermost wide region and said innermost surface of said bottom dielectric isolation region, and said narrow protruding trench region being offset from a centerline of said innermost wide region when viewed in cross section.

9. 9. The semiconductor structure of claim 8 wherein said first bottom silicon region and said second bottom silicon region extend inwardly into said backside interlayer dielectric region.

10. 6. The semiconductor structure of claim 5 wherein said gate comprises a high dielectric constant metal gate in a gate-all-around (GAA) configuration surrounding said at least one channel region.

11. 10. The semiconductor structure of claim 1 wherein said backside contact does not contact said bottom dielectric isolation region.

12. 10. The semiconductor structure of claim 1 wherein said backside contact has a maximum diameter greater than a maximum diameter of said second bottom silicon region.

13. a plurality of field effect transistors each having a first source-drain region, a second source-drain region, at least one channel region connecting the first source-drain region and the second source-drain region, a gate adjacent to the at least one channel region, a bottom dielectric isolation region inside the gate, and first and second bottom silicon regions located inside the first and second source-drain regions, respectively; Rear power supply network; Surface wiring network; a plurality of contacts interconnecting the surface wiring network and a plurality of the first source-drain regions; and a plurality of backside contacts each projecting through a corresponding one of the second bottom silicon regions into a corresponding one of the second source-drain regions and each connected to the backside power distribution network; A semiconductor array structure comprising:

14. 14. The semiconductor array structure of claim 13, wherein each back contact has an asymmetric shape when viewed in cross section.

15. the plurality of backside contacts do not contact the bottom dielectric isolation region; and 14. The semiconductor array structure of claim 13, wherein a maximum diameter of each of said plurality of backside contacts is greater than a maximum diameter of said second bottom silicon region.

16. 14. The semiconductor array structure of claim 13, wherein a maximum diameter of said plurality of backside contacts is half the distance between adjacent ones of said plurality of gates.

17. a signal source coupled to the surface wiring network; and a power supply coupled to the backside power supply network; 14. The semiconductor array structure of claim 13 further comprising:

18. 1. A method of forming a semiconductor structure, comprising: providing a precursor structure having a nanosheet stack outside a high Ge concentration SiGe epitaxial growth layer and a low Ge concentration SiGe epitaxial growth layer on a base substrate; removing the Ge-rich SiGe epitaxial growth layer and forming a bottom dielectric isolation (BDI) in the area vacated by the Ge-rich SiGe epitaxial growth layer; forming two sacrificial placeholders at least partially in the Ge-low SiGe epitaxial growth layer, and forming source-drain regions outside the two sacrificial placeholders; forming a middle-of-line (MOL) structure and a back-end-of-line (BEOL) structure outside the preceding structure, and bonding a carrier wafer to the outside of the back-end-of-line (BEOL) structure; flipping the carrier wafer to remove the substrate and stopping on the Ge-low SiGe epitaxial growth layer; removing the Ge-low SiGe epitaxial growth layer selectively with respect to the BDI and the sacrificial placeholder; forming a backside interlayer dielectric (ILD) inside the BDI; forming a backside contact opening in at least the backside ILD to expose one of the two sacrificial placeholders; and forming a back contact in the back contact opening. A method for providing

19. 20. The method of claim 18, further comprising removing at least a portion of the revealed one of the two sacrificial placeholders, wherein during the forming the back contact opening and the removing the at least a portion of the revealed one of the two sacrificial placeholders, a centerline of the at least a portion of the revealed one of the two sacrificial placeholders is offset from a centerline of the back contact opening.

20. The method of claim 19, further comprising forming a gate between the source-drain regions surrounding a channel portion of the nanosheet stack.

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