Vertical transport field effect transistor with high performance output.

Abstract

A vertical transport field effect transistor (VTFET) is on the wafer. The VTFET has a first width. The first width is a contact poly pitch (CPP). A lower source / drain region of the VTFET extends from the VTFET by at least the first width. A contact from a front side of the VTFET is connected to the lower source / drain region.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to vertical-transport field-effect transistors (VTFETs) with high performance output. [Background technology]

[0002] Semiconductor devices are fabricated by sequentially depositing insulating (dielectric), conductive, and semiconducting layers of material onto a semiconductor substrate and using lithography to pattern the various layers to form circuit components and elements thereon. Generally, these semiconductor devices include multiple circuits that form an integrated circuit (IC) fabricated on the semiconductor substrate.

[0003] VTFET devices allow vertical current flow from the lower source / drain region to the upper source / drain region. In a VTFET device, the lower source / drain region is located closest to the wafer, with a gate region above the lower source / drain region and an upper source / drain region above the gate region. The lower source / drain region is located closest to the wafer on which the circuit is formed, and the upper source / drain region is located furthest from the wafer on which the circuit is formed. When an even number of VTFETs are placed in series, i.e., the source / drain region of the first VTFET is directly connected to the source / drain region of the second VTFET, the lower source / drain region of the last VTFET in the series has an output at the bottom of the circuit, i.e., closest to the wafer. The challenge here is that the output must be directed to the front of the circuit so that it can be routed to other circuitry via conventional interconnect wiring in metal layers above the device layer where the series VTFETs are located. Summary of the Invention

[0004] In a first embodiment, a vertical transport field effect transistor (VTFET) is on the wafer. In the first embodiment, the VTFET has a first width, the first width being a contact poly pitch (CPP). In the first embodiment, a lower source / drain region of the VTFET extends from the VTFET by at least the first width. In the first embodiment, a contact from a front side of the VTFET is connected to the lower source / drain region.

[0005] In a first embodiment, the contact is connected to the lower source / drain region at a front surface of the lower source / drain region. In a first embodiment, the contact is connected to the lower source / drain region at a back surface of the lower source / drain region. In a first embodiment, the contact is greater than the first width. In a first embodiment, the contact from the front surface of the VTFET, connected to the lower source / drain region, is an output connection.

[0006] Embodiments of the present invention provide for larger contacts to the backside of the lower source / drain regions of the VTFET device. Embodiments of the present invention provide for reduced resistance for high performance devices using backside power supplies. Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or provided to the source / drain / gate regions of the VTFET through a backside power delivery network.

[0007] In a second embodiment, there is a first plurality of vertical transport field effect transistors (VTFETs) on a wafer. In the second embodiment, a portion of the first plurality of VTFETs has a first width. In the second embodiment, the first width is a contact poly pitch (CPP). In the second embodiment, a second plurality of VTFETs is adjacent to the first plurality of VTFETs on the wafer. In the second embodiment, a portion of the second plurality of VTFETs has a first width. In the second embodiment, a shared top contact is connected to each of the top source / drain regions of the first plurality of VTFETs and the second plurality of VTFETs. In the second embodiment, the bottom source / drain regions of the first plurality of VTFETs extend at least the first width from a first VTFET of the first plurality of VTFETs, and the bottom source / drain regions of the first plurality of VTFETs are connected to each VTFET of the first plurality of VTFETs. In the second embodiment, a contact from the front side of the wafer is connected to the bottom source / drain regions of the first plurality of VTFETs.

[0008] In a second embodiment, a contact may be connected to the lower source / drain regions of the first plurality of VTFETs at a front surface of the lower source / drain regions. In a second embodiment, a contact may be connected to the lower source / drain regions of the first plurality of VTFETs at a back surface of the lower source / drain regions. In a second embodiment, the contact is greater than the first width. In a second embodiment, the contact from the front surface of the VTFET connected to the lower source / drain regions is an output connection.

[0009] Embodiments of the present invention provide for larger contacts to the backside of the bottom source / drain regions of the VTFET device. Embodiments of the present invention provide for output sharing with adjacent circuitry both laterally and vertically within a single CPP. Embodiments of the present invention avoid a higher resistance path for power supply through the RX or active area region to the contact region.

[0010] In a third embodiment, a first plurality of vertical transport field effect transistors (VTFETs) are on the wafer. In the third embodiment, each VTFET of the first plurality of VTFETs has a first width, the first width being a contact poly pitch (CPP). In the third embodiment, a second plurality of VTFETs are on the wafer, the second plurality of VTFETs being adjacent to the first plurality of VTFETs. In the third embodiment, a lower source / drain region of the first plurality of VTFETs extends at least the first width from a first VTFET of the first plurality of VTFETs. In the third embodiment, a top contact is connected to an upper source / drain region of the second plurality of VTFETs, the top contact extending at least the first width from a second VTFET of the second plurality of VTFETs.

[0011] In a third embodiment, the lower contact is connected to the lower source / drain region and to a metal line in a first metal layer, the first metal layer overlying the first and second plurality of VTFETs. In the third embodiment, the upper contact is connected to the metal line. In the third embodiment, the active region is adjacent to the first and second plurality of VTFETs within a first width, and the active region is connected to the metal line in the first metal layer. In the third embodiment, the lower source / drain region is connected to the active region. In the third embodiment, the upper contact is connected to the active region. In the third embodiment, a contact from the front of the VTFET connected to the lower source / drain region is an output connection. In the third embodiment, the contact is larger than the first width.

[0012] Embodiments of the present invention provide for larger contacts to the backside of the lower source / drain regions of the VTFET device. Embodiments of the present invention provide reduced resistance for high performance devices using backside power. Embodiments of the present invention provide for larger contacts to the RX or active area region providing reduced resistance. Embodiments of the present invention provide for shared outputs with adjacent circuitry both laterally and vertically within a single CPP. Embodiments of the present invention avoid a higher resistance path for power supply through the RX or active area region to the contact region. Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or supplied to the source / drain / gate regions of the VTFET through a backside power delivery network. [Brief explanation of the drawings]

[0013] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0014] [Figure 1] 1 shows a cross-sectional view of a VTFET semiconductor structure having front contacts for the upper source / drain regions, the lower source / drain regions, and the gate region according to a first embodiment of the present invention.

[0015] [Figure 2] 1 shows a cross-sectional view of a VTFET semiconductor structure having front contacts for the upper source / drain and gate regions and back contacts for the lower source / drain regions according to a first embodiment of the present invention.

[0016] [Figure 3] 1 shows a cross-sectional view of a VTFET semiconductor structure having front contacts for the upper source / drain regions and back contacts for the lower source / drain and gate regions according to a first embodiment of the present invention.

[0017] [Figure 4A] FIG. 1 illustrates a top view of a semiconductor structure including two sets of two VTFETs in parallel in series, according to one embodiment of the present invention.

[0018] [Figure 4B] 1 shows a cross-sectional view of section A of a semiconductor structure including two sets of two VTFETs in parallel in series according to a first embodiment of the present invention.

[0019] [Figure 4C] 1 shows a cross-sectional view of section A of a semiconductor structure including two sets of two VTFETs in parallel in series according to a second embodiment of the present invention.

[0020] [Figure 4D] 10 shows a cross-sectional view of section A of a semiconductor structure including two sets of two VTFETs in parallel in series according to a third embodiment of the present invention.

[0021] [Figure 5A] FIG. 1 shows a top view of a semiconductor structure including two series sets of two VTFETs in parallel in a first string and four VTFETs in parallel in a second string with connected outputs, according to a first embodiment of the present invention.

[0022] [Figure 5B] FIG. 1 shows a cross-sectional view of cross section X1 of a semiconductor structure including two series sets of two VTFETs in parallel in a first column and four VTFETs in parallel in a second column with connected outputs, according to a first embodiment of the present invention.

[0023] [Figure 6A] FIG. 10 shows a top view of a semiconductor structure including two series sets of two VTFETs in parallel in a first string and four VTFETs in parallel in a second string with connected outputs, according to a second embodiment of the present invention.

[0024] [Figure 6B] FIG. 10 shows a cross-sectional view of section X2 of a semiconductor structure including two series sets of two VTFETs in parallel in a first row and four VTFETs in parallel in a second row with connected outputs, according to a second embodiment of the present invention.

[0025] [Figure 7] 1 illustrates a top view of a semiconductor structure having a shared output region for multiple columns of semiconductor structures, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0026] Embodiments of the present invention recognize that a vertical transport field effect transistor (VTFET) has vertical current flow. Embodiments of the present invention recognize that a VTFET includes a lower source / drain region and an upper source / drain region. Embodiments of the present invention recognize that the lower source / drain region is closer to the backside of the VTFET (closer to the wafer) and the upper source / drain region is closer to the frontside of the VTFET (closer to the conventional interconnect wiring). Embodiments of the present invention recognize that the input goes to one source / drain region and the output goes to one source / drain region, such that either the input or the output is at the backside of the device and either the input or the output is at the frontside of the device. Therefore, embodiments of the present invention recognize that the lower source / drain at the backside of the VTFET must reach the frontside of the semiconductor device. Embodiments of the present invention recognize that in conventional VTFETs, the pitch (or width) between the gates of adjacent devices in the same semiconductor layer is commonly known as the contacted gate pitch (CGP) or contact poly pitch (CPP).

[0027] Embodiments of the present invention provide for larger contacts to the backside of the lower source / drain regions of the VTFET device. Embodiments of the present invention provide reduced resistance for high performance devices using backside power. Embodiments of the present invention provide for larger contacts to the RX or active area region providing reduced resistance. Embodiments of the present invention provide for shared outputs with adjacent circuitry both laterally and vertically within a single CPP. Embodiments of the present invention avoid a higher resistance path for power supply through the RX or active area region to the contact region. Embodiments of the present invention provide for any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to be distributed or supplied to the source / drain / gate regions of the VTFET through a backside power delivery network.

[0028] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in various ways and therefore should not be construed as limited to the embodiments disclosed herein. Reference will now be made in detail to embodiments of the present invention. Example embodiments are illustrated in the accompanying drawings, in which like reference numerals refer to like elements throughout.

[0029] The following presents a summary to provide a basic understanding of one or more embodiments of the present disclosure. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. Although aspects of the present invention are described with reference to given example architectures, it should be understood that other architectures, structures, substrate materials, process features, and steps may vary within the scope of the aspects of the present invention.

[0030] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as semiconductor devices. The embodiments can be implemented in conjunction with integrated circuit fabrication techniques currently used in the art for advanced semiconductor devices, and only those commonly implemented process steps necessary for understanding the described embodiments are included. The figures represent cross-sectional portions of portions of advanced semiconductor devices after fabrication and are not drawn to scale, but instead are drawn to illustrate features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to variously utilize the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0031] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it can be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0032] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods in terms of their orientation in the drawings. The terms "on," "above," "on," "on," "positioned on," or "positioned on top of" mean that a first element is above a second element, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "direct contact" means that a first element and a second element are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0033] In the following detailed description, some of the processing steps, materials, or operations known in the art may be combined for purposes of presentation and illustration, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. Additionally, for the sake of brevity and to maintain focus on the unique features of the elements of the present invention, descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other cases, some known processing steps or operations may not be described. It should be understood that the following description instead focuses on the unique features or elements of various embodiments of the present invention.

[0034] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive in a storage access network, etc.). If the designer does not create the chip or the photolithography masks used to create the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for the creation of photolithography masks, which typically include multiple copies of the chip design to be formed on a wafer. The photolithography mask is utilized to define the areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0035] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads affixed to a motherboard or other higher-level carrier) or multi-chip packages (such as ceramic carriers with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards, or other input devices and central processing units.

[0036] It should also be understood that material compounds are described in terms of the listed elements, e.g., SiGe. These compounds may include different ratios of elements within the compound, e.g., SiGe may include SiGe, where x is less than or equal to 1, etc. Additionally, other elements may be included in the compound and still function according to the present principles. Compounds with additional elements will be referred to herein as alloys.

[0037] References herein to "one embodiment" or "an embodiment," as well as other variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations, in various places throughout this specification do not necessarily all refer to the same embodiment.

[0038] References in the specification to "one embodiment," "another embodiment," "another embodiment," "an embodiment," etc. may mean that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, if a particular feature, structure, or characteristic is described in connection with one embodiment, it is understood that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0039] It should be understood that the use of any of the following terms, " / ," "and / or," and "at least one of," is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B), for example, in the case of "A / B," "A and / or B," and "at least one of A and B." As a further example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such language is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A, B, and C). This may be extended for as many items as are listed, as would be readily apparent to one skilled in the art.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0041] Spatially relative terms such as "below," "bottom," "lower," "top," and "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if the device in the figures were inverted, elements described as being "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an above and below orientation. A device can be oriented differently (rotated 90 degrees or at another orientation), and the spatially relative descriptors used herein can be interpreted accordingly. Also, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0042] Although terms such as "first" and "second" may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be called a second element without departing from the scope of the present concept.

[0043] Broadly speaking, the various processes used to form semiconductor chips fall into four broad categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition (PECVD), a process that uses energy in a plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0044] Semiconductor lithography is the formation of three-dimensional relief images or patterns on semiconductor substrates for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed with a photosensitive polymer called a photoresist. The patterns created by lithography or photolithography are typically used to define or protect selected surfaces and portions of semiconductor structures during subsequent etching processes.

[0045] Removal is any process, such as etching or chemical-mechanical planarization (CMP), that removes material from a wafer. Examples of etching processes include either wet (e.g., chemical) or dry etching processes. One example of a removal or dry etching process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote, wide-beam ion / plasma source to remove substrate material by means of physical inert and / or chemically reactive gases. Like other dry plasma etching techniques, IBE offers advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry etching process is reactive ion etching (RIE). Generally, RIE uses a highly chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma erode the wafer surface, reacting with and removing the surface material.

[0046] Deposition processes for metal liners and sacrificial materials include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which deposition species are formed as a result of a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). A solid product of the reaction is deposited on a surface, forming a film, coating, or layer of the solid product. Variations in CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metal organic CVD (MOCVD), and combinations thereof may also be utilized. In an alternative embodiment using PVD, the sputtering equipment may include a direct current diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In an alternative embodiment using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In an alternative embodiment using GCIB deposition, a high pressure gas is expanded in a vacuum and then condensed into clusters, which can be ionized and directed toward the surface, thereby providing highly anisotropic deposition.

[0047] Vertical transport field-effect transistors (VTFETs) have become a viable device option for scaling semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to the 5-nanometer (nm) node and beyond. VTFET devices include one or more fin channels with source / drain regions on the top and bottom sides of the fin at the ends of the fin channel. Current flows vertically (e.g., perpendicular to the substrate) through the fin channel, e.g., from the bottom source / drain region to the top source / drain region. Vertical transport architecture devices are designed to address the limitations of horizontal device architectures, e.g., with respect to density, performance, power consumption, and integration due to, e.g., decoupling gate length from contact gate pitch, providing density comparable to Fin-FETs with larger contact poly pitch (CPP), and providing lower middle-of-line (MOL) resistance.

[0048] In a first embodiment, Figure 1 shows VTFET 100 with contacts 114, 124, and 134 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 100. In a second embodiment, Figure 2 shows VTFET 200 with contacts 214 and 234 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 200, and contact 224 directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 200. In a third embodiment, Figure 3 shows VTFET 300 with contact 314 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 300.

[0049] 1 is a cross-sectional view of a VTFET 100 formed on a bulk substrate 102. The substrate 102 may be formed from any suitable semiconductor structure, including various silicon-containing materials, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and stacks thereof. Silicon is the semiconductor material most often used in wafer fabrication, although alternative semiconductor materials may be utilized as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. In one exemplary embodiment, the substrate 102 is silicon.

[0050] VTFET 100 includes an STI region 104 composed of a dielectric material, such as silicon oxide or silicon oxynitride, and formed by methods known in the art. For example, in one exemplary embodiment, STI region 104 is a shallow trench isolation oxide layer.

[0051] The VTFET 100 includes upper source / drain regions 110 and lower source / drain regions 120 on opposite sides of a fin 130. In one embodiment, the upper source / drain regions 110 are formed between dielectric layers 170. In one embodiment, the lower source / drain regions 120 are formed in the substrate 102 between shallow trench isolation regions 104. The upper source / drain regions 110 and lower source / drain regions 120 are formed, for example, by an epitaxial growth process. The epitaxially grown upper source / drain regions 110 and lower source / drain regions 120 can be in-situ doped, meaning that dopants are incorporated into the epitaxy film during the epitaxy process. Other alternative doping techniques can be used, including, but not limited to, ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, etc., and the dopants may include, for example, n-type dopants selected from the group of phosphorus (P), arsenic (As), and antimony (Sb) at various concentrations, and p-type dopants selected from the group of boron (B), gallium (Ga), indium (In), and thallium (Tl). For example, in a non-limiting example, the range of dopant concentrations is from 1×10 18 / cm 3 ~1x10 21 / cm 3 According to one embodiment, the lower source / drain region 120 may be boron-doped SiGe for a p-type field effect transistor (P-FET) or phosphorus-doped silicon for an n-type field effect transistor (N-FET). It is understood that the term "source / drain region" as used herein means that a given source / drain region can be either a source region or a drain region depending on the application.

[0052] Terms such as "epitaxial growth and / or deposition" and "epitaxially forming and / or growing" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the grown semiconductor material has the same crystalline properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the deposition surface of a semiconductor substrate with sufficient energy to move around on the surface and orient themselves relative to the crystalline arrangement of atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystalline surface exhibits a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0053] Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Typically, higher temperatures result in faster deposition, but faster deposition can result in crystalline defects and film cracking.

[0054] A number of different sources may be used for the epitaxial growth of compressively strained layers. In some embodiments, the gas source for deposition of the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source, including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source, including, but not limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Meanwhile, an epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used. After epi formation, a drive-in anneal can be applied to move the dopants closer to the bottom of the fin channel.

[0055] In one embodiment, as used herein, "semiconductor fin" or fin 130 refers to a semiconductor material having a pair of parallel vertical sidewalls. As used herein, a surface is "vertical" if there is a vertical plane that does not deviate by more than three times the root-mean-square roughness of the surface. In one embodiment, each fin 130 has a height ranging from about 20 nm to about 200 nm and a width ranging from about 5 nm to about 30 nm. Other heights and / or widths less than or greater than the ranges mentioned herein may also be used herein. Each fin 130 is spaced from its nearest neighbor by a pitch ranging from about 20 nm to about 100 nm; the pitch is measured from a point or reference plane on one semiconductor fin to the exact same point or reference plane on a neighboring semiconductor fin. Additionally, the fins 130 are generally oriented parallel to one another. Although this application describes and illustrates a single fin 108, any number of fins may be used along with the gate region surrounding them, and the fins may be of any shape.

[0056] The fin 130 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including, but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and stacks thereof. Silicon is the semiconductor material most often used in wafer fabrication, although alternative semiconductor materials may be utilized as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. In one exemplary embodiment, the fin 130 is silicon.

[0057] In one embodiment, the lower spacer layer 140 is formed over the STI regions 104 and the lower source / drain regions 120. In one embodiment, the lower spacer layer 140 is formed around the fin 130. Suitable materials for the lower spacer layer 140 include, for example, silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiO x The lower spacer layer 140 can be deposited using directional deposition techniques, such as high-density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition deposits the spacer material preferably on exposed horizontal surfaces but not on lateral sidewalls. Alternatively, the lower spacer layer 140 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recessing.

[0058] In one embodiment, an upper spacer layer 160 is formed over the gate region between the fin 130 and the dielectric layer 170. In one embodiment, the upper spacer layer 160 is formed around the fin 130. Suitable materials for the upper spacer layer 160 include, for example, silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiO x The lower spacer layer 140 can be deposited using directional deposition techniques such as high-density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition deposits the spacer material preferably on exposed horizontal surfaces but not on lateral sidewalls. Alternatively, the upper spacer layer 160 can be formed by overfilling the space with a dielectric material followed by chemical mechanical planarization (CMP) and dielectric recessing.

[0059] A gate region is formed around the fin 130 on the lower spacer layer 140. In an exemplary embodiment, the gate region is deposited around the fin 130 on the lower spacer layer 140 using, for example, ALD, CVD, RFCVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), or molecular layer deposition (MLD). The gate region may include a gate dielectric layer 150 and a gate conductor layer 132. The gate dielectric layer 150 may be formed from a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (TaO), titanium oxide (TiO), barium strontium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (YO), aluminum oxide (AlO), lead scandium tantalate, and lead zinc niobate. High-k materials may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate conductor layer 132 may include a metal gate or work function metal (WFM). The WFM for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), combinations of Ti and Al alloys, a stack including a barrier layer (e.g., TiN, TaN, etc.) followed by one or more of the aforementioned WFM materials, etc. It should be understood that a variety of other materials may be used for the gate conductor layer 132 as desired.

[0060] In one embodiment, the dielectric layer 170 is made of, for example, silicon oxide (SiO x), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As noted above, the term "low-k" as used herein refers to a material having a relative dielectric constant, k, lower than that of silicon dioxide. In one embodiment, dielectric layer 170 can be formed using a deposition technique including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin-on coating, or sputtering.

[0061] In one embodiment, the upper source / drain region 110, the lower source / drain region 120, and the gate region are connected to interconnect wiring and / or a power distribution network (not shown) through contacts 114, 124, and 134, respectively. In one embodiment, as shown in FIG. 1 , contacts 114, 124, and 134 are formed to connect directly to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 100. In one embodiment, contacts 114, 124, and 134 may comprise any suitable conductive material, such as copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that can be used include, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques can be used to form contacts 114, 124, and 134.

[0062] In a second embodiment, FIG. 2 shows VTFET 200 with contacts 214 and 234 directly connected to interconnect wiring and / or a power distribution network (not shown) on the front side of VTFET 200, and contact 224 directly connected to interconnect wiring and / or a power distribution network (not shown) on the back side of VTFET 200. In the second embodiment, VTFET 200 shares substantially similar features to those described above with reference to VTFET 100. For example, upper source / drain region 210 is substantially similar to upper source / drain region 110. While a substrate similar to substrate 102 shown in FIG. 1 is not shown in FIG. 2, it should be noted that those skilled in the art will recognize that VTFET 200 may be formed on a substrate similar to substrate 102 shown in FIG. 1.

[0063] In the second embodiment, the orientation of the contacts in VTFET 200 is the primary difference compared to VTFET 100. In the second embodiment, contacts 214 and 234 are directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 200, and contact 224 is directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 200.

[0064] In a third embodiment, FIG. 3 shows VTFET 300 with contact 314 directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 300. In the third embodiment, VTFET 300 shares substantially similar features to those described above with reference to VTFET 100 and VTFET 200. For example, upper source / drain region 310 is substantially similar to upper source / drain region 110 and upper source / drain region 210. While a substrate similar to substrate 102 shown in FIG. 1 is not shown in FIG. 3, it should be noted that those skilled in the art will recognize that VTFET 300 may be formed on a substrate similar to substrate 102 shown in FIG. 1.

[0065] In the third embodiment, the orientation of the contacts in VTFET 300 is the primary difference compared to VTFET 100 and VTFET 200. In the third embodiment, contact 314 is directly connected to the interconnect wiring and / or power distribution network (not shown) on the front side of VTFET 300, and contacts 324 and 334 are directly connected to the interconnect wiring and / or power distribution network (not shown) on the back side of VTFET 300.

[0066] FIG. 4A illustrates a top view of a semiconductor structure 400A including two sets of two parallel VTFETs in series, according to one embodiment of the present invention. In one embodiment, the first two VTFETs in FIG. 4A are shown in parallel. In other words, a shared input is provided to the first VTFET and the second VTFET, and a shared output extends from both the first VTFET and the second VTFET. As shown in FIG. 4A, the first VTFET includes a shared lower source / drain region 420A, a fin 430A, and an upper source / drain region (not shown). As shown in FIG. 4A, the second VTFET includes a shared lower source / drain region 420A, a fin 432A, and an upper source / drain region (not shown). As explained, the upper source / drain regions of each VTFET are not shown for clarity. Note that in a preferred embodiment, the shared lower source / drain region 420A may be connected to a backside power distribution network (not shown). In an alternative embodiment, the shared lower source / drain region 420A may be connected to a front power supply network (not shown). In one embodiment, the shared lower source / drain region 420A may be two separate lower source / drain regions connected by a shared bottom contact that is connected to a front or back power supply network (not shown).

[0067] As shown in FIG. 4A , in one embodiment, the first VTFET includes a gate region 440A that surrounds at least a portion of the fin 430A, and the second VTFET includes a gate region 442A that surrounds at least a portion of the fin 432A. In one embodiment, the semiconductor structure 400A includes a shared gate region 472 connected to both the gate region 440A and the gate region 442A. In one embodiment, the shared gate region 472 is connected to a gate contact 474, which extends toward the front surface of the semiconductor structure 400A. In one embodiment, the gate contact 474 may extend toward the back surface of the semiconductor structure 400A. In an alternative embodiment, the shared gate region 472 may not be present, and both the gate region 440A and the gate region 442A may have their own gate contacts (not shown) that extend toward the front or back surface of the semiconductor structure 400A.

[0068] In one embodiment, the second two VTFETs in FIG. 4A are shown in parallel. In other words, a shared input is provided to the third and fourth VTFETs, and a shared output extends from both the third and fourth VTFETs. As shown in FIG. 4A, the third VTFET includes a shared lower source / drain region 422A, a fin 434A, and an upper source / drain region (not shown). As shown in FIG. 4A, the fourth VTFET includes a shared lower source / drain region 422A, a fin 436A, and an upper source / drain region (not shown). As explained, the upper source / drain regions of each VTFET are not shown for clarity.

[0069] As shown in FIG. 4A , in one embodiment, the third VTFET includes a gate region 444A that surrounds at least a portion of the fin 434A, and the fourth VTFET includes a gate region 446A that surrounds at least a portion of the fin 436A. In one embodiment, the semiconductor structure 400A includes a shared gate region 476 connected to both the gate region 444A and the gate region 446A. In one embodiment, the shared gate region 476 is connected to a gate contact 478, which extends toward the front surface of the semiconductor structure 400A. In one embodiment, the gate contact 478 may extend toward the back surface of the semiconductor structure 400A. In an alternative embodiment, the shared gate region 476 may not be present, and both the gate region 444A and the gate region 446A may have their own gate contacts (not shown) that extend toward the front or back surface of the semiconductor structure 400A.

[0070] 4A , in one embodiment, the semiconductor structure 400A includes the shared lower source / drain region 422A described above connected to the third and fourth VTFETs. The shared lower source / drain region 422A extends one CPP from the fourth VTFET before connecting to the shared front contact 482A. In one embodiment, the shared back contact 482A is centered approximately one CPP from the center of the adjacent fourth VTFET. In one embodiment, the shared front contact 482A extends to connect to a front power delivery network (not shown).

[0071] FIG. 4B illustrates a cross-sectional view of section A of a semiconductor structure 400B including two series sets of two parallel VTFETs according to a first embodiment of the present invention. As shown in FIG. 4B, the first VTFET includes a shared lower source / drain region 420B, a fin 430B, an upper source / drain region 410B, and a gate region 440B surrounding a portion of the fin 430B. As shown in FIG. 4B, the second VTFET includes a shared lower source / drain region 420B, a fin 432B, an upper source / drain region 412B, and a gate region 442B surrounding a portion of the fin 432B. Note that in alternative embodiments, the first and second VTFETs may have individual / separate lower source / drain regions connected by a shared bottom contact (not shown). As mentioned above, in a preferred embodiment, the shared lower source / drain region 420B may be connected to a backside power supply network (not shown).

[0072] In one embodiment, as shown here, the front contact extends to the left edge of gate region 440 A and the right edge of gate region 446 A. In alternative embodiments, as known in the art, the front contact may extend any horizontal distance, so long as the front contact is at least electrically connected to the upper source / drain regions, as described below.

[0073] As shown in Figure 4B, the third VTFET includes a shared lower source / drain region 422B, a fin 434B, an upper source / drain region 414B, and a gate region 444B surrounding a portion of fin 434B. As shown in Figure 4B, the fourth VTFET includes a shared lower source / drain region 422B, a fin 436B, an upper source / drain region 416B, and a gate region 446B surrounding a portion of fin 436B.

[0074] As shown in FIG. 4B , in a first embodiment, the semiconductor structure 400B includes the shared lower source / drain region 422B described above connected to the third and fourth VTFETs. The shared lower source / drain region 422B extends one channel pack (CPP) from the fourth VTFET before connecting to the shared front contact 482B. In one embodiment, the shared front contact 482B is centered approximately one channel pack (CPP) from the center of the adjacent VTFET. In one embodiment, the shared front contact 482B extends to connect to a front power delivery network (not shown). In one embodiment, the shared front contact 482B is substantially the same as the cell height of any of the VTFETs in the semiconductor structure 400B. In the first embodiment, the shared front contact 482B is directly connected to the shared lower source / drain region 422B.

[0075] FIG. 4C illustrates a cross-sectional view of section A of a semiconductor structure 400C including two series sets of two parallel VTFETs according to a second embodiment of the present invention. As shown in FIG. 4C, the first VTFET includes a shared lower source / drain region 420C, a fin 430C, an upper source / drain region 410C, and a gate region 440C surrounding a portion of the fin 430C. As shown in FIG. 4C, the second VTFET includes a shared lower source / drain region 420C, a fin 432C, an upper source / drain region 412C, and a gate region 442C surrounding a portion of the fin 432C. Note that in alternative embodiments, the first and second VTFETs may have individual / separate lower source / drain regions connected by a shared bottom contact (not shown). As mentioned above, in a preferred embodiment, the shared lower source / drain region 420C may be connected to a backside power supply network (not shown).

[0076] As shown in Figure 4C, the third VTFET includes a shared lower source / drain region 422C, a fin 434C, an upper source / drain region 414C, and a gate region 444C surrounding a portion of fin 434C. As shown in Figure 4C, the fourth VTFET includes a shared lower source / drain region 422C, a fin 436C, an upper source / drain region 416C, and a gate region 446C surrounding a portion of fin 436C.

[0077] As shown in FIG. 4C , in a second embodiment, the semiconductor structure 400C includes the shared lower source / drain region 422C described above connected to the third and fourth VTFETs. The shared lower source / drain region 422C extends one channel pack (CPP) from the fourth VTFET before connecting to the shared front contact 482C. In one embodiment, the shared front contact 482C is centered approximately one channel pack (CPP) from the center of the adjacent VTFET. In one embodiment, the shared front contact 482C extends to connect to a front power delivery network (not shown). In one embodiment, the shared front contact 482C is substantially the same as the cell height of either VTFET in the semiconductor structure 400C. In the second embodiment, the shared front contact 482C is connected to a metallization layer 490C in an upper region of the lower source / drain region 422C. In the second embodiment, the metallization layer 490C is within and directly connected to the shared lower source / drain region 422C.

[0078] FIG. 4D illustrates a cross-sectional view of section A of a semiconductor structure 400D including two series sets of two parallel VTFETs according to a third embodiment of the present invention. As shown in FIG. 4D, the first VTFET includes a shared lower source / drain region 420D, a fin 430D, an upper source / drain region 410D, and a gate region 440D surrounding a portion of fin 430D. As shown in FIG. 4D, the second VTFET includes a shared lower source / drain region 420D, a fin 432D, an upper source / drain region 412D, and a gate region 442D surrounding a portion of fin 432D. Note that in alternative embodiments, the first and second VTFETs may have individual / separate lower source / drain regions connected by a shared bottom contact (not shown). As mentioned above, in a preferred embodiment, the shared lower source / drain region 420D may be connected to a backside power supply network (not shown).

[0079] As shown in Figure 4D, the third VTFET includes a shared lower source / drain region 422D, a fin 434D, an upper source / drain region 414D, and a gate region 444D surrounding a portion of fin 434D. As shown in Figure 4D, the fourth VTFET includes a shared lower source / drain region 422D, a fin 436D, an upper source / drain region 416D, and a gate region 446D surrounding a portion of fin 436D.

[0080] As shown in FIG. 4D , in a third embodiment, a semiconductor structure 400D includes the above-described shared lower source / drain region 422D connected to a third VTFET and a fourth VTFET. The shared lower source / drain region 422D extends one channel pack (CPP) from the fourth VTFET before connecting to a shared front contact 482D. In one embodiment, the shared front contact 482D is centered approximately one channel pack (CPP) from the center of an adjacent VTFET. In one embodiment, the shared front contact 482D extends to connect to a front power delivery network (not shown). In one embodiment, the shared front contact 482D is substantially the same height as either VTFET in the semiconductor structure 400D. In the third embodiment, the shared front contact 482D is connected to a metallization layer 490D in a region below the lower source / drain region 422D. In the third embodiment, the metallization layer 490D is within and directly connected to the shared lower source / drain region 422D. In a third embodiment, the metallization layer 490D may extend part or all of the length of the shared lower source / drain region 422D. In a third embodiment, the metallization layer 490D may extend part or all of the length of the shared lower source / drain region 420D (not shown).

[0081] FIG. 5A illustrates a top view of a semiconductor structure 500A including two series sets of two VTFETs in parallel in a first column and four VTFETs in parallel in a second column with connected outputs, according to a first embodiment of the present invention. As shown in FIG. 5A, in one embodiment, the first column 502 of VTFETs includes a first VTFET 510, a second VTFET 511, a third VTFET 512, and a fourth VTFET 513 in parallel. VTFETs 510, 511, 512, and 513 have a shared lower source / drain region 514. As discussed above, VTFETs 510, 511, 512, and 513 each have an upper source / drain region (not shown) connected to a shared upper contact 515A. In one embodiment, the shared upper contact 515A extends horizontally from the first column 502, one channel per channel, from the fourth VTFET 513.

[0082] 5A , in one embodiment, the second column 504 of VTFETs includes a first set 520 of parallel VTFETs and a second set 522 of parallel VTFETs. In one embodiment, the first set 520 of VTFETs has a shared bottom source / drain region 521. In one embodiment, the second set 522 of VTFETs has a shared bottom source / drain region 523A. As discussed above, the first set 520 of VTFETs and the second set 522 of VTFETs each have a top source / drain region (not shown) that is connected to a shared top contact 524, placing the first set 520 of VTFETs and the second set 522 of VTFETs in series. In one embodiment, the shared bottom source / drain region 523A extends horizontally from the second column 504, one channel pack (CPP) from a VTFET in the second set 522 of VTFETs to a bottom contact 524A.

[0083] In one embodiment, the semiconductor structure 500A includes a shared gate region 506. Two contacts are located in the shared gate region 506 that are connected to a front or back power supply network (not shown). The shared gate region 506 is connected to the gate regions of each of the VTFETs in the first string of VTFETs 502 and the second string of VTFETs 504.

[0084] In one embodiment, the semiconductor structure 500A includes front metal layer contacts 530A in a first row 502. As shown in FIG. 5A, in one embodiment, the front metal layer contacts 530A are square in shape. In alternative embodiments, the front metal layer contacts 530A may be circular, e.g., vias, or any other shape. In yet another alternative embodiment, the front metal layer contacts 530A may be any number of front metal layer contacts 530A (i.e., more than one). In one embodiment, the front metal layer contacts 530A connect the shared top contact 515A to the metal layer 534A. In one embodiment, the semiconductor structure 500A includes front metal layer contacts 532A in a second row 504. As shown in FIG. 5A, in one embodiment, the front metal layer contacts 532A are square in shape. In alternative embodiments, the front metal layer contacts 532A may be circular, e.g., vias, or any other shape. In yet another alternative embodiment, the front metal layer contact 532A may be any number of front metal layer contacts 532A (i.e., more than one). In one embodiment, the front metal layer contact 532A connects the bottom contact 524A to the metal layer 534A. In one embodiment, the metal layer 534A may be any metal layer overlying the top of the semiconductor structure 500A. In other words, the metal layer 534A may be a metal layer overlying the top of any of the VTFETs in the semiconductor structure 500A.

[0085] In one embodiment, as shown, the front contact extends to the left edge of the gate region of the first column 502. In alternative embodiments, as known in the art, the front contact may extend any horizontal distance, as long as the front contact is at least electrically connected to the upper source / drain regions, as described below. In one embodiment, as shown, the front contact extends to the left edge of the gate region of the second column 504 and to the right edge of the gate region of the second column 504. In alternative embodiments, as known in the art, the front contact may extend any horizontal distance, as long as the front contact is at least electrically connected to the upper source / drain regions, as described below.

[0086] FIG. 5B shows a cross-sectional view of section X1 of a semiconductor structure 500B including two series sets of two VTFETs in parallel in a first column and four VTFETs in parallel in a second column with connected outputs, according to a first embodiment of the present invention. In one embodiment, the semiconductor structure 500B includes a front metal layer contact 530B. In one embodiment, the front metal layer contact 530B connects the shared top contact 515B to metal layer 534B. In one embodiment, the semiconductor structure 500B includes a front metal layer contact 532B. In one embodiment, the front metal layer contact 532B connects the bottom contact 524B to metal layer 534B. In one embodiment, the bottom contact 524B is connected to the shared bottom source / drain region 523B. In one embodiment, the metal layer 534B may be any metal layer overlying the top of the semiconductor structure 500B. In other words, the metal layer 534B may be a metal layer overlying the top of any of the VTFETs in the semiconductor structure 500B.

[0087] FIG. 6A illustrates a top view of a semiconductor structure 600A including two series sets of two VTFETs in parallel in a first column and four VTFETs in parallel in a second column with connected outputs, according to a second embodiment of the present invention. As shown in FIG. 6A, in one embodiment, the first column 602 of VTFETs includes a first VTFET 610, a second VTFET 611, a third VTFET 612, and a fourth VTFET 613 in parallel. VTFETs 610, 611, 612, and 613 have a shared lower source / drain region 614. As discussed above, VTFETs 610, 611, 612, and 613 each have an upper source / drain region (not shown) connected to a shared upper contact 615A. In one embodiment, the shared upper contact 615A extends horizontally from the first column 602, extending one channel pack (CPP) from the fourth VTFET 613 to connect to the RX region 616A. In one embodiment, the shared top contact 615A extends to connect with the bottom contact 624A.

[0088] As shown in FIG. 6A , in one embodiment, the second column 604 of VTFETs includes a first set 620 of parallel VTFETs and a second set 622 of parallel VTFETs. In one embodiment, the first set 620 of VTFETs has a shared bottom source / drain region 621. In one embodiment, the second set 622 of VTFETs has a shared bottom source / drain region 623A. As discussed above, the first set 620 of VTFETs and the second set 622 of VTFETs each have a top source / drain region (not shown) that is connected to a shared top contact 624, placing the first set 620 of VTFETs and the second set 622 of VTFETs in series. In one embodiment, the shared bottom source / drain region 623A extends horizontally from the second column 604, from a VTFET in the second set 622 of VTFETs to a bottom contact 624A. In one embodiment, the shared bottom source / drain region 623A is connected to the bottom contact 624A.

[0089] In one embodiment, the semiconductor structure 600A includes a shared gate region 606. Two contacts are located in the shared gate region 606 that are connected to a front or back power supply network (not shown). The shared gate region 606 is connected to the gate regions of each of the VTFETs in the first string of VTFETs 602 and the second string of VTFETs 604.

[0090] In one embodiment, the semiconductor structure 600A includes a front metal layer contact 634A. In one embodiment, the front metal layer contact 634A connects the bottom contact 624A to the first metal layer 632A. In one embodiment, the first metal layer 632A is any metal layer above the VTFET. As shown in FIG. 6A , in one embodiment, the front metal layer contact 634A is square in shape. In alternative embodiments, the front metal layer contact 634A may be circular, e.g., a via, or any other shape.

[0091] In one embodiment, as shown, the front contact extends to the left edge of the gate region of the first column 602. In alternative embodiments, as known in the art, the front contact may extend any horizontal distance, so long as the front contact is at least electrically connected to the upper source / drain regions, as described below. In one embodiment, as shown, the front contact extends to the left edge of the gate region of the second column 604 and to the right edge of the gate region of the second column 604. In alternative embodiments, as known in the art, the front contact may extend any horizontal distance, so long as the front contact is at least electrically connected to the upper source / drain regions, as described below.

[0092] 6B shows a cross-sectional view of section X2 of a semiconductor structure 600B including two series sets of two VTFETs in parallel in a first column and four VTFETs in parallel in a second column with connected outputs, according to a second embodiment of the present invention. In one embodiment, the shared lower source / drain region 623B is connected to a bottom contact 624B. In one embodiment, the RX region 616A is connected to the bottom contact 624B. In one embodiment, the bottom contact 624B is connected to a first metal layer 632B by a front metal layer contact 634B.

[0093] 7 shows a top view of a semiconductor structure 700A having a shared output region for multiple columns of semiconductor structures, according to one embodiment of the present invention. Note that semiconductor structure 700A may include any layout of VTFET devices, including non-VTFET transistor devices or other circuitry (not shown). For example, semiconductor structure 700A may include any number of VTFETs in series, parallel, or any combination thereof.

[0094] As shown in FIG. 7 , semiconductor structure 700A includes a first string 700 of VTFETs. The first string 700 of VTFET devices includes four VTFETs in parallel, a shared top contact connected to the top source / drain region of each VTFET, and a shared bottom source / drain region of each of the four VTFETs. In one embodiment, semiconductor structure 700A includes a second string 704 of VTFETs as a first pair 706 of VTFETs and a second pair 708 of VTFETs. In one embodiment, the first pair 706 of VTFETs is in parallel with a shared bottom source / drain region, and the second pair 708 of VTFETs is in parallel with a shared bottom source / drain region 734. The first pair 706 of VTFETs and the second pair 708 of VTFETs are in series and connected by a shared top contact connected to the top source / drain region of each VTFET in the pair of VTFETs. In one embodiment, the shared lower source / drain region 734 extends 1 CPP down from the VTFETs in the second pair of VTFETs 708 to at least the bottom contact 732, discussed below, and is connected to the bottom contact 736. In other words, the center of the bottom contact 736 is at least 1 CPP from the center of the VTFET fin closest to the bottom contact 732 in the second pair of VTFETs 708. In one embodiment, the shared gate region 702 is connected to the gate region of each VTFET in the first string of VTFETs 700 and the second string of VTFETs 704, similar to the embodiment discussed above.

[0095] As shown in FIG. 7 , semiconductor structure 700A includes a third string 710 of VTFETs. The third string 710 of VTFET devices includes four VTFETs in parallel, a shared top contact connected to the top source / drain region of each VTFET, and a shared bottom source / drain region of each of the four VTFETs. In one embodiment, semiconductor structure 700A includes a fourth string 714 of VTFETs as a first pair 716 of VTFETs and a second pair 718 of VTFETs. In one embodiment, the first pair 716 of VTFETs is in parallel with a shared bottom source / drain region, and the second pair 718 of VTFETs is in parallel with a shared bottom source / drain region 730. The first pair 716 of VTFETs and the second pair 718 of VTFETs are in series and connected by a shared top contact connected to the top source / drain region of each VTFET in the VTFET pair. In one embodiment, the shared lower source / drain region 730 extends horizontally from the second pair of VTFETs 718 at least 1 CPP from a VTFET in the second pair of VTFETs 718 to, and is connected to, the bottom contact 732. In other words, the center of the bottom contact 732 is at least 1 CPP from the center of the VTFET fin closest to the bottom contact 732 in the second pair of VTFETs 718. In one embodiment, the shared gate region 712 is connected to the gate region of each VTFET in the third column of VTFETs 710 and the fourth column of VTFETs 714, similar to the embodiment discussed above.

[0096] 7, semiconductor structure 700A includes a fifth string 720 of VTFETs and a sixth string 724 of VTFETs. In one embodiment, the fifth string 720 of VTFET devices includes four VTFETs in parallel, a shared top contact connected to the top source / drain region of each of the four VTFETs, and a shared bottom source / drain region. In one embodiment, the sixth string 724 of VTFET devices includes four VTFETs in parallel, a shared top contact connected to the top source / drain region of each of the four VTFETs, and a shared bottom source / drain region. In one embodiment, a shared gate region 722 is connected to the gate region of each of the VTFETs in the fifth string 720 of VTFETs and the sixth string 724 of VTFETs, similar to the embodiment discussed above. While FIG. 7 does not show connections from any of the VTFETs in the fifth column 720 or the sixth column 724 to the bottom contact 732 or bottom contact 736, it should be noted that connections from any of the top source / drain regions, bottom source / drain regions, or gate regions of the VTFETs in the fifth column 720 or the sixth column 724 may be connected to the bottom contact 732, bottom contact 736, the shared bottom source / drain region 730, and the shared bottom source / drain region 734.

[0097] In one embodiment, the front contact extends to the left edge of the gate region and / or the right edge of the gate region, as shown in Figure 7. In alternative embodiments, as known in the art, the front contact may extend any horizontal distance, so long as the front contact is at least electrically connected to the upper source / drain regions, as described below.

[0098] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a vertical transport field effect transistor (VTFET) on a wafer, the VTFET having a first width, the first width being a contact poly pitch (CPP); a lower source / drain region of the VTFET extending from the VTFET by at least the first width; and a contact from the front side of the VTFET connected to the lower source / drain region; A semiconductor device comprising:

2. 2. The semiconductor device of claim 1, wherein the contact connects to the lower source / drain region at a front surface of the lower source / drain region.

3. 2. The semiconductor device of claim 1, wherein the contact is connected to the lower source / drain region at a back surface of the lower source / drain region.

4. The semiconductor device of claim 1 , wherein the contact has a width greater than the first width.

5. 2. The semiconductor device of claim 1, wherein the contact from the front side of the VTFET connected to the lower source / drain region is an output connection.

6. a first plurality of vertical transport field effect transistors (VTFETs) on a wafer, a portion of the first plurality of VTFETs having a first width, the first width being a contact poly pitch (CPP); a second plurality of VTFETs on the wafer adjacent to the first plurality of VTFETs, a portion of the second plurality of VTFETs having the first width; a shared top contact, the shared top contact connected to an upper source / drain region of each of the first plurality of VTFETs and the second plurality of VTFETs; lower source / drain regions of the first plurality of VTFETs extending at least the first width from a first VTFET of the first plurality of VTFETs, the lower source / drain regions of the first plurality of VTFETs being connected to a respective VTFET of the first plurality of VTFETs; and contacts from the front side of the wafer connected to the lower source / drain regions of the first plurality of VTFETs; A semiconductor device comprising:

7. 7. The semiconductor device of claim 6, wherein the contacts are connected to the lower source / drain regions of the first plurality of VTFETs at a front surface of the lower source / drain regions.

8. 7. The semiconductor device of claim 6, wherein the contacts are connected to the lower source / drain regions of the first plurality of VTFETs at a backside of the lower source / drain regions.

9. The semiconductor device of claim 6 , wherein the first plurality of VTFETs are in parallel.

10. The semiconductor device of claim 6 , wherein the second plurality of VTFETs are in parallel.

11. The semiconductor device of claim 6 , wherein the first plurality of VTFETs and the second plurality of VTFETs are in series.

12. 7. The semiconductor device of claim 6, further comprising a backside power delivery network, said backside power delivery network being on a backside of said wafer, said backside power delivery network being connected to a plurality of lower source / drain regions of said second plurality of VTFETs, said backside power delivery network being selected from the group consisting of power supply or ground.

13. The semiconductor device of claim 6 , wherein the contact has a width greater than the first width.

14. 7. The semiconductor device of claim 6, wherein the contacts from the front side of the first plurality of VTFETs connected to the lower source / drain regions are output connections.

15. a first plurality of vertical transport field effect transistors (VTFETs) on a wafer, each VTFET of the first plurality of VTFETs having a first width, the first width being a contact poly pitch (CPP); a second plurality of VTFETs on the wafer, the second plurality of VTFETs being adjacent to the first plurality of VTFETs; a lower source / drain region of the first plurality of VTFETs extending at least the first width from a first VTFET of the first plurality of VTFETs; and a top contact connected to the top source / drain regions of the second plurality of VTFETs, the top contact extending at least the first width from a second VTFET of the second plurality of VTFETs; A semiconductor device comprising:

16. further comprising bottom contacts connected to the lower source / drain regions and to metal lines in a first metal layer, the first metal layer overlying the first plurality of VTFETs and the second plurality of VTFETs; the top contact is connected to the metal line; 16. The semiconductor device of claim 15.

17. an active region within the first width adjacent the first plurality of VTFETs and the second plurality of VTFETs; Furthermore, the active area is connected to a metal line in a first metal layer; the lower source / drain region is connected to the active region; the top contact is connected to the active region; 16. The semiconductor device of claim 15.

18. 16. The semiconductor device of claim 15, wherein the first plurality of VTFETs are in series.

19. 16. The semiconductor device of claim 15, wherein the top contacts connected to the top source / drain regions of the second plurality of VTFETs are output connections.

20. a third plurality of VTFETs adjacent to the first plurality of VTFETs; and active regions of the third plurality of VTFETs 16. The semiconductor device of claim 15, further comprising: the active region extending inside the first width of the second plurality of VTFETs.

Images