Methods for improving channel mobility in SiC MOSFETs

Abstract

A method for manufacturing a SiC semiconductor device (10) includes providing a SiC substrate (20) having a SiC epitaxial layer (30) thereon and treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of a first material (35). The method further includes thermally oxidizing a top surface (31) of the SiC epitaxial layer (30) to grow a thermal oxide layer (40) and etching the thermal oxide layer (40). The method further includes implanting dopants of a second material (36) into the SiC epitaxial layer (30) to create a drain (50) and a source (60), activating the dopants with an activation anneal, and depositing a metal gate (70).

Description

[Technical Field]

[0001] explanation The present disclosure relates to methods for manufacturing silicon carbide (SiC) semiconductor devices. The present disclosure further relates to silicon carbide (SiC) semiconductor devices for high power switching applications. [Background technology]

[0002] Silicon carbide (SiC) is the only compound semiconductor that can be thermally oxidized like silicon. This allows the thermally grown oxide on SiC to be used as the gate dielectric to form metal-oxide semiconductor (MOS) devices. SiC MOS field-effect transistors (MOSFETs) are promising candidates for high-power switching applications. Their low on-resistance and large load current make them ideal for use as switching devices.

[0003] A lateral MOSFET consists of two highly conductive p-type semiconductor regions separated from an n-type substrate by a reverse-biased pn diode, a source, and a drain. A metal gate covers the region between the source and drain and is separated from the semiconductor by a gate oxide. The flow of charge carriers from the source to the drain, also known as the channel, is controlled by a voltage applied to the gate.

[0004] However, with the development of electronic technology, the demands on semiconductor devices and circuits have increased due to higher temperatures, higher frequencies, etc. Silicon (Si) cannot meet these requirements, especially those of power switches, due to its material properties, and therefore SiC materials have been developed for semiconductor devices operating at high power, high temperatures, and higher frequencies.

[0005] Insulated gate bipolar transistors (IGBTs) and metal-oxide semiconductor field-effect transistors (MOSFETs) are widely used for power switching applications. These devices have a structure in which the gate electrode is electrically isolated from the device body. Because the only thing that needs to be done is to charge and discharge a capacitor formed by the gate electrode and the device body, the gate control current is significantly smaller than, for example, a gate turn-off transistor.

[0006] Despite the high bulk mobility of SiC, low inversion channel mobility has been reported in SiC MOSFETs, resulting in a much higher on-state resistance than expected from the bulk SiC characteristics. These are due to the density of interface states D at the SiO2 / SiC interface. it This is due to the large D at the SiO2 / SiC interface. it is in the range between 10e11 and 10e13 cm-2 eV-1, but is less than 10e10 cm-2 eV-1 for SiO2 / Si. it The nature of the , is generally attributed to the presence of C-related defects and intrinsic oxide acceptor defects, whereas the D it The properties of SiC are mainly due to C-related donor defects. The presence of carbon in SiC epitaxial layers is due to implantation during oxidation, which results in immobile C clusters such as di-interstitial carbon (Ci)_2.

[0007] However, standard ion implantation into SiC also creates electrically active defects that can trap charge carriers. These, in addition to the C-related defects formed during oxidation, reduce charge carrier mobility in the channel.

[0008] For n-channel MOSFETs, there are several D itVarious methods have been proposed to reduce the D at the top of the SiC bandgap. The use of POA with donor impurities of either N, P or Sb in either NO or POCl or POI. it This results in a decrease in the carrier density (1e11 cm-2 eV-1 for POA and low 1e12 cm-2 eV-1 for POI) and an increase in carrier mobility (90 cm-2 V-1 s-1 for POA and 20-100 cm-2 V-1 s-1 for POI). it The reason for the decrease in SiO2 and subsequent increase in carrier mobility has been explained in terms of N (or P) atoms passivating the C clusters. The increase in carrier mobility has also been explained in terms of counterdoping. By this mechanism, the accumulation of N, P, or Sb in the channel region near the surface passivates interface defects and increases electron mobility in the n-channel by converting the epitaxial layer doping from p- to n-type. Nevertheless, both POA and POI have several drawbacks that can affect the reliability of fabricated devices. Namely, the concentration of incorporated N or P can be difficult to control by POA and flat-band voltage shift due to the introduction of N, P, or Sb in SiO2. Furthermore, P is more easily incorporated into SiC than N, making it possible to obtain normally-on devices. Summary of the Invention [Problem to be solved by the invention]

[0009] The purpose is to prevent the density of interface states at the SiO2 / SiC interface from increasing. It is a further object to increase carrier mobility in the channel of a SiC semiconductor device. [Means for solving the problem]

[0010] This object is solved by the features of the independent claims. Therefore, a method for manufacturing a SiC semiconductor device that does not require a post-oxidation anneal or a pre-oxidation implant is provided, and a corresponding SiC semiconductor device is also provided.

[0011] Plasma immersion ion implantation (PIII) or pulsed plasma doping (PIII) is a surface modification technique that extracts accelerated ions from a plasma by applying a high-voltage pulsed DC or pure DC power source and targets them to a suitable substrate or electrode onto which a semiconductor wafer is placed, implanting the appropriate dopant. The electrode is the cathode for electropositive plasma, while it is the anode for electronegative plasma. Plasma can be generated in a properly designed vacuum chamber with the aid of various plasma sources, such as electron cyclotron resonance plasma sources, helicon plasma sources, capacitively coupled plasma sources, inductively coupled plasma sources, DC glow discharge, and metal vapor arc sources, which yield plasmas with the highest ion density and lowest contamination levels. Vacuum chambers can be of two types: diode and triode types, depending on whether the power supply is applied to the substrate, as in the former case, or to a perforated grid, as in the latter case.

[0012] Thus, a method for manufacturing a SiC semiconductor device includes providing a SiC substrate having a SiC epitaxial layer thereon and treating the SiC epitaxial layer with plasma immersion ion implantation (PIII) using dopants of a first material. The method further includes thermally oxidizing a surface of the SiC epitaxial layer to grow a thermal oxide layer (40) and etching the thermal oxide layer (40). The method further includes implanting dopants of a second material into the SiC epitaxial layer to create drain and source regions, activating the dopants with an activation anneal, and depositing a metal gate.

[0013] The method for manufacturing a SiC semiconductor device includes the optional step of a further plasma immersion ion implantation using Si.

[0014] The method for manufacturing a SiC semiconductor device includes a further optional step of plasma immersion ion implantation using Ar to pre-amorphize the SiC epitaxial layer before treating the SiC epitaxial layer with plasma immersion ion implantation (PIII) using dopants of the first material.

[0015] The above-described method for fabricating SiC semiconductor devices can be used to counteract the adverse effects of specially performed plasma immersion ion implantation.

[0016] Interface state density D at the SiO2 / SiC interface it can be reduced, and then the carrier mobility can be increased.

[0017] Furthermore, the optional Si PIII process further improves carrier mobility. During oxidation, these Si-rich layers are oxidized, minimizing the formation of C clusters and increasing carrier mobility within the channel of the SiC semiconductor device.

[0018] The additional step of Ar PIII allows the channel region to be made deeper. The silicon carbide (SiC) semiconductor device includes a SiC semiconductor substrate having a top surface and a bottom surface, and a SiC epitaxial layer having a top surface and a bottom surface. The SiC epitaxial layer is formed on the top surface of the SiC semiconductor substrate. The SiC semiconductor device further includes source and drain structures formed on the top surface of the SiC epitaxial layer, a thermal oxide, a metal gate, and a first region having dopants of a first material that may be part of a channel. The thermal oxide covers the first region, at least a portion of the source structure, and at least a portion of the drain structure. Thus, the metal gate is electrically insulated from the first region, the source structure, and the drain structure by the thermal oxide and overlaps the first region and at least a portion of the source and drain structures.

[0019] The SiC semiconductor device optionally comprises a second region that is PIII treated with Si. The SiC semiconductor device optionally comprises an Ar-preamorphized SiC epitaxial layer.

[0020] The SiC semiconductor substrate is a 3C—SiC substrate, a 4H—SiC substrate, or a 6H—SiC substrate. The SiC substrate is n-doped or p-doped, and the SiC epitaxial layer is n-doped or p-doped in the same manner as the SiC substrate.

[0021] The SiC semiconductor element can be used as a SiC transistor, which may be, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a SiC junction field effect transistor (SiC-JFET), or a SiC bipolar junction transistor (SiC-BJT).

[0022] Finally, it is pointed out that all proposed features and methods can be used alone, but also in combination with two or more.

[0023] The present disclosure relates to implanting dopants into SiC semiconductor element XYZXYZ. As a result of the described SiC semiconductor devices being fabricated by the described embodiments of the method, the described features and characteristics of the method are also disclosed with respect to the SiC semiconductor devices, and vice versa. Thus, the present disclosure includes several aspects, and all features described with respect to one of the aspects are also disclosed herein with respect to the other aspects, even if each feature is not explicitly mentioned in the context of a particular aspect.

[0024] Exemplary embodiments are described below using schematic diagrams and reference numbers. The figures show: [Brief explanation of the drawings]

[0025] [Figure 1a] The process for manufacturing a SiC semiconductor device is shown. [Figure 1b] The process for manufacturing a SiC semiconductor device is shown. [Figure 1c] The process for manufacturing a SiC semiconductor device is shown. [Figure 1d] The process for manufacturing a SiC semiconductor device is shown. [Figure 1e] The process for manufacturing a SiC semiconductor device is shown. [Figure 1f] The process for manufacturing a SiC semiconductor device is shown. [Figure 1g] The process for manufacturing a SiC semiconductor device is shown. [Figure 2] DLTS spectra of as-grown and PIII-treated 4H-SiC are shown. [Figure 3a] The transfer and output characteristics of the MOSFET are shown. [Figure 3b] The transfer and output characteristics of the MOSFET are shown. DETAILED DESCRIPTION OF THE INVENTION

[0026] The accompanying drawings are included to provide a further understanding. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. The same reference numbers indicate elements or components having the same function. Insofar as elements or components correspond to each other in terms of their function in different figures, their description will not be repeated for each of the following figures. For clarity, elements may not in some cases be labeled with corresponding reference numbers in all figures.

[0027] 1a to 1g show steps in a method for manufacturing a semiconductor device 10. FIG. In this regard, terms such as "above," "under," "top," "upper," and "bottom" refer to the orientation or direction as shown in the figures and relative to stacking direction A. Thus, the height or thickness of a described element is relative to stacking direction A, and the lateral direction B is oriented perpendicular to stacking direction A (see Figures 1a-1g).

[0028] In FIG. 1a, a SiC substrate 20 having a top surface 21 and a bottom surface 22 is provided. On the top surface 21 of the SiC substrate 20 is a SiC epitaxial layer 30 having a bottom surface 31 and a top surface 32. The bottom surface 31 of the SiC epitaxial layer 30 faces the top surface 21 of the SiC substrate 20. The SiC substrate 20 can be n-doped or p-doped to a concentration of at least 1e18 cm-3. The SiC epitaxial layer 30 is doped in the same manner as the SiC substrate 20 and can also be n-doped or p-doped to a concentration between 1e14 cm-3 and 1e16 cm-3. The SiC substrate 20 can be, for example, a 3C-SiC substrate, a 4H-SiC substrate, or a 6H-SiC substrate. In the case of a 3C-SiC epitaxial layer, the SiC substrate 20 can be replaced with, for example, a silicon (Si) substrate.

[0029] FIG. 1b illustrates the treatment of the SiC epitaxial layer 30 with plasma immersion ion implantation (PIII), which generates a first region 33 in the SiC epitaxial layer 30 using a dopant of a first material 35. The doping concentration of the dopant of the first material 35 in the SiC epitaxial layer 30 is in the range of 1e16 to 1e20 cm-3. The dopant of the first material 35 of the n-doped semiconductor element 10 may be, for example, an element derived from Group 2 elements (Be, Mg, Ca, Sr, Ba, Ra) or Group 13 elements (B, Al, Ga, In, Tl, Nh). Alternatively, the dopant of the first material 35 of the p-doped semiconductor element 10 may be, for example, an element derived from Group 15 elements (N, P, As, Sb, Bi, Mc) or Group 16 elements (O, S, Se, Te, Po, Lv). For example, PIII can use energies in the range of 1-30 keV and aluminum dopants. The implantation is carried out at room temperature (RT) (approximately 20-22°C) or at temperatures between 300°C and 500°C.

[0030] After implantation of the dopant of the first material 35, Figure 1c shows an optional additional PIII step. This PIII step uses an energy range of 1-15 keV and silicon as the additional dopant 37 to create second regions 34 in the SiC epitaxial layer 30. The doping concentration of the dopant in the SiC epitaxial layer 30 is in the range of 1e15-1e18 cm-3. The implantation is performed at room temperature (RT) or at temperatures between 300°C and 500°C. In this way, during oxidation, this Si-rich layer 34 is oxidized, minimizing the formation of C clusters and increasing carrier mobility.

[0031] FIG. 1d illustrates a fabrication step following an implantation step of either a dopant of a first material 35, such as Al, or a dopant of the first material 35 and silicon. This step illustrates thermal oxidation of the top surface 31 of the SiC epitaxial layer 30, such that a thermal oxide layer 40 of SiO is grown on top of the SiC epitaxial layer 30. The oxide layer 40 has a top surface 41 and a bottom surface 42. A SiO / SiC interface 45 is created between the top surface 31 of the SiC epitaxial layer 30 and the bottom surface 42 of the thermal oxide layer 40. The thermal oxidation is performed at a temperature between 1100°C and 1400°C.

[0032] The density of interface states at the SiO2 / SiC interface 45, D it is a typical MOSFET standard implant on the order of about 1e12-1e13 cm-2eV-1. When both Al and Si PIII are used, the interface state density D it is smaller than 1e12cm-2eV-1, and the on-resistance R_on decreases by 8 to 10%.

[0033] The carrier mobility in the channel of a typical MOSFET with standard implantation is about 20-50 cm2 / Vs. When both Al and Si PIIIs are used, the carrier mobility in the channel is higher than 100 cm2 / Vs.

[0034] After standard channel implantation, the carbon vacancy (Vc) concentration in the SiC epitaxial layer is higher than 1e14 cm-3. When Al PIII is used, the carbon vacancy (Vc) concentration is less than 1e11 cm-3. When Si PIII is performed on top of Al PIII, the carbon vacancy (Vc) concentration is even lower.

[0035] Furthermore, prior to treating the SiC epitaxial layer 30 with plasma immersion ion implantation (PIII) using the first material 35 and / or Si dopants, the SiC epitaxial layer 30 can be treated with plasma immersion ion implantation (PIII) using Ar with an energy in the range of 5 to 10 keV to preamorphize the SiC epitaxial layer 30. The Ar PIII contributes to deepening the channel.

[0036] FIG. 1e shows the thermal oxide layer 40 etched back at its edges until the SiC epitaxial layer 30 with the doped first region 33 underneath is visible.

[0037] Figure 1f shows the implantation of a dopant of a second material 36 into the SiC epitaxial layer 30, resulting in the creation of a drain 50 and a source 60. The implantation is performed at room temperature or at a temperature between 300°C and 500°C. The dopant concentration of the second material 36 is in the range of 1e17-1e21 cm-3, but is at least an order of magnitude higher than the dopant concentration of the first material used in PIII, e.g., Al. The implantation can be, for example, an n+ implantation using an n-dopant. The implantation is followed by a 30-minute activation anneal at a temperature between 1600°C and 1700°C. The activation anneal is a thermal treatment that compensates for implant damage caused by the dopant.

[0038] In the step shown in FIG. 1g, a metal gate 50 is deposited on top 41 of the etched-back thermal oxide layer 40.

[0039] While this is a basic lateral structure, the disclosure of the embodiments also extends to vertical SiC MOSFET devices.

[0040] The SiC semiconductor device 10 can be used as a SiC transistor, which may be, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a SiC junction field effect transistor (SiC-JFET), or a SiC bipolar junction transistor (SiC-BJT).

[0041] Figure 2 shows the Fourier-Transformed Deep-Level Transient Spectroscopy (FT-DLTS) spectra of as-grown SiC (solid line) and PIII-treated SiC (dashed line). Capacitance (pF) is plotted against temperature (K).

[0042] Plasma immersion ion implantation (PIII) is considered for channel formation. Standard ion implantation into SiC during growth creates several electrically active levels, including EH1 (Ec -0.4 eV), Z1 / 2 (Ec -0.65 eV), EH3 (Ec -0.72 eV), EH4 (Ec -0.8 eV), EH5 (Ec -1.0 eV), and EH6 / 7 (Ec -1.6 eV). The concentrations of these levels range from 1e13 to 1e15 cm-3. These electron traps hinder carrier mobility within the channel. PIII, on the other hand, does not result in the formation of electrically active levels, except for two levels labeled ON1 and ON2, which do not affect device functionality. This allows for seamless charge carrier flow within the channel without trapping effects from electrical traps.

[0043] 3a and 3b show the simulated output and transfer characteristics of MOSFETs with channels formed by standard ion implantation (solid line) and PIII (dashed line).

[0044] Figure 3a shows that the simulated devices have the same threshold voltage (V_th), and therefore the gain in on-resistance R_on is solely due to the lower defect density.

[0045] Figure 3b shows the output characteristics when PIII is used. It can be seen that the curve for the PIII-treated MOSFET (dashed line) shows an improvement compared to the standard ion implantation (solid line), meaning that R_on is reduced.

[0046] 1-3 described above represent exemplary embodiments of the improved SiC semiconductor device 10 and its manufacturing method, and therefore do not constitute an exhaustive list of all embodiments. Actual arrangements and methods may differ, for example, from the embodiments shown for the SiC semiconductor device 10. [Explanation of symbols]

[0047] Reference sign 10 SiC semiconductor elements 20 SiC substrate 21 Top surface of SiC substrate 22 Bottom surface of SiC substrate 30 SiC epitaxial layer 31 Top surface of SiC epitaxial layer 32 Bottom surface of SiC epitaxial layer First region of 33SiC epitaxial layer Second region of 34SiC epitaxial layer 35 Dopant of the first material 36 Dopant of the second material 37 Additional dopant Si 40 Thermal oxide layer 41 Top surface of thermal oxide layer 42 Bottom of the thermal oxide layer 45 SiO2 / SiC interface 50 Drain 60 Sources 70 Metal Gate

Claims

1. A method for manufacturing a SiC semiconductor element (10), comprising: - providing a SiC substrate (20) having a SiC epitaxial layer (30) thereon; - treating said SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of a first material (35); - thermally oxidizing the upper surface (31) of said SiC epitaxial layer (30) so as to grow a thermal oxide layer (40); - etching said thermal oxide layer (40); - implanting dopants of a second material (36) into said SiC epitaxial layer (30) so as to create a drain (50) and a source (60); - activating said dopants with an activation anneal; - depositing a metal gate (70).

2. the PIII is carried out at room temperature RT or at a temperature between 300°C and 500°C, using dopants of the first material (35) whose doping concentration in the SiC epitaxial layer (30) is in the range of 1e16 to 1e20 cm-3, and at an energy in the range of 1 to 30 keV; A method for manufacturing the SiC semiconductor device (10) according to claim 1.

3. the implantation is carried out at room temperature RT or at a temperature between 300°C and 500°C using a dopant of the second material (36) whose doping concentration in the SiC epitaxial layer (20) is in the range of 1e17 to 1e21 cm-3, the doping concentration of the dopant of the second material (36) in the SiC epitaxial layer (20) being at least one order of magnitude higher than the doping concentration of the dopant of the first material (35) in the SiC epitaxial layer (20); A method for manufacturing the SiC semiconductor element (10) according to claim 1 or 2.

4. the activation anneal is carried out at a temperature between 1600°C and 1700°C for 30 minutes; A method for manufacturing a SiC semiconductor device (10) according to claim 1, 2 or 3.

5. treating the SiC epitaxial layer (30) with a further plasma immersion ion implantation (PIII) with an energy in the range of 1 to 15 keV, at room temperature RT or at a temperature between 300°C and 500°C, using Si such that the doping concentration of Si in the SiC epitaxial layer (30) is in the range of 1e15 to 1e18 cm-3, A method for manufacturing a SiC semiconductor device (10) according to any one of the preceding claims.

6. - treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using Ar with an energy in the range of 5-10 keV to pre-amorphize the SiC epitaxial layer (30) before treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of the first material (35), A method for manufacturing a SiC semiconductor device (10) according to any one of the preceding claims.

7. A SiC semiconductor element (10), - a SiC substrate (20), - a SiC epitaxial layer (30), - a SiC epitaxial layer (30) comprising a first region (33) treated by plasma immersion ion implantation (PIII) using dopants of a first material (35); a thermal oxide layer (40), - a drain (50), - sauce (60), a metal gate (70), A semiconductor device (10) comprising:

8. the dopants of the first material (35) used for PIII are derived from elements of group 2 (Be, Mg, Ca, Sr, Ba, Ra) or elements of group 13 (B, Al, Ga, In, Tl, Nh); The semiconductor device (10) of claim 7.

9. The dopant of the first material (35) used for PIII is Al with an energy in the range of 1 to 30 keV and a doping concentration in the SiC epitaxial layer (30) in the range of 1e16 to 1e20 cm-3. The SiC semiconductor device (10) of claim 8.

10. the dopants of the first material (35) used in PIII are derived from elements of group 15 (N, P, As, Sb, Bi, Mc) or group 16 (O, S, Se, Te, Po, Lv); The SiC semiconductor device (10) of claim 7.

11. - a second region (34) PIII-treated with Si, The SiC semiconductor element (10) according to any one of claims 7 to 10.

12. the Si from the second region (34) is implanted with an energy in the range of 1 to 15 keV and with a doping concentration in the SiC epitaxial layer (30) in the range of 1e15 to 1e18 cm-3; The SiC semiconductor device (10) of claim 11.

13. - Ar with an energy in the range of 5-10 keV is implanted into the SiC epitaxial layer (30) to pre-amorphize the SiC epitaxial layer (30); The SiC semiconductor device (10) of claim 7.

14. - the SiC substrate (20) is a 3C-SiC substrate, a 4H-SiC substrate or a 6H-SiC substrate; The SiC semiconductor element (10) according to any one of claims 7 to 13.

15. - said SiC substrate (20) is n-doped or p-doped with a doping concentration of at least 1e18 cm-3; - the SiC epitaxial layer (30) is n-doped or p-doped in the same way as the SiC substrate (30), with a doping concentration in the range of 1e14 to 1e16 cm-3; The SiC semiconductor element (10) according to any one of claims 7 to 14.

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