Apparatus, configuration and system for operating a hardware-based artificial neural network and method for training the same

Abstract

The present invention relates to an apparatus for operating a hardware-based artificial neural network, the apparatus comprising at least one hardware-based artificial neural network, at least one interfering device for coupling at least one interfering signal to at least one region of the hardware-based artificial neural network, and at least one coupling device, the coupling device being arranged between the interfering device and the hardware-based artificial neural network and designed to transmit at least one interfering signal from the interfering device to the at least one region. The present invention provides an improved hardware-based artificial neural network exhibiting improved performance.

Description

[Technical Field]

[0001] The present invention relates to an apparatus, arrangement and system for operating a hardware-based artificial neural network, and a method for training the same. [Background technology]

[0002] Artificial intelligence can be used to detect patterns in technological applications such as image recognition or machine parameter monitoring. Artificial neural networks, which mimic the function of biological neurons, can provide artificial intelligence. These artificial neural networks can be trained with training data using evolution-based methods, where training adjusts the artificial neural networks, thereby improving their ability to perform their tasks. Individual elements of the artificial neural network are reassociated during each training iteration.

[0003] In principle, such systems can be implemented as hardware-based systems, i.e., systems in which hardware physically forms a network, or as software-based systems, particularly as virtual networks simulated or emulated on hardware portions, such as RAM memory and / or processors. In hardware-based systems, configurable electronic elements are linked together to form an artificial neural network. The number of linked elements can be reduced by tens without causing a loss in the system's performance. Furthermore, hardware-based artificial neural networks may have elements that are not connected to other parts of the network, i.e., unconnected and unused elements that cannot be reduced without degrading or losing the performance of the hardware-based artificial neural network.

[0004] To mitigate this effect, for example, Cramer, B., Stoeckel, D., Kreft, M., Wibral, M., Schemmel, J., Meier, K., Priesemann, V., “Control of criticality and computation in spiking neuromorphic networks with plasticity”, Nature Communications, 11(1)(2020) 2853, it is known to increase the signal-to-noise ratio between linked elements as much as possible, thereby increasing the number of subcomponents to thousands and the number of evolutionarily linkable connections to tens of thousands.

[0005] Compared to software-based artificial neural networks, hardware-based artificial neural networks currently have a much more limited number of elements and connections, are less trainable, and are less complex and flexible. Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved hardware-based artificial neural network that eliminates the aforementioned drawbacks. [Means for solving the problem]

[0007] This object is achieved by the features of the independent claims. Advantageous refinements are the subject matter of the dependent claims and the following description.

[0008] According to a first aspect, the present invention relates to an apparatus for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network, the apparatus according to the invention comprising at least one interfering device for injecting at least one interfering signal into at least one region of the hardware-based artificial neural network, and at least one coupling device, the coupling device being arranged between the interfering device and the hardware-based artificial neural network and designed to transmit the at least one interfering signal from the interfering device throughout the at least one region.

[0009] Hardware-based artificial neural networks are understood to include both biologically-based neural networks, in which nodes typically have similar characteristics (weights, transfer functions, etc.) and are arranged in layers, and electronic circuits, in contrast to biologically-based neural networks, in which the nodes of the network have different digital and / or analog circuit elements. These may also not be in the form of layers as in biologically-based networks, but instead be probabilistically connected as electronic circuits, whereby some circuit elements, for example, can use terminals provided as outputs as inputs and vice versa. From the perspective of current electronics, this results in "stupid" overall circuits that can acquire their "intelligence" through training. Therefore, hardware-based artificial neural networks can be referred to as trainable electronic networks. Circuit elements can also form the nodes of the corresponding network. Hardware-based artificial neural networks can also be referred to as physical neural networks.

[0010] In software-based artificial neural networks, the output of each node in a layer of the network is determined sequentially, whereas in hardware-based artificial neural networks, the node output is obtained simultaneously for all nodes in a layer. This means that in software-based artificial neural networks, the number of nodes affects the time required to calculate the output of the artificial neural network. However, in hardware-based artificial neural networks, the number of nodes in a layer makes no difference to the time it takes to determine the output. The time it takes to determine the output data is determined solely by the number of layers.

[0011] The present invention provides an apparatus for operating a hardware-based artificial neural network, in which an interfering signal is injected into at least one region of the hardware-based artificial neural network. The interfering signal is injected into the entire region, i.e., the interfering signal is present in the entire region, or the region corresponds to the region of the hardware-based artificial neural network covered by the interfering signal. The at least one region can be smaller than the entire hardware-based artificial neural network. The apparatus further includes an interfering device capable of injecting the interfering signal into the hardware-based artificial neural network. To inject the interfering signal, a coupling device is provided between the interfering device and the hardware-based artificial neural network. In one example, the coupling device may simply comprise an air-filled space between the interfering device and the hardware-based artificial neural network. The interfering signal emitted by the interfering device passes through the coupling device and is injected into the at least one region. Injecting the interfering signal increases noise in the at least one region, thereby reducing the signal-to-noise ratio during signal transmission between elements, e.g., nodes, of the hardware-based artificial neural network. Thus, contrary to all efforts in electronic circuit implementation, instead of increasing the signal-to-noise ratio in at least one region of the hardware-based artificial neural network, a spatial and / or temporal and / or partial reduction of the signal-to-noise ratio is counterintuitively implemented. This reduction is limited to at least one region where the interference signal is injected, i.e., it is limited to some electronic components of the hardware-based artificial neural network circuit. The signal-to-noise ratio (S / N) is defined as S / N = 10 * log (effective power / noise) (expressed in decibels (dB)) or S / N = 20 * log (effective signal voltage / noise signal voltage). An S / N ratio greater than 15 dB is readily transmittable, while an S / N ratio less than 10 dB is considered noisy. When the effective signal power is equal to the noise signal power, the signal becomes indistinguishable at the receiver. The performance of a hardware-based artificial neural network trained with an injected interference signal is surprisingly improved.Since training is performed using the injected interference signal, the normal operation of the hardware-based artificial neural network is also performed by injecting the interference signal. Improved performance is understood to mean, inter alia, that pattern, e.g., image or speech, recognition is performed correctly with a higher probability without increasing the number of nodes in the network. Thus, an improved hardware-based artificial neural network is provided that eliminates the above-mentioned drawbacks of the prior art.

[0012] According to one example, the hardware-based artificial neural network in at least one region can have at least one component designed to reduce the signal-to-noise ratio upon receiving at least one interfering signal, the interfering device preferably generating an optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization interfering signal.

[0013] The signal-to-noise ratio can be reduced by increasing the noise in the component. To this end, the component can be designed to be sensitive to interfering signals. For example, if an optical interfering signal is used, the noise in the component can increase during the transmission of the electrical signal within the component.

[0014] By way of further example, the interference device may have a plurality of individually actuatable interference elements for injecting interference signals into the hardware-based artificial neural network, the interference elements preferably injecting interference signals into different regions of the hardware-based artificial neural network.

[0015] Thus, multiple regions of the hardware-based artificial neural network, preferably the entire hardware-based artificial neural network, may be affected by an interfering signal. Because the interfering elements can be controlled independently of each other, each region of the hardware-based artificial neural network may be subject to its own interfering signal individually. These regions may overlap and / or be separated from each other.

[0016] Furthermore, a plurality of interference elements can be arranged to be distributed throughout the layer, for example, preferably in the form of an array, and the coupling device comprises a medium having a plurality of coupling elements for transmitting at least one interference signal to at least one region, the coupling elements being distributed within the layer in the same manner as the interference elements.

[0017] Thus, interference elements can be used to generate interference signal patterns, which are then transmitted to the hardware-based artificial neural network via a coupling device involving coupling elements. Because the distribution of interference elements within a layer is known, specific regions of the hardware-based artificial neural network can be targeted with interference signals. In particular, the distribution of interference elements within a layer can be designed so that the interference elements are arranged similarly to the components of the neural network, allowing specific interference signals to be injected into individual components.

[0018] Furthermore, at least some of the plurality of interference elements may be designed as resistive heaters, Peltier elements, light emitting diodes, electromagnetic emitters and / or transmitters, and / or piezoelectric components.

[0019] In a further example, at least one region can have a range that corresponds to the size of the hardware-based artificial neural network, or is designed to be smaller than the size of the hardware-based artificial neural network.

[0020] If at least one region has the same extent as the hardware-based artificial neural network, the interference or combining device can be uniformly shaped to apply the interference signal uniformly to the entire hardware-based artificial neural network. Finer structuring allows the interference signal to be injected only into different regions within a component, such as the signal input or signal output of a circuit element of the hardware-based artificial neural network. For example, if the extent of at least one region is equal to the extent of the components of the hardware-based artificial neural network, with each component assigned a region, then a separate interference signal can be injected into each component of the neural network.

[0021] Thus, the multiple combining elements can have the same structure as the multiple interference elements. Furthermore, the structure of the combining elements can correspond to the structure of the hardware-based artificial neural network. However, this does not exclude the possibility that the structure of the combining elements can be finer or coarser than the structure of the interference elements or the hardware-based artificial neural network.

[0022] According to another example, the apparatus may comprise at least one semiconductor chip comprising a hardware-based artificial neural network, preferably formed in an integrated circuit, more preferably a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0023] A neural network can be designed as a circuit on a semiconductor chip, and the nodes of the neural network can be formed as components of the circuit. In instances where elements of a neural network are designed as components of a field programmable gate array, the field programmable gate array can be configured such that the circuit structure of the elements of the field programmable gate array forms the neural network. A hardware-based artificial neural network that is also implemented on the field programmable gate array can be further trained. In contrast, a hardware-based artificial neural network must be hardwired onto an application-specific integrated circuit and otherwise optimized beforehand.

[0024] The apparatus may also include a shielding device for shielding external interference signals of the same type as the at least one interference signal, and the shielding device may surround the hardware-based artificial neural network, the combining device, and the interference device.

[0025] The shielding device may be designed, for example, as a housing that forms the outer shell of the device. Thus, the interference device, the coupling device, and the hardware-based artificial neural network are enclosed by the shielding device. The shielding device can shield external interference signals that can change the signal-to-noise ratio in an uncontrollable and unrepeatable manner. Thus, the interference signals of the interference device almost exclusively cause changes in the signal-to-noise ratio in the area of ​​the neural network.

[0026] In a second aspect, the present invention relates to an arrangement of a plurality of devices according to the preceding description, wherein the hardware-based artificial neural networks of each device are electrically connected in series and / or parallel with each other, and wherein the interfering device of at least a first device of the plurality of devices and a second device of the plurality of devices is preferably designed as a common interfering device, and wherein the output layer of the hardware-based artificial neural network of a third device of the plurality of devices is preferably also designed to control the interfering device of a fourth device of the plurality of devices.

[0027] The advantages, effects and improvements of the arrangement result from those of the device described above, and in this respect, therefore, to avoid repetition, reference is made to the previous description.

[0028] The configuration comprises at least two devices according to the preceding description. In this configuration, the output layer of the hardware-based artificial neural network of a first device is electrically connected to, among other things, the input of an interfering device of a second device or multiple other devices. The first device can then control or influence the function of the interfering device of the second device. In this way, each device can be coupled to the interfering device of the other devices in the configuration via the electrical connection of its neural network.

[0029] In yet a third aspect, the present invention relates to a system comprising a plurality of configurations according to the preceding description, wherein a first of the plurality of configurations is designed to control at least one interference device in a second of the plurality of configurations.

[0030] The advantages, effects and improvements of the system result from those of the devices and arrangements described above, and in this respect reference is therefore made to the foregoing description to avoid repetition.

[0031] The first configuration may form, for example, a base layer, and the device emits an output signal, which is processed as an input signal by the device of the second configuration, for example after further processing. In this case, at least one interference device of the device of the second configuration may be coupled to the output layer of at least one device of the first configuration. This may be referred to as forward coupling. Furthermore, it is also conceivable that at least one interference device of the device of the first configuration may be coupled to the output layer of at least one device of the second configuration. This may be referred to as backward coupling.

[0032] Additionally, multiple systems can be considered subsystems and combined into a composite system, where the subsystems are coupled together in the manner described above. In this way, more complex systems with improved performance can be formed. For example, such a complex system may process different types of signals (optical and acoustic), with one subsystem processing optical signals and another processing acoustic signals.

[0033] In a fourth aspect, the present invention relates to a method for training an artificial neural network in an apparatus according to the preceding description, the method comprising at least the following steps: defining target output data during processing of supplied training data; supplying the training data to the hardware-based artificial neural network and injecting at least one interfering signal into at least one region of the hardware-based artificial neural network by at least one interfering device; obtaining output data from the hardware-based artificial neural network; determining whether there is at least one deviation between the output data and the target output data, said deviation being outside a predetermined tolerance range; terminating the method if the deviation is within the tolerance range; modifying the hardware-based artificial neural network, preferably modifying at least one interfering signal, and repeating the above steps if the deviation is outside the predetermined tolerance range.

[0034] The advantages, effects and improvements of the method result from those of the device described above, and in this respect reference is therefore made to the foregoing description to avoid repetition.

[0035] The method is used to train a hardware-based artificial neural network in a state perturbed by an interfering device. Thus, the neural network is trained by interfering with signal transmissions in at least one region where an interfering signal is injected. In addition to changes made to the hardware-based artificial neural network, changes are also made to the at least one injected interfering signal during each training run. To this end, at least one parameter of the at least one interfering signal can be changed, such as intensity, frequency, duration, etc. Changing the at least one parameter also changes the at least one interfering signal. Thus, the method can be used to integrate an interfering device into the training of the neural network. Thus, the method can provide a trained hardware-based artificial neural network that performs better than a neural network that is not injected with an interfering signal.

[0036] According to one example, the injected interfering signal may produce a signal-to-noise ratio of 15 dB or less, preferably 10 dB or less, and more preferably 0 dB or less in at least one region.

[0037] In general, readily transmittable signals often have a signal-to-noise ratio greater than 15 dB. A signal-to-noise ratio of less than 10 dB is considered very noisy. If the effective signal power is equal to the noise signal power, the signal becomes indistinguishable at the receiver. Nevertheless, neural networks can, in principle, detect noise patterns at signal-to-noise ratios of 0 dB or less, thereby allowing even indistinguishable signals to influence the output of subsequent nodes in the neural network. The signal-to-noise ratio can also be less than 0 dB, preferably at least -40 dB, more preferably -15 dB, and even more preferably -10 dB.

[0038] It is also contemplated that the hardware-based artificial neural network may be trained, for example, without injecting an interfering signal, prior to the step of defining the target output data during processing of the supplied training data.

[0039] This means that, as known from the prior art, a neural network can be initially trained to obtain an initial performance, e.g., a first accuracy value for recognizing a particular pattern. Subsequent additional training with interference signal injection can exceed the initial performance, e.g., achieve a second accuracy value for detecting the particular pattern, which is greater than the first accuracy value.

[0040] According to a further example, at least one interference device may have at least a plurality of individually actuatable interference elements, each interference element designed to inject an interference signal into the hardware-based artificial neural network, each interference element preferably injecting the interference signal into a different region of the hardware-based artificial neural network, the plurality of actuatable interference elements may be actuated such that the interference signal forms a predetermined interference signal pattern on the hardware-based artificial neural network, and multiple training iterations of the hardware-based artificial neural network are preferably performed sequentially with different predefined interference signal patterns.

[0041] A predefined interference signal pattern can be used, for example, for the initial training iteration. In subsequent training runs, the interference signal pattern can be varied by varying the activity of individual or multiple individually actuatable interference elements, for example, by lowering or increasing signal strength. Because a predefined interference signal pattern can be injected initially, training can be accelerated using an interference signal pattern that has already been classified as suitable. Furthermore, the predefined interference signal pattern can also be used unchanged throughout training.

[0042] According to a fifth aspect, the present invention relates to a method for training an artificial neural network in an arrangement according to the preceding description, preferably applied to a hardware-based artificial neural network of an apparatus after the apparatus has been trained separately outside the arrangement by a method for training an artificial neural network in an apparatus according to the preceding description.

[0043] The advantages, effects and improvements of the method for training an artificial neural network in a configuration arise from the advantages, effects and improvements of the above-described apparatus, configuration and the additional methods described above. In this respect, therefore, reference is made to the foregoing description to avoid repetition.

[0044] Using the method for training an artificial neural network within a configuration, all devices in the configuration can be matched to one another through training, improving the performance of the configuration. For this purpose, the devices in the configuration can be trained together from the beginning. Alternatively, each device can be trained individually first, so that the corresponding interfering device is not affected by the output signals of the other devices. Only in the second training run, when the devices in the configuration are matched to one another, can the interfering device be affected by the output signals of the other devices in the configuration.

[0045] In a sixth aspect, the present invention relates to a method for training an artificial neural network in a system according to the preceding description, the method for training an artificial neural network in an apparatus according to the preceding description being applied to a hardware-based artificial neural network of the apparatus, preferably after the arrangement has been separately trained outside the system by a method for training an artificial neural network in an arrangement according to the preceding description.

[0046] The advantages, effects and improvements of the method for training an artificial neural network in a system arise from the advantages, effects and improvements of the apparatus, arrangements, systems and other methods described above, and in this respect therefore, to avoid repetition, reference is made to the foregoing description.

[0047] In a method for training an artificial neural network in a system, different configurations of the system are coordinated with each other. In this case, the configurations can be initially trained separately without the devices of the other configurations affecting the interfering signal devices. Furthermore, in this case, before training the configuration, the devices of the configuration can be trained separately from each other without the other devices affecting the interfering devices. Alternatively, the configurations and the devices they contain can be matched with each other in a single training of the system, and the output signals of the configurations can affect the interfering devices of the other configurations. [Brief explanation of the drawings]

[0048] In the following, the invention will be explained by means of exemplary embodiments with reference to the accompanying drawings.

[0049] [Figure 1A] A schematic diagram of the apparatus is shown. [Figure 1B] A schematic diagram of the apparatus is shown. [Figure 2A] 1A and 1B show a schematic diagram of the device according to the invention in more detail. [Figure 2B] 1A and 1B show a schematic diagram of the device according to the invention in more detail. [Figure 3] 1 shows a schematic diagram of an example of a device with an FPGA chip. [Figure 4A] 4 shows a schematic diagram of a further embodiment of the example of FIG. 3. [Figure 4B] 4 shows a schematic diagram of a further embodiment of the example of FIG. 3. [Figure 5] 1 shows a schematic diagram of an example of an apparatus with two interference devices. [Figure 6] A schematic diagram of the basic structure of an FPGA chip is shown. [Figure 7] 1 shows a schematic diagram of an example of a device with a capacitive interference element. [Figure 8] 1 shows a schematic diagram of an example of a device with heating and cooling interference elements. [Figure 9] 1 shows a schematic diagram of an example of a device with a heated interference element. [Figure 10] 1 shows a schematic diagram of an example of a device with a sound-generating interference element. [Figure 11] 1 shows a schematic diagram of an example of a device with an interference element that emits electromagnetic radiation; [Figure 12] 1 shows a schematic diagram of an example of an apparatus with a pattern-generating interference signal device. [Figure 13] 1 shows a schematic diagram of a configuration involving multiple devices. [Figure 14] 1 shows a schematic diagram of a system with multiple configurations. [Figure 15] 10 shows a schematic diagram of a further example of a system for alternative modes of presentation; [Figure 16] 1 shows a schematic diagram of an example having multiple systems networked together via interference devices. [Figure 17] 10 shows a schematic diagram of a further example of the configuration of the device. [Figure 18] 1 shows a flowchart of a method for training an artificial neural network in a system. DETAILED DESCRIPTION OF THE INVENTION

[0050] 1A and 1B illustrate an apparatus, described in more detail below, with 1A showing a spatial configuration and 1B showing a cross-sectional view of the essential components of the apparatus. This example shows an FPGA chip on a control circuit board 13, whose individual components are configured and trained via an evolutionary learning process to link and form a hardware-based artificial neural network 11. This layer of the hardware-based artificial neural network 11 roughly corresponds to industrially available chip-based systems and activation mechanisms described in the prior art.

[0051] In the following, the term "FPGA" is used to represent any freely configurable electronic semiconductor chip. At a distance d, specified in more detail in the following examples, a further layer, optionally with an array-like structure, is arranged as an interference device 12, the elements of which are shown here as small spheres and can be switched on / off or adjusted in a controlled manner as interference elements. Actuation elements are not shown here.

[0052] This layer of the interference device 12 can generate interference signals in a pattern, referred to as the "interference signal layer." The interference signal layer, or elements thereof, can generate interference signals that are locally cross-coupled to at least one region of the hardware-based artificial neural network 11 via a space that is part of the coupling device 15, and the interference signal is injected into the entire region. This region thus corresponds to the region of the hardware-based artificial neural network 11 that is covered by the interference signal. The region can cover the entire network, i.e., the interference signal can be injected into the entire network. This can be done uniformly. Furthermore, for example, if multiple regions are provided, the range of the region can be assigned to a group of individual components of the FPGA, individual individual components, or only sub-regions of individual components.

[0053] Suitable interference signal array components can be miniature heating or cooling elements, optical, acoustic, resistive, electromagnetic, capacitive, mechanical, or even quantum mechanical components—anything that can be injected into an electronic circuit such as that implemented in a layer of a hardware-based artificial neural network 11 is applicable.

[0054] Through the coupling device 15, hereafter also referred to as the "coupling space," the signals generated by the interference device 12 can be cross-coupled to the layers of the hardware-based artificial neural network 11 in a pattern. Corresponding to the elements of the layers of the interference device 12, the coupling device 15 can be, for example, a medium mediating thermal, resistive, electromagnetic, capacitive, mechanical, or even quantum mechanical signal transmission. In the simplest case, it can be a homogeneous medium, such as a gas, liquid, or solid. However, in principle, the medium can comprise a combination of different materials structured vertically and / or horizontally to achieve localized effects in the direction of the layers of the hardware-based artificial neural network 11 and to match their array structure. That is, the medium of the coupling device 15 can be adapted to suit the configuration of the linkable elements of the FPGA chip, i.e., the hardware-based artificial neural network. The distance d can also be varied but is usually selected to be small compared to the surface area of ​​the layers of the hardware-based artificial neural network 11, in order to generate localized effects within the hardware-based artificial neural network 11, especially within the FPGA chip.

[0055] In contrast to the conventional use of semiconductor chips and semiconductor components, the components mounted in the layers of the hardware-based artificial neural network 11 may be partially, but not completely, shielded from external influences, whereby injection is possible only from the layers of the interference device 12.

[0056] Therefore, due to the increased sensitivity of the components of the hardware-based artificial neural network 11 to external signals, the encapsulation of the device can serve as a shielding device 14 against these very interfering signals.

[0057] In this basic configuration of the hardware-based artificial neural network 11 according to the present invention, the main components of the evolutionary learning process are the layers of the hardware-based artificial neural network 11. The layers of the interference devices 12 form higher-level but subordinate components, making this process in the layers of the hardware-based artificial neural network 11 more complex and capable of being optimized through its own evolutionary algorithm or a second evolutionary algorithm and learning process. The whole of the units 11-15 can be understood and referred to as an intelligent hardware AI system and can be called an AI basic unit.

[0058] The training process can be carried out in two variations: in the first option, the hardware-based artificial neural network 11 and the interfering device 12 can be modified simultaneously in an evolutionary process; in the second option, only the hardware-based artificial neural network 11 can be trained first, and if this training gives good results, the interfering device 12 can be added. If the apparatus comprises several hardware-based artificial neural networks 11 and several interfering devices 12, any combination can be subjected to individual and joint training according to the first or second option.

[0059] In contrast to prior art systems, by avoiding undefined interference effects, a defined separation of interfering signals by the interfering device 12 and the coupling device, highly complex systems become feasible and controllable, increasing the likelihood of achieving good training results.

[0060] Figures 2A and 2B show examples illustrating spatial relationships, with Figure 2A showing a three-dimensional exploded view and Figure 2B showing a cross section along line SS in Figure 2A.

[0061] The FPGA chip 24, on which the hardware-based artificial neural network is implemented, may be placed on a board 21 (e.g., a multi-layer PCB) for activating and configuring the FPGA via terminals 26. Configuration may be performed via a digital computer. The FPGA 24 may not be encapsulated in a shielded state, but instead be covered with a coupling medium 23 of a coupling device, followed by an interference device 22, shown here in the form of a checkerboard array with individual interference elements for locally generating an interference signal for the FPGA. The interference device 22 is then connected via terminals 27 to a board 25 for activating the interference elements. In the simplest case, any pattern can be generated by switching on and off the interference elements of the interference device, which locally act on the FPGA chip 24 via the coupling medium 23.

[0062] Regarding the distance d in FIG. 1A, in this example, it is small compared to the surface area of ​​the FPGA chip 24. Typically, the distance is between 0.1 mm and 5 mm, but preferably 0.5 mm. The geometric relationship can be seen in the cross section SS in FIG. 2B.

[0063] By way of example, the array of interference devices 22 can consist of small heating or Peltier elements, which can be structured over a medium 23 with high thermal conductivity, for example a metal or diamond layer. This layer can be configured as an array of columns with good and bad thermal conductivity, and the temperature pattern can be transferred to an FPGA, which can generate variable, trainable, and switchable interference signal patterns.

[0064] The first structuring degree of the interference device, which is a measure of the structuring of the distribution of interference elements, can be adapted to match the structuring of the FPGA, which in this example can be specified with a second structuring degree, i.e., can be selected to be geometrically similar. Next, in each region where the interference device injects an interference signal into the hardware-based artificial neural network implemented in the FPGA, a basic element of the FPGA is placed. In other words, one basic element of the FPGA is operated by each interference element.

[0065] However, this is not necessary, since the first degree of structuring can be equally well structured whether it is finer or coarser than the second degree of structuring, and it is preferred that the ratio between the first degree of structuring and the second degree of structuring has a value in the range of 10:1 for finer structuring and 0.1:1 for coarser structuring.

[0066] The bonding medium 23 of the bonding device can have a structuring designated by a third degree of structuring, which can also be finer or coarser than the second degree of structuring.

[0067] Figure 3 shows a compact technical configuration of the device described in Figures 1A and 1B. A semiconductor chip holder 31, e.g., ceramic with multiple contact pads, can be arranged on which an FPGA chip 32 with linkable electronic basic components 33 can be placed. Furthermore, a coupling medium 34 and an interference device 35 with an array of interference elements can be placed directly on top of it.

[0068] The entire chip can then be encapsulated 36 to shield it from external influences. In the case of electromagnetic elements in an interference device, this can be, for example, a metal encapsulation, and in the case of optical interference signals, it can be an opaque coating.

[0069] This compact chip design allows such chips to be combined on a single board to form complex structures or even stacks, as explained in the example below: This kind of chip can be used to assemble multiple AI basic units and combine them into layers and hierarchies.

[0070] 4A and 4B show schematic diagrams of exemplary combinations of compact chip systems. FIG. 4A shows the device as the AI ​​basic unit of FIG. 3, comprising an FPGA 41, a coupling medium 43 of the coupling device, and an interferometric device 42 with electrical contact pads 44. The thickness of the coupling medium can vary between 100 μm and 5 mm, preferably between 200 μm and 600 μm. Furthermore, the coupling medium can have multiple coupling elements, which can be structured or unstructured according to a third structuring degree. Structuring of the coupling medium is provided, particularly for use with signal patterns.

[0071] In Figure 4B, two devices are shown combined together. The combination of the two devices includes two FPGAs 41, which are connected to a common interference device 42 via two coupling media 43. The FPGAs are positioned head-to-head.

[0072] In a similar manner, further combinations can be realized as horizontal or vertical stacks. The advantage of using a common interferometric device for multiple FPGAs is that it reduces operational complexity.

[0073] Furthermore, during training by the FPGA, interference signal patterns can be generated that are either fixed in advance or optimized by evolutionary-based methods. Such a system also has the advantage that the upper and lower FPGAs can be exposed to different interference signal patterns in a time-separated sequence or alternating, resulting in more complex training and a more complex AI system without the need for complex switching.

[0074] Figure 5 shows a further variation, in which an FPGA 51 is placed between two coupling media 53a and 53b and two interference signal layers 52a and 52b, which provides multiple options for injecting interference signals in well-defined situations, albeit with increased device complexity.

[0075] For example, the central FPGA chip can be symmetrically injected with the same interference signal pattern from above and below. Alternatively, for example, the FPGA chips can be asymmetrically injected with the same or different interference signal patterns. Another alternative, for example, can be time-separated injections from above and below. Furthermore, for example, asymmetric interference signals can be injected alternately from above and below.

[0076] The basic principles and structure of an FPGA chip array are shown schematically in Figure 6. Because FPGAs are typically structured as an array, the representation of rows 1 to m and columns 1 to n was chosen for clarity.

[0077] Electronic elementary elements, whose positions can be identified by indices 11, 12, [...], m5, mn, can be connected to each other in a short-circuit-proof configuration via four connections A, B, C, D in each case to form a hardware-based artificial neural network, in which even incorrect wiring connections are permitted, for example, using the output of an element as an input.

[0078] As an example, elements of an FPGA can be digital or analog, as shown by the basic elements in positions 11-15 of the top row of the illustrated array. The symbols used correspond to electronic nomenclature. Analog and digital devices can be mixed. Electronic elements mn are not shielded from interference in the usual way, but may even have assemblies that are sensitive to optical, acoustic, thermal, electromagnetic, and other signals generated by interfering devices. The types of configurations used in training and evolutionary programs are conventional and will not be described in detail here.

[0079] In FIG. 7, three layers of the apparatus (hardware-based artificial neural network, coupling device, and interference device) are shown with capacitive interference.

[0080] In this example, the FPGA 71, as a hardware-based artificial neural network, has a second degree of structuring that is finer than the first and third degrees of structuring of the interference signal device 72 and the coupling device 73. The structuring of the FPGA, the interference device, and the coupling device can be of the same or different types. Therefore, it is possible to operate not only a single basic element of the FPGA, but also a group of basic elements simultaneously, or even only a sub-region of the basic elements.

[0081] The interference device 72 may, for example, comprise small metal plates or pads 72a as interference elements, embedded in an electrically insulating medium 72b. Each pad 72a can be activated by a computer program, similar to the operation of an FPGA. In the simplest example, as shown in 74, three assignments of each pad are possible: 1. application of a positive or negative voltage Ux; 2. open pad, i.e., no potential connection, where the pad seeks its potential in the chip environment itself; and 3. ground connection, allowing any charge pattern to be generated in the array.

[0082] In the example shown, the coupling devices 73 are structured in the same way, so that beneath each metal pad there is placed a high-permittivity material 73a embedded in a low-permittivity medium 73b as a coupling element. At the surface of the FPGA 71, the metal pads form local capacitors through which displacement currents can be injected into locally adjacent regions of the hardware-based artificial neural network.

[0083] In the evolutionary training process, the assignment of interference elements 72a can be changed via an evolutionary algorithm, similar to training a hardware-based artificial neural network. This means that a random assignment of input signals can first be generated and applied to the interference device 72. The input signals can then be received by an artificial neural network implemented in an FPGA. If this is correctly interpreted by the neural network at the output, the configuration of the interference device 72 remains unchanged, and the next training signal is applied to the FPGA. If the input signals are interpreted incorrectly, the assignment of some pads or interference elements is randomly changed, similar to switching connections in an FPGA. Both algorithms can be consistent, but do not have to be. This can be repeated hundreds to thousands of times (sometimes referred to as "generations" in evolutionary algorithms) to achieve the desired success rate for the entire device.

[0084] Figure 8 shows a three-layer AI chip that can generate interference signals via an array of heating and / or Peltier elements 82, which in this example represent interference elements. Temperature can be transferred from the interference elements to local elementary elements in an FPGA 81 via a coupling device 83. The elementary elements arranged as an array in FPGA locations 11-mn can be fabricated as temperature-sensitive elements according to standard semiconductor fabrication methods, or they can be designed so that they react in terms of signal behavior to small temperature differences, such as a few degrees or fractions thereof.

[0085] The coupling device 83 in this example also consists of two components: a cylinder region 83a with high thermal conductivity and a region 83b with low thermal conductivity between them. The material 83a can be a metal, such as copper or silver, or a diamond layer processed by semiconductor technology. The insulating material 83b can be a plastic material, glass, or even a ceramic material with low thermal conductivity.

[0086] The interference device 82 in this example can have multiple heating and / or cooling elements, such as small resistive elements or Peltier elements, as interference elements. In this way, any temperature pattern can be transferred to the underlying FPGA. The temperature difference can be selected within a wide range, for example, from -20°C to 100°C, but is preferably close to or below room temperature.

[0087] The structure of this AI basic unit is shown in vertical cross section SS in box 85 shown in the upper center of Figure 8. Again, the array structures of interference devices, coupling devices, and neural network layers do not need to match, i.e., the number of interference elements and coupling elements can, but does not necessarily, correspond to the number of basic electronic elements.

[0088] The generated temperature patterns are typically static, i.e., they remain constant for the operating cycle of the neural network corresponding to the decision run. However, it is also possible to generate dynamic changes over multiple decision runs of the FPGA.

[0089] The training procedure is similar to that described in FIG.

[0090] An apparatus with an interference device having only a heating element is shown in Figure 9. Otherwise, this example is configured similarly to that described in Figures 7 and 8.

[0091] 10 shows an interference device 102 having miniature acoustic transmitters as interference elements that emit acoustic signals at different frequencies, for example via vibrations. The acoustic transmitters can be piezoelectric elements, piezoelectric crystals, or miniature diaphragms that generate individually activated acoustic patterns.

[0092] In this example, the coupling device 103 may comprise an acoustic transmission area 103a (e.g., a mechanical solid-state coupling or a miniature sonotrode) and an acoustic attenuating intermediate space 103b (e.g., a sound-absorbing material, e.g., a material with very small cavities).

[0093] The FPGA 101 basic elements can be designed to be perturbed to some degree via acoustic frequencies. For example, if the FPGA basic electronic elements have an acoustic receiver component, the effect can be designed to be enhanced and more complex. This may apply to some or all of the FPGA basic elements. The advantage of using acoustics is their wide frequency range, which ranges from infrasonic frequencies through the human audible range to ultrasonic frequencies. This allows for the generation of acoustic patterns at not only one frequency, but also different frequencies.

[0094] This example graphically illustrates the expanding range of possibilities associated with introducing interference and coupling devices into a hardware-based artificial neural network. In interconnected configurations and systems, as illustrated in the following diagrams, each of these interference devices can vary in intensity as a fixed acoustic pattern, shift in frequency as a whole, change its frequency composition / spectrum, vary as a pattern, or operate in a combination of the above options.

[0095] Assuming the entire system of hardware-based artificial neural networks, interfering devices, and coupling devices is optimized for a specific frequency pattern and achieves its highest success rate with this operating pattern, modifying / detuning the interfering signal will lead to worse results. In extreme cases, the neural network will only function at specific intensity or frequency intervals. This means that for devices previously operating in a suboptimal manner, the interfering signal alone can be used to worsen or improve the device. This opens up the option of interconnecting many devices hierarchically or even non-hierarchically, which can potentially affect the success rate of the neural network and, therefore, other hardware-based artificial neural networks connected to it.

[0096] 11 shows an FPGA 111 equipped with an artificial neural network of the type already described. In this example, the interference device 112 can have as an interference element a small transmitter for high frequency electromagnetic waves up to the microwave range, which transmitter can be designed for example like an antenna, or it can transmit its signal to the FPGA via the coupling device 113 by means of a waveguide 113a as a coupling element.

[0097] Similarly, the interference device could have an infrared element or a visible or UV LED as the interference element. Furthermore, injection could be performed via an optical fiber or a small pinhole as the coupling element. As with Figure 10, this device allows for a very wide range of operation and training types.

[0098] FIG. 12 shows an alternative arrangement involving an interference device capable of generating an interference signal only in a pattern. For this purpose, the coupling device 123 may have two or more layers 123a, 123b, in which, for example, alternating transparent and opaque concentric rings are applied as a pattern, with the centers of the concentric rings of the two layers shifted relative to each other. This results in a symmetrical or asymmetrical superposition pattern. The interference device 122 may also comprise an array of light-emitting diodes. In this case, the coupling device 123 is not an array as in the previous example. Instead, the superposition pattern may define the pattern formed by the interference signal in a neural network. The FPGA chip 121 may have, for example, light-sensitive components in its electronic basic elements.

[0099] Figure 13 shows the configuration of the device as an ensemble of AI basic units corresponding to Figures 3 to 5. The FPGA chip 131 can be electrically connected to a control circuit board 135, and the interference device 132 can be electrically connected to the underside of the control circuit board 136, which is shown upside down and transparent. The coupling device 133 is located between them.

[0100] Via first actuation 139 to FPGA 131 on control circuit board 135 and second actuation 140 to interference device 132 on control circuit board 136, AI basic units 134 can be trained individually and / or jointly as previously described. If each AI basic unit 134 is trained on a different group of features, e.g., one to recognize cats, a second to recognize dogs, a third to recognize horses, etc., the configuration of Figure 13 forms a more complex AI system with higher performance / intelligence than the AI ​​basic units exhibit as individual devices.

[0101] The interference devices may also be partially electrically connected to one another as shown schematically via dashed lines 137, 138. This provides further options for overall configuration control and evolutionary training.

[0102] These connections can be used to transmit signals between interference devices 132, which can permanently change the performance of other AI elementary units, e.g., by simply injecting an interference signal into each AI elementary unit to manipulate the corresponding artificial neural network in the FPGA, as previously described. This can be done, for example, by increasing or decreasing the strength of the interference signal of the connected AI elementary unit. This means that each AI elementary unit can operate in an improved or optimal manner, such as in the device connected via dashed connection line 138, or can be detuned and degraded or switched off, such as in the device connected via connection line 137. For example, in the animal recognition example above, if half of the AI ​​elementary units can recognize animals and the other half can recognize artwork that resembles animals, such interconnections can ensure that many AI elementary units are initially controlled in a suboptimal range by the detuning of their respective interference devices, operating at, for example, 80% of their maximum performance. When an input signal (e.g., an image of a mule) is provided to the device, each AI elementary unit will classify this input signal differently.

[0103] A device capable of recognizing cats may, for example, output a 2% match rate between mules and cats, a device capable of recognizing horses may, for example, output a 90% match rate, and a device capable of recognizing art may respond with a detection range of, for example, a few percent to 60% for horse sculptures. The AI ​​base unit with the highest match rate (in this case, the device capable of recognizing horses) can switch its interference device to optimal operation. Furthermore, previously detuned interference devices of connected AI base units can also simultaneously switch to optimal interference signal mode, for example, one AI base unit for detecting wild horses, one for detecting zebras, and one for detecting equine hybrids. At the same time, through its connection to the device capable of recognizing art, it can suppress all but the device with the highest hit rate. This device with the highest hit rate in detecting art can optimally adjust its interference device and activate additional devices capable of detecting art through its connection.

[0104] This allows new iterations of the mule image to be initiated until it is determined which object in the entire system the mule comes closest to, be it an animal or an artwork.

[0105] Such a configuration has one more training layer than the AI ​​basic units, i.e., a layer of interconnection between devices, which can also be achieved through evolutionary optimization strategies.

[0106] Using multiple (at least two) configurations according to Figure 13, a complex system can be constructed, organized hierarchically or otherwise, as shown in Figure 14. While a base layer 141 with any number of AI basic units is shown, for clarity, Figure 14 shows only four devices, referenced a1-a4, which can be interconnected and activated or suppressed via electrical connections 143 between associated interference devices. In this layer, an input signal 144 can be input to all AI basic units a1-a4, for example, by connecting the device inputs in parallel.

[0107] The AI ​​basic unit with the highest recognition probability can be cross-coupled to the next higher layer 142, where an input signal 144 can now be applied to all AI basic units; for clarity, only two devices b1 and b2 are shown in layer 142, but these devices can also be partially or fully interconnected via electrical connections 143 between interfering devices. At this layer, the AI ​​basic unit with the highest recognition probability can also be determined, which can then generate an output signal 147.

[0108] Typically, the number of AI basic units can be greatest in the lowest layer and decrease toward higher layers. However, this is not required. At each layer, expanded decision categories or new links can also be created. For example, after an object is recognized, patterns can be compared in higher-level layers, and acoustic signals can be added in the next layer to reveal discrepancies that would otherwise lead to misclassification. For example, an object recognized as a cat may neigh like a horse. Such a system can have larger AI basic units in higher layers than in lower layers.

[0109] The left side of Figure 15 shows a system with a hierarchical AI structure, which consists of three layers 151, 152, 153 with inputs 154 and outputs 155, similar to Figure 14. Such complex AI interconnections are grouped below as cylinders 156 with inputs 154 and outputs 155, as shown on the right side of Figure 15, to allow for more complex structures to be represented.

[0110] Figure 16 shows a schematic representation of a more complex structure. It consists of several systems according to Figure 15, shown as cylinders 164-166. They can be oriented in layers in the same direction, but for clarity, only cylinder 164 is shown, by way of example, with inputs 161 pointing downwards and outputs 169 pointing upwards.

[0111] Systems can be arranged in domains marked with specific patterns on top of the corresponding cylinder, one pattern marking each system in the domain.

[0112] Figure 16 shows three domains that can be made up of three system types 164, 165, and 166. As can be seen in system type 166, not all systems within a domain need to be directly adjacent. Individual systems can also be located as standalone units in separate domains (not shown here). In this way, strong and weak interactions between domains can be achieved via interference devices.

[0113] Systems within a domain may receive a common input signal. Suitably, the domains may be configured so that each domain receives a different or modified input signal (e.g., a portion of the common input signal shown in Figure 16 at 161, 162, and 163).

[0114] There can be reciprocal or directed connections between systems, through which systems can stimulate or inhibit, and stimulate or inhibit, other systems. These connections typically start from the top layer, the result layer (see Figure 15). When input signals 161-163 are applied, individual systems can arrive at more complex responses faster, with different recognition probabilities than if these connections were not present.

[0115] Similar to the operation of the individual systems in Figures 14 and 15, systems within and outside the domain can be strengthened and weakened. Connections to other domains can easily be very far away, as shown, for example, by the connecting arrow from system 164a to system 164b, allowing larger system ensembles to control their activity via interference devices. These system ensembles have further layers of training in addition to those already described above.

[0116] Systems with the highest hit rate in a domain can be interconnected via the switching layer 167, and their results sent to the projection layer 168, where the results of other domains with high hit rates and the input signal can be input and displayed for comparison.

[0117] This configuration allows for the implementation of, for example, the chaos-like structures suspected to exist in the human brain. Systems correspond to the columnar structures of the cerebral cortex, and domains correspond, for example, to the visual, auditory, tactile, or olfactory cortex. Through interconnections between systems and domains, association-like modes can be created and trained, ultimately representing associations between phenomena that are not actually related to each other, such as the implementation of optical patterns in music. As can be seen, by using underlying devices, such as FPGAs with interferometric devices, interconnecting and manipulating them via the interferometric devices, linking the devices to form configurations, aggregating them into systems, and then arranging the systems into layers and domains, an overall AI system can be created, which can be made universally intelligent by running multiple evolutionary training cycles sequentially and / or simultaneously. The more extensive the system, the more complex the training structure can be.

[0118] 17A-17D show an alternative arrangement. When the interference device 172 is not located near the FPGA 171 and the interference signal is injected into multiple FPGAs in the same or similar manner, but more broadly rather than in a finer pattern than in FIGS. 1-16, the arrangement can include multiple FPGAs 171 and control circuit boards arranged in a square around a common interference device 172, which can be configured as a column, as in FIG. 17A. A group of four such FPGAs 171, or as many as eight (only seven are shown for clarity), can form an AI basic unit in conjunction with the interference device 172 and intervening coupling device 173.

[0119] Figures 17B-17D show further examples of devices in plan view, where in Figure 17B the FPGAs of the device are arranged in a triangular configuration, and in Figure 17C they are arranged in a hexagonal configuration.

[0120] FIG. 17D shows an arrangement in which FPGAs, and thus hardware-based artificial neural networks, are arranged in a rectangular chain system. The coupling medium of the coupling device 173 can be a gas or material that easily transmits the respective interference signals to the FPGA chip. Typically, it can be uniformly formed from the interference signal train 172 due to the width effect. Alternatively, it can comprise layers or other types of configurations of highly and less transparent materials. Other groupings can be implemented in a similar manner. What all of these have in common is that they can be combined into more complex configurations, systems, and ensembles, such as those described in FIGS. 13-16.

[0121] 18 shows a flow chart illustrating a method for training a system according to the foregoing description, which begins with a method 180 for training an artificial neural network in an apparatus according to the foregoing description. The apparatus of the system may be trained first.

[0122] In a first optional step 187 of method 180, the hardware-based artificial neural network of the device can be initially trained without the injection of an interfering signal. In this step, the hardware-based artificial neural network is trained to preliminary performance values.

[0123] A further step 181 can define target output data representing the desired results of processing the supplied training data by the hardware-based artificial neural network. This step can be performed at any time before the subsequent steps, and can also be performed simultaneously with or before optional step 187.

[0124] Furthermore, in step 182, the supplied training data can be used to train the hardware-based artificial neural network. To this end, the training data is input to an input layer of the neural network, and an interference device injects an interference signal into at least one region of the hardware-based artificial neural network. In this process, a portion of the nodes of the hardware-based artificial neural network, all of the nodes, or multiple nodes can be placed in at least one region.

[0125] In a further step 183, the output data of the hardware-based artificial neural network is obtained. Because the network is hardware-based, the training data is processed simultaneously by all nodes in the network layer, so that the output data is available within a few milliseconds.

[0126] Thereafter, in step 184, the deviation between the output data and the target output data is determined. If the deviation is outside a predefined tolerance, for example, if the deviation is greater than 1%, the hardware-based artificial neural network is reconfigured. At least one interfering signal can also optionally be modified. If multiple interfering signals are used, it is sufficient to modify a single interfering signal, for example, by activating an interfering element of an interfering device.

[0127] Steps 182-184 are repeated with the modified hardware-based artificial neural network and possibly the modified interference signal as inputs.

[0128] If the deviation is within the predefined tolerance, the training of the device ends at step 185 .

[0129] Once all devices have been trained with the method 180, a configuration of devices can be trained 188 with a further method. For this purpose, devices of the configuration that are coupled to each other via an interference device are trained according to steps 182 to 186. However, this does not exclude the possibility of training a configuration without previously performing the aforementioned method on the devices.

[0130] Training the configuration may proceed in a manner similar to method 180, with at least some of the interfering devices potentially being influenced or controlled by hardware-based artificial neural networks of other devices.

[0131] When all configurations of the system have been trained using method 188, the system can be trained according to method 189. For this purpose, devices or configurations of the system that are coupled to each other via interference devices are trained according to steps 182 to 186. However, this does not exclude the possibility of training the system without previously performing the aforementioned method on the configurations or devices.

[0132] Furthermore, the ensemble can be trained by first training the system as described above and then training the entire ensemble, although this does not exclude the possibility of training the ensemble without pre-training the system, configuration, and / or device.

[0133] The above examples do not limit the invention in any way. On the contrary, the invention can be modified in many ways. All of the above-mentioned features of the invention, either alone or in combination with each other, can be essential to the invention.

Claims

1. An apparatus for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network (11, 24, 32, 41, 51, 71, 81, 101, 111, 121, 131, 171) in which modifiable electronic elements are linked together to form an artificial neural network, wherein the apparatus comprises at least one interference device for injecting at least one interference signal into at least one region of the hardware-based artificial neural network ( An apparatus comprising (12, 22, 35, 42, 52a, 52b, 72, 82, 102, 112, 122, 132, 172) and at least one coupling device (15, 23, 34, 43, 53a, 53b, 73, 83, 103, 113, 123, 133, 173), wherein the coupling device is positioned between the interference device and the hardware-based artificial neural network and is designed to transmit the at least one interference signal from the interference device across the at least one region.

2. The apparatus according to claim 1, wherein the hardware-based artificial neural network in the at least one region has at least one component designed to reduce the signal-to-noise ratio upon receiving the at least one interference signal, and the interference device preferably generates optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization interference signals.

3. The apparatus according to claim 1 or 2, wherein the interference device has a plurality of individually operable interference elements (72a) for injecting interference signals into the hardware-based artificial neural network, the interference elements preferably inject interference signals into different regions of the hardware-based artificial neural network.

4. The apparatus according to claim 3, wherein the plurality of interference elements are preferably arranged in the form of an array and distributed throughout the layer, and the coupling device comprises a medium having a plurality of coupling elements (73a, 83a, 103a, 113a) for transmitting the at least one interference signal to the at least one region, the coupling elements being distributed within the layer in the same manner as the interference elements.

5. The apparatus according to claim 1, wherein the at least one region is designed to have a range corresponding to the size of the hardware-based artificial neural network or to be smaller than the size of the hardware-based artificial neural network.

6. The apparatus according to claim 1, wherein the apparatus has at least one semiconductor chip, the semiconductor chip comprises the hardware-based artificial neural network, the hardware-based artificial neural network is preferably formed by an integrated circuit, more preferably by a field-programmable gate array or an application-specific integrated circuit.

7. The apparatus according to claim 1, comprising shielding devices (14, 36) for shielding external interference signals of the same type as the at least one interference signal, wherein the shielding devices surround the hardware-based artificial neural network, the coupling device, and the interference device.

8. A configuration of an apparatus according to claim 1, wherein the hardware-based artificial neural networks of the apparatus are electrically connected to each other in series and / or in parallel, preferably the interference device of at least a first apparatus among the plurality of apparatuses and the interference device of a second apparatus among the plurality of apparatuses are designed as a common interference device, and more preferably the output layer of the hardware-based artificial neural network of a third apparatus among the plurality of apparatuses is designed to control the interference device of a fourth apparatus among the plurality of apparatuses.

9. A system comprising the configurations of claim 8, wherein a first configuration of the plurality of configurations is designed to control at least one interference device in a second configuration of the plurality of configurations.

10. A method for training an artificial neural network in the apparatus described in claim 1, wherein the method (180) comprises at least the following steps: - Defining target output data during processing of supplied training data (181); - Supplying the training data to the hardware-based artificial neural network (182) and injecting at least one interference signal into the at least one region of the hardware-based artificial neural network by the at least one interference device; - Obtaining output data from the hardware-based artificial neural network (183); - Determining whether there is at least one deviation between the output data and the target output data (184), and determining that the deviation is outside a predetermined tolerance range; If the deviation is within the tolerance range: - To terminate the above method (185); If the deviation is outside the predetermined tolerance range: - Modifying the hardware-based artificial neural network (186), and preferably modifying the at least one interference signal; - Repeat steps 182-184 above. A method that includes [a certain feature].

11. The method according to claim 10, wherein the injected interference signal generates a signal-to-noise ratio of 15 dB or less, preferably 10 dB or less, and more preferably 0 dB or less in the at least one region.

12. The method according to claim 10 or 11, wherein, prior to the step of defining target output data while processing supplied training data, the hardware-based artificial neural network is trained without injecting interference signals (187).

13. The method according to claim 10, wherein the at least one interference device is at least designed as described in claim 3, and the operable plurality of the interference elements are operated such that the interference signal forms a predefined interference signal pattern on the hardware-based artificial neural network, and the plurality of training iterations of the hardware-based artificial neural network are preferably performed sequentially with different predefined interference signal patterns.

14. A method for training an artificial neural network in the configuration of claim 8, wherein the method (188) of claim 10 is applied to the hardware-based artificial neural network of the device after the device has been individually trained outside the configuration by the method (180) of claim 10.

15. A method (189) for training an artificial neural network in the system according to claim 9, wherein the method (180) according to claim 10 for training an artificial neural network in a device is preferably applied to the hardware-based artificial neural network of the device after the configuration has been individually trained outside the system by the method (188) according to claim 14 for training an artificial neural network in the configuration.

Images