In-situ adsorbate formation for dielectric etching

Abstract

1. A method for processing a substrate, the method comprising: flowing an etching gas, O2, and an adsorbate precursor into a plasma processing chamber configured to hold a substrate including a silicon-containing dielectric layer and a patterned mask layer, the etching gas comprising hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and patterning the silicon-containing dielectric layer on the substrate using the plasma, the adsorbate forming a sidewall passivation layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of the filing date of U.S. Non-Provisional Patent Application No. 17 / 937,179, filed September 30, 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates generally to methods for processing substrates, and in particular embodiments to enhancing neutral species adsorption via in-situ adsorbate formation for dielectric etching. [Background technology]

[0003] Generally, semiconductor devices, such as integrated circuits (ICs), are fabricated by sequentially depositing and patterning layers of dielectric, conductive, and semiconducting materials over a substrate to form a network of monolithically integrated electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias). Many of the processing steps used to form the constituent structures of semiconductor devices are performed using plasma processes. Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor industry has repeatedly reduced the minimum feature size of semiconductor devices to a few nanometers to increase component integration density. Accordingly, the semiconductor industry is increasingly demanding plasma processing technologies to provide processes that pattern features, often with atomic-scale dimensions, with accuracy, precision, and profile control. Meeting this challenge, along with the uniformity and repeatability required for high-volume IC production, requires further innovation in plasma processing technology. [Means for solving the problem]

[0005] According to one embodiment of the present invention, a method of processing a substrate includes flowing an etching gas, O2, and an adsorbate precursor into a plasma processing chamber configured to hold a substrate including a silicon-containing dielectric layer and a patterned mask layer, the etching gas comprising hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and patterning a silicon-containing dielectric layer on the substrate using the plasma, the adsorbate forming a sidewall passivation layer.

[0006] According to one embodiment of the present invention, a method of processing a substrate includes flowing an etchant containing hydrogen and fluorine, O, and an adsorbate precursor into a plasma processing chamber, the adsorbate precursor comprising PH, BH, Si, x H y , H2S, or NH3; generating a plasma in a plasma processing chamber while flowing an etchant, O2, and an adsorbate precursor, where the adsorbate precursor is oxidized to form an adsorbate comprising P, B, Si, S, or N; and exposing the substrate to the plasma in the plasma processing chamber to form a recess in a silicon-containing dielectric layer of the substrate, where the recess has an aspect ratio of at least 50:1, and the adsorbate forms a sidewall passivation layer in the recess.

[0007] According to one embodiment of the present invention, a method of processing a substrate includes depositing an organic layer on a silicon-containing dielectric layer of the substrate, patterning the organic layer by a halogen-free plasma etching process, and patterning the silicon-containing dielectric layer by a halogen-based plasma etching process using the patterned organic layer as an etch mask, the halogen-based plasma etching process including generating a halogen-containing plasma from a gas mixture including a halogen-containing etching gas in a plasma processing chamber, and flowing O and an adsorbate precursor into the plasma processing chamber, the adsorbate precursor including PH, BH, Si, and / or HCl. x H y , H2S, or NH3, wherein the adsorbate precursor is oxidized under a halogen-containing plasma to form an adsorbate comprising P, B, Si, S, or N; and forming a recess in a silicon-containing dielectric layer of the substrate by exposing the substrate to the halogen-containing plasma in a plasma processing chamber, wherein the recess has an aspect ratio of at least 50:1 and the adsorbate forms a sidewall passivation layer in the recess.

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figures 1A-1C] 1A and 1B illustrate cross-sectional views of a substrate during an exemplary process of semiconductor manufacturing, including a plasma etching process for forming high aspect ratio (HAR) features on the substrate, according to various embodiments, where FIG. 1A shows an incoming substrate including a dielectric layer and a patterned hard mask layer, FIG. 1B shows the substrate during formation of HAR features by the plasma etching process, and FIG. 1C shows the substrate after completing the plasma etching process. [Figure 2A-2B]2A and 2B show cross-sectional views of a substrate during a plasma etching process, where FIG. 2A shows the substrate with etchant species causing lateral etching and FIG. 2B shows the substrate with a passivation layer preventing lateral etching. [Figure 3A-3C] 3A and 3B show schematic surface structures with various adsorbates on silicon oxide, where FIG. 3A shows H3PO4 adsorption, FIG. 3B shows HF adsorption, and FIG. 3C shows HF-H3PO4 co-adsorption. [Figures 4A-4C] 4A illustrates a process flow diagram of a semiconductor manufacturing method including a plasma etching process for forming HAR features, according to various embodiments, where FIG. 4A illustrates one embodiment, FIG. 4B illustrates an alternative embodiment, and FIG. 4C illustrates yet another embodiment. [Figure 5] 1 illustrates a plasma system for performing semiconductor manufacturing processes, according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010] This application relates to the fabrication of semiconductor devices, e.g., integrated circuits including semiconductor devices, and more specifically, high-capacity three-dimensional (3D) memory devices such as 3D-NAND (or vertical NAND), 3D-NOR, or dynamic random access memory (DRAM) devices. Fabrication of such devices may generally require forming conformal high-aspect-ratio (HAR) features of circuit elements (e.g., contact holes). Features having an aspect ratio (the ratio of the feature height to the feature width) greater than 50:1 are generally considered high-aspect-ratio features, and in some cases, fabricating higher aspect ratios, such as 100:1, may be desirable for advanced 3D semiconductor devices. In such applications, HAR features may be formed in dielectric layers (e.g., silicon oxide, silicon nitride, or oxide / nitride layer stacks) by highly anisotropic plasma etching processes with high fidelity. However, conventional HAR etching methods may typically involve tens, sometimes hundreds, of processing steps, complicating process optimization and etching throughput. Therefore, a simple yet effective HAR process may be desirable. Embodiments of the present application disclose a method for fabricating HAR features through a plasma etching process based on the combination of halogen-based etch chemistries and in-situ neutral adsorbate formation. The method can advantageously enhance the etch rate by increasing the amount of neutral species in the plasma. Furthermore, the neutral adsorbates may also provide sidewall passivation, improving the anisotropy of the plasma etch process. The inventors of the present disclosure have also determined that coadsorption of two adsorbates (e.g., HF and H3PO4) may be thermodynamically favorable, which may advantageously benefit the effect of neutral species on etch rate and sidewall passivation. While some adsorbate species (e.g., HO) may require low temperatures (e.g., below −50° C.) for effective sidewall passivation, the present method, in various embodiments, may be advantageously applied for in-situ adsorbate formation of species (e.g., H3PO4) that do not require such low temperatures. As a result, the methods disclosed herein may enable new, cost-effective HAR dielectric etch processes.In various embodiments, the present methods allow for the in-situ formation of non-volatile adsorbate species by flowing an adsorbate precursor (e.g., PH) and an oxidant (e.g., O) into a plasma processing chamber. In certain embodiments, other types of adsorbates containing other elements, such as B, S, Si, and / or N, may also be used.

[0011] An exemplary plasma etching process for forming high aspect ratio (HAR) features according to various embodiments will now be described with reference to FIGS. 1A-1C. The effect of sidewall passivation by a passivation layer will then be described with reference to FIGS. 2A-2B. Subsequently, different modes of adsorption will be compared in terms of simulated adsorption energies in FIGS. 3A-3C. An exemplary process flow diagram will then be shown in FIGS. 4A-4C. FIG. 5 provides an exemplary capacitively coupled plasma (CCP) system for carrying out semiconductor fabrication processes according to various embodiments. All figures are for illustrative purposes only and are not drawn to scale, including the aspect ratios of the features.

[0012] 1A-1C illustrate cross-sectional views of a substrate 100 during an exemplary process of semiconductor manufacturing, including a plasma etching process for forming HAR features on the substrate, according to various embodiments.

[0013] FIG. 1A shows an incoming substrate 100 that includes a dielectric layer 110 and a patterned hardmask layer 120 .

[0014] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In particular embodiments, the substrate may include silicon germanium wafers, silicon carbide wafers, gallium arsenide wafers, gallium nitride wafers, and other compound semiconductors. In other embodiments, the substrate includes heterogeneous layers, such as layers of silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, and silicon on silicon or SOI substrates.

[0015] In various embodiments, substrate 100 may be part of a semiconductor device and may have undergone several steps of processing, such as following conventional processing. For example, a semiconductor structure may include substrate 100 in which various device regions have been formed. At this stage, substrate 100 may include isolation regions, such as shallow trench isolation (STI) regions, and other regions formed therein.

[0016] A dielectric layer 110 may be formed over the substrate 100. In various embodiments, the dielectric layer 110 is a target layer to be patterned into one or more high aspect ratio (HAR) features. In certain embodiments, the HAR features being etched into the dielectric layer 110 may be contact holes, slits, or other suitable structures, including recesses. In certain embodiments, the dielectric layer 110 may be a silicon oxide layer. In alternative embodiments, the dielectric layer 110 may comprise silicon nitride, silicon oxynitride, or an O / N / O / N layer stack (stacked layers of oxide and nitride). The dielectric layer 110 may be deposited using any suitable technique, such as vapor deposition, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes, such as plasma-enhanced CVD (PECVD) and other processes. In one embodiment, the dielectric layer 110 has a thickness of 1 μm to 10 μm. In another embodiment, the dielectric layer 110 may include a layer stack, with each layer of the stack having a thickness between 50 nm and 2.5 μm.

[0017] Still referring to FIG. 1A , a patterned hard mask layer 120 is formed on the dielectric layer 110. In various embodiments, the patterned hard mask layer 120 may include an amorphous carbon layer (ACL). In one or more embodiments, the patterned hard mask layer 120 may include spin-on carbon, tungsten carbide, boron carbide, or other suitable carbon-containing mask material. The patterned hard mask layer 120 may be formed by first depositing a hard mask layer using, for example, a suitable spin-coating technique or a vapor deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other plasma processes such as plasma-enhanced CVD (PECVD) and other processes. The deposited hard mask layer may then be patterned using a lithography process and an anisotropic etching process, for example, using an oxygen-based etch chemistry. The relative thicknesses of the patterned hard mask layer 120 and the dielectric layer 110 may have any suitable relationship. For example, patterned hardmask layer 120 can be thicker than dielectric layer 110, thinner than dielectric layer 110, or the same thickness as dielectric layer 110. In particular embodiments, patterned hardmask layer 120 has a thickness between 1 μm and 4 μm. In one embodiment, patterned hardmask layer 120 comprises an amorphous carbon layer (ACL) and has a thickness of 2.5 μm and a critical dimension (CD) of 75 nm, although in other embodiments, the thickness and CD of patterned hardmask layer 120 can each have any suitable value.

[0018] The patterned hardmask layer 120 and / or the dielectric layer 110 can collectively be considered part of the substrate 100. Additionally, the substrate 100 can include other layers as well. For example, for the purpose of patterning the hardmask layer, there can be a three-layer structure including a photoresist layer, a SiON layer, and an optical planarization layer (OPL).

[0019] Fabricating HAR features in the dielectric layer 110 can be performed by a plasma etching process using a combination of gases according to various embodiments. The process gases can include a halogen-containing etching gas, an oxidizer (e.g., O), and an adsorbate precursor.

[0020] In various embodiments, the etching gas may include hydrogen and fluorine, such as hydrogen fluoride (HF). The HF species and / or other fluorine-containing species may serve as etchant species for etching the dielectric layer 110.

[0021] In certain embodiments, the HF in the process gas may be less than 70% by volume of the total gas flow. In one or more embodiments, the HF in the process gas may be less than 50% by volume, or in other embodiments, less than 10% by volume. Alternatively, the process gas may be HF-free. In certain embodiments, the process gas may contain little or no HF, although HF may be formed in situ in the presence of a plasma from a reaction between a fluorine-containing gas and a hydrogen-containing gas in the etching gas. In one embodiment, the process gas may include a fluorocarbon and a hydrogen-containing gas (e.g., CF4 and H2). In another embodiment, the process gas may include a non-carbon fluorine-containing gas and a hydrogen-containing gas (e.g., NF3 and H2, SF6 and H2, PF3 and H2, or PF5 and H2).

[0022] In various embodiments, the etching gas may include a hydrofluorocarbon, a combination of a hydrocarbon and a fluorine-containing gas, or a combination of a fluorocarbon and a hydrogen-containing gas. In certain embodiments, one or more fluorocarbons may be used as the primary etching gas. For example, the process gas may include a saturated fluorocarbon, an unsaturated fluorocarbon, or a combination thereof. In this disclosure, an unsaturated fluorocarbon refers to any compound containing carbon and fluorine that has at least one carbon-carbon double bond (C=C bond) or triple bond (C≡C bond), and a saturated fluorocarbon refers to any compound containing carbon and fluorine that does not have either a C=C bond or a C≡C bond. In certain embodiments, the unsaturated fluorocarbon may include hexafluorobutadiene (C4F6), hexafluoro-2-butyne (C4F6), or hexafluorocyclobutene (C4F6), and the saturated fluorocarbon may include octafluoropropane (C3F8), perfluorobutane (C4F 10 ) or Perfrenapent (C5F 12 ) may be included. In various embodiments, other gases, such as noble gases and / or balancing agents, may also be added. For example, in certain embodiments, argon (Ar) and dioxygen (O2) may be included as a noble gas and a balancing agent, respectively. In alternative embodiments, the gas combination may further include a third fluorocarbon. In one embodiment, the third fluorocarbon may be octafluorocyclobutane (C4F8), octafluoro-2-butene (C4F8), hexafluoropropylene (C3F6), carbon tetrafluoride (CF4), or fluoroform (CHF3). While the above examples are primarily fluorine-based etching gases, other halogen-containing gases (e.g., BCl3, Cl2, and HBr) may also be used.

[0023] An adsorbate precursor and an oxidant (e.g., O) may be included in the process gas so that adsorbates can be formed in the plasma processing chamber through oxidation under plasma conditions. In various embodiments, the adsorbate may include phosphorus. In one or more embodiments, the adsorbates formed in the plasma processing chamber may include phosphoric acid (H3PO4). The inventors of the present disclosure have determined that H3PO4 can be an effective adsorbate for providing sidewall passivation. However, H3PO4 is non-volatile, and therefore, directly supplying it in the gas phase to the plasma processing chamber is impractical. In various embodiments, the method delivers an adsorbate precursor to enable in-situ formation of the adsorbate in the plasma processing chamber. In-situ formation of an adsorbate, such as H3PO4, can overcome the non-volatility issue. Accordingly, the adsorbate precursor may include phosphorus. Examples of P-containing adsorbate precursors include PH3 and PCl3.

[0024] In other embodiments, the adsorbate may contain other elements such as B, S, Si, and / or N, and the adsorbate precursor may contain these elements accordingly. In certain embodiments, the adsorbate precursor may contain BH, Si, x H y , H2S, or NH3. Correspondingly, adsorbates formed in plasma processing chambers may include boric acid, silicic acid, sulfuric acid, nitric acid, or similar acidic molecules containing B, S, Si, and / or N. These acidic molecules may be exposed to phosphoric acid (H3PO4) to exhibit similar behavior, thereby serving as effective adsorbates for sidewall passivation.

[0025] Furthermore, in various embodiments, these adsorbates are primarily neutral species in plasma systems and can be effective in surface modification / activation during plasma etching processes such as reactive ion etching (RIE). The present method can advantageously improve etch rates by increasing the amount of neutral species in the plasma.

[0026] The inventors of the present disclosure have determined that a specific additive gas combination of an oxidizer (e.g., O) and an oxidizable adsorbate precursor (e.g., PH) can be important for enabling in-situ adsorbate formation, thereby enabling effective sidewall passivation and etch rate enhancement. The presence of oxygen species in the presence of plasma enables and promotes the oxidation reaction of the adsorbate precursor. In certain embodiments, the plasma etching process may use a gas combination including an etching gas and an additive gas mixture including O and PH. Furthermore, the inclusion of a hydrogen-containing gas (e.g., H) may be advantageous for generating reactive ionic species in the plasma by promoting molecular dissociation, which may enhance the etch rate. Accordingly, in another embodiment, the additive gas mixture may include O, H, and PH. In yet another embodiment, the additive gas mixture may include O, H, and BH, O, H, and Si. x H y , O2, H2 and H2S, O2, H2 and NH3, O2, H2 and CO2, O2, H2 and CO. In certain embodiments, more than one adsorbate may be used. In one or more embodiments, in addition to adsorbates containing P, B, S, Si, and / or N, additional adsorbates (e.g., HO) may be formed in the plasma processing chamber.

[0027] All gases can be continuously flowed at a steady flow rate, or in certain embodiments, their flow rates can be individually varied during the plasma etching process. Furthermore, various gas pulsing strategies can be applied in the present method. For example, portions of the process gases (e.g., O and adsorbate precursors) can be intermittently flowed into the plasma processing chamber using gas pulsing. Such gas pulsing can allow for fine tuning of the adsorbate concentration and therefore the degree of passivation within the plasma processing chamber.

[0028] In certain embodiments, the ratio of the flow rate of the halogen-containing etching gas (e.g., CF) to the flow rate of the adsorbate precursor (e.g., PH) may be between 100:1 and 1:1. In one or more embodiments, the ratio of the flow rates may be between 100:1 and 10:1, and in other embodiments, between 100:1 and 20:1.

[0029] In certain embodiments, the ratio of the oxidant (e.g., O) flow rate to the adsorbate precursor (e.g., PH) flow rate may be between 100:1 and 1:1. In one or more embodiments, the ratio of the flow rates may be between 100:1 and 10:1, and in other embodiments, between 100:1 and 20:1.

[0030] In certain embodiments, the ratio of the flow rate of the halogen-containing etching gas to the flow rate of the oxidizer (e.g., O) may be between 100:1 and 1:1. In one or more embodiments, the ratio of the flow rates may be between 100:1 and 10:1, and in other embodiments, between 100:1 and 20:1.

[0031] In various embodiments, the substrate temperature during the plasma etching process can be maintained above 0°C, for example, between 0°C and 50°C. Most methods using HF and / or certain adsorbate species (e.g., HO) as the primary etching gas may require low-temperature conditions (e.g., <0°C) for adequate etching performance, primarily due to the fact that physisorption of HF can occur only at very low temperatures. By using new types of adsorbate species instead of or in addition to HF, the present method can advantageously eliminate the low-temperature requirement from the plasma etching process for HAR features in dielectric materials. As a result, etch rates can be improved by controlling the temperature over a wider range according to the present method.

[0032] FIG. 1B shows substrate 100 during the formation of HAR features by a plasma etching process.

[0033] In FIG. 1B, high aspect ratio (HAR) features are formed as recesses 125 in the dielectric layer 110 by a plasma etching process. As shown in FIG. 1B, the recesses 125 can be formed by the plasma etching process to be straight and uniform across the substrate 100 with little or no curvature. The curvature refers to a deviation from a purely anisotropic profile, from a perfectly straight recess to a recess with an outward curvature. The curvature typically occurs near the top of the sidewall of the etching target (e.g., the dielectric layer 110) and can be caused by bending of the incident ion trajectories of the ions used during the plasma etching process. The curvature can be eliminated or minimized by sidewall passivation within the recesses 125. Such passivation can be achieved by a passivation layer 130 of adsorbate species. In one or more embodiments, the passivation layer 130 can also include deposits of polymeric species derived from carbon-containing gases (e.g., saturated and / or unsaturated fluorocarbons) in the etching gas.

[0034] 1B, the sufficient etch rate also enables the recess 125 to have a high aspect ratio in a shorter process time compared to conventional HAR etching methods. Without wishing to be bound by any theory, the presence of adsorbates at the etch front (e.g., the exposed top surface of the dielectric layer 110) may catalyze the reaction of the etchant (e.g., an F-containing species) with the dielectric layer 110, thus increasing the etch rate. At the same time, due to good selectivity to the hard mask during the plasma etching process, only a small percentage of the hard mask may be consumed.

[0035] Recess 125 can be any shape and structure, including contact holes, slits, or other suitable structures containing recesses useful in semiconductor device fabrication. In various embodiments, the feature defined by recess 125 has a critical dimension (CD) of 200 nm or less. In particular embodiments, the CD can be between 50 nm and 200 nm. For example, the feature can include a slit having a CD of about 150 nm. In alternative embodiments, recess 125 can include a hole with an upper opening of 80 nm or less in diameter.

[0036] FIG. 1C shows the substrate 100 after the plasma etching process is completed.

[0037] 1B, recess 125 may be further extended as shown in FIG. 1C by etching through the entire thickness of dielectric layer 110 to reach the top surface of substrate 100. Plasma etching processes according to various embodiments may provide good selectivity to silicon (Si) in addition to the hard mask. Accordingly, plasma etching may be selective to silicon-containing substrate 100, and formation of recess 125 may advantageously stop at the top surface of substrate 100.

[0038] In various embodiments, RF pulsing in the kHz range can be used to power the plasma. Using RF pulsing can facilitate generating high-energy ions (>keV) in the plasma for the plasma etch process while reducing charging effects. Charging effects during the process are a phenomenon in which electrons accumulate charge on insulating materials (e.g., the silicon oxide of the dielectric layer 110), creating local electric fields that can direct positive ions to the sidewalls and cause lateral etching. Therefore, it can also be important to fine-tune the power conditions of the plasma etch process to minimize critical dimension (CD) widening of high aspect ratio (HAR) features. In certain embodiments, a moderate duty cycle of 40% to 80% can be used. In one embodiment, 18 kW of bias power can be pulsed at a frequency of 5 kHz with a duty cycle of 60%.

[0039] In certain embodiments, the plasma etch process can be advantageously performed as a continuous process having a process time of 60 minutes or less to form high aspect ratio (HAR) features having aspect ratios of 100: 1 or greater. In other embodiments, the plasma etch process can be applied as part of a cyclic plasma process that includes various steps (e.g., an etch step, a deposition step, a flash step, and a by-product control step).

[0040] In various embodiments, process parameters may be selected to optimize the properties of high aspect ratio (HAR) features, taking into account various factors including, among others, controlled deposition levels, selectivity to hard mask, sidewall passivation in the HAR features, and good critical dimension uniformity (CDU). The process parameters may include gas selection, gas flow rate, pressure, temperature, process time, and plasma conditions such as source power, bias power, and RF pulsing conditions.

[0041] Further processing can follow conventional processes, such as removing the patterned hard mask layer 120, followed by filling the recesses 125 with a conductive material to form HAR conductive features (e.g., contact plugs for a memory array). For example, the conductive material can be copper formed using electroplating. However, any suitable conductive material and deposition method can be used. A planarization process (e.g., chemical mechanical planarization) can then be used to remove excess conductive material from the top surface of the dielectric layer 110.

[0042] 2A-2B show cross-sectional views of a substrate 100 during a plasma etching process. Figure 2A shows the substrate 100 with etchant species causing lateral etching, and Figure 2B shows the substrate 100 with a passivation layer 130 preventing lateral etching. The structure of the substrate 100 may be identical to that shown in Figures 1A-1C and therefore will not be repeated.

[0043] FIG. 2A shows substrate 100 after a plasma etching process is performed without sidewall passivation of recess 125. In this example, when etchant 210 (e.g., F-containing species) in the plasma impinges on the sidewall of recess 125, the etchant may cause lateral etching, which may then result in widening / curving of recess 125. Because the degree of lateral etching may vary at different depths of recess 125, the sidewall of recess 125 may not be straight. The recess may be tapered and / or curved, as shown in FIG. 2A. As a result, the HAR features in dielectric layer 110 may suffer from line meandering and / or pattern collapse. To avoid such issues, in various embodiments, adding a hydrogen-containing gas to the process gas may enable and improve sidewall passivation.

[0044] 2B shows substrate 100 after performing a plasma etching process with sidewall passivation of recess 125. Sidewall passivation can be achieved by forming a passivation layer 130 that includes an adsorbate (e.g., H3PO4). Passivation layer 130 protects the sidewalls of recess 135 from etchant 210.

[0045] 3A-3C show schematic surface structures with various adsorbates on silicon oxide.

[0046] The present inventors have confirmed through quasi-continuous density functional theory (QC-DFT) simulations that P-containing adsorbates can be advantageous in providing sidewall passivation without cryogenic conditions. Furthermore, they have demonstrated a synergistic enhancement of adsorption energy for HF-H3PO4 co-adsorption. Figure 3A shows the adsorption of H3PO4 on the hydrophilic surface of SiO2, and the simulated adsorption energy (E ads ) is -0.8837 eV. Figure 3B shows the adsorption of HF on the hydrophilic surface of SiO2, with a simulated E ads is -0.4920 eV. Figure 3C shows the coadsorption of HF and H3PO4 on the hydrophilic surface of SiO2, and the simulated E adsis -1.4519 eV. The results are summarized in Table 1. The simulated E for coadsorption ads (-1.4519 eV) is the value of the two simulated E ads (-1.3757 eV), indicating a synergistic enhancement of adsorption energy. This result demonstrates that the presence of HF or H3PO4 during the plasma etching process can advantageously enhance the adsorption of the second adsorbate type, H3PO4 or HF, respectively. Accordingly, the present method can benefit from the inclusion of these two types of adsorbates for better adsorbate effects (e.g., etch rate and / or sidewall passivation).

[0047] [Table 1]

[0048] 4A-4C show process flow diagrams of semiconductor manufacturing methods including a plasma etching process for forming HAR features on a substrate including a material layer, according to various embodiments. The process flow can follow the diagrams described above (e.g., FIGS. 1A-1C) and will not be described again.

[0049] 4A, according to some embodiments, process flow 40 may begin by flowing an etching gas, dioxygen (O), and an adsorbate precursor (e.g., PH) into a plasma processing chamber (block 410). Next, a plasma may be generated in the plasma processing chamber (block 420), where the adsorbate precursor is oxidized to form an adsorbate (e.g., HPO). A plasma etching process may then be performed using the plasma to plasma-pattern a silicon-containing dielectric layer of a substrate disposed in the plasma processing chamber (block 430, FIGS. 1A-1C), where the adsorbate forms a sidewall passivation layer.

[0050] In FIG. 4B, according to an alternative embodiment, process flow 42 includes a mixture of hydrogen and fluorine, dioxygen (O), PH, BH, Si x H y The process may begin by flowing an etchant containing O, H, S, or NH, and an adsorbate precursor containing O (block 412). Next, a plasma can be generated in the plasma processing chamber while flowing the etchant, O, and adsorbate precursor, and the adsorbate precursor is oxidized to form adsorbates containing P, B, Si, S, or N (block 422). The substrate can then be exposed to the plasma to form recesses in the silicon-containing dielectric layer of the substrate, and the adsorbates form a sidewall passivation layer within the recesses (block 432, FIGS. 1A-1C).

[0051] 4C, according to yet another embodiment, process flow 44 may begin with depositing an organic layer on a silicon-containing dielectric layer of a substrate (block 404), followed by patterning the organic layer using a halogen-free plasma etching process (block 406, FIG. 1A). A halogen-based plasma etching process may then be performed to pattern the silicon-containing dielectric layer using the patterned organic layer as an etch mask (block 424, FIGS. 1B-1C). The halogen-based plasma etching process may begin with generating a halogen-containing plasma in a plasma processing chamber from a gas mixture including a halogen-containing etching gas (block 426), followed by adding dioxygen (O), PH3, B2H6, SiH6, and HCl to the plasma processing chamber. x H y An adsorbate precursor comprising H, S, or NH is flowed (block 428), and the adsorbate precursor is oxidized under a halogen-containing plasma to form an adsorbate comprising P, B, Si, S, or N. The substrate may then be exposed to a halogen-containing plasma in a plasma processing chamber to form a high aspect ratio (HAR) recess in a silicon-containing dielectric layer of the substrate (block 434), and the adsorbate forms a sidewall passivation layer in the recess.

[0052] FIG. 5 illustrates a plasma processing system 50 for performing semiconductor manufacturing processes, according to various embodiments.

[0053] 5 shows substrate 100 disposed on a substrate holder 554 (e.g., a circular electrostatic chuck (ESC)) inside plasma processing chamber 510 near the bottom. Substrate 100 may optionally be maintained at a desired temperature using a heater / cooler 556 surrounding substrate holder 554. The temperature of substrate 100 may be maintained by a temperature controller 540 connected to substrate holder 554 and heater / cooler 556. The ESC may be coated with a conductive material (e.g., a carbon-based or metal nitride-based coating) so that electrical connection can be made to substrate holder 554.

[0054] 5, substrate holder 554 can be the bottom electrode of plasma processing chamber 510. In the illustrative example of FIG. 5, substrate holder 554 is connected to two RF bias power supplies 570 and 580 through blocking capacitors 590 and 591. In some embodiments, a conductive circular plate near the top inside plasma processing chamber 510 is top electrode 552. In FIG. 5, top electrode 552 is connected to DC power supply 550 of plasma processing system 50.

[0055] Gases may be introduced into the plasma processing chamber 510 by a gas delivery system 520. The gas delivery system 520 includes multiple gas flow controllers for controlling the flow of multiple gases into the chamber. Each gas flow controller of the gas delivery system 520 may be assigned to a fluorocarbon, a noble gas, and / or a balancing agent. In some embodiments, an optional center / edge splitter may be used to independently adjust the gas flow rates at the center and edge of the substrate 100.

[0056] RF bias power supplies 570 and 580 can be used to supply continuous wave (CW) power or pulsed RF power to maintain a plasma such as plasma 560. Plasma 560, shown between top electrode 552 and bottom electrode (which is also substrate holder 554), illustrates a direct plasma generated near substrate 100 in plasma processing chamber 510 of plasma processing system 50. Etching can be performed by exposing substrate 100 to plasma 560 while powering substrate holder 554 with RF bias power supplies 570, 580 and, optionally, top electrode 552 with DC power supply 550.

[0057] The configuration of the plasma processing system 50 described above is merely exemplary. In alternative embodiments, various alternative configurations for the plasma processing system 50 can be used. For example, an inductively coupled plasma (ICP) can be used with RF source power coupled to a planar coil above the top dielectric cover, and gas inlets and / or gas outlets can be coupled to the top wall, etc. In various embodiments, the RF power, chamber pressure, substrate temperature, gas flow rates, and other plasma process parameters can be selected according to a respective process recipe. In some embodiments, the plasma processing system 50 can be a resonator, such as a helical resonator.

[0058] Although not described herein, embodiments of the present invention may also be applied to remote plasma systems and batch systems, for example, a substrate holder may be capable of supporting multiple wafers that are spun about a central axis as they pass through different plasma zones.

[0059] Illustrative embodiments of the present invention are summarized here, although other embodiments may be understood from the entire specification and claims appended hereto.

[0060] Example 1. A method of processing a substrate, the method comprising: flowing an etching gas, O2, and an adsorbate precursor into a plasma processing chamber configured to hold a substrate including a silicon-containing dielectric layer and a patterned mask layer, the etching gas comprising hydrogen and fluorine; generating a plasma in the plasma processing chamber while flowing the etching gas, O2, and the adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate; and patterning the silicon-containing dielectric layer on the substrate using the plasma, the adsorbate forming a sidewall passivation layer.

[0061] Example 2. The method of Example 1, wherein the adsorbate comprises H3PO4 and the adsorbate precursor comprises PH3.

[0062] Example 3. The method of any one of Examples 1 or 2, wherein the adsorbate comprises boron.

[0063] Example 4. The method of any one of Examples 1-3, wherein the adsorbate comprises silicon.

[0064] Example 5. The method of any one of Examples 1-4, wherein the adsorbate comprises sulfur.

[0065] Example 6. The method of any one of Examples 1-5, wherein the adsorbate comprises nitrogen.

[0066] Example 7. The method of any one of Examples 1-6, wherein the etching gas is HF-free.

[0067] Example 8. The method of any one of Examples 1-7, wherein the etching gas is a gas mixture comprising dihydrogen (H2) and a fluorocarbon.

[0068] Example 9. The method of any one of Examples 1-8, wherein the etching gas is a gas mixture comprising dihydrogen (H2) and NF3, H2 and SF6, H2 and PF3, or H2 and PF5.

[0069] Example 10. The method of any one of Examples 1-9, wherein the silicon-containing dielectric layer comprises silicon oxide or silicon nitride.

[0070] Example 11. The method of any one of Examples 1-10, wherein the ratio of the O2 gas flow rate to the adsorbate precursor gas flow rate is between 100:1 and 1:1.

[0071] Example 12. The method of any one of Examples 1 to 11, further comprising maintaining the temperature of the substrate between 0°C and 50°C.

[0072] Example 13. A method of processing a substrate, comprising: flowing an etchant comprising hydrogen and fluorine, O2, and an adsorbate precursor into a plasma processing chamber, the adsorbate precursor comprising PH3, B2H6, SixHy, HS, or NH3; generating a plasma in the plasma processing chamber while flowing the etchant, O2, and adsorbate precursor, the adsorbate precursor being oxidized to form an adsorbate comprising P, B, Si, S, or N; and exposing the substrate to the plasma in the plasma processing chamber to form a recess in a silicon-containing dielectric layer of the substrate, the recess having an aspect ratio of at least 50:1, and the adsorbate forming a sidewall passivation layer in the recess.

[0073] Example 14. The method of Example 13, wherein the substrate further comprises a patterned amorphous carbon layer (ACL) over the silicon-containing dielectric layer, the patterned ACL being an etch mask during forming the recesses.

[0074] Example 15. The method of any of Examples 13 or 14, wherein the recesses define features having a critical dimension of between 50 nm and 200 nm.

[0075] Example 16. The method of any one of Examples 13-15, further comprising maintaining the temperature of the substrate between 0°C and 50°C.

[0076] Example 17. A method of processing a substrate, comprising: depositing an organic layer on a silicon-containing dielectric layer of the substrate; patterning the organic layer by a halogen-free plasma etching process; and patterning the silicon-containing dielectric layer by a halogen-based plasma etching process using the patterned organic layer as an etch mask, wherein the halogen-based plasma etching process comprises generating a halogen-containing plasma from a gas mixture including a halogen-containing etching gas in a plasma processing chamber; and flowing O and an adsorbate precursor into the plasma processing chamber, wherein the adsorbate precursor is selected from the group consisting of PH, BH, Si, and HCl. x H y , H2S, or NH3, wherein the adsorbate precursor is oxidized under a halogen-containing plasma to form an adsorbate comprising P, B, Si, S, or N; and forming a recess in a silicon-containing dielectric layer of a substrate by exposing the substrate to the halogen-containing plasma in a plasma processing chamber, wherein the recess has an aspect ratio of at least 50:1 and the adsorbate forms a sidewall passivation layer in the recess.

[0077] Example 18. The method of Example 17, wherein the halogen-containing plasma is a capacitively coupled plasma (CCP).

[0078] Example 19. The method of any one of Examples 17 or 18, wherein flowing the O2 and adsorbate precursor comprises intermittently flowing the O2 and adsorbate precursor.

[0079] Example 20. The method of any one of Examples 17-19, further comprising maintaining the temperature of the substrate between 0°C and 50°C during the halogen-based plasma etching process.

[0080] While the present invention has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this specification. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. A method for processing a substrate, Etching gas, O ２ The steps include, and flowing an adsorbent precursor, wherein the plasma processing chamber is configured to hold the substrate including a silicon-containing dielectric layer and a patterning mask layer, and the etching gas includes hydrogen and fluorine, The etching gas, O ２ and a step of generating plasma in the plasma processing chamber while the adsorbent precursor is flowing, wherein the adsorbent precursor is oxidized to form adsorbent, A step of patterning the silicon-containing dielectric layer on the substrate using the plasma, wherein the adsorbent forms a sidewall passivation layer while maintaining the substrate at a temperature above 0°C. A method having

2. The adsorbent is H ３ PO ４ The adsorbent precursor includes PH ３ The method according to claim 1, including the method described in claim 1.

3. The method according to claim 1, wherein the adsorbent contains boron.

4. The method according to claim 1, wherein the adsorbent includes silicon.

5. The method according to claim 1, wherein the adsorbent contains sulfur.

6. The method according to claim 1, wherein the adsorbent contains nitrogen.

7. The method according to claim 1, wherein the etching gas is HF-free.

8. The etching gas is dihydrogen (H ２ The method according to claim 7, wherein the gas mixture is a mixture of ) and fluorocarbons.

9. The etching gas is dihydrogen (H ２ ), NF ３ , H ２ , SF ６ , H ２ , PF ３ , or H ２ , PF ５ and is a gas mixture, the method according to claim 7.

10. The method according to claim 1, wherein the silicon-containing dielectric layer comprises silicon oxide or silicon nitride.

11. O236036 ２ The method according to claim 1, wherein the ratio of gas flow rates is between 100:1 and 1:

1.

12. A method for processing a substrate, Etching agent containing hydrogen and fluorine, O ２ The steps include, and flowing an adsorbent precursor into a plasma processing chamber, wherein the adsorbent precursor contains PH 3, The etching agent, O ２ and a step of generating plasma in the plasma processing chamber while the adsorbent precursor is flowing, wherein the adsorbent precursor is oxidized and an adsorbent containing H3PO4 is formed, A step of forming a recess in the silicon-containing dielectric layer of a substrate by exposing the substrate to the plasma in the plasma processing chamber, while maintaining the substrate at a temperature above 0°C, wherein the recess has an aspect ratio of at least 50:1, and the adsorbent forms a side wall passivation layer in the recess. A method having

13. The method according to claim 12, wherein the substrate further comprises a patterned amorphous carbon layer (ACL) on the silicon-containing dielectric layer, the patterned ACL serving as an etching mask during the step of forming the recesses.

14. The method according to claim 12, wherein the recess defines a feature portion having a limiting dimension between 50 nm and 200 nm.

15. A method for processing a substrate, The steps include depositing an organic layer on the silicon-containing dielectric layer of the substrate, The process involves a halogen-free plasma etching process to pattern the organic layer, The steps include: using the patterned organic layer as an etching mask and patterning the silicon-containing dielectric layer by a halogen-based plasma etching process; It has, The halogen-based plasma etching process described above is In a plasma processing chamber, the steps include generating a halogen-containing plasma from a gas mixture containing a halogen-containing etching gas, O ２ and a step of flowing an adsorbent precursor, wherein the adsorbent precursor contains pH 3, and the adsorbent precursor is oxidized under the halogen-containing plasma to form an adsorbent containing H3PO4, A step of forming a recess in the silicon-containing dielectric layer of the substrate by exposing the substrate to the halogen-containing plasma in the plasma processing chamber, while maintaining the temperature of the substrate above 0°C and below 50°C, wherein the recess has an aspect ratio of at least 50:1, and the adsorbent forms a side wall passivation layer in the recess. A method having

16. The method according to claim 15, wherein the halogen-containing plasma is a capacitively coupled plasma (CCP).

17. O ２ And the step of flowing the adsorbent precursor is O ２ The method according to claim 15, further comprising the step of intermittently flowing the adsorbent precursor.

18. The method according to claim 8, wherein the fluorocarbon is an unsaturated fluorocarbon.

19. The method according to claim 8, wherein the fluorocarbon is a saturated fluorocarbon.

20. The method according to claim 15, wherein the silicon-containing dielectric layer has a hydrophilic surface.

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