Semiconductor device and manufacturing method

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33), and a first electrode (31), the semiconductor body (2) comprising a first region (21) that is a source or emitter region, and a well region (22), the first region (21) being of a first conductivity type and the well region (22) being of a different second conductivity type, the well region (22) being separated from the gate electrode (33) by a gate insulating layer (4), the first region (21) being electrically contacted by the first electrode (31) that is a source or emitter electrode, and the first region (21) comprising at least one current limiting region (5), the at least one current limiting region (5) being made of at least one electrically insulating material.

Description

[Technical Field]

[0001] A semiconductor device is provided, as well as a method for manufacturing such a semiconductor device. [Background technology]

[0002] US Patent Application Publication Nos. 2017 / 0243970, 2017 / 0229535 and 2015 / 0108564 relate to semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved is to provide a semiconductor device that has an improved trade-off between conduction loss and short circuit withstand time (SCWT). [Means for solving the problem]

[0004] This object is achieved, inter alia, by a semiconductor device and a method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] For example, the semiconductor devices described herein may include one or more current-limiting regions made of an electrically insulating material and located in the source or emitter region. At least one current-limiting region may provide a source resistance R S increases. This R S The increase must be in such a way that it does not significantly impede device performance in normal operation and improves short circuit behavior.

[0006] According to at least one embodiment, a semiconductor device includes a semiconductor body, a gate electrode, and a first electrode. For example, the semiconductor body is a wide-bandgap semiconductor material such as SiC, Ga2O3, or GaN. However, the semiconductor body may alternatively be silicon, or Si for short. The electrodes may also be made of at least one metal or a highly doped and / or ohmic conductive semiconductor material such as poly-Si.

[0007] According to at least one embodiment, the semiconductor body comprises a first region, for example, the first region is a source region or an emitter region.

[0008] According to at least one embodiment, the semiconductor body includes a well region. The well region is adjacent to the first region. That is, the first region can contact the well region and thus be in direct physical contact with the well region. The channel region is a portion of the well region and can have the same doping concentration. During operation, electrons flow through the channel region from the source region to the drift region along the gate insulating layer. In operation of the semiconductor device, the channel region can be the portion of the well region adjacent to the gate insulating layer.

[0009] According to at least one embodiment, the first region is of a first conductivity type and the well region is of a different second conductivity type. For example, the first conductivity type may be n-type and the second conductivity type may be p-type, or vice versa. Hereinafter, the first conductivity type will be referred to as n-type. Therefore, if the first conductivity type were instead p-type, the doping relationships described below would have to be reversed.

[0010] According to at least one embodiment, the well region is adjacent to the gate electrode and separated from the gate electrode by a gate insulating layer, which may be directly between the gate electrode and the well region.

[0011] According to at least one embodiment, the first region is electrically contacted by a first electrode, e.g., a source electrode or an emitter electrode. Thus, the first electrode can contact the semiconductor body at least in the first region. For example, a well can be electrically contacted by the first electrode or by an otherwise separate electrode.

[0012] According to at least one embodiment, the first region includes one current-limiting region or multiple current-limiting regions, and at least one current-limiting region can correspond to a recess in at least one assigned first region, i.e., at least one current-limiting region can correspond to at least one recess formed in at least one assigned first region.

[0013] Thus, the at least one current-limiting region is comprised of at least one electrically insulating material. For example, the difference in specific conductivity between the material of the first region and the at least one electrically insulating material of the current-limiting region is at least 10% so that the current-limiting region does not conduct a significant amount of current compared to the first region. 2 times, or at least 10 3 times, or at least 10 4 For example, the at least one electrically insulating material is a solid material at a temperature of, for example, at least 250K to 400K.

[0014] For example, the at least one electrically insulating material may be a metal oxide, a semiconductor oxide, a metal nitride, or a semiconductor nitride. For example, the at least one current-limiting region may include one or more of the following materials: SiO2, Si3N4, Al2O3, YO3, ZrO2, HfO2, La2O3, Ta2O5, and TiO2. The same materials may also be used for the gate insulating layer, which may also be called a gate oxide.

[0015] In at least one embodiment, a semiconductor device comprises a semiconductor body, a gate electrode, and a first electrode; the semiconductor body comprises a first region and a well region adjacent to the first region, the first region being of a first conductivity type and the well region being of a different second conductivity type; the well region is adjacent to the gate electrode and separated from the gate electrode by a gate insulating layer; the first region is electrically contacted by a first electrode; the first region has at least one current limiting region; The at least one current-limiting region is comprised of at least one electrically insulating material.

[0016] Thus, the present application describes, for example, a metal-insulator-semiconductor field-effect transistor (MISFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET), for example based on silicon carbide SiC material, in which at least one recess is etched in the source or emitter region and filled with an electrically insulating material in order to improve the trade-off between conduction losses and short-circuit capability.

[0017] SiC MOSFETs are currently available from several vendors. Offered in either planar or trench cell designs, SiC MOSFETs offer competitive static losses, fast dynamic performance, and sufficient reliability. In terms of fault handling capability, SiC MOSFETs still fall short of the typical industry standard value of about 10 μs exhibited by their Si counterparts. This is typically associated with a strong trade-off between conduction losses and short-circuit withstand voltage (SCWT). SCWT and on-state device resistance (R) DS,on One approach for the best trade-off between S The best way to do this is to use

[0018] Thus, for example, a SiC MOSFET is described herein in which a portion of the source region is etched away and filled with an electrically insulating material such as SiO2. + Removing a portion of the source reduces the total source area and, as a result, the source resistance R S increases.

[0019] Therefore, at least one current-limiting region of the present proposal reduces the total source area and increases the channel-contact path for carriers. Both effects contribute to the source resistance R S Increase the value of R S Increasing the value of , the saturation current I SAT The depth d of the etched region and its length L are determined by the conduction current R DS,on The MOSFET can be suitably designed to achieve the desired effect on the SC current while ignoring its effect on the total resistance between the source and drain in the on-state, also called the resistance between the source and drain.

[0020] According to at least one embodiment, the semiconductor device is a power device. This means, for example, that the semiconductor device is configured for a maximum current through the well region of at least 10 A or at least 50 A. Optionally, the maximum current is up to 500 A or up to 1.5 kA. Alternatively or additionally, the semiconductor device is configured for a maximum voltage between the source and drain or emitter and collector of at least 0.6 kV or at least 1.2 kV. Optionally, the maximum voltage can be up to 6.5 kV.

[0021] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode and the first electrode overlap the first region. Here and hereinafter, "top view" may refer to a view perpendicular to the top surface of the semiconductor body to which the first electrode is applied and on which the first region is located.

[0022] According to at least one embodiment, the at least one current confinement region is spaced apart from the gate electrode and / or the first electrode in a top view of the semiconductor body, e.g., the at least one current confinement region is spaced apart from the gate electrode and the first electrode in a top view.

[0023] According to at least one embodiment, the at least one current limiting region is located in the assigned first region with mirror symmetry, e.g., within manufacturing tolerances. That is, in a top view of the semiconductor body, the first region and the at least one current limiting region have an axis of mirror symmetry, e.g., with respect to the shapes of the first region and the at least one current limiting region. The axis of mirror symmetry may extend parallel to the gate electrode and / or the first electrode in a top view and / or may be located between the gate electrode and the first electrode. Alternatively, a non-mirror symmetric arrangement of the at least one current limiting region in the assigned first region in a top view is also possible.

[0024] According to at least one embodiment, in a top view of the semiconductor body, the first region extends completely between the at least one current confinement region and the first electrode and between the at least one current confinement region and the gate electrode, i.e., a portion of the first region between the at least one current confinement region and the respective electrode is, for example, on the top surface of the semiconductor body in a top view of the semiconductor body.

[0025] Alternatively, the at least one current limiting region may be partially covered by the first electrode and / or the gate electrode, or the at least one current limiting region contacts the first electrode and / or the gate electrode, from the point of view of the semiconductor body.

[0026] According to at least one embodiment, the at least one current-limiting region is located between the first electrode and the gate electrode, for example, all of the at least one current-limiting region is located between the electrodes.

[0027] According to at least one embodiment, when viewed in a cross-section of the semiconductor body, the first region extends completely around the at least one current limiting region in a direction toward the well region. This can mean that the first region is embedded in the well region and / or that the at least one current limiting region is embedded in the first region. For example, when viewed in cross-section, in this case, a portion of the first region is completely around the at least one current limiting region, such that there is no direct connection path within the semiconductor body from the at least one current limiting region to the well region without crossing the first region.

[0028] The term "cross-section of the semiconductor body" may refer to a cross-section through the first region, through the current confinement region, or through at least one of the current confinement regions, and through the gate electrode, for example in a direction perpendicular to the top surface of the semiconductor body and / or perpendicular to a main extension direction of the gate electrode.

[0029] According to at least one embodiment, the volume of the at least one current-limiting region is at least 5%, or at least 10%, or at least 20%, or at least 40%, or at least 60% of the total volume of the first region and the at least one current-limiting region combined. Alternatively or additionally, the percentage is at most 95%, or at most 85%, or at most 75%. For example, the percentage is at least 40% and at most 85%.

[0030] For example, the at least one current-limiting region increases the electrical resistance through the first region between the first electrode and the channel region by at least 1.1 times, or at least 1.5 times, or at least 2 times, or at least 5 times. Alternatively or additionally, the factor is at most 100, or at most 25, or at most 15, or at most 10, or at most 5. For example, the factor is at least 2 and at most 10. The electrical resistance through the first region may refer to the normal operating current for which the semiconductor device is designed in the on-state. These factors refer to a device that does not have at least one current-limiting region in the first region but is identical in structure within manufacturing tolerances.

[0031] For example, the at least one current-confining region reduces a cross-section of current flow in the first region from the first electrode to the well region adjacent to the gate insulating layer, i.e., the channel region, by at least 1.1 times, or at least 1.5 times, or at least 2 times, or at least 5 times. Alternatively or additionally, the factor is at most 100, or at most 15, or at most 10, or at most 5, or at most 2. For example, the factor is at least 2 and at most 10.

[0032] According to at least one embodiment, the at least one current-limiting region is at least one recess in the first region. That is, the at least one electrically insulating material is located in at least one recess in the first region. If there are two or more recesses and two or more current-limiting regions, there may be a one-to-one allocation between the recesses and the current-limiting regions and / or the at least one electrically insulating material. The at least one electrically insulating material may completely fill its assigned recess. There may be two or more electrically insulating materials per recess.

[0033] According to at least one embodiment, the at least one electrically insulating material terminates in alignment with the first region. Thus, the upper surface can be planar across the first region and the at least one current-limiting region. In other words, the first region and the electrically insulating material form a flat surface and terminate in alignment with each other.

[0034] According to at least one embodiment, the semiconductor body further comprises a drift region, the drift region being of the first conductivity type and having, for example, a lower maximum doping concentration compared to the first region and the well region.

[0035] According to at least one embodiment, the semiconductor body further comprises a second region, e.g., a drain region or a collector region. In the case of a drain region, the second region is also of the first conductivity type, but e.g., has a higher maximum doping concentration than the drift region. In the case of a collector region, the second region is of the second conductivity type.

[0036] According to at least one embodiment, the drift region is located between the well region and the second region, such that the first region is separated from the second region by the well region.

[0037] According to at least one embodiment, the semiconductor device further comprises a second electrode, e.g., a collector electrode or a drain electrode, which can be located on a side of the second region remote from the drift region and / or a side of the second region remote from the first region.

[0038] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode and the first electrode each extend along a straight line, and if there are multiple first electrodes and / or gate electrodes, there may be multiple straight lines along which the first electrodes and / or gate electrodes extend.

[0039] According to at least one embodiment, the first region extends parallel to the gate electrode and / or the first electrode, and thus the semiconductor device can have a stripe design including multiple linear stripes of the gate electrode and / or the first electrode.

[0040] According to at least one embodiment, in a top view of the semiconductor body, the gate electrode and / or the first electrode each include a plurality of subsections. For example, the subsections correspond to unit cells. The unit cells can be arranged, for example, in a regular two-dimensional lattice. The semiconductor body can extend continuously across all the unit cells and include a plurality of first regions arranged accordingly. Thus, the semiconductor device can have a cellular design including a plurality of cells, each having a first electrode, a corresponding gate electrode, and a corresponding first region with at least one current-confining region.

[0041] According to at least one embodiment, the semiconductor device has a planar design, i.e., the gate insulating layer and the gate electrode are applied to a planar portion of an upper surface of the semiconductor body, and the first region and the at least one current-limiting region can be located on the upper surface.

[0042] According to at least one embodiment, the semiconductor device has a trench design. Therefore, the gate insulating layer and the gate electrode are partially or completely disposed within a trench in the semiconductor body. For example, the depth of the trench begins at the top surface of the semiconductor body and exceeds the depth of the well region. Again, the first region and at least one current-limiting region can be located at the top surface.

[0043] According to at least one embodiment, there is exactly one current limiting region per first region. In the case of multiple first regions, there can be a one-to-one assignment between first regions and current limiting regions.

[0044] Alternatively, there may be multiple current-limiting regions in the first region. In the case of multiple first regions, there may be multiple current-limiting regions per first region. The current-limiting regions of each first region, or exactly one first region, are spaced apart from one another in a top view of the semiconductor body.

[0045] In a top view of the semiconductor body, the or each current limiting region may be completely surrounded by a respectively assigned first region.

[0046] According to at least one embodiment, the current-limiting regions are arranged along a stripe or along multiple stripes. Optionally, the current-limiting regions are arranged along a column or along multiple columns in a top view, with the stripes and columns being oriented perpendicular to each other. In the case of multiple first regions, this can apply to each of the first regions, with each first region being assigned multiple current-limiting regions.

[0047] According to at least one embodiment, when viewed from the top of the semiconductor body, the current-constraining regions are shaped as at least one of a triangle, a square, a rectangle, a hexagon, and a circle. When viewed from the top, all of the current-constraining regions can have the same shape and / or area. Alternatively, current-constraining regions of different shapes and / or sizes can be combined with one another per first region.

[0048] Additionally, a method for manufacturing a semiconductor device is provided, by which a semiconductor device is manufactured as set forth in connection with at least one of the above-described embodiments, and therefore features of the semiconductor device are also disclosed for the method, and vice versa.

[0049] In at least one embodiment, the manufacturing method is for manufacturing a semiconductor device. The method may include, for example, in the listed order: providing a semiconductor body; forming a first region and a well region in a semiconductor body; Etching at least one recess in the first region to create at least one current-constraining region, and filling the at least one recess with at least one electrically insulating material; applying a gate insulating layer to the semiconductor body; applying a gate electrode and a first electrode to the semiconductor; Includes:

[0050] According to at least one embodiment, at least one recess is etched into the semiconductor body, and then at least a portion of the doping for the first region is applied into the semiconductor body through the at least one recess. That is, by forming the at least one recess, at least one deeper region of the semiconductor body is exposed, and then the dopant for the first region is provided in this at least one deeper region. Thus, for example, a relatively deep doping can be achieved with moderate ion energy in ion implantation or moderate time and / or temperature in diffusion doping.

[0051] According to at least one embodiment, at least a portion of the doping of the first region is applied between etching the at least one recess and applying the at least one electrically insulating material to the at least one recess. Thus, forming the at least one current-limiting region can be divided into substeps that are not necessarily sequential.

[0052] According to at least one embodiment, the method further includes forming at least one plug region in the semiconductor body, the at least one plug region being of the second conductivity type and having a maximum doping concentration greater than a maximum doping concentration of the well region, the at least one plug region being for electrically contacting the well region, for example, by a first electrode.

[0053] According to at least one embodiment, the first region extends deeper into the semiconductor body than the at least one plug region.

[0054] According to at least one embodiment, creating the first region includes two different doping steps such that the doping profile of the first region in cross section is stepped, i.e., the first region can widen towards the top surface.

[0055] The semiconductor devices and methods described herein will be explained in more detail below by way of exemplary embodiments with reference to the drawings. In the individual figures, like elements are designated by like reference numerals. However, the relationships between elements are not shown to scale, and rather, individual elements may be exaggerated to facilitate understanding. [Brief explanation of the drawings]

[0056] [Figure 1] 1 is a schematic cross-sectional perspective view of an exemplary embodiment of a semiconductor device described herein. [Figure 2]1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 4] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 5] 1 is a schematic cross-sectional perspective view of an exemplary embodiment of a semiconductor device described herein. [Figure 6] 1 is a schematic cross-sectional perspective view of an exemplary embodiment of a semiconductor device described herein. [Figure 7] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 8] 1 is a schematic diagram of a simulated electrical characteristic of a semiconductor device described herein compared to a corresponding semiconductor device without at least one current-constraining region. [Figure 9] 1 is a schematic diagram of a simulated electrical characteristic of a semiconductor device described herein compared to a corresponding semiconductor device without at least one current-constraining region. [Figure 10] 1 is a schematic diagram of a simulated electrical characteristic of a semiconductor device described herein compared to a corresponding semiconductor device without at least one current-constraining region. [Figure 11] 1 is a schematic diagram of a simulated electrical characteristic of a semiconductor device described herein compared to a corresponding semiconductor device without at least one current-constraining region. [Figure 12] 1 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device as described herein. [Figure 13] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein. [Figure 14] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein. DETAILED DESCRIPTION OF THE INVENTION

[0057] 1 shows an exemplary embodiment of a semiconductor device 1. The semiconductor device 1 comprises a semiconductor body 2, for example of SiC. The semiconductor body 2 includes a first region 21, a well region 22, and a drift region 23. A plug region 25 is provided for making electrical contact with the well region 22.

[0058] The semiconductor device 1 further comprises a gate electrode 33 separated from the semiconductor body 2 by a gate insulating layer 4. There is also a first electrode 31, which is in electrical contact with the first region 21 and the plug region 25. The gate insulating layer 4 and the first electrode 31 are located on a top surface 20 of the semiconductor body 2. The top surface 20 is planar. The gate electrode 33 and the first electrode 31 may each extend along a straight line that is perpendicular to the cross section shown in FIG.

[0059] For example, the first region 21 and the drift region 23 are n-doped, and the well region 22 and the plug region 25 are p-doped. If the semiconductor device 1 is an insulated-gate bipolar transistor (IGBT) or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), the first region 21 is an emitter region and the first electrode 31 is an emitter electrode. If the semiconductor device 1 is a junction gate field-effect transistor (JFET), a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET), the first region 21 is a source region and the first electrode 31 is a source electrode.

[0060] The first region 21 includes a current limiting region 5. The current limiting region 5 is made of an electrically insulating material, such as SiO2. The current limiting region 5 extends along a straight line parallel to the gate electrode 33 and the first electrode 31. The current limiting region 5, like the first region 21, is located directly on the upper surface 20.

[0061] The depth of first region 21 into semiconductor body 2 begins at top surface 20 and exceeds the depth of current confinement region 5 into semiconductor body 2. When viewed in cross section, first region 21 extends all the way around current confinement region 5 towards well region 22 in which first region 21 is embedded.

[0062] Optionally, the at least one current-limiting region 5 is arranged in mirror symmetry with respect to the first region 21 in top view and in cross section. For example, in top view of the top surface 20, the current-limiting region 5 is arranged symmetrically within the first region 21 and between the electrodes 31, 33. Thus, there may be a line of mirror symmetry M with respect to the current-limiting region 5 and the first region 21.

[0063] Thus, Figure 1 shows the basic concept of the proposed semiconductor device 1, where recesses are etched inside the first region 21. The etched and filled recesses can have different shapes and depths and can be uniform or non-uniform along the direction perpendicular to the cross section of Figure 1 (see also Figures 2 to 7 below).

[0064] In at least one proposed current-limiting region 5, the total source area or emitter area is reduced and the channel-contact path for carriers is increased. Both effects contribute to the source resistance R S or a corresponding increase in the value of the emitter resistance R S Increasing the value of increases the saturation current I SAT The depth d of the current-limiting region 5 along the cross section of FIG. 1 parallel to the upper surface 20 and its length L are set to the nominal condition, e.g., the total R DS,on The ion implantation current may be suitably designed to achieve the desired effect on short circuit current while keeping its effect negligible during conduction in the ion implantation current.

[0065] The semiconductor device 1 of Fig. 1 has a planar design. In contrast to that, the semiconductor device 1 of Fig. 2 has a trench design. The gate electrode 33 and the gate insulating layer 4 are therefore at least partially located in a trench into the semiconductor body 2. The top surface 20 is therefore not planar, in contrast to the case of Fig. 1, since it is penetrated by a trench. The gate electrode 33, for example, starts at the top surface 20 and extends deeper into the semiconductor body 2 than the well region 22.

[0066] 2 further shows that there are a plurality of first regions 21, and therefore current-limiting regions 5, arranged symmetrically with respect to the gate electrode 33. There may be a plurality of units shown in FIG. 2 adjacent to each other, so that there may be a plurality of stripes of gate electrode 33 and first electrode 31 extending perpendicular to the projection plane of FIG.

[0067] This symmetrical arrangement of FIG. 2 (see also FIG. 13) and / or the trench design of FIG. 2 can of course be applied to all other embodiments as well.

[0068] The current-limiting region 5 per first region 21 in FIG. 2 has the same design as in FIG. 1, i.e., a trough design with a rectangular parallelepiped shape. According to FIG. 2, the trough has sharp edges and corners. According to FIG. 1, the trough has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of the at least one current-limiting region 5.

[0069] 2 further shows that there is a second electrode 32 and that the semiconductor body 2 includes a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, and 25 are formed by growth and / or doping, such as ion implantation. In the case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode, and the second region is a collector region of the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is a drain electrode, and the second region is a drain region of the same doping type as the first region. This is also true for all other embodiments of the semiconductor device 1. For example, in FIG. 1, the second region 24 and the second electrode 32 can be present directly on the side of the drift region 23 facing outward from the top surface 20, as in FIG. 2.

[0070] Furthermore, according to Fig. 2, the plug region 25 starts from the top surface 20 and reaches deeper into the semiconductor body 2 than the first region 21. Otherwise, with reference to Fig. 1, the plug region 25 can have the same depth as the first region 21, or it can be shallower or deeper than the first region 21. Both possibilities can be applied to all embodiments.

[0071] 1, in FIG. 2 at least one current-confining region 5 per first region 21 is spaced apart from the first electrode 31, the gate electrode 33 and the gate insulating layer 4. In FIG.

[0072] For example, the maximum doping concentration of the first region 21, the second region 24, and the at least one plug region 25 is at least 1×10 18 cm -3 , or at least 5 × 10 18 cm -3 , or at least 1 × 10 19 cm -3 , and / or up to 5 × 10 20 cm -3 , or up to 2×10 20 cm -3 , or up to 1×10 20 cm -3Furthermore, the maximum doping concentration of the well region 22, and therefore the channel region adjacent to the gate insulating layer 4, is at least 5×10 16 cm -3 or at least 1×10 17 cm -3 and / or up to 5×10 19 cm -3 or up to 5×10 18 cm -3 Depending on the voltage class of the semiconductor device 1, the maximum doping concentration of the drift region 23 may be at least 1×10 11 cm -3 , or at least 1 × 10 12 cm -3 , or at least 1 × 10 13 cm -3 , and / or up to 1 × 10 17 cm -3 , or up to 5×10 16 cm -3 , or up to 1×10 16 cm -3 The thickness of the gate insulating layer 4 may be, for example, 10 nm to 250 nm, or 80 nm to 150 nm. These parameters may also be applied individually or collectively to all other embodiments.

[0073] Otherwise, the same applies to Figure 2 as to Figure 1, and vice versa. 3 and 4, similar to FIG. 1, there is one current-limiting region 5 per first region 21. The current-limiting regions 5 may be arranged in mirror symmetry with respect to the first region 25, with the axis of mirror symmetry extending perpendicular to the top surface 20.

[0074] In contrast to what is shown in Figure 1, according to Figures 3 and 4, the current confinement region 5 extends beyond the gate insulating layer 4 and the gate electrode 33. Such an arrangement is also possible in all other embodiments. Alternatively, in contrast to what is shown in Figures 3 and 4, the current confinement region 5 may be located non-mirror symmetrically within the first region 21 such that the current confinement region 5 terminates away from the gate insulating layer 4 and therefore does not extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0075] 3, the current-confining region 5 is formed as a shallow trough within the first region 21, which is also formed as a single trough. The depth d of the current-confining region 5 is, for example, 10% to 90% or 40% to 80% of the depth D of the first region 21. The first region 21 and the plug region 25 may have the same depth, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 μm and / or at most 2 μm.

[0076] According to FIG. 4 , the current-confining region 5 is formed as a deep trough within the first region 21, which is formed as two troughs, one above the other, with the trough adjacent to the top surface 20 having a larger extent parallel to the projection plane of FIG. 4 . Again, the maximum depth d of the current-confining region 5 can be 10% to 90%, or 40% to 80%, of the total depth D of the first region 21, which is made up of two troughs. Due to the design with two stacked troughs, the first region 21 can extend deeper into the semiconductor body 2 than the plug region 25. The plug region 25 can be as deep as the trough of the first region 21 adjacent to the top surface 20, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.2 μm and / or at most 4 μm.

[0077] For example, the troughs next to the upper surface 20 are first formed by corresponding doping, then recesses for the current-limiting regions 5 are formed, and then doping for the troughs further from the upper surface 20 is provided through the recesses before the electrically insulating material is applied. Thus, the trough in FIG. 4 has a stepped design when viewed in cross section. Otherwise, in the configuration of FIG. 4, deep troughs having a rectangular shape with rounded corners, as shown in FIG. 3, for example, are also possible.

[0078] Both designs with shallow or deep first regions 21 as shown in Figures 3 and 4 are possible in all other embodiments.

[0079] For example, the length L of the current-limiting region 5 is 10% to 90%, or 40% to 80%, or 50% to 70% of the width B of the first region 21. This is also possible in all other embodiments.

[0080] Otherwise, the same applies to Figures 3 and 4 as to Figures 1 and 2, and vice versa.

[0081] 5-7, there are multiple current-limiting regions 5 per first region 21. With respect to the parameters d, D, B, and L described above for the case of a single current-limiting region 5 per first region 21, the same applies to the case of multiple current-limiting regions 5 per first region 21, with L corresponding to the total width of all the respective current-limiting regions 5. Compare, for example, FIG. 6. With multiple current-limiting regions 5, there are more design parameters to achieve an optimized first region.

[0082] In the case where there is only one current-confining region 5 in the direction perpendicular to the gate electrode 33 and / or first electrode 31, referring to FIG. 5, the total width L is the same as the width W of the individual insulating current-confining region 5 as shown in FIG. 4.

[0083] However, according to Figure 5, there is one stripe of subsequent current-limiting regions 5 extending parallel to electrodes 31, 33. In top view, current-limiting regions 5 are rectangular or square in shape, optionally with rounded corners, each having a width W and a length range V. For example, V is 0.5L to 100L, or 0.5L to 10L, or 0.7L to 5L.

[0084] For example, the distance Zs between adjacent current-constraining regions 5 along a stripe may be 10% to 75% or 10% to 40% of the width W and / or length V. The individual current-constraining regions 5 within a stripe may be spaced equidistantly or at different distances from each other than those shown in FIG. 5. These aspects, individually or collectively, may also apply to all other embodiments.

[0085] Other than as shown, the current-limiting region 5 does not have to be square in shape in top view, but may be rectangular, hexagonal, regular or irregular polygonal, or circular in top view, as in all other embodiments.

[0086] 5 to 7, all the current-limiting regions 5 per first region 21 have the same shape. This is not essential. That is, current-limiting regions 5 of different shapes may be combined within one first region 21.

[0087] There can be N stripes of current-limiting regions 5 between the electrodes 31 and 33, where N is a natural number greater than or equal to 2. For example, N can be up to 10 or up to 4. In the example of FIG. 6, N is 2. For example, 0.1 B / N≦W≦0.99 B / N, 0.4 B / N≦W≦0.95 B / N, or 0.7 B / N≦W≦0.90 B / N. Alternatively or additionally, the distance Zt between adjacent current-limiting regions 5 in the transverse direction perpendicular to the stripes is 10% to 75% or 10% to 40% of the length range V. Alternatively or additionally, for example, 0.1 B / N≦V≦100 B / N, 0.4 B / N≦V≦10 B / N, or 0.7 B / N≦V≦5 B / N may apply. The current-limiting regions 5 can be arranged equidistantly parallel and perpendicular to the electrodes 31 and 33.

[0088] As shown in Figure 6, all N stripes have the same number of current-limiting regions 5, so that in each case there are K current-limiting regions 5 adjacent to each other in the direction parallel to the stripes. This results in a regular array of N x K current-limiting regions 5, all of which have the same shape.

[0089] However, this is not required. That is, current-constraint regions 5 of different shapes and sizes can be combined, and different numbers K of current-constraint regions 5 can be provided per stripe, and / or different numbers N of current-constraint regions 5 in the direction parallel to the width L. For example, current-constraint regions 5 of different widths W can be provided, such that, as an example, there can be rows parallel to the direction along the width L having a single wide current-constraint region 5 alternating with rows having multiple narrower current-constraint regions 5.

[0090] In Figure 7, N is shown to be 3. Optionally, the stripes furthest from the first electrode 31 reach beyond the gate insulating layer 4. However, other than as shown in Figure 7, all stripes may be further from the gate electrode 33, for example in a top view of the top surface 20.

[0091] Each of the stripes in Figure 7 can be made up of multiple current-constraining regions 5 as in Figures 5 and 6, or there can be only a single current-constraining region 5 per stripe as in Figures 1-4, and similarly for all other embodiments.

[0092] The current restriction regions 5 in Figures 5 to 7 are of shallow design, for example compared to Figure 3 above. It is also possible that all or some of the current restriction regions 5 per first region 21 are of deep design, as shown in connection with Figure 4.

[0093] Otherwise, the same applies to Figures 5-7 as to Figures 1-4, and vice versa.

[0094] Figures 8 to 11 show the gate-source voltage V GS Simulated isothermal power J at 15V and 300K D Against V DS and the drain-source voltage V of the semiconductor device 1, E1, in Figure 1, compared to the corresponding reference MOSFET design 9 without the current-limiting region. DS = 600V and V GS、スイング 1 and 2. The electrical and thermal short-circuit waveforms are shown at VDD = -5V / +15V. See Figures 8 and 9. Figures 10 and 11 show corresponding data for two semiconductor devices E1, E2, and E3, which have deep current-limiting regions 5 as shown in Figure 4. For device E1 corresponding to Figure 1, the quotient d / D of the depth d of the current-limiting region 5 to the depth D of the first region 21 is 0.65. Devices E2 and E3 corresponding to Figure 4 have quotients d / D of 1.40 and 2.00, respectively, where D refers to the depth of the first region 21 in Figure 1. The quotient L / B of the length L of the current-limiting region 5 to the width B of the first region 21 is 0.5.

[0095] Maximum saturation current during short circuit I SAT、ピーク The achieved reduction in the on-state resistance R DS,on Note that the increase in I is greater than the increase in I. SATSince the maximum value of .DELTA..times ...

[0096] 12 shows a method for manufacturing a semiconductor device 1. In method step S1, a semiconductor body 2 is provided. For example, the semiconductor body 2 provides a drift region 23. Then, in method step S2, a first region 21 and a well region 22 are formed in the semiconductor body 2 and in a plug region 25.

[0097] Next, in step S3, at least one recess is etched in the first region 21 and the at least one recess is filled with at least one electrically insulating material to create at least one current-limiting region 5 per first region 21.

[0098] Next, in step S4, a gate insulating layer 4 is applied, followed by a step S5 in which a gate electrode 33 and a first electrode 31, and optionally a second electrode 32, are applied to the semiconductor body 2.

[0099] The method steps do not necessarily have to be performed in the order described. Furthermore, the method steps may be intermixed, for example some of the electrodes 31, 32, 33 may be applied before etching and some of the electrodes 31, 32, 33 may be applied after etching.

[0100] An example of a semiconductor device 1 is shown in top view in Figure 13. It can be seen that the stripes of gate electrode 33 are located symmetrically, for example, between two stripes of the first electrode 31 halves and therefore between two stripes of the first region 21 having the current-limiting region 5. The structure in Figure 13 corresponds to unit cells that can be multiplied so that multiple unit cells can be placed adjacent to each other.

[0101] This stripe design is equally applicable to the embodiments of Figures 1 and 3 to 7. In Figure 2, a symmetrical design of this kind is already shown.

[0102] Otherwise, the same applies to Figures 1-12 as to Figure 13, and vice versa.

[0103] 14, the semiconductor device 1 can also have a cellular design when viewed from above, such that rectangular or square unit cells can be produced. For example, a unit cell has a first electrode 31 at its center, surrounded by a gate electrode 33. Such unit cells can be arranged two-dimensionally, such that the semiconductor device 1 can include many such unit cells.

[0104] Otherwise, the same applies to FIG. 14 as to FIG. 13, and vice versa.

[0105] Components shown in the figures illustratively follow one another directly in the designated order, unless otherwise indicated. Components that are not touching in the figures are illustratively spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the orientation of the drawn components relative to one another is accurately reproduced in the figures.

[0106] It should be noted that the invention described herein is not limited by the description based on the exemplary embodiments, but rather the invention encompasses any novel feature and any combination of features, including any combination of features in the claims, even if the feature or combination itself is not explicitly named in the claims or exemplary embodiments. [Explanation of symbols]

[0107] List of Reference Numbers 1. Semiconductor devices 2. Semiconductor body 20 top surface of semiconductor body 21 First region (source region or emitter region) 22 well area 23 Drift Region 24 Second region (drain region or collector region) 25 plug area 31 First electrode (source electrode or emitter electrode) 32 Second electrode (drain electrode or collector electrode) 33 gate electrode 4 Gate insulating layer 5 Current Limit Area 9 Comparative Examples of Semiconductor Devices B Width of the first area d Depth of the current limiting region D Depth of the first region E1 First example of a semiconductor device E2 First example of a semiconductor device E3 First example of a semiconductor device L Length of the current limiting area M Mirror symmetry line S. Method Steps T is the time in microseconds J D Current density in the drain region (A / cm 2 ) V DS Voltage between the drain and source electrodes (V) V Length range of current limiting area W has an insulating current limiting area Zs: Distance between current-limiting regions along the stripe Zt: Distance between current-restricted regions in the transverse direction

Claims

1. A semiconductor device (1) comprising a semiconductor body (2), a gate electrode (33) and a first electrode (31), the semiconductor body (2) comprises a first region (21) which is a source region or an emitter region, and a well region (22) located adjacent to the first region (21), the first region (21) being of a first conductivity type and the well region (22) being of a different second conductivity type; the well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by a gate insulating layer (4); The first region (21) is electrically contacted by the first electrode (31), which is a source electrode or an emitter electrode; The first region (21) has at least one current limiting region (5), A semiconductor device (1), wherein said at least one current-limiting region (5) consists of at least one electrically insulating material.

2. 10. The semiconductor device (1) of claim 9, wherein, in a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap the first region (21), and the at least one current confinement region (5) is spaced apart from the gate electrode (33) and the first electrode (31).

3. 10. The semiconductor device (1) according to claim 9, wherein, in a top view of the semiconductor body (2), the first region (21) extends completely between the at least one current limiting region (5) and the first electrode (31), and between the at least one current limiting region (5) and the gate electrode (33), and the at least one current limiting region (5) is located between the first electrode (31) and the gate electrode (33).

4. 10. The semiconductor device (1) of claim 9, wherein, when viewed in a cross section of the semiconductor body (2) through the first region (21) and through the gate electrode (33), the first region (21) extends entirely around the at least one current limiting region (5) in a direction towards the well region (22) such that the first region (21) is embedded in the well region (22) and the at least one current limiting region (5) is embedded in the first region (21).

5. 10. The semiconductor device (1) according to any one of the preceding claims, wherein the volume of the at least one current-limiting region (5) is at least 10% and at most 95% of the total volume of the at least one current-limiting region (5) together with the first region (21).

6. the at least one current-limiting region (5) is a metal oxide or a semiconductor oxide; the at least one current limiting region (5) is at least one recess in the first region (21), and the at least one electrically insulating material fills the at least one recess; the at least one electrically insulating material aligns with and terminates in the first region (21); A semiconductor device (1) according to any one of the preceding claims.

7. the semiconductor body (2) further comprises a drift region (23) of the first conductivity type and also a second region (24) which is a drain region or a collector region, the drift region is located between the well region (22) and the second region (24); The semiconductor device (1) further comprises a second electrode (32) which is a collector electrode or a drain electrode, the second electrode (32) being located on a side of the second region (24) farther from the drift region (23); The semiconductor body (2) is SiC, A semiconductor device (1) according to any one of the preceding claims.

8. In a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, and the first region (21) extends parallel to the gate electrode (33) and the first electrode (31), or In a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each comprise a plurality of subsections arranged along at least one arrangement line, and the first region (21) extends between adjacent subsections of the gate electrode (33) and the first electrode (31). A semiconductor device (1) according to any one of the preceding claims.

9. 10. The semiconductor device (1) according to any one of the preceding claims, wherein the gate insulating layer (4) and the gate electrode (33) are of planar design so as to be applied to a planar portion of a top surface (20) of the semiconductor body (2), and the first region (21) is located on the top surface (20).

10. 9. The semiconductor device (1) according to any one of claims 1 to 8, wherein the semiconductor device (1) is of trench design such that the gate insulating layer (4) and the gate electrode (33) are at least partially arranged in a trench in the semiconductor body (2), the depth of the trench starting from the top surface (20) of the semiconductor body (2) and exceeding the depth of the well region (22), and the first region (21) being located at the top surface (20).

11. 10. The semiconductor device (1) according to any one of the preceding claims, wherein there is exactly one current-limiting region (5) in the first region (21).

12. The semiconductor device (1) according to any one of claims 1 to 10, wherein there are a plurality of the current limiting regions (5) in the first region (21), and the current limiting regions (5) are spaced apart from one another in a top view of the semiconductor body (2).

13. 10. The semiconductor device (1) according to the preceding claim, wherein the current confinement region (5) is arranged along a stripe or along multiple stripes.

14. 10. The semiconductor device (1) of claim 1, wherein, in a top view of the semiconductor body (2), the current confinement region (5) is shaped as at least one of a triangle, a square, a rectangle, a hexagon, and a circle.

15. 10. A method for manufacturing a semiconductor device (1) according to any one of the preceding claims, said method comprising the steps of: providing said semiconductor body (2); forming the first region (21) and the well region (22) in the semiconductor body (2); Etching at least one recess in said first region (21) so as to create said at least one current limiting region (5), and filling said at least one recess with said at least one electrically insulating material; applying said gate insulating layer (4) to said semiconductor body (2); applying said gate electrode (33) and said first electrode (31) to said semiconductor body (2); A method comprising:

16. 10. The method according to the preceding claim, wherein the at least one recess is etched into the semiconductor body (2), then at least a part of the doping of the first region (21) is applied through the recess into the semiconductor body (2), and then the at least one electrically insulating material is filled into the at least one recess.

17. forming at least one plug region (25) in the semiconductor body (2), the at least one plug region (25) being of a second conductivity type and having a maximum doping concentration higher than a maximum doping concentration of the well region (22), the at least one plug region (25) being for electrically contacting the well region (22); the first region (21) extends deeper into the semiconductor body (2) than the at least one plug region (25); A method according to any one of the preceding two claims.

18. 10. The method of claim 1, wherein creating the first region (21) comprises two different doping steps, such that the doping profile of the first region (21) in cross section is stepped.

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