Single-die reinforced galvanic isolation device

Abstract

A microelectronic device (100) includes an insulating device (101). The insulating device includes a lower insulating element (119), an upper insulating element (148), and an inorganic dielectric plateau (152) between the lower and upper insulating elements. The inorganic dielectric plateau includes an upper etch stop layer (136) and a lower etch stop layer (129) between the upper and lower insulating elements. The upper etch stop layer provides an endpoint signal during a plateau etch process (161), which provides feedback regarding the amount of inorganic dielectric plateau that has been etched. The lower etch stop layer (129) provides an etch stop function, ensuring complete plateau etching (161) and protecting the underlying metal bond pad (122). The inorganic dielectric plateau includes alternating layers of high-stress silicon dioxide (141) and low-stress silicon dioxide (132), which provide a means for strengthening the inorganic dielectric plateau.

Description

[Technical Field]

[0001] This description relates to the field of microelectronic devices. More particularly, but not exclusively, this description relates to galvanic isolation devices in microelectronic devices. [Background technology]

[0002] Galvanic isolation is the principle of isolating functional sections of an electrical system to prevent current flow, while energy or information can still be exchanged between sections by other means, such as capacitance, induction, electromagnetic waves, optical, acoustic, or mechanical means. Galvanic isolation can be used when two or more electrical circuits communicate, but their ground or reference nodes may be at different potentials. It is an effective way to break ground loops by preventing unwanted current from flowing between two units that share a reference conductor. Galvanic isolation is also used for safety purposes as a means to prevent accidental current from passing through a person's body and reaching ground.

[0003] An insulator is a device designed to allow data and power transmission between two systems or circuits while minimizing direct current and unwanted transient currents between them. In most applications, insulators act as a barrier to high voltages in addition to allowing the systems to function properly. When capacitive elements are used as insulators, dielectric breakdown is a major concern, especially in high-voltage applications.

[0004] As advances in integrated circuit and semiconductor manufacturing design continue, improvements in microelectronic devices, including galvanic isolation, are simultaneously pursued. Summary of the Invention

[0005] The following presents a simplified summary of the invention in order to provide a basic understanding of one or more aspects of the present invention patent description. This summary is not intended to be an extensive overview of the description, to identify key or critical elements of the description, or to delineate its scope. Rather, the primary purpose of this summary is to present some concepts of the description in a simplified form as a prelude to the more detailed description that is presented later.

[0006] An example of a microelectronic device including a galvanic isolation device, hereinafter referred to as an isolation device, is described. The isolation device includes a lower insulating element, hereinafter referred to as a lower metal coil, an upper insulating element, hereinafter referred to as an upper metal coil, and an enhanced galvanic isolation device inorganic dielectric stack, hereinafter referred to as a plateau between the lower and upper metal coils. The plateau includes an upper etch stop layer and a lower etch stop layer between the upper and lower metal coils within the plateau. The upper etch stop layer provides an electrical signal in the plateau etch process that provides feedback regarding the amount of plateau etched. The lower etch stop layer provides an etch stop function that provides a complete plateau etch and protection of the underlying metal bond pad. The combination of the upper and lower bond pads is advantageous because it provides a means for forming a very thick (greater than 10 micrometers) plateau between the upper and lower metal coils. The plateau also includes alternating layers of high stress silicon dioxide and low stress silicon dioxide, which provide a means of strengthening the plateau that improves its crack resistance. [Brief explanation of the drawings]

[0007] The presently described embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to like elements. Also, references to "an" or "one" example in this description are not necessarily to the same example, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with one example, it is understood that it is within the knowledge of one skilled in the art to implement such feature, structure, or characteristic in connection with other examples, whether or not explicitly described.

[0008] The accompanying drawings are incorporated into and form a part of this specification to illustrate one or more examples of the present description. Various advantages and features of the present description will arise from the following detailed description, taken in conjunction with the appended claims and with reference to the accompanying drawings.

[0009] [Figure 1A] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1B] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1C] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1D] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1E] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1F] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1G] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1H]1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1I] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1J] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1K] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1L] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1M] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1N] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1O] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1P] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1Q] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1R] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1S] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation. [Figure 1T] 1A-1D are cross-sectional views of an exemplary microelectronic device comprising an insulating device shown in successive stages of an exemplary method of formation.

[0010] [Figure 2]1 shows a perspective view of a microelectronic device including an insulating device. DETAILED DESCRIPTION OF THE INVENTION

[0011] Examples of the present description are described with reference to the accompanying figures. The figures are not drawn to scale and are provided merely to illustrate the present description. Several aspects of the present description are described below in connection with example applications for illustration. Many specific details, relationships, and methods are set forth to provide an understanding of the present description. The description is not limited to the order of acts or events shown, as some acts may occur in different orders and / or concurrently with other acts or events. Additionally, not all shown acts or events are required to implement the methodology described.

[0012] The following co-pending patent applications have related subject matter and are incorporated herein by reference: U.S. Patent Application No. 17 / 957,847 (Texas Instruments Docket No. T102472US01, West et al., entitled "Galvanic Isolation Device") and U.S. Patent Application No. 17 / 957,875 (Texas Instruments Docket No. T101074US01, West et al., entitled "Galvanic Isolation Device"), which are not admitted by reference in this paragraph to be prior art with respect to the present invention. [Patent Document 1] U.S. Patent Application No. 17 / 957,847 [Patent Document 2] U.S. Patent Application No. 17 / 957,875

[0013] The following co-pending patent applications have related subject matter and are incorporated herein by reference: U.S. Provisional Patent Application No. 63 / 377,877 (Texas Instruments Docket No. T101057US01), U.S. Provisional Patent Application No. 63 / 411,934 (Texas Instruments Docket No. T92887US01), U.S. Provisional Patent Application No. 63 / 411,942 (Texas Instruments Docket No. T92904US01), U.S. Provisional Patent Application No. 63 / 411,952 (Texas Instruments Docket No. T100209US01), and U.S. Provisional Patent Application No. 63 / 411,961 (Texas Instruments Docket No. T102233US01). These patent applications are not admitted to be prior art with respect to the present invention by reference in this paragraph. [Patent Document 3] U.S. Provisional Patent Application No. 63 / 377,877 [Patent Document 4] U.S. Provisional Patent Application No. 63 / 411,934 [Patent Document 5] U.S. Provisional Patent Application No. 63 / 411,942 [Patent Document 6] U.S. Provisional Patent Application No. 63 / 411,952 [Patent Document 7] U.S. Provisional Patent Application No. 63 / 411,961

[0014] Additionally, while some of the examples shown herein are shown in two-dimensional views with various regions having depths and widths, these regions are only illustrative of portions of devices that are actually three-dimensional structures. Thus, when fabricated on an actual device, these regions have three dimensions, including length, width, and depth. Additionally, while the present invention is illustrated by examples directed to active devices, these examples do not limit the scope or applicability of the present invention. Active devices of the present invention are not limited to the physical structures shown. These structures are included to demonstrate the utility of the present invention and its application to the presently preferred examples.

[0015] The exemplary microelectronic devices described hereinafter may include or be formed from semiconductor materials such as silicon (Si), silicon carbide (SiC), silicon germanium (SiGe), gallium arsenide (GaAs), or organic semiconductor materials. The semiconductor materials may be embodied as semiconductor wafers. The microelectronic devices include one or more galvanically isolated devices. The microelectronic devices may also include one or more semiconductor components, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistor (IGBT) gate drivers, input / output and control circuitry, and microprocessors, microcontrollers, and / or microelectromechanical components or systems (MEMS). The microelectronic devices may be manifested as single-chip devices or may be included in multi-chip modules (MCMs). The semiconductor chips may further include inorganic and / or organic materials that are not semiconductors, e.g., insulators such as inorganic dielectric materials or polymers, or conductors such as metals.

[0016] For purposes of this description, the term "high voltage" refers to an operating potential greater than 450 volts, and the term "low voltage" refers to an operating potential less than 100 volts. For example, the high voltage portion of an isolation device may operate between 450 volts and 1200 volts, and the low voltage portion of an isolation device may operate between 1.5 volts and 30 volts.

[0017] It should be noted that terms such as top, bottom, front, back, on, above, below, and below may be used herein. These terms do not limit the location or orientation of a structure or element, but rather provide a spatial relationship between structures or elements. Similarly, terms such as "inward" and "outward" refer to directions toward and away from, respectively, the geometric center of a device or area and designated portions of a device or area.

[0018] For purposes of this description, the term "lateral" refers to a direction parallel to the plane of the top surface of the microelectronic device, and the term "vertical" refers to a direction perpendicular to the plane of the top surface of the microelectronic device.

[0019] For purposes of this specification, the term "conductive" should be interpreted as "electrically conductive." The term "conductive" refers to materials and structures that are capable of supporting a steady state electrical current, such as direct current (DC).

[0020] For purposes of this specification, the "dielectric constant" of a material refers to the ratio of the (absolute) dielectric constant of the material to the dielectric constant of a vacuum at frequencies below 1 Hertz (Hz). The vacuum dielectric constant is approximately 8.85×10 -12 It is measured in farads per meter (F / m).

[0021] For purposes of this specification, unless otherwise specified, the term high stress silicon dioxide refers to a silicon dioxide layer having a stress between -150 MPa and -80 MPa, and the term low stress silicon dioxide refers to a silicon dioxide layer having a stress between -60 MPa and -10 MPa, with negative stress implying compressive stress and positive stress implying tensile stress.

[0022] FIG. 1A is a cross-sectional view of a portion of an isolation device 101 after formation of a first level interconnect 106 of an exemplary microelectronic device 100. The microelectronic device 100 may be implemented as part of a multi-chip array to provide galvanic isolation between high-voltage and low-voltage components. The isolation device 101 in this example is a transformer, but may also include capacitors, magnetic insulators, optical insulators, thermal insulators, or other elements requiring galvanic isolation between high-voltage and low-voltage elements. The microelectronic device 100 is formed on a substrate 102, which may be part of a semiconductor wafer or may include additional microelectronic devices. The substrate 102 comprises a semiconductor material. The semiconductor material may include crystalline silicon or another semiconductor material, such as silicon germanium, silicon carbide, gallium nitride, or gallium arsenide, by way of example.

[0023] A pre-metal dielectric (PMD) layer 104 is formed on the substrate 102. The PMD layer 104 includes one or more dielectric layers of silicon dioxide, phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), organosilicate glass (OSG), low-k dielectric materials, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, or other dielectric materials. The PMD layer 104 is formed by one or more dielectric deposition processes, such as a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a high-aspect-ratio process (HARP) using ozone and tetraethyl orthosilicate (TEOS), a high-density plasma deposition (HDP), or an atmospheric pressure chemical vapor deposition (APCVD) process.

[0024] Contacts 105 of the first-level interconnect 106 are formed through the PMD layer 104 for electrical connection to the substrate 102. The contacts 105 are electrically conductive and may include tungsten on a titanium adhesion layer and may include a titanium nitride liner. The contacts 105 may be formed by etching contact holes through the PMD layer 104 and forming the titanium adhesion layer by a physical vapor deposition (PVD) process. A titanium nitride liner may be formed on the titanium adhesion layer by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. Tungsten may be formed on the titanium nitride liner by an organic metallization chemical vapor deposition (MOCVD) process using tungsten hexafluoride reduced by silane and hydrogen. The tungsten, titanium nitride, and titanium on the top surface of the PMD layer 104 outside the contacts 105 may be removed by a tungsten etch-back process, a tungsten chemical-mechanical polishing (CMP) process, or both.

[0025] By way of example, the metallization of the insulating device 101 is described with an etched aluminum-based interconnect system. The insulating device 101 may also be formed using a copper-based interconnect system. First-level interconnects 106 are formed on the PMD layer 104 and make electrical connections to the contacts 105. The first-level interconnects 106 are electrically conductive. The first-level interconnects 106 may have an etched aluminum structure and may include a titanium nitride or titanium tungsten adhesion layer (not shown) on the PMD layer 104, an aluminum layer (not shown) with a few atomic percent of silicon, titanium, or copper on the adhesion layer, and a titanium nitride antireflective layer (not shown) on the aluminum layer. Although not specifically shown, an etch mask is formed, followed by a reactive ion etching (RIE) process that etches the antireflective layer, aluminum layer, and adhesion layer in the locations exposed by the etch mask, followed by removal of the etch mask to form the first-level interconnects 106.

[0026] 1B-1D, a lower dielectric stack 123 is formed, which may include multiple dielectric layers and a second-level interconnect 113 layer. Formation of the lower dielectric stack 123 begins after the formation of the first-level interconnect 106, with a first interlevel dielectric layer (ILD) 107 being formed over the first-level interconnect 106. The first ILD layer 107 may include a multilayer silicon dioxide-based dielectric stack. The multilayer silicon dioxide-based dielectric stack is formed by depositing a 400 nm to 800 nm first gap-fill silicon dioxide layer 108 over the first-level interconnect 106 and the exposed PMD layer 104. A first high-stress silicon dioxide layer 109 is formed on the first gap-fill silicon dioxide layer 108 to a thickness of 1000 nm to 1500 nm, which is planarized by a chemical-mechanical planarization (CMP) step (not specifically shown) to leave a 600 nm to 800 nm stack of the first gap-fill silicon dioxide layer 108 and the first high-stress silicon dioxide layer 109 over the first-level interconnect 106. After the CMP step (not specifically shown), a 2000 to 2500 nm first low-stress silicon dioxide layer 110 is deposited by a PECVD or CVD process on the CMP-planarized first high-stress silicon dioxide layer 109. A second high-stress silicon dioxide layer 111 to a thickness of 200 nm to 500 nm is then deposited on the first low-stress silicon dioxide layer 110 to complete the first ILD layer 107.

[0027] After forming the first ILD layer 107, a first-level via 112 is formed in the first ILD layer 107 to provide electrical connection to the first-level interconnect 106. The first-level via 112 can be formed by etching a via hole through the first ILD layer 107 and forming a titanium adhesion layer by a physical vapor deposition (PVD) process. A titanium nitride liner can be formed on the titanium adhesion layer by atomic layer deposition (ALD) or chemical vapor deposition (CVD). Tungsten can be formed on the titanium nitride liner by a metalorganic chemical vapor deposition (MOCVD) process using tungsten hexafluoride reduced by silane and hydrogen. The tungsten, titanium nitride, and titanium on the top surface of the first-level via 112 outside the via hole can be removed by a tungsten etch-back process, a tungsten chemical-mechanical polishing (CMP) process, or both.

[0028] Referring to FIG. 1C , second-level interconnect 113 is formed on first ILD layer 107 to make electrical contact with first-level via 112. Second-level interconnect 113 is electrically conductive. Second-level interconnect 113 may have an etched aluminum structure, including a titanium nitride or titanium tungsten adhesion layer (not shown) on first ILD layer 107, an aluminum layer (not shown) with a few atomic percent of silicon, titanium, or copper on the adhesion layer, and a titanium nitride anti-reflective layer (not shown) on the aluminum layer. A second interconnect etch mask 114 is then formed, followed by a reactive ion etching (RIE) process that etches the anti-reflective layer, aluminum layer, and adhesion layer at locations exposed by the etch mask, and then removes the etch mask to form second-level interconnect 113. In this example, lower metal coil 119 of isolation device 101 may be formed within second-level interconnect 113, although it may also be formed at other levels. Also formed in second level interconnect 113 is a ground ring 120 (ground outside the plane of the cross section of FIG. 1C) for isolation device 101. A grounded second level interconnect fill metal 121 (ground outside the plane of the cross section of FIG. 1C) may be formed in the second level interconnect. A bottom bond pad 122 may also be formed in second level interconnect 113.

[0029] 1D-1H, a series of dielectric layers are deposited that form the plateau 152 of the isolation device 101 between the lower metal coil 119 shown in FIG. 1C and the upper metal coil 148 shown in FIG. 1I. Referring to FIG. 1D, a silicon nitride / silicon oxynitride bilayer 124 is formed on the second-level interconnect 113. The silicon nitride / silicon oxynitride bilayer 124 may include a silicon nitride layer and a silicon nitride layer. The silicon nitride layer has a thickness of 100 nm to 600 nm and a stress of -1 GPa to -100 MPa. The silicon oxynitride layer has a thickness of 300 nm to 1000 nm and a stress of -150 MPa to 0 MPa. A second gap-fill silicon dioxide layer 125 (in this example, HDP oxide) is formed on the silicon nitride / silicon oxynitride bilayer 124. The second gap-fill silicon dioxide layer 125 is deposited to a thickness of 1000 nm to 1800 nm.

[0030] 1E, a second low-stress silicon dioxide layer 126 is formed on the second gap-fill silicon dioxide layer 125. The second low-stress silicon dioxide layer 126 is deposited to a thickness of 2000 nm to 3000 nm. After deposition of the second low-stress silicon dioxide layer 126, the second low-stress silicon dioxide layer 126 is planarized using a CMP process 127.

[0031] Referring to FIG. 1F, an intermediate dielectric stack 128 including multiple dielectric layers is deposited. To form the intermediate dielectric stack 128, a lower etch stop layer, referred to herein as a first silicon oxynitride etch stop layer 129, is deposited on the second low-stress silicon dioxide layer 126. The first silicon oxynitride etch stop layer 129 is deposited by a CVD or PECVD process, has a thickness of 500 nm to 1500 nm, and has a stress of -120 MPa to 0 MPa. A third low-stress silicon dioxide layer 130 is deposited on the first silicon oxynitride etch stop layer 129. The third low-stress silicon dioxide layer 130 is deposited by a CVD or PECVD process, has a thickness of 2000 nm to 4000 nm. A third high-stress silicon dioxide layer 131 is deposited on the third low-stress silicon dioxide layer 130. The third high-stress silicon dioxide layer 131 is deposited by a CVD or PECVD process and has a thickness of 100 nm to 400 nm. A fourth low-stress silicon dioxide layer 132 is deposited on the third high-stress silicon dioxide layer 131. The fourth low-stress silicon dioxide layer 132 is deposited by a CVD or PECVD process and has a thickness of 2000 nm to 4000 nm. A fourth high-stress silicon dioxide layer 133 is deposited on the fourth low-stress silicon dioxide layer 132. The fourth high-stress silicon dioxide layer 133 is deposited by a CVD or PECVD process and has a thickness of 100 nm to 400 nm. A fifth low-stress silicon dioxide layer 134 is deposited on the fourth high-stress silicon dioxide layer 133. The fifth low-stress silicon dioxide layer 134 is deposited by a CVD or PECVD process and has a thickness of 2000 nm to 4000 nm. A fifth high-stress silicon dioxide layer 135 is deposited on the fifth low-stress silicon dioxide layer 134. The fifth high-stress silicon dioxide layer 135 is deposited by a CVD or PECVD process and has a thickness of 100 nm to 400 nm. An upper etch stop layer, referred to herein as a second silicon oxynitride etch stop layer 136, is deposited on the fifth high-stress silicon dioxide layer 135.The second silicon oxynitride etch stop layer 136 is deposited by a CVD or PECVD process, has a thickness of 100 nm to 400 nm, and has a stress of −120 MPa to 0 MPa.

[0032] 1G, the upper dielectric alignment photolithography layer 137 is patterned and exposed to provide upper dielectric alignment photolithography openings 138 in an etch mask and to generate alignment marks (not specifically shown) to enable alignment of the top metal interconnect 145 of the exemplary transformer to the second-level interconnect 113. Reactive ion etching is used to remove the second silicon oxynitride etch stop layer 136 and the fifth high-stress silicon dioxide layer 135 in the open areas. Portions of the fifth low-stress silicon dioxide layer 134 within the upper dielectric alignment photolithography openings 138 may also be removed by an RIE process. It is advantageous to provide alignment marks near the top of the plateau to facilitate acceptable alignment of the upper metal coil 148 and the lower metal coil 119.

[0033] Referring to FIG. 1H, a series of dielectric depositions forms an upper dielectric stack 139. Formation of the upper dielectric stack 139 begins with the formation of a sixth low-stress silicon dioxide layer 140 on the second silicon oxynitride etch stop layer 136 and on the fifth low-stress silicon dioxide layer 134 in the upper dielectric alignment photolithography opening 138. The sixth low-stress silicon dioxide layer 140 is deposited by a CVD or PECVD process and has a thickness of 2000 nm to 3000 nm. After the formation of the sixth low-stress silicon dioxide layer 140, a sixth high-stress silicon dioxide layer 141 is formed on the sixth low-stress silicon dioxide layer 140. The sixth high-stress silicon dioxide layer 141 is formed by a CVD or PECVD process and has a thickness of 100 nm to 400 nm. After forming the sixth high-stress silicon dioxide layer 141, a seventh low-stress silicon dioxide layer 142 is formed on the sixth high-stress silicon dioxide layer 141. The seventh low-stress silicon dioxide layer 142 is deposited by a CVD or PECVD process and has a thickness of 2000 nm to 4000 nm. After forming the seventh low-stress silicon dioxide layer 142, an upper dielectric stack silicon oxynitride 143 is formed on the seventh low-stress silicon dioxide layer 142. The upper dielectric stack silicon oxynitride 143 can be formed by a PECVD process using, for example, a combination of BTBAS and TEOS or a combination of dichlorosilane and nitrous oxide. The upper dielectric stack silicon oxynitride 143 can have a thickness of 100 nm to 400 nm and a stress of -120 MPa to 0 MPa. Following the formation of the upper dielectric stack silicon oxynitride 143, an upper dielectric stack silicon nitride 144 is formed on the upper dielectric stack silicon oxynitride 143. The upper dielectric stack silicon nitride 144 is deposited by a CVD or PECVD process and has a thickness between 200 nm and 1200 nm and a stress between -1 GPa and -100 MPA. The top metal stack should contain at least one layer of low stress silicon dioxide, at least one layer of high stress silicon dioxide, at least one layer of silicon oxynitride, and at least one layer of silicon nitride.

[0034] Referring to FIG. 1I, a top metal interconnect 145 is formed on an upper dielectric stack silicon nitride 144. The top metal interconnect 145 may have an etched aluminum structure and may include a titanium nitride or titanium tungsten adhesion layer (not specifically shown), the upper dielectric stack silicon nitride 144, an aluminum layer with a few atomic percent of silicon, titanium, or copper on the adhesion layer, and an anti-reflective layer of titanium nitride on the aluminum layer (not specifically shown). A top metal interconnect photolithography mask 146 is formed, followed by a reactive ion etching (RIE) process that etches the anti-reflective layer, aluminum layer, and adhesion layer at locations exposed by the etch mask. The RIE process leaves a recess 147 in the underlying upper dielectric stack silicon nitride 144. The cross section in FIG. 1H is shown before removal of the top metal interconnect photolithography mask 146. The RIE used to etch the top metal interconnect can remove up to 200 nm of the underlying upper dielectric stack silicon nitride 144 in areas exposed to the RIE. Features of the top metal interconnect 145 shown in FIG. 1H include a top metal coil 148 and an upper bond pad 149.

[0035] Referring to FIG. 1J, a layer of photoresist is patterned and exposed with an SOR photolithography mask opening 151, leaving an SOR photolithography mask 150 (greater than 5 μm thick) covering the upper bond pad 149 and upper metal coil 148, allowing removal of the upper dielectric stack silicon oxynitride 143, the upper dielectric stack silicon nitride 144, and portions of the seventh low-stress silicon dioxide layer 142 above the lower bond pad 122.

[0036] Referring to FIG. 1K, a cross section is shown after a first lower bond pad opening etch step (not specifically shown) that removes the upper dielectric stack silicon nitride 144, the upper dielectric stack silicon oxynitride 143, and the seventh low stress silicon dioxide layer 142 using 1-2 μm of the seventh low stress silicon dioxide layer etch removal 153 in the SOR photolithography mask opening 151 area.

[0037] Referring to FIG. 1L, a protective overcoat (PO) inorganic dielectric stack 154 is formed on the top metal interconnect 145, the exposed upper dielectric stack silicon nitride 144, and the exposed seventh low-stress silicon dioxide layer 142. The PO inorganic dielectric stack 154 may include a PO silicon dioxide layer 155 (HDP oxide in this example) formed on the top metal interconnect 145, the upper dielectric stack silicon nitride 144, the upper dielectric stack silicon oxynitride 143, and the seventh low-stress silicon dioxide layer 142. The PO silicon dioxide layer 155 has a thickness of 1000 nm to 1500 nm and a stress of −120 MPa to −90 MPa. After the formation of the PO silicon dioxide layer 155, a PO high-stress silicon dioxide layer 156 is formed on the PO silicon dioxide layer 155. PO high stress silicon dioxide layer 156 is formed by a CVD or PECVD process and has a thickness of 100 nm to 400 nm and a stress of -150 MPa to -80 MPa. After the formation of PO high stress silicon dioxide layer 156, PO silicon oxynitride layer 157 is formed on PO high stress silicon dioxide layer 156. Silicon oxynitride layer 157 is deposited using PECVD deposition and has a thickness of 600 nm to 2400 nm and a stress of -120 MPa to 0 MPa. PO silicon dioxide layer 155, PO high stress silicon dioxide layer 156, and PO silicon oxynitride layer 157 form PO inorganic dielectric stack 154.

[0038] 1M, a PO photolithography pattern 158 and a PO etch process 171 are used to remove the PO inorganic dielectric stack 154 in the areas over the upper bond pad 149 and the lower bond pad 122. In the area of ​​the upper bond pad 149, the PO inorganic dielectric stack 154 is completely removed, exposing the upper bond pad 149. In the area over the lower bond pad 122, the PO inorganic dielectric stack 154 is completely removed, as well as the seventh low-stress silicon dioxide layer 142 and the sixth high-stress silicon dioxide layer 141.

[0039] 1N, a plateau photolithography mask 170 is formed. The plateau photolithography mask exposed area 159 includes both the region over the lower bond pad 122 and an exposed region 160 extending beyond a portion of the first silicon oxynitride etch stop layer 129.

[0040] 1O-1Q, the RIE etch process to expose the underside bond pads 122 is sequential but consists of multiple steps involving various fluorine-based etch chemistries. To clarify the etch profile in the etch process, the RIE etch process will be described in terms of a first plateau RIE etch sub-process 161, a second plateau RIE etch sub-process 162, and a third plateau RIE etch sub-process 164.

[0041] 1O, a first plateau RIE etch sub-process 161 etches a portion of the plateau 152 in the plateau photolithography mask exposed area 159 above the lower bond pad 122. The first plateau RIE etch sub-process 161 etches the multiple dielectric layers until the first plateau RIE etch sub-process 161 reaches the second silicon oxynitride etch stop layer 136.

[0042] In the region above the grounded second level interconnect fill metal 121, the first plateau RIE etch sub-process 161 is stopped by the second silicon oxynitride etch stop layer 136. In the region above the lower bond pad 122, the first plateau RIE etch sub-process 161 etches into the fourth low-stress silicon dioxide layer 132. It is advantageous to expose the second silicon oxynitride etch stop layer 136 as a means for providing an endpoint signal for the first plateau RIE etch sub-process 161. The first plateau RIE etch sub-process 161 consumes approximately 33% of the available resist thickness.

[0043] 1P, a second plateau RIE etch sub-process 162 etches through the interlevel dielectric stack 128 above the lower bond pad 122. The second plateau RIE etch sub-process 162 etches through the first silicon oxynitride etch stop layer 129, terminating in the second low-stress silicon dioxide layer 126. The interaction between the PO etch step 171, the second silicon oxynitride etch stop layer 136, the first plateau RIE etch sub-process 161, and the second plateau RIE etch sub-process 162 and the plateau 152 results in an oxide foot space 163 between the edge of the plateau photolithography mask 170 nearest the lower bond pad 122 and the lower bond pad 122.

[0044] 1Q, a third plateau RIE etch sub-process 164 is used to remove the remaining second low-stress silicon dioxide layer 126, the second gap-fill silicon dioxide layer 125, and the silicon nitride / silicon oxynitride bilayer 124 over the lower bond pad 122. After the third plateau RIE etch sub-process 164 is completed, the remaining plateau photolithography mask 170 is removed. The first plateau RIE etch sub-process 161, the second plateau RIE etch sub-process 162, and the third plateau RIE etch sub-process 164 may be performed sequentially without an air break.

[0045] The first plateau RIE etch sub-process 161, the second plateau RIE etch sub-process 162, and the third plateau RIE etch sub-process 164 all use a fluorine-based etch chemistry that also contains carbon and oxygen. The fluorine-based etch chemistry may include at least one alternation between an etch chemistry having a first carbon-to-oxygen ratio and an etch chemistry having a second carbon-to-oxygen ratio greater than the first carbon-to-oxygen ratio during the combined processing of the first plateau RIE etch sub-process 161, the second plateau RIE etch sub-process 162, and the third plateau RIE etch sub-process 164. The first carbon-to-oxygen ratio may be advantageously used to etch to prevent retrograde profiling. Also, the fluorine-based etch chemistry may alternate at least once between an atomic carbon-to-atomic oxygen ratio of less than 2 and an atomic carbon-to-atomic oxygen ratio of greater than 2 during the combined processing of the first plateau RIE etch sub-process 161, the second plateau RIE etch sub-process 162, and the third plateau RIE etch sub-process 164. For example, the carbon source may alternate between C5F8 and C4F8 with a constant O2 flow (e.g., C5F8, O2, and Ar at about 16 / 18 / 800 standard cubic centimeters per minute (sccm) alternating with C4F8, O2, and Ar at about 16 / 18 / 800 sccm). If a silicon nitride / silicon oxynitride bilayer 124 is present, a carbon-to-oxygen ratio greater than the second carbon-to-oxygen ratio may be used for the fluorine-based etch chemistry. If a silicon nitride / silicon oxynitride bilayer 124 is present, an atomic carbon-to-atomic oxygen ratio greater than 3 may be used for the fluorine-based etch chemistry.

[0046] 1R, a cross section shows the microelectronic device 100 after the plateau photolithography mask 170 has been removed and after the ammonia plasma 165 process. The ammonia plasma 165 deposits SiO 2 on the exposed silicon dioxide surfaces of the lower dielectric stack 123, the middle dielectric stack 128, and the upper dielectric stack 139.x N y A layer 166 is formed on the exposed areas of the lower dielectric layer stack 123, the middle dielectric layer stack 128, and the upper dielectric layer stack 139. x N y Forming layer 166 is beneficial for minimizing moisture absorption, which can adversely affect the dielectric layer integrity and high voltage performance of isolation device 101 .

[0047] 1S, a second PO layer 167 of a polymeric material, such as polyimide, benzocyclobutene (BCB), or polybenzoxazole (PBO), may be formed on the PO inorganic dielectric stack 154. The second PO layer 167 is formed by a spin-on process (not specifically shown) followed by a curing process (not specifically shown). A pattern and etch process is used to remove the second PO layer 167 over the upper bond pad 149 and the lower bond pad 122.

[0048] Referring to FIG. 1T, an upper level wire bond 169 is formed in electrical contact with upper bond pad 149 and a lower level wire bond 168 is formed in electrical contact with lower bond pad 122 .

[0049] 2, there is shown a perspective view of a microelectronic device 200 including an isolation device 201. Elements of isolation device 201 that are visible in the perspective view include substrate 202, upper coil 248, upper bond pad 249, upper wire bond 269, second PO layer 267, lower bond pad 222, and lower wire bond 268. Plateau oxide legs 280 and oxide leg spaces 263 are also visible in the perspective view.

[0050] Modifications may be made to the examples described, and other examples are possible, within the scope of the invention.

Claims

1. A microelectronic device comprising: A substrate; an inorganic dielectric on the substrate; 1. An isolation device comprising: a plateau on the inorganic dielectric material, a lower dielectric stack on the inorganic dielectric, comprising at least one low-stress silicon dioxide layer and at least one high-stress silicon dioxide layer; an intermediate dielectric stack on the side dielectric stack, the intermediate dielectric stack including a lower etch stop layer, at least one layer of the low stress silicon dioxide, and at least one layer of high stress silicon dioxide on the lower etch stop layer; an upper dielectric stack on the intermediate dielectric stack, the upper dielectric stack including at least one layer of low stress silicon dioxide, at least one layer of high stress silicon dioxide, at least one layer of silicon oxynitride, and at least one layer of silicon nitride; the plateau comprising: a lower insulating element in the lower dielectric stack; an upper insulating element on the upper dielectric stack; the isolation device, a dielectric protective overcoat on the upper insulating element; an upper bond pad in electrical contact with the upper insulating element; a lower bond pad electrically connected to the lower insulating element; 2. A microelectronic device comprising:

2. 10. The microelectronic device of claim 1, wherein the insulating device includes a ground ring around the lower insulating element.

3. 10. The microelectronic device of claim 1, wherein the insulating device comprises a filler metal.

4. 10. The microelectronic device of claim 1, wherein the insulating device includes a photolithographic alignment mark within the plateau.

5. 10. The microelectronic device of claim 1, wherein the lower dielectric stack comprises a bilayer of silicon oxynitride and silicon nitride on the lower insulating element.

6. 10. The microelectronic device of claim 1, wherein the lower dielectric stack comprises a layer of gap-fill silicon dioxide and a layer of low-stress silicon dioxide.

7. 10. The microelectronic device of claim 1, wherein the lower etch stop layer of the intermediate dielectric stack is silicon nitride.

8. 10. The microelectronic device of claim 1 further comprising an upper etch stop layer in the intermediate dielectric stack above the lower etch stop layer.

9. 10. The microelectronic device of claim 8, wherein the upper etch stop layer of the intermediate dielectric stack is silicon nitride.

10. 1. A method of manufacturing an electronic device, comprising: forming an inorganic dielectric layer on a substrate; forming an insulating device; Including, forming the isolation device forming a plateau, forming a lower dielectric stack on the inorganic dielectric, the lower dielectric stack including at least one low-stress silicon dioxide layer and at least one high-stress silicon dioxide layer; forming a lower insulating element in the lower dielectric stack; forming an intermediate dielectric stack on the lower dielectric stack, the intermediate dielectric stack including a lower etch stop layer, an upper etch stop layer, at least one layer of low stress silicon dioxide, and at least one layer of high stress silicon dioxide between the lower etch stop layer and the upper etch stop layer; forming an upper dielectric stack on the intermediate dielectric stack, the upper dielectric stack including at least one layer of low stress silicon dioxide, at least one layer of high stress silicon dioxide, at least one layer of silicon oxynitride, and at least one layer of silicon nitride; forming an upper insulating element on the upper dielectric stack; forming the plateau, forming an upper bond pad in electrical contact with the upper insulating element; forming a lower bond pad electrically connected to the lower insulating element; A method comprising:

11. The method of claim 10 further comprising forming a filler metal within the plateau.

12. 11. The method of claim 10, further comprising forming photolithographic alignment marks within the plateau.

13. 11. The method of claim 10, further comprising forming a bilayer of silicon oxynitride and silicon nitride on the lower insulating element.

14. 11. The method of claim 10, further comprising forming a layer of gap-fill silicon dioxide in the lower dielectric stack.

15. 11. The method of claim 10, wherein the lower etch stop layer comprises silicon oxynitride.

16. 11. The method of claim 10, wherein the upper etch stop layer comprises silicon oxynitride.

17. 11. The method of claim 10, further comprising performing a dielectric etch process on the plateau, wherein an endpoint signal is provided when the upper etch stop layer is exposed.

18. 1. A method for forming a microelectronic device including an insulating device having a lower insulating element, an upper insulating element, and a plateau therebetween, the plateau having multiple alternating layers of low stress silicon dioxide and high stress silicon dioxide, the method comprising: etching multiple alternating layers of low-stress silicon dioxide and high-stress silicon dioxide by a process including a fluorine-based etch chemistry having at least one alternation between an etch chemistry having a first carbon-to-oxygen ratio and an etch chemistry having a second carbon-to-oxygen ratio greater than the first carbon-to-oxygen ratio; method.

19. 20. The method of claim 18, wherein the plateau etching is continuous without an air break.

20. 20. The method of claim 18, further comprising thereafter etching the silicon nitride / silicon oxynitride bilayer with a fluorine-based etch chemistry having a carbon to oxygen ratio greater than the second carbon to oxygen ratio.

21. 1. A method of forming an electronic device, comprising: Etching a plateau, the plateau comprising: a lower dielectric stack having at least one low-stress silicon dioxide layer and at least one high-stress silicon dioxide layer; an intermediate dielectric stack on the lower dielectric stack, the intermediate dielectric stack having a lower etch stop layer of silicon oxynitride, an upper etch stop layer of silicon oxynitride, and at least one layer of low stress silicon dioxide and at least one layer of high stress silicon dioxide between the lower etch stop layer and the upper etch stop layer; an upper dielectric stack on the intermediate dielectric stack, the upper dielectric stack having at least one layer of low stress silicon dioxide, at least one layer of high stress silicon dioxide, at least one layer of silicon oxynitride, and at least one layer of silicon nitride; Including, etching the plateau with a process comprising a fluorine-based etch chemistry having at least one alternation between an etch chemistry having a carbon-to-oxygen ratio less than 2 and an etch chemistry having a carbon-to-oxygen ratio greater than 2, the process removing a portion of the upper dielectric stack, a portion of the middle dielectric stack, and a portion of the lower dielectric stack; forming a lower insulating element in the lower dielectric stack; forming an upper insulating element on the upper dielectric stack; A method comprising:

Images