Buried Trench Capacitor

Abstract

The microelectronic device (100) includes a buried trench capacitor (170) beneath an electronic component (174) of the microelectronic device. The buried trench capacitor may be formed between a silicon oxide-capped p-type buried trench capacitor polysilicon region (126) and a buried trench capacitor deep n-type region (108) separated by a buried trench capacitor liner dielectric (124) in one example, or may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region (106) separated by a buried trench capacitor liner dielectric in a second example. One terminal of the deep trench capacitor is made through the substrate (102) via a deep trench substrate contact (134), and the second terminal is made through a well contact that connects to the capacitor through a deep well region in one example, or through a polysilicon layer in a second example.

Description

[Technical Field]

[0001] The present disclosure relates to the field of microelectronic devices. More particularly, but not exclusively, the present disclosure relates to buried trench capacitors in microelectronic devices. [Background technology]

[0002] Bypass capacitors are used in conjunction with microelectronic devices such as switch-mode power converters. In such devices, capacitor characteristics, such as electromagnetic interference (EMI), are critical to performance. EMI has traditionally been improved by moving bypass capacitors from a separate chip onto the same chip as the microelectronic device. Further improvements are needed in integrating capacitors into microelectronic devices. Summary of the Invention

[0003] The present disclosure introduces a microelectronic device, the microelectronic device including a buried trench capacitor below a top surface. In one embodiment, the buried trench capacitor can be formed between a silicon oxide-capped buried trench capacitor polysilicon region and a buried trench capacitor deep well region, the buried trench capacitor polysilicon region and the buried trench capacitor deep well region being separated by a buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor can be formed by a buried trench capacitor polysilicon region and a silicon epitaxial region, the buried trench capacitor polysilicon region and the silicon epitaxial region being separated by a buried trench liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made through a well contact that connects to the capacitor through the deep well region in one embodiment and through the polysilicon layer in a second embodiment. [Brief explanation of the drawings]

[0004] [Figure 1A] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1B] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1C] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1D] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1E] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1F] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1G] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1H] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1I] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1J] 1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 1K]1A-1C are cross-sectional views of a first embodiment of an exemplary microelectronic device comprising a buried trench capacitor shown in successive stages of an exemplary method of formation.

[0005] [Figure 2A] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2B] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2C] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2D] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2E] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2F] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2G] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2H] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. [Figure 2I] 1A-1C are cross-sectional views of a second embodiment of an exemplary microelectronic device with a buried trench capacitor shown in successive stages of an exemplary method of formation. DETAILED DESCRIPTION OF THE INVENTION

[0006] The present disclosure will be described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided solely to illustrate the present disclosure. Several aspects of the present disclosure are described hereinafter with reference to example applications for purposes of explanation. It should be understood that numerous specific details, relationships, and methods are shown to aid in understanding the present disclosure. The present disclosure is not limited by the described order of acts or events, as some acts may occur in different orders and / or concurrently with other acts or events. Additionally, not all described acts or events are required to implement a methodology in accordance with the present disclosure.

[0007] Additionally, while some of the embodiments illustrated herein are shown in two-dimensional views with various regions having depths and widths, it should be clearly understood that these regions are only partial views of devices that are actually three-dimensional structures. Thus, these regions, when fabricated on an actual device, have three dimensions, including length, width, and depth. Additionally, while the present invention is illustrated by embodiments directed to active devices, these illustrations are not intended to be limitations on the scope or applicability of the present invention. The active devices of the present invention are not intended to be limited to the physical structures illustrated. These structures are included to demonstrate the utility and application of the present invention to the presently preferred embodiments.

[0008] It should be noted that terms such as top, bottom, front, back, on, above, below, and below may be used in this disclosure. These terms should not be construed to limit the location or orientation of a structure or element, but should be used to provide spatial relationships between structures or elements. Similarly, terms such as "inward" and "outward" refer to directions toward and away from the geometric center of a device or area and designated portions of a device or area, respectively.

[0009] For purposes of this disclosure, the term "lateral" will be understood to refer to a direction parallel to the plane of the top surface of a microelectronic device, and the term "vertical" will be understood to refer to a direction perpendicular to the plane of the top surface of the microelectronic device of the present invention.

[0010] For purposes of this disclosure, the term "conductive" should be interpreted as "electrically conductive." The term "conductive" refers to materials and structures that are capable of supporting a steady state electrical current, i.e., direct current (DC).

[0011] The microelectronic device is formed in and on a substrate having a semiconductor material. The microelectronic device includes buried capacitor cells below a top surface of the semiconductor material. The buried capacitor cells include a trench liner dielectric layer within each buried capacitor cell. The buried capacitor cells further include a conductive trench fill material on the trench liner dielectric layer within each buried capacitor cell.

[0012] The microelectronic device may have deep trenches adjacent to an array of buried capacitor cells that provide contact to the substrate. For purposes of this disclosure, the term deep trench is a trench that is deeper in the semiconductor material than the field oxide.

[0013] An electrical component is located above the buried trench capacitor array of the integrated buried capacitor. In one example, the electrical component is a transistor, such as a laterally diffused metal-oxide-semiconductor (LDMOS) transistor, a drain-extended metal-oxide-semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field-effect transistor, a gated bipolar, a gated unipolar semiconductor device, or an insulated gate bipolar transistor (IGBT). In another example, the electronic component is, for example, a silicon-controlled rectifier (SCR), a metal-oxide-semiconductor (MOS)-triggered SCR, a MOS-controlled thyristor, a gated diode, an amplifier, or a Schottky diode. Locating the buried capacitor within a microelectronic device below or near the electrical components of the microelectronic device is beneficial because physically locating the buried trench capacitor array below or near the electrical components can reduce electromagnetic interference (EMI) of the microelectronic device. Additionally, physically locating the buried trench capacitor array below, or at least partially below, the electrical components conserves silicon area.

[0014] 1A-1K are cross-sections of an exemplary microelectronic device 100 depicted at successive stages of an exemplary method of formation including a buried trench capacitor array 170 as part of an integrated buried capacitor 172 that provides a source of capacitance for an electrical component 174.

[0015] Referring to FIG. 1A, a microelectronic device 100 includes a substrate 102 having a semiconductor material 103, referred to herein as silicon 103. In an alternative version of this example, the substrate 102 may include a dielectric material such as silicon dioxide or sapphire to provide a silicon-on-insulator substrate. In this example, the substrate 102 may include a base wafer 104, such as a silicon wafer. The base wafer 104 may have a first conductivity type, shown in this example as p-type. A doped first epitaxial layer 106 is formed on the base wafer 104. The first epitaxial layer 106 may include primarily silicon and consist essentially of silicon and a dopant, such as boron. The first epitaxial layer 106 has a first epitaxial top surface 107. In this example, the first epitaxial layer 106 may have a first conductivity type, i.e., p-type. The first epitaxial layer 106 may have a thickness of, for example, 5 microns to 15 microns.

[0016] A buried layer 110 may be formed in the first epitaxial layer 106. The buried layer 110 has a second conductivity type opposite the first conductivity type. In this example, the second conductivity type is n-type. The buried layer 110 may be formed by implanting a dopant of the second conductivity type, such as phosphorus, arsenic, or antimony, into the first epitaxial layer 106. The buried layer 110 may have an average dopant density that is more than twice the average dopant density of the first epitaxial layer 106. The base wafer 104 may be annealed after the buried layer implantation.

[0017] 1B, a pad oxide layer 112 may be formed on the first epitaxial top surface 107 of the first epitaxial layer 106. The pad oxide layer 112 may comprise primarily silicon dioxide and may be formed by a thermal oxidation process or a thermal chemical vapor deposition (CVD) process, and may have a thickness of, for example, 50 nanometers to 200 nanometers. A nitride cap layer 114 may be formed on the pad oxide layer 112. The nitride cap layer 114 may comprise primarily silicon nitride and may be formed by a low-pressure chemical vapor deposition (LPCVD) furnace process, and may have a thickness of, for example, 100 nanometers to 500 nanometers. A hard mask layer 116 may be formed on the nitride cap layer 114. The hard mask layer 116 may comprise primarily silicon dioxide and may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process, and may have a thickness of 1 micron to 3 microns, depending on the depth of the subsequently formed buried capacitor trench 122, as shown in FIG. 1C. The pad oxide layer 112 may provide stress relief between the first epitaxial layer 106 and the combination of the nitride cap layer 114 and hard mask layer 116. The nitride cap layer 114 may provide a stop layer for subsequent etch and planarization processes. The hard mask layer 116 may provide a hard mask during a subsequent buried capacitor etch process 120, discussed in FIG. 1C , to form buried capacitor trenches 122. Next, a buried capacitor trench mask 118 may be formed on the hard mask layer 116 with buried capacitor trench mask openings 119 that expose the hard mask layer 116 in areas for the buried capacitor trenches 122. The buried capacitor trench mask 118 may include photoresist and may optionally include an antireflective material such as a bottom antireflective coating (BARC). The buried capacitor trench mask 118 may be formed by a photolithography process.

[0018] Referring to FIG. 1C , a buried capacitor etch process 120 is performed to form buried capacitor trenches 122 in the first epitaxial layer 106. A buried capacitor trench 122 is formed for each desired capacitor cell, forming an array of capacitor cells. The buried capacitor etch process 120 may include multiple steps. In one implementation, a hard mask etch may first be performed to remove the hard mask layer 116 exposed by the buried capacitor trench mask 118 of FIG. 1B, and then a silicon etch may be performed to remove the nitride cap layer 114, the pad oxide layer 112, and the first epitaxial layer 106 in the areas exposed by the hard mask layer 116 to form the buried capacitor trenches 122. The buried capacitor trenches 122 may extend from the first epitaxial top surface 107 into the first epitaxial layer 106 and into the base wafer 204. During the silicon etch, the buried capacitor trench mask 118 may also be partially or completely removed, leaving the hard mask layer 116 to prevent etching of areas outside the buried capacitor trenches 122. Figure 1C shows the buried capacitor etch process 120 upon completion, with the buried capacitor trench mask 118 having been removed by a subsequent buried capacitor trench etch cleanup process (not specifically shown). The organic polymer within the buried capacitor trench mask 118 may be removed using an oxygen plasma, followed by a series of wet etch processes including an aqueous mixture of sulfuric acid and hydrogen peroxide, an aqueous mixture of ammonium hydroxide and hydrogen peroxide, and an aqueous mixture of hydrochloric acid and hydrogen peroxide.

[0019] A buried capacitor deep well 108 may be formed in the first epitaxial layer 106, extending along the edges of the buried capacitor trench 122 and beyond the bottom edge of the buried layer 110. The buried capacitor deep well 108 may be formed by implanting a dopant of a second conductivity type, such as phosphorus, using a tilted implant to implant the dopant into the first epitaxial layer 106 along the edges of the buried capacitor trench 122 and beyond the buried layer 110, followed by thermal driving to diffuse and activate the implanted dopant. The buried capacitor deep well 108 may have an average concentration of dopant of the second conductivity type that is 2 to 10 times greater than the average concentration of dopant of the first conductivity type in the first epitaxial layer 106 outside the buried capacitor deep well 108. By implanting through the walls of the buried capacitor trench 122, the tilted implant may provide improved implant distribution.

[0020] 1D , a buried capacitor trench liner dielectric layer 124, referred to herein as trench liner dielectric layer 124, is formed in the buried capacitor trench 122 and contacts the first epitaxial layer 106 and base wafer 104, as well as the buried capacitor deep well 108 and buried layer. The trench liner dielectric layer 124 may extend over the hard mask layer 116, the nitride cap layer 114, and the pad oxide layer 112. The trench liner dielectric layer 124 may include a single layer of a silicon-nitride or silicon dioxide compound, or may include multiple layers of silicon-nitride, silicon dioxide, or other dielectric materials. After forming the trench liner dielectric layer 124, a trench liner dielectric layer etch process (not specifically shown) is used to form a trench liner gap 125 through the bottom of the trench liner dielectric layer 124, exposing the base wafer 104.

[0021] 1E, trench fill material 126 is formed in buried capacitor trench 122 on trench liner dielectric layer 124. Trench fill material 126 is electrically conductive. Trench fill material 126 may be implemented as polycrystalline silicon, which primarily comprises silicon and is commonly referred to as polysilicon. Alternatively, trench fill material 126 may be implemented as amorphous silicon or semi-amorphous silicon. Trench fill material 126 may have a first conductivity type, which in this example is p-type. Trench fill material 126 may have a conductivity of 5×10 18 cm -3 and 1 x 10 20 cm -3 and may have an average concentration of dopant of 0.1 to 0.5, providing a low equivalent resistance for buried trench capacitor array 170. Trench fill material 126 may be formed by pyrolysis of a silicon-containing reagent gas that includes doped polysilicon reagent 127. Trench fill material 126 fills buried capacitor trenches 122 and may extend outside buried capacitor trenches 122.

[0022] 1F , the trench fill material 126 and the trench liner dielectric layer 124 are removed from outside the buried capacitor trench 122. The trench fill material 126 and the trench liner dielectric layer 124 may be removed by a planarization process, such as a chemical-mechanical polishing (CMP) process 128, as shown in FIG. 1F . Alternatively, the trench fill material 126 and the trench liner dielectric layer 124 may be removed by an etch-back process. The process of removing the trench fill material 126 and the trench liner dielectric layer 124 outside the buried capacitor trench 122 leaves the trench fill material 126 on the trench liner dielectric layer 124 within the buried capacitor trench 122. The process of removing the trench fill material 126 and the trench liner dielectric layer 124 may leave the nitride cap layer 114 and the pad oxide layer 112 on the first epitaxial top surface 107 of the first epitaxial layer 106. The nitride cap layer 114 may provide a selective template layer for the subsequent polysilicon oxidation process 129 shown in FIG. 1G.

[0023] 1G, a polysilicon oxidation process 129 is used to form a buried capacitor silicon dioxide cap 130, which provides a dielectric barrier over the trench fill material 126 of the buried trench capacitor array 170. The polysilicon oxidation process 129 may use oxygen or oxygen and steam at high temperatures to oxidize the trench fill material 126 at the first epitaxial top surface 107 of the first epitaxial layer 106. The nitride cap layer 114 prevents oxidation in areas other than the trench fill material 126.

[0024] 1H, the nitride cap layer 114 and the pad oxide layer 112 are removed. The nitride cap layer 114 may be removed by a wet etch process using an aqueous solution of phosphoric acid at 140°C to 170°C. The pad oxide layer 112 may be removed by a wet etch process using an aqueous solution of buffered hydrofluoric acid. The pad oxide layer 112 removal process is optimized to remove the pad oxide layer 112 but not remove excessive buried capacitor silicon dioxide cap 130 to the point of affecting the dielectric integrity of the buried capacitor silicon dioxide cap 130. After removal of the pad oxide layer 112, the buried capacitor silicon dioxide cap 130 remains continuous over the trench fill material 126.

[0025] Referring to FIG. 1I, an epitaxial silicon capping layer 132 is deposited over the buried capacitor silicon dioxide cap 130. The epitaxial silicon capping layer 132 has a first conductivity type, which in this example is p-type. The epitaxial silicon capping layer 132 may be, by way of example, 1 micron to 3 microns thick. The epitaxial silicon capping layer 132 is doped with 1×10 ions of a p-type dopant, such as boron. 15 atoms / cm 3 ~1×10 16 atoms / cm 3 The concentration of

[0026] 1J, a top epitaxial silicon 136 layer having a first conductivity type (e.g., p-type) doping and an integrated deep trench 134 is formed. After deposition of the epitaxial silicon capping layer 132, the top epitaxial silicon 136 layer is deposited. The top epitaxial silicon 136 layer has a top epitaxial silicon top surface 137. The top epitaxial silicon 136 may, for example, have a doping density of 1×10 15 atoms / cm 3 ~1×10 16 atoms / cm 3 The top epitaxial silicon 136 layer may include a p-type dopant, such as boron, at a concentration of 0.01%. The thickness of the top epitaxial silicon 136 layer may be, for example, 5 to 15 microns. After the formation of the top epitaxial silicon 136 layer, a pattern and implant process is used to form the deep trench deep well region 138. The deep trench deep well region 138 has a second conductivity type (e.g., n-type). Alternatively, the deep trench deep well region 138 may be formed after the formation of the integrated deep trench 134.

[0027] The integrated deep trenches 134 provide electrical connections from the top epitaxial silicon top surface 137 of the microelectronic device 100 to the base wafer 104. The formation of the integrated deep trenches 134 consists of an integrated deep trench hard mask layer formation step, a photolithography pattern step, a plasma etch step, and a cleanup step (none of which are specifically shown) to form the integrated deep trenches 134.

[0028] After the deep trench 140 is formed, a deep trench liner 142 is deposited. The deep trench liner 142 is a dielectric layer. For example, the deep trench liner 142 may be 50 Å to 300 Å. The deep trench liner 142 may be a single layer or multiple layers of dielectric materials, such as silicon nitride, silicon oxynitride, and silicon dioxide. After the deep trench liner 142 is deposited, a deep trench liner etch process is used to create a deep trench liner gap 145, which provides a conductive path between a subsequently deposited conductive deep trench polysilicon fill 146 and the base wafer 104. After the deep trench liner gap 145 is formed, a polysilicon deposition process is used to form a conductive deep trench polysilicon fill 146 on the deep trench liner 142. For example, the conductive deep trench polysilicon fill 146 is doped p-type with a dopant, such as boron. A CMP process (not specifically shown) then removes the conductive deep trench polysilicon filling 146 and the deep trench liner 142 outside the deep trench 140.

[0029] Referring to FIG. 1K, the remaining process steps required to complete the formation of the integrated deep trench 134 and the electrical component 174 (in this example, a CMOS transistor) are shown. A buried capacitor array 170, or a portion of the buried capacitor array 170, may be located below the electrical component 174. A well 150 is implanted to provide electrical contact to the integrated deep trench 134, the integrated buried capacitor 172, and the deep trench deep well region 138 of the buried trench capacitor array 170. A field oxide 148 is formed in a series of steps consisting of a pattern, etch, field oxide fill, and CMP steps (none of which are specifically shown). The field oxide 148 provides insulation for the electrical component 174 as well as electrical isolation for the integrated deep trench 134. The remaining components of the CMOS transistor in the example device shown in FIG. 1K consist of a gate oxide 152 on the top epitaxial silicon top surface 137 and a gate electrode material 154 on the gate oxide 152, which forms a transistor gate electrode 156. The transistor includes halo implant regions 158 and source / drain implant regions 160. Sidewalls 162 are formed on the lateral surfaces of the gate electrode 157. A metal silicide 159 may be formed on exposed silicon surfaces on the top epitaxial silicon top surface 137 of the silicon. A pre-metal dielectric (PMD) 164 is formed on the top epitaxial silicon top surface 137 of the microelectronic device 100. Contacts 165 and metallization 166 are formed to provide electrical contact between a first buried trench capacitor terminal 176 of the integrated buried capacitor 172, a second buried trench capacitor terminal 178 of the integrated buried capacitor 172, and the electrical component 174.

[0030] A first buried trench capacitor terminal 176 provides electrical connection through the substrate 102 via the integrated deep trench 134 to the conductive buried capacitor trench fill material 126. A second buried trench capacitor terminal 178 provides electrical connection through the well 150 and the deep trench deep well region 138 to the buried trench capacitor buried capacitor deep well 108.

[0031] Microelectronic device 100 can be viewed as consisting of three distinct regions. The first region is buried trench capacitor array 170. The second region is integrated buried capacitor 172, which includes buried trench capacitor array 170 and integrated deep trench 134. The third region is electrical component 174, which in this example is a CMOS transistor.

[0032] 2A-2I are cross-sections of an exemplary microelectronic device 200 depicted at successive stages of an exemplary method of formation including a buried trench capacitor array 270 as part of an integrated buried capacitor 272, which provides a source of capacitance for an electrical component 274.

[0033] Referring to FIG. 2A , microelectronic device 200 is formed in and on substrate 202 having semiconductor material 203, referred to herein as silicon 203. In this example, substrate 202 may include a base wafer 204, such as a silicon wafer. In an alternative version of this example, substrate 202 may include a dielectric material, such as silicon dioxide or sapphire, to provide a silicon-on-insulator substrate. Base wafer 204 may have a first conductivity type, which in this example may be p-type. A first epitaxial layer 206 is formed on base wafer 204. First epitaxial layer 206 may include primarily silicon and may consist essentially of silicon and a dopant, such as boron. First epitaxial layer 206 has a first epitaxial top surface 207. In this example, first epitaxial layer 206 may have a first conductivity type, i.e., p-type. The first epitaxial layer 206 may have a thickness of, for example, 5 microns to 15 microns.

[0034] A buried layer 210 may be formed in the first epitaxial layer 206. The buried layer 210 has a second conductivity type opposite the first conductivity type. In this example, the second conductivity type is n-type. The buried layer 210 may be formed by implanting a dopant of the second conductivity type, such as phosphorus, arsenic, or antimony, into the first epitaxial layer 206. The buried layer 210 may have an average dopant density that is more than twice the average dopant density of the first epitaxial layer 206. The base wafer 204 may be annealed after the buried layer implantation.

[0035] 2B, a pad oxide layer 212 may be formed on the first epitaxial top surface 207 of the first epitaxial layer 206. The pad oxide layer 212 may comprise primarily silicon dioxide and may be formed by a thermal oxidation process or a thermal chemical vapor deposition (CVD) process, and may have a thickness of, for example, 50 nanometers to 200 nanometers. A nitride cap layer 214 may be formed on the pad oxide layer 212. The nitride cap layer 214 may comprise primarily silicon nitride and may be formed by a low-pressure chemical vapor deposition (LPCVD) furnace process, and may have a thickness of, for example, 100 nanometers to 500 nanometers. A hard mask layer 216 may be formed on the nitride cap layer 214. The hard mask layer 216 may comprise primarily silicon dioxide and may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process, and may have a thickness of 1 micron to 3 microns, depending on the depth of the subsequently formed buried capacitor trench 222, as shown in FIG. 1C. The pad oxide layer 212 may provide stress relief between the first epitaxial layer 206 and the combination of the nitride cap layer 214 and hard mask layer 216. The nitride cap layer 214 may provide a stop layer for subsequent etch and planarization processes. The hard mask layer 216 may provide a hard mask during a subsequent buried capacitor etch process 220, discussed in FIG. 1C , to form the buried capacitor trench 122. Next, a buried capacitor trench mask 218 may be formed on the hard mask layer 216 with buried capacitor trench mask openings 219 that expose the hard mask layer 216 in areas for the buried capacitor trench 222. The buried capacitor trench mask 218 may include photoresist and may optionally include an antireflective material such as a bottom antireflective coating (BARC). The buried capacitor trench mask 218 may be formed by a photolithography process.

[0036] 2C , a buried capacitor etch process 220 is performed to form a buried capacitor trench 222 in the first epitaxial layer 206. The buried capacitor etch process 220 may include multiple steps. In one implementation, for example, a hard mask etch may first be performed to remove the hard mask layer 216 exposed by the buried capacitor trench mask 218 of FIG. 2B , and then a silicon etch may be performed to remove the nitride cap layer 214, the pad oxide layer 212, and the first epitaxial layer 206 in the areas exposed by the hard mask layer 216 to form the buried capacitor trench 222. The buried capacitor trench 222 may extend from the first epitaxial top surface 207 into the first epitaxial layer 206 and into the base wafer 204. During the silicon etch, the buried capacitor trench mask 218 may also be partially or completely removed, leaving the hard mask layer 216 to prevent etching of areas outside the buried capacitor trench 222. Figure 2C shows the buried capacitor etch process 220 upon completion, with the buried capacitor trench mask 218 having been removed by a subsequent buried capacitor trench etch cleanup process (not specifically shown). The organic polymer within the buried capacitor trench mask 218 may be removed using an oxygen plasma, followed by a series of wet etch processes including an aqueous mixture of sulfuric acid and hydrogen peroxide, an aqueous mixture of ammonium hydroxide and hydrogen peroxide, and an aqueous mixture of hydrochloric acid and hydrogen peroxide.

[0037] 2D , a trench liner dielectric layer 224 is formed in the buried capacitor trench 222 and contacts the first epitaxial layer 206 and the base wafer 204. The trench liner dielectric layer 224 may extend over the hard mask layer 216, the nitride cap layer 214, and the pad oxide layer 212. The trench liner dielectric layer 224 may include a single layer of a silicon-nitride compound or a silicon dioxide compound, or may include multiple layers of a silicon-nitride compound, a silicon dioxide compound, or other dielectric material.

[0038] 2E, a conductive buried capacitor trench fill material 226 is formed in the buried capacitor trench 222 on the trench liner dielectric layer 224. The conductive buried capacitor trench fill material 226 may be implemented as polycrystalline silicon, which primarily comprises silicon and is commonly referred to as polysilicon. Alternatively, the conductive buried capacitor trench fill material 226 may be implemented as amorphous silicon or semi-amorphous silicon. The conductive buried capacitor trench fill material 226 may have a second conductivity type, which in this example is n-type. The conductive buried capacitor trench fill material 226 may have a conductivity of 5×10 to provide a low equivalent resistance for the buried trench capacitor array 270. 18 cm -3 and 1 x 10 20 cm -3 The conductive buried capacitor trench fill material 226 may have an average concentration of dopant of 0.05 wt. %. The conductive buried capacitor trench fill material 226 may be formed by pyrolysis of a silicon-containing reagent gas that includes a doped polysilicon reagent 227. The conductive buried capacitor trench fill material 226 fills the buried capacitor trench 222 and may extend outside the buried capacitor trench 222.

[0039] 2F, the conductive buried capacitor trench fill material 226 and the trench liner dielectric layer 224 are removed from outside the buried capacitor trench 222. As shown in FIG. 1F, the conductive buried capacitor trench fill material 226 and the trench liner dielectric layer 224 may be removed by a planarization process, such as a chemical-mechanical polishing (CMP) process 228. Alternatively, the conductive buried capacitor trench fill material 226 and the trench liner dielectric layer 224 may be removed by an etch-back process. The process of removing the conductive buried capacitor trench fill material 226 and the trench liner dielectric layer 224 outside the buried capacitor trench 222 leaves the conductive buried capacitor trench fill material 226 on the trench liner dielectric layer 224 within the buried capacitor trench 222. The process of removing the conductive buried capacitor trench fill material 226 and the trench liner dielectric layer 224 may leave the nitride cap layer 214 and the pad oxide layer 212 on the top surface 207 of the first epitaxial layer 206. The nitride cap layer 214 may provide a stop layer for a CMP process 228 or an etch-back process. The nitride cap layer 214 and the pad oxide layer 212 are then removed (not specifically shown). The nitride cap layer 214 may be removed by a wet etch process using an aqueous solution of phosphoric acid at 140° C. to 170° C. The pad oxide layer 212 may be removed by a wet etch process using an aqueous solution of buffered hydrofluoric acid.

[0040] 2G, an n-type epitaxial silicon capping layer 232 is deposited on the first epitaxial top surface 207 and is in electrical contact with the conductive buried capacitor trench fill material 226. The n-type epitaxial silicon capping layer 232 may be, by way of example, 1 micron to 3 microns thick. The n-type epitaxial silicon capping layer 232 is doped with 1×10 n-type dopants, such as arsenic or phosphorous. 15 atoms / cm 3 ~1×10 16 atoms / cm 3 may contain at a concentration of

[0041] 2H, a top epitaxial silicon layer 236 having p-type doping and an integrated deep trench 234 is formed. The top epitaxial silicon 136 is, for example, 1×10 15 atoms / cm 3 ~1×10 16 atoms / cm 3 The top epitaxial silicon layer 236 may include a p-type dopant, such as boron, at a concentration of 0.1 μm or more. The top epitaxial silicon layer 236 has a top epitaxial silicon top surface 237. The thickness of the top epitaxial silicon 236 layer may be, by way of example, 5 to 15 microns. The integrated deep trench 234 provides electrical connection from the top epitaxial silicon top surface 237 of the microelectronic device to the base wafer 204. Formation of the integrated deep trench 234 begins with a pattern and implant step to form a deep trench deep n-type well 238, followed by a pattern and etch step to define a deep trench 240.

[0042] After the formation of the deep trench 240, a deep trench liner 242 is deposited. The deep trench liner 242 is a dielectric layer. The deep trench liner 242 may be, for example, 50 Å to 300 Å thick. The deep trench liner 242 may be a single layer or multiple layers of dielectric materials, such as silicon nitride, silicon oxynitride, and silicon dioxide. After the deposition of the deep trench liner 242, a deep trench liner etch process is used to create a deep trench liner gap 245, which provides a conductive path between a subsequently deposited conductive deep trench polysilicon fill 246 and the base wafer 204. After the formation of the deep trench liner gap 245, a polysilicon deposition process is used to form a conductive deep trench polysilicon fill 246 on the deep trench liner 242. The conductive deep trench polysilicon fill 246 is, for example, doped n-type with a dopant, such as phosphorus. A CMP process then removes the conductive deep trench polysilicon filling 246 and the deep trench liner 242 outside the deep trench 240.

[0043] Referring to FIG. 2I, the remaining process steps required to complete the formation of the integrated deep trench 234 and the electrical component 274 (in this example, a CMOS transistor) are shown. A well 250 is implanted to provide electrical contact to the deep n-type implant 238 in the integrated deep trench 234 to the integrated buried capacitor 272 and buried trench capacitor array 270. In a series of steps consisting of pattern, etch, field oxide fill, and CMP steps, a field oxide 248 is formed. The field oxide 248 provides isolation for the electrical component 274 as well as electrical isolation for the integrated deep trench 234. The remaining components of the electrical component 274 of the example device shown in FIG. 2I are composed of a gate oxide 252 on the top epitaxial silicon top surface 237 and a gate electrode material 254, such as polysilicon, on the gate oxide 252, which forms a transistor gate electrode 256. The electrical component 274 includes a halo implant region 258 and a source / drain implant region 260. Sidewalls 262 are formed on the lateral surfaces of the transistor gate electrode 256. A metal silicide 259 may be formed on exposed silicon surfaces on the top epitaxial silicon top surface 237 of the silicon. A pre-metal dielectric (PMD) 264 is formed on the top epitaxial silicon top surface 237 of the microelectronic device 200. Contacts 265 and metallization 266 are formed to provide electrical contact between a first buried trench capacitor terminal 276 of the integrated buried capacitor 272, a second buried trench capacitor terminal 278 of the integrated buried capacitor 272, and the electrical component 274.

[0044] A first buried trench capacitor terminal 276 of the integrated embedded capacitor 272 provides electrical connection to the base wafer 204 through the integrated deep trench 234 and the substrate 202. A second buried trench capacitor terminal 278 of the integrated embedded capacitor 272 provides electrical connection to the conductive buried capacitor trench fill material 226 through the well 250 and the n-type epitaxial silicon capping layer 232.

[0045] The microelectronic device 200 can be viewed as consisting of three distinct regions. The first region is a buried trench capacitor array 270. The second region is an integrated buried capacitor 272, which includes the buried trench capacitor array 270 and the integrated deep trench 234. The third region is an electrical component 274, which in this example is a CMOS transistor, but may also be a laterally diffused metal-oxide-semiconductor (LDMOS) transistor, a drain-extended metal-oxide-semiconductor (DEMOS) transistor, a bipolar junction transistor, a junction field-effect transistor, a gated bipolar, a gated unipolar semiconductor device, an insulated-gate bipolar transistor (IGBT), a silicon-controlled rectifier (SCR), a metal-oxide-semiconductor (MOS)-triggered SCR, a MOS-controlled thyristor, a gated diode, a resistor, an amplifier, and a Schottky diode.

[0046] Referring to FIG. 3, a top view highlighting key features of FIG. 1K is shown, including buried trench capacitor array 370, integrated buried capacitor 372, and electronic component 374 (CMOS transistor in this example). All components are within silicon 303. Trench fill material 326, trench liner dielectric layer 324, and buried capacitor deep well 308 form buried trench capacitor array 370. Buried trench capacitor array 370 is below electrical component 374. It is advantageous to place buried trench capacitor array 370 below electronic component 374 to conserve area and reduce electromagnetic interference (EMI) for microelectronic device 300. Contact 365 is shown, but metallization is not shown for clarity. The deep trench component is composed of conductive deep trench polysilicon fill material 346, deep trench liner 342, and deep trench deep well 338. Well 350 contacts D-well 338 to provide an electrical path to buried trench capacitor array 370. Electrical component 374 (in this example a CMOS transistor) consists of gate electrode material 354 and source and drain regions 360 surrounded by isolation regions 348.

[0047] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Many modifications to the disclosed embodiments may be made in accordance with the disclosure herein without departing from the spirit or scope of the present disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Rather, the scope of the present disclosure is defined according to the following claims and their equivalents.

Claims

1. A microelectronic device comprising: a base wafer having a layer of silicon; a first epitaxial layer on the base wafer, the first epitaxial layer having a first epitaxial layer top surface; a buried trench capacitor extending into the first epitaxial layer; a second epitaxial layer over the buried trench capacitor; and 2. A microelectronic device comprising:

2. 10. The microelectronic device of claim 1, wherein the buried trench capacitor comprises: a buried trench capacitor array below the second epitaxial layer; the buried trench capacitor array comprising: a buried capacitor trench in the first epitaxial layer and in the base wafer; a buried capacitor deep well of a first conductivity type around the buried capacitor trench; a trench liner dielectric within the buried capacitor trench; a trench liner gap through the trench liner dielectric to the base wafer; a trench fill material on the trench liner dielectric in the buried capacitor trench, the trench fill material being electrically conductive and having a second conductivity type opposite the first conductivity type; a buried trench capacitor silicon dioxide cap on the trench fill material; 2. A microelectronic device comprising:

3. 3. The microelectronic device of claim 2, wherein the buried trench capacitor further comprises: a first buried trench capacitor terminal in contact with the base wafer; a second buried trench capacitor terminal in contact with the buried capacitor deep well around the buried trench capacitor; 2. A microelectronic device comprising:

4. 3. The microelectronic device of claim 2, further comprising an epitaxial silicon capping layer of said second conductivity type on said buried trench capacitor silicon dioxide cap.

5. 3. The microelectronic device of claim 2 further comprising a buried layer of said first conductivity type within said first epitaxial layer.

6. 3. The microelectronic device of claim 2, further comprising an electrical component at the surface of the second epitaxial layer that extends at least partially over the buried trench capacitor array.

7. 3. The microelectronic device of claim 2, further comprising an integrated deep trench including a deep trench liner gap providing an electrical connection between a first buried trench capacitor terminal and the trench fill material of the buried trench capacitor array.

8. 3. The microelectronic device of claim 2, Further comprising a deep trench n-type deep well; The deep trench n-type deep well provides an electrical connection between a second buried trench capacitor terminal and the buried capacitor deep well of the buried trench capacitor array.

9. A microelectronic device comprising: a base wafer having a layer of silicon; a first epitaxial layer on the base wafer having a first epitaxial layer top surface; 1. A buried trench capacitor, comprising: an array of buried trench capacitor cells in the first epitaxial layer, each buried trench capacitor cell comprising: a buried capacitor trench in the first epitaxial layer and in the base wafer; a buried capacitor trench liner dielectric within the buried capacitor trench; an n-type conductive buried capacitor trench fill material on the buried capacitor trench liner dielectric; the buried trench capacitor comprising: an n-type epitaxial silicon capping layer over the buried trench capacitor; a first buried trench capacitor terminal in contact with the base wafer; a second recessed trench capacitor terminal in contact with the n-type epitaxial silicon capping layer; a second p-type epitaxial layer on the n-type epitaxial silicon capping layer; Including, Microelectronic devices.

10. 10. The microelectronic device of claim 9, further comprising an electrical component extending at least partially over the array of buried trench capacitor cells.

11. 10. The microelectronic device of claim 9, further comprising an integrated deep trench including a deep trench liner gap providing an electrical connection between a first buried trench capacitor terminal and the n-type conductive buried capacitor trench fill material of the buried trench capacitor.

12. 10. The microelectronic device of claim 9, further comprising a deep trench n-type deep well providing electrical connection between a second buried trench capacitor terminal and the n-type epitaxial silicon capping layer.

13. 1. A method of forming a microelectronic device, comprising: forming a first epitaxial layer on a base wafer having a top surface; forming a buried trench capacitor extending into the first epitaxial layer; forming a second epitaxial layer over the buried trench capacitor; A method comprising:

14. 14. The method of claim 13, wherein forming the buried trench capacitor comprises: forming a buried trench capacitor array below the second epitaxial layer; forming a buried capacitor trench in the first epitaxial layer and in the base wafer; forming a deep well of a first conductivity type around said buried capacitor trench; forming a trench liner dielectric within the buried capacitor trench; forming a trench liner gap through the trench liner dielectric down to the base wafer; forming a trench fill material in the buried capacitor trench over the trench liner dielectric, the trench fill material being electrically conductive and having a second conductivity type; forming a buried trench capacitor silicon dioxide cap on the trench fill material; Including, forming the buried trench capacitor array.

15. 15. The method of claim 14, wherein forming the buried trench capacitor comprises: forming a first buried trench capacitor terminal in contact with the base wafer; forming a second buried trench capacitor terminal in contact with the deep well around the buried trench capacitor; A method comprising:

16. 14. The method of claim 13, wherein a p-type epitaxial silicon capping layer is formed on the buried trench capacitor silicon dioxide cap.

17. 14. The method of claim 13, wherein an n-type buried layer is formed in the first epitaxial layer.

18. 14. The method of claim 13, wherein an electrical component of the microelectronic device is in electrical parallel contact with the buried trench capacitor array.

19. 14. The method of claim 13, wherein the integrated deep trenches include a deep trench liner gap that provides an electrical connection between a first buried trench capacitor terminal and the trench fill material of the buried trench capacitor array.

20. 14. The method of claim 13, wherein a deep trench n-type deep well provides an electrical connection between a second buried trench capacitor terminal and the deep well of the buried trench capacitor array.

21. 1. A method of forming a microelectronic device with an embedded capacitor, comprising: forming a first epitaxial layer on a substrate base wafer; forming a buried trench capacitor array, forming a buried capacitor trench in the first epitaxial layer and in the base wafer; forming a buried capacitor trench liner dielectric over the buried capacitor trench; forming an n-type conductive buried capacitor trench fill material on the buried capacitor trench liner dielectric; forming the buried trench capacitor array, forming a second p-type epitaxial layer over the buried trench capacitor array; forming a first buried trench capacitor terminal in contact with the base wafer; forming a second buried trench capacitor terminal in contact with the deep well around the buried trench capacitor; A method comprising:

22. 22. The method of claim 21, wherein a deep trench n-type deep well provides an electrical connection between a second buried trench capacitor terminal and the first epitaxial layer of the buried trench capacitor array.

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