Package and device including the package

JP2025531907A5Pending Publication Date: 2026-07-17QUALCOMM INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
QUALCOMM INC
Filing Date
2023-08-07
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

Existing packages face challenges in achieving better performance due to the configuration of integrated devices and chiplets, which can lead to increased signal and current latency, and higher production costs.

Method used

A package configuration is introduced that includes a substrate with dielectric layers and interconnects, coupled with chiplets and metallization portions, and encapsulation layers, allowing for reduced electrical paths and redistributed functionality among integrated devices and chiplets, thereby improving performance and reducing costs.

Benefits of technology

The proposed configuration reduces signal and current latency while achieving high performance capabilities and cost reductions by optimizing electrical paths and redistributing package functionality.

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Abstract

1. A package comprising: a substrate including at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion.
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