Gate driving technique for high-side N-type power transistors without using bootstrap capacitors

Abstract

Techniques and apparatus for driving the gate of a high-side transistor in a switched-mode power supply (SMPS) circuit, such as an inverting buck-boost converter or a buck converter. One exemplary technique for pulling down the gate voltage of the high-side transistor involves a multi-stage approach, in which the gate voltage is first discharged to a lower voltage level, and once the gate voltage drops below a certain level, an auxiliary switch can take over to completely turn off the high-side transistor. One exemplary SMPS circuit generally includes a high-side transistor, a pull-down gate driver having an output coupled to the gate of the high-side transistor, a pulse generator having an output coupled to the input of the pull-down gate driver, and a first switch coupled between the gate and source of the high-side transistor.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 934,487, filed Sep. 22, 2022, which is incorporated herein by reference.

[0002]

[0002] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to gate driver architectures and methods for driving gates in switched mode power supplies. [Background technology]

[0003]

[0003] A voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. While linear regulators tend to be small and compact, many applications can benefit from the increased efficiency of switching regulators (also called switching converters). Linear regulators can be implemented, for example, by low-dropout (LDO) regulators. Switching regulators can be implemented, for example, by switched-mode power supplies (SMPS) such as buck converters, boost converters, buck-boost converters, or charge pumps.

[0004] For example, a buck converter is a type of SMPS that typically includes (1) a high-side switch coupled between a relatively high voltage rail and a switching node, (2) a low-side switch coupled between the switching node and a relatively low voltage rail, and (3) an inductor coupled between the switching node and a load (e.g., represented by a shunt capacitive element). The high-side switch and the low-side switch may be implemented using transistors, although the low-side switch may alternatively be implemented using a diode.

[0005]

[0005] A power management integrated circuit (power management IC or PMIC) is used to manage the power needs of a host system and may include and / or control one or more voltage regulators (e.g., step-down converters or step-down / step-up converters). PMICs can be used in battery-operated devices such as cell phones, tablets, laptops, wearables, etc. to control the flow and direction of power within the device. A PMIC can perform various functions for the device, such as DC-DC conversion (e.g., using voltage regulators as described above), battery charging, power source selection, voltage scaling, and power sequencing. Summary of the Invention

[0006]

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no one of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the claims that follow, several features will now be briefly described. After considering this description, and particularly after reading the section entitled "Detailed Description of the Invention," one will understand how the features of the present disclosure provide the advantages described herein.

[0007] An aspect of the present disclosure provides a switched mode power supply (SMPS) circuit that generally includes a high-side transistor, a pull-down gate driver having an output coupled to a gate of the high-side transistor, a pulse generator having an output coupled to an input of the pull-down gate driver, and a first switch coupled between the gate and source of the high-side transistor.

[0008]

[0008] Certain aspects of the present disclosure provide a power management integrated circuit (PMIC) that includes at least a portion of the SMPS circuitry described herein.

[0009] Certain aspects of the present disclosure provide a method of supplying power, generally including: pulling down a gate voltage of a high-side transistor in an SMPS circuit; and, when the gate voltage is pulled down to a particular voltage level, closing a first switch to effectively short-circuit the gate and source of the high-side transistor, turning the high-side transistor off.

[0010] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of the various aspects may be employed. [Brief explanation of the drawings]

[0011]

[0011] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description briefly summarized above can be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only certain exemplary embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the description may be incorporated into other equally effective embodiments. [Figure 1]

[0012] 1 shows a block diagram of an exemplary device including a switched mode power supply (SMPS) circuit in which aspects of the present disclosure may be implemented. [Figure 2A]

[0013] FIG. 1 is a block diagram of an example SMPS circuit in which aspects of the present disclosure may be implemented. [Figure 2B]

[0014] FIG. 1 is a circuit diagram of an example gate driver and an example inverting buck-boost converter in which aspects of the present disclosure may be implemented. [Figure 3A-1]

[0015] 3A-1 is a circuit diagram (FIG. 3A-1) and a corresponding timing diagram (FIG. 3A-2) of an exemplary gate driver architecture for an inverting buck-boost converter that uses a bootstrap capacitor to power the high-side gate driver. FIGS. 3A-1 and 3A-2 are hereinafter referred to as FIG. 3A. [Figure 3A-2] 3A-1 is a circuit diagram (FIG. 3A-1) and a corresponding timing diagram (FIG. 3A-2) of an exemplary gate driver architecture for an inverting buck-boost converter that uses a bootstrap capacitor to power the high-side gate driver. FIGS. 3A-1 and 3A-2 are hereinafter referred to as FIG. 3A. [Figure 3B]

[0016] 1 is a cross-sectional view of an exemplary semiconductor device fabricated using a triple well process. [Figure 3C-1]

[0017] 3C-1 and 3C-2 are circuit diagrams (FIG. 3C-1) and corresponding timing diagrams (FIG. 3C-2) of an exemplary gate driver architecture for an inverting buck-boost converter that uses a bootstrap capacitor to power the pull-down portion of a segmented high-side gate driver. [Figure 3C-2]3C-1 and 3C-2 are circuit diagrams (FIG. 3C-1) and corresponding timing diagrams (FIG. 3C-2) of an exemplary gate driver architecture for an inverting buck-boost converter that uses a bootstrap capacitor to power the pull-down portion of a segmented high-side gate driver. [Figure 3D-1]

[0018] 3D-1 and 3D-2 are circuit diagrams (hereinafter referred to as FIG. 3D) and corresponding timing diagrams (FIG. 3D-2) of an exemplary gate driver architecture for an inverting buck-boost converter using a pulse generator and one or more auxiliary switches, according to certain aspects of the present disclosure. [Figure 3D-2] 3D-1 and 3D-2 are circuit diagrams (hereinafter referred to as FIG. 3D) and corresponding timing diagrams (FIG. 3D-2) of an exemplary gate driver architecture for an inverting buck-boost converter using a pulse generator and one or more auxiliary switches, according to certain aspects of the present disclosure. [Figure 3E]

[0019] FIG. 1 is a circuit diagram of an example implementation of an auxiliary switch using back-to-back n-channel field-effect transistors (NFETs), according to an embodiment of the present disclosure. [Figure 3F]

[0020] FIG. 1 is a circuit diagram of an example implementation of a pull-down portion of a segmented high-side gate driver, in accordance with certain aspects of the present disclosure. [Figure 4]

[0021] FIG. 1 is a circuit diagram of an example gate driver architecture for a step-down converter using a pulse generator and an auxiliary switch, in accordance with an aspect of the present disclosure. [Figure 5]

[0022] FIG. 1 is a flow diagram of an example operation for providing power according to an aspect of the present disclosure.

[0012]

[0023] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0024] Certain aspects of the present disclosure provide techniques and apparatus for driving the gate of a high-side transistor in a switched-mode power supply (SMPS) circuit, such as an inverting buck-boost converter or a buck converter. One exemplary technique for pulling down the gate voltage of the high-side transistor involves a multi-stage approach, in which the gate voltage is first discharged to reduce the voltage, and once the gate voltage drops below a certain level, an auxiliary switch can take over to completely turn off the high-side transistor.

[0014]

[0025] Various aspects of the present disclosure will now be described more fully with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of the present disclosure is intended to encompass all aspects of the present disclosure disclosed herein, whether implemented independently or in combination with any other aspects of the present disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects described herein. Furthermore, the scope of the present disclosure is intended to encompass such apparatuses or methods practiced using other structure, functions, or structure and functions in addition to or other than the various aspects of the present disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of a claim.

[0015]

[0026] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0016]

[0027] As used herein, the term "connected to" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected to" can also be used herein to mean the use of a wire, trace, or other conductive material to electrically connect element A and element B (and any components electrically connected between them).

[0017] Device example

[0028] It should be understood that aspects of the present disclosure may be used in a variety of applications. Although the disclosure is not limited in this respect, the circuits disclosed herein may be used in any of a variety of suitable devices, such as power supplies, battery charging circuits, or power management circuits in communication systems, video codecs, audio equipment such as music players and microphones, televisions, camera equipment, and test equipment such as oscilloscopes. Communication systems intended to be included within the scope of the present disclosure include, by way of example only, cellular radiotelephone communication systems, satellite communication systems, two-way wireless communication systems, one-way pagers, two-way pagers, personal communication systems (PCSs), personal digital assistants (PDAs), Internet of Things (IoT) devices, and the like.

[0018]

[0029] 1 illustrates an example device 100 in which aspects of the present disclosure may be implemented. Device 100 may be a battery-operated device such as a mobile phone, a personal digital assistant (PDA), a handheld device, a wireless device, a laptop computer, a tablet, a smartphone, an IoT device, a wearable device, an augmented reality device, or the like.

[0019]

[0030] The device 100 may include a processor 104 that controls operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). The memory 106 may include both read-only memory (ROM) and random access memory (RAM) and provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0020]

[0031] In certain aspects, device 100 may also include a transmitter 110 and / or a receiver 112 to enable transmission and / or reception, respectively, of data between device 100 and a remote location. For certain aspects, transmitter 110 and receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached to or otherwise coupled to housing 108 of device 100 and electrically coupled to transceiver 114. In certain aspects, device 100 may include multiple transmitters, multiple receivers, and / or multiple transceivers (not shown).

[0021]

[0032] The device 100 may also include a signal detector 118 that can be used to detect and quantify the level of signals received by the transceiver 114. The signal detector 118 can detect such signal parameters as total energy, energy per subcarrier per symbol, and power spectral density, among others. The device 100 may also include a digital signal processor (DSP) 120 for use in processing the signals.

[0022]

[0033] Device 100 may further include a battery 122 that is used to power various components of device 100. In some embodiments, battery 122 may be rechargeable.

[0023]

[0034] Device 100 may also include a power management integrated circuit (PMIC) (also referred to as a power management unit (PMU)) 124 for managing power from the battery to various components of device 100. PMIC 124 may perform various functions for the device, such as DC-DC conversion, battery charging, power source selection, voltage scaling, and power sequencing. In an aspect, PMIC 124 may include at least a portion of a power supply circuit, which may include a switched-mode power supply (SMPS) circuit 125. SMPS circuit 125 can be implemented with various suitable switched-mode power supply circuit topologies, such as, for example, a buck converter, a boost converter, an inverting buck-boost converter, or a charge pump. In an aspect, SMPS circuit 125 may include a high-side gate driver architecture having a pulse generator, a pull-down gate driver having an input coupled to the output of the pulse generator and an output coupled to the gate of a high-side transistor, and one or more switches coupled between the gate and source of the high-side transistor, as described below. In an aspect, the PMIC 124 may include a battery charging circuit (eg, a master-slave battery charging circuit) for charging the battery 122.

[0024]

[0035] The various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus.

[0025] Exemplary power supply circuit with gate drivers and switching circuitry

[0036] 2A is a block diagram of an exemplary switched-mode power supply (SMPS) circuit 200 in which aspects of the present disclosure may be implemented. The SMPS circuit 200 may include control logic 210, a gate driver 220, and a switching circuit 230. The control logic 210 may output control signals to control the timing of components within the gate driver 220. The gate driver 220 may output signals having specified output signal swings to control control inputs (e.g., gates) of switching devices (e.g., power field-effect transistors (FETs)) within the switching circuit 230. The gate driver 220 may be powered from any of a variety of suitable power supply voltages.

[0026]

[0037] 2B is a circuit diagram 250 of a portion of an example gate driver 220 and an example switching circuit 230 in which aspects of the present disclosure may be implemented. The gate driver 220 may include logic buffers 222, 224 and a switch, which may be implemented by transistors M10 and M11, as shown. The logic buffer 222 may have an input coupled to an output of the control logic 210 and an output coupled to a control input of transistor M10. In this example, transistor M10 is implemented as a p-type field-effect transistor (PFET) having a source coupled to a first voltage rail (labeled “Vdd1”), a gate coupled to the output of the logic buffer 222, and a drain coupled to an output node 226 of this portion of the gate driver 220. The logic buffer 224 may have an input coupled to another output of the control logic 210 and an output coupled to a control input of transistor M11. In this example, transistor M11 is implemented as an n-type field-effect transistor (NFET) having a drain coupled to the output node 226 of this portion of gate driver 220, a gate coupled to the output of logic buffer 224, and a source coupled to a second voltage rail (labeled "Vdd2") having a lower voltage than the first voltage rail (Vdd1). The power supply inputs of logic buffers 222, 224 may be coupled to the first and second voltage rails or may be coupled to one or more different power supply rails.

[0027]

[0038] In this example, switching circuit 230 is implemented as an inverting buck-boost converter. However, it should be understood that the switching circuit may alternatively be implemented as any of a variety of other suitable switching converter topologies, such as a boost converter or a buck converter. As shown, the inverting buck-boost converter includes power transistors M0 and M1, an inductive element L1 (e.g., implemented by one or more inductors), and a capacitive element C1 (e.g., implemented by one or more capacitors). High-side transistor M0 is an NFET having a drain coupled to an input node 227 (also referred to herein as the “input voltage node”) of the inverting buck-boost converter (having a voltage Vin supplied by a power supply 234), a gate coupled to the output of gate driver 220 (i.e., output node 226), and a source coupled to a switching node 228 (also referred to herein as the “switching voltage (VSW) node”). Low-side transistor M1 is also an NFET having its drain coupled to switching node 228, its gate coupled to another output of gate driver 220 (not shown in FIG. 2B ), and its source coupled to an output node 232 (also referred to herein as an “output voltage node”) of the inverting buck-boost converter (having voltage Vout). The portion of gate driver 220 (e.g., low-side gate driver) for controlling the control input of low-side transistor M1 is not shown, but can be implemented in a manner similar to that described above for the portion of gate driver 220 (e.g., high-side gate driver) for controlling the control input of high-side transistor M0. In some embodiments, transistor M1 may be replaced with another suitable component, such as a diode with an anode coupled to output node 232 and a cathode coupled to switching node 228.

[0028]

[0039] A first terminal of inductive element L1 is coupled to switching node 228, and a second terminal of inductive element L1 is coupled to a reference potential node (e.g., electrical ground) of the inverting buck-boost converter. A first terminal of capacitive element C1 is coupled to output node 232, and a second terminal of capacitive element C1 is coupled to the reference potential node. The output voltage Vout of the inverting buck-boost converter is developed across capacitive element C1 as shown. In an inverting buck-boost converter, Vout generally has an opposite polarity to Vin and is adjustable (e.g., between −3 V and −10 V) based on the duty cycle of switching transistors M0 and M1.

[0029]

[0040] In operation, logic buffers 222, 224 may receive control signals (e.g., smaller amplitude logic level signals) from the control logic and generate signals to drive the control inputs (e.g., gates) of transistors M10, M11. In some embodiments, the buffer output signals may have a larger voltage swing than the control signals received from control logic 210. In this manner, the output signal from gate driver 220 on output node 226 may be pulled up to turn on power transistor M0 or pulled down to turn off transistor M0, according to the switching frequency and duty cycle of the inverting buck-boost converter. Similarly, another output signal from gate driver 220 may be used to control the operation of power transistor M1, where the gate may be pulled up to turn on transistor M1 or pulled down to turn off transistor M1. The gate signals may be operated in a break-before-make manner, such that transistor M0 is turned off before transistor M0 is turned on, and vice versa. As described above, Vout is controlled based on the duty cycle of switching power transistors M0 and M1.

[0030]

[0041] The gate drive signal from gate driver 220 may exceed Vin at the drain of transistor M0 (e.g., by 5V) to fully turn on this n-type transistor. To fully turn off transistor M0, the gate drive signal may be driven at least as low as the switching voltage (VSW) at the source of this n-type transistor. Thus, output node 226 should be driven (by gate driver 220) to Vin plus some additional voltage (e.g., 5V) and pulled down to VSW (which may be, for example, −10V). Thus, if Vin is +5V, the gate may be driven with a swing between +10V and −10V. This voltage swing can be particularly challenging when trying to keep transistor M0 off in an inverting buck-boost converter.

[0031] Exemplary Gate Driver for High-Side Transistor with Bootstrap Capacitor

[0042] Figure 3A is a circuit diagram 300 of an inverting buck-boost converter, an example implementation of a gate driver, and a corresponding timing diagram 310. The inverting buck-boost converter is similar to the inverting buck-boost converter of Figure 2B and uses the same reference numbers.

[0032]

[0043] 3A includes a floating rail generator 301, a switch Sboot, a bootstrap capacitor Cboot, a high-side (HS) level shifter 302, a low-side (LS) level shifter 303, an HS gate driver 304, and an LS gate driver 305. The gate driver may also include a deep n-well (DNW) bias circuit 306.

[0033]

[0044] The floating rail generator 301 may be a voltage source (e.g., a power supply circuit) configured to generate a floating voltage (Vfloat,n) referenced to Vout, where Vfloat,n may be, for example, approximately 3-5 V higher than Vout to provide a gate-to-source voltage (Vgs) sufficient to turn on transistor M1. The higher the floating voltage Vfloat,n, the higher the Vgs that the LS gate driver 305 can apply to transistor M1, and the lower the drain-to-source on-resistance R that can be achieved. DS,on will be low. In one embodiment, if Vout is −10V, then Vfloat,n may be −5V, as an example. Floating rail generator 301 is coupled between output node 232 and floating power rail 311.

[0034]

[0045] The LS level shifter 303 and the LS gate driver 305 may each have a power supply input coupled between the floating power rail 311 and the output node 232 to receive power from the floating rail generator 301. The LS level shifter 303 has an input coupled to the output of the control logic 210 to receive a low-side control signal (labeled "LS_CTL"). The LS level shifter 303 may also have a separate power supply input coupled between the digital voltage rail (labeled "DVDD") and (digital domain) electrical ground, as shown in FIG. 3A. In this manner, the LS level shifter 303 can level-shift the logic level signal (LS_CTL) received from the control logic 210, which swings from 0V to DVDD, to an LS drive signal (labeled "LS_DRV") that swings from Vout to Vfloat,n. The LS gate driver 305 has an input coupled to the output of the LS level shifter 303 and an output coupled to the gate of the low-side transistor M1. In this way, the gate of transistor M1 can be driven with a control signal that swings from Vout to Vfloat,n, which should be sufficient to turn transistor M1 off or on.

[0035]

[0046] In FIG. 3A, switch S is coupled between floating power rail 311 and a first terminal of bootstrap capacitor C. A second terminal of capacitor C is coupled to switching node 228 having switching voltage V. By selectively charging bootstrap capacitor C from V via switch S (e.g., when high-side transistor M is off and V is low), a bootstrap power rail 313 is generated having a floating bootstrap voltage V referenced to V. Thus, the V domain dynamically varies with V. With bootstrapping, V can rise as high as V plus the voltage across floating rail generator 301 when transistor M is on, as shown by the waveform of V in timing diagram 310. When transistor M is off, V drops because V drops.

[0036]

[0047] The HS level shifter 302 and the HS gate driver 304 may each have a power supply input coupled between the bootstrap power rail 313 and the switching node 228 to receive power from the capacitor Cboot when the switch Sboot is open and from the floating rail generator 301 when the switch Sboot is closed. The HS level shifter 302 has an input coupled to the output of the control logic 210 to receive a high-side control signal (labeled “HS_CTL”). The HS level shifter 302, like the LS level shifter 303, may also have a separate power supply input coupled between the digital voltage rail (DVDD) and (digital domain) electrical ground. In this manner, the HS level shifter 302 can level-shift a logic level signal (HS_CTL) received from the control logic 210 and swinging from 0V to DVDD to an HS drive signal (labeled “HS_DRV”) swinging from VSW to Vboot, as shown in timing diagram 310. HS gate driver 304 has an input coupled to the output of HS level shifter 302 and an output coupled to the gate of high-side transistor M0. In this manner, the gate of transistor M0 can be driven with a control signal that swings from VSW to Vboot.

[0037]

[0048] As described above in connection with FIG. 2B , the HS gate driver 304 (and / or the LS gate driver 305) may include a p-type metal-oxide-semiconductor (PMOS) transistor (e.g., transistor M10) and an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., transistor M11). In one embodiment, the gate driver may be fabricated using a triple-well semiconductor process, as shown in the cross-sectional view of an exemplary semiconductor 385 in FIG. 3B . The semiconductor 385 includes a p-substrate 386, a deep n-well 387, a p-well 388, and an n-well 389. Doping is used to fabricate an NMOS transistor 390 (with n+ doped regions for the source (S) and drain (D)) on the p-well 388 and a PMOS transistor 392 (with p+ doped regions for the source (S) and drain (D)) on the n-well 389. PMOS transistor 392 has deep n-well isolation (but may not have other isolation), and deep n-well 387 is located on p-substrate 386. As shown in FIG. 3B, the body of PMOS transistor 392 may be n+ doped and shorted to deep n-well 387. This n-well should not go negative when the PMOS gate (G) is swinging negative, so that the body diode 394 from p-substrate 386 does not become forward biased and can cause latch-up. To avoid latch-up (and forward-biasing the body diode), the PMOS gate voltage can be effectively clamped to a certain voltage level (e.g., ≥ 0V). Therefore, when the gate driver is swinging down into the negative voltage region, the body connection can be isolated and a separate reference or power supply voltage can be provided to prevent latch-up effects.

[0038]

[0049] 3A may also include a DNW bias circuit 306 having an output coupled to the PFET transistor body in the HS gate driver 304. The DNW bias circuit 306 may provide a separate power supply to the body to prevent latch-up.

[0039]

[0050] In an inverting buck-boost converter such as that shown in circuit diagram 300, there are several design challenges associated with driving the high-side n-type transistor M0. The HS gate driver 304 is referenced to VSW, which can typically switch very quickly from the negative voltage domain (VOUT) to the positive voltage domain (VIN), as shown by the VSW waveform in timing diagram 310. For example, VSW may swing between −10 V and +10 V, slewing in 1 to 3 ns in some converters. The floating voltage source Vboot in this topology may require a large capacitor Cboot to provide charge to the HS level shifter 302 and the HS gate driver 304 (e.g., when switch Sboot is open). Due to its large size, the bootstrap capacitor Cboot may be external to the integrated circuit (e.g., PMIC) along with the remaining components of the inverting buck-boost converter, occupying a significant area within the device containing the converter. Furthermore, using Vfloat,n (from the floating rail generator 301 referenced to Vout) to charge the capacitor Cboot can be inefficient, and there can be issues recharging the capacitor Cboot during high-impedance states (e.g., when both transistors M0 and M1 are off and VSW is 0 V), during startup, during pulse-skipping mode, when the HS driver is not switching, or over time. Furthermore, designing the HS level shifter 302 can be difficult because HS_DRV swings between negative and positive voltage regions and the HS level shifter's power inputs (Vboot and VSW) fluctuate together. Preventing the HS level shifter 302 from losing its state while transitioning between the negative and positive regions can be a design challenge. Furthermore, deep n-well (DNW) biasing can also be difficult in an inverting buck-boost converter for the same reason; the DNW bias voltage should be positive (e.g., clamped to >0 V) to prevent parasitic diodes (e.g., body diode 394) from being forward-biased in the triple-well process of FIG. 3B.

[0040]

[0051] Figure 3C is a circuit diagram 320 of another exemplary gate driver architecture for the inverting buck-boost converter of Figures 2B and 3A, along with a corresponding timing diagram 330. Most of the circuit diagram 320 of Figure 3C is similar to the circuit diagram 300 of Figure 3A, and so the same reference numerals are used and the description will not be repeated.

[0041]

[0052] The primary difference between circuit diagrams 300 and 320 is that the HS gate driver is split in FIG. 3C into an HS pull-up gate driver 324 and an HS pull-down gate driver 326 (referred to as a "segmented HS gate driver"), each operating on a different power domain but with an output coupled to the gate of transistor MO. The pull-up driver 324 can operate as a buffer without pull-down capability, and the pull-down driver 326 can operate as an inverting buffer without pull-up capability. For example, the pull-up driver 324 can be implemented by an inverter with its output coupled to the gate of a p-type field-effect transistor (PFET). In contrast, the pull-down driver 326 can be implemented by two cascaded inverters with their outputs coupled to the gate of an n-type field-effect transistor (NFET).

[0042]

[0053] 3C also includes a segmented level shifter, i.e., HS level shifter 302 and another HS level shifter 322. The input of HS level shifter 322 is coupled to the output of control logic 210 to receive HS_CTL, while the input of HS level shifter 302 may be coupled to the output of control logic 210 via inverter 321. In this case, the input of inverter 321 is coupled to the output of control logic 210 to receive the HS_CTL signal, and the output of inverter 321 is coupled to the input of HS level shifter 302. The output of HS level shifter 322 is coupled to the input of pull-up driver 324, and the output of HS level shifter 302 is coupled to the input of pull-down driver 326.

[0043]

[0054] Here, the pull-down driver 326 and the HS level shifter 302 may each have a power supply input coupled between the bootstrap power rail 313 and the switching node 228 to receive power from the capacitor Cboot when the switch Sboot is open and from the floating rail generator 301 when the switch Sboot is closed, similar to that described above for the HS gate driver 304 and the HS level shifter 302 of Figure 3A. However, the HS level shifter 322 and the pull-up driver 324 receive power from different power domains.

[0044]

[0055] In one aspect, a power supply circuit (e.g., a boost converter) referenced to Vin or another suitable voltage may be used to generate a voltage (labeled "CBST") on boosted power rail 323 that is greater than Vin (e.g., 3-5V, e.g., 4V). In this case, HS level shifter 322 and pull-up driver 324 may each have a power supply input coupled between boosted power rail 323 and input node 227 having Vin. HS level shifter 322, like HS level shifter 302 and LS level shifter 303, may also have a separate power supply input coupled between the digital voltage rail (DVDD) and (digital domain) electrical ground. In this manner, HS level shifter 322 may level-shift a logic level signal (HS_CTL) received from control logic 210 that swings from 0V to DVDD to an HS pull-up drive signal (labeled "HS_DRV_PU") that swings from Vin to CBST, as shown in timing diagram 330. Vin and CBST are DC voltages and do not track VSW. Additionally, HS level shifter 302 can level shift HS_CTL into an HS pull-down drive signal (labeled "HS_DRV_PD") that swings from VSW to Vboot, as shown in timing diagram 330. In this way, the gate of transistor M0 can be pulled up to CBST by pull-up driver 324 (when HS_CTL is logic high) and pulled down to VSW by pull-down driver 326 (when HS_CTL is logic low).

[0045]

[0056] In the segmented gate driver of FIG. 3C, the bootstrap capacitor Cboot can be significantly reduced in size and capacitance compared to the capacitor Cboot of FIG. 3A. This is because the bootstrap capacitor Cboot of FIG. 3C is used to bias the HS level shifter 302 rather than actually supplying power to the gate of transistor M0 as in FIG. 3A. Therefore, the capacitor Cboot can be implemented as an internal capacitor within an integrated circuit for a switching regulator using the topology of FIG. 3C. However, Vfloat,n is still used to charge the capacitor Cboot, which can be inefficient. Furthermore, the design of the HS level shifter 302 on the Vboot domain and the DNW bias design are still difficult in this implementation.

[0046] Exemplary Gate Driver for High-Side Transistor Without Bootstrap Capacitor

[0057] Certain aspects of the present disclosure provide apparatus and techniques for driving the gate of a high-side power transistor in a switching regulator using a segmented driver with a two-stage pulldown approach, where the high-side gate voltage is pulled down to a voltage using the output voltage domain instead of the VSW domain, below which an auxiliary switch can take over to completely turn off the high-side transistor. This two-stage transition can be achieved by introducing a pulse generator and auxiliary switch in the high-side pulldown path of the gate driver architecture, and by powering the HS level shifter, pulse generator, and HS pulldown gate driver from rails at Vfloat,n and Vout.

[0047]

[0058] 3D is a circuit diagram 340 of an example gate driver architecture for the inverting buck-boost converter of FIGS. 2B and 3A, and a corresponding timing diagram 350, in accordance with certain aspects of the present disclosure. Most of the circuit diagram 340 of FIG. 3D is similar to the circuit diagram 320 of FIG. 3C, and so the same reference numerals are used and the description will not be repeated.

[0048]

[0059] 3D adds a pulse generator 344 and a switch S1. In some embodiments, the circuit diagram 340 may also include control logic 348 (e.g., to implement a high-impedance (Hi-Z) detection circuit) and a switch S2, as shown in FIG.

[0049]

[0060] 3C, an input of inverter 321 is coupled to the output of control logic 210 to receive the HS_CTL signal, and an output of inverter 321 is coupled to the input of HS level shifter 302. Pulse generator 344 may be implemented, for example, by a one-shot circuit (also known as a monostable multivibrator). An input of pulse generator 344 may be coupled to the output of HS level shifter 302, and an output of the pulse generator may be coupled to an input of pull-down driver 326. The outputs of pull-up driver 324 and pull-down driver 326 are coupled to the gate of transistor M0.

[0050]

[0061] In contrast to circuit diagram 320 of FIG. 3C, HS level shifter 302, pulse generator 344, and pull-down driver 326 of FIG. 3D may each have a power supply input coupled between floating power rail 311 and output node 232. Inverter 321 and HS level shifter 302 may also have a power supply input coupled between the digital voltage rail (DVDD) and (digital domain) electrical ground. In this manner, HS level shifter 302 can level-shift the HS_CTL signal into a first HS pull-down drive signal (labeled "HS_DRV_GS_SW") that swings from Vout to Vfloat,n, as shown in timing diagram 350. Due to inverter 321, HS_DRV_GS_SW at the output of HS level shifter 302 is the inverse of the HS_CTL signal.

[0051]

[0062] Pulse generator 344 is configured to generate an output pulse when an appropriate trigger signal is applied. In this case, pulse generator 344 may be triggered by the rising edge of the HS_DRV_GS_SW signal, causing the pulse generator to output a second HS pull-down drive signal (labeled "HS_DRV_PD") having a single pulse on each rising edge of the HS_DRV_GS_SW signal, as shown in timing diagram 350. The pulse swings from Vout to Vfloat,n due to the power supply rails coupled to pulse generator 344.

[0052]

[0063] 3C, HS level shifter 322 and pull-up driver 324 each have a power supply input coupled between boosted power rail 323 and input node 227 having Vin. In this manner, HS level shifter 322 can level-shift the HS_CTL signal into an HS pull-up drive signal (labeled "HS_DRV_PU") that swings from Vin to CBST, as shown in timing diagram 350, and the HS_DRV_PU signal can control pull-up driver 324 with the correct timing to pull up the gate of transistor MO to CBST when HS_CTL (and HS_DRV_PU) are logic high.

[0053]

[0064] Switch S1 is coupled between the gate and source of transistor M0. A control input of switch S1 may be coupled to the output of HS level shifter 302 (i.e., to the input of pulse generator 344). In one embodiment, switch S1 may be implemented by back-to-back transistors, such as back-to-back n-type field effect transistors (NFETs) M2 and M3, as shown in FIG. 3E. In this case, the sources of NFETs M2 and M3 may be coupled together, and the gates of NFETs M2 and M3 may be coupled together and coupled to the control input of switch S1, labeled "Drive" in FIG. 3E. The drain of NFET M2 may be coupled to one terminal of switch S1 (labeled "Terminal 1"), and the drain of the NFET may be coupled to another terminal of switch S1 (labeled "Terminal 2").

[0054]

[0065] 3F is a circuit diagram of an example implementation of pull-down driver 326 according to an aspect of the present disclosure. In this example, pull-down driver 326 is implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter (comprising PFET M4 and NFET M5), a second CMOS inverter (comprising PFET M6 and NFET M7) coupled in series with the first CMOS inverter, and NFET M9 having a gate coupled to the output of the second CMOS inverter. The input of pull-down driver 326 may be coupled to the gates of PFET M4 and NFET M5 in the first inverter. The drains of PFET M4 and NFET M5 may be coupled together and to the gates of PFET M6 and NFET M7 in the second inverter. The drains of PFET M6 and NFET M7 may be coupled together and to the gate of NFET M9. The pull-down driver 326 may also include an NFET M8 having its source and body coupled to the drain of NFET M9 and having its drain coupled to the output of the pull-down driver. The sources of PFETs M4 and M6 (and the gate of NFET M8) may be coupled to a higher power supply voltage rail (labeled "Supply 2"), and the sources of NFETs M5, M7, and M9 may be coupled to a lower power supply voltage rail (labeled "Supply 1"). A deep n-well bias voltage (labeled "DNW" and may be the output of the DNW bias circuit 306) may be coupled to the bodies of PFETs M4 and M6. While shown in FIG. 3F as a deep n-well bias voltage, this may instead be replaced by a deep p-well bias voltage depending on the semiconductor process used to implement the pull-down driver circuit. In this implementation of pull-down driver 326 in FIG. 3F, a logic high signal applied to the input of the pull-down driver pulls the output low (to power supply 1 level), while a logic low signal applied to the input causes the output to be high impedance (off).

[0055]

[0066] As described above, the high-side pull-down path (comprising pulse generator 344, pull-down driver 326, and switch S1) can pull down the gate voltage of transistor M0 using a two-stage transition. When the HS_CTL signal transitions from logic high to logic low, the HS_DRV_GS_SW signal transitions from Vout to Vfloat,n. When Vfloat,n is applied to the control input of switch S1, the gate of transistor M0 is initially at CBST and the source is initially at Vin, but the goal is to pull the gate down to VSW to completely turn off the high-side transistor M0. Switch S1, whose control input is Vfloat,n, cannot close first to short the gate of transistor M0 to its source. Therefore, pulse generator 344 is triggered to output a pulse on the rising edge of the HS_DRV_GS_SW signal to control pull-down driver 326. Pull-down driver 326 has a pull-down stage comprising an n-type transistor having its source coupled to output node 232 (at Vout). When a pulse of Vfloat,n is applied to the gate of the pull-down n-type transistor in pull-down driver 326, charge is extracted from the gate of transistor M0, and the pull-down n-type transistor acts as a first discharge path 352, causing the gate voltage of transistor M0 to drop towards Vout.

[0056]

[0067] Switch S1 begins to close when VSW or the gate voltage of transistor M0 falls below Vfloat,n (e.g., the back-to-back n-channel transistors turn on), and the gate of transistor M0 is effectively shorted to switching node 228 when switch S1 is fully closed (e.g., the gate-source voltages of the back-to-back transistors are sufficiently high, e.g., above their threshold voltages). Closing switch S1 ensures that the gate voltage of transistor M0 follows VSW, turning transistor M0 off and creating a second discharge path 354 from the gate of transistor M0 through switch S1. Depending on the pulse length from pulse generator 344, discharge paths 352, 354 may discharge simultaneously for a short period of time. The pulse length should be set long enough to ensure that the gate voltage of transistor M0 is pulled down below Vfloat,n, turning off pull-down driver 326, before the pulse on the HS_DRV_PD signal ends.

[0057]

[0068] In an aspect, instead of relying on a fixed pulse length of the HS_DRV_PD signal, as set by pulse generator 344, a closed-loop approach may be used to initially pull down the gate voltage of transistor M0. In this case, the gate voltage of high-side transistor M0 may be sensed, and the application of Vfloat,n by pull-down driver 326 may be terminated when the gate voltage is at a predetermined voltage below Vfloat,n. This may help ensure that discharge path 352 is on long enough so that switch S1 may be activated to discharge any remaining voltage on the gate of transistor M0.

[0058]

[0069] This gate drive architecture and two-stage approach of FIG. 3D has several advantages. For example, closing switch S1 as described above ensures that transistor M0 is fully turned off when HS_CTL is logic low, even if VSW becomes more negative than Vout (e.g., at high load currents) due to a significant voltage drop across low-side transistor M1. Also, by referencing the high-side pull-down path (stage 1 of the transition) to Vout instead of VSW, the pull-down path is referenced to a stable voltage rather than a varying voltage, and the design of the high-side pull-down path is much easier without the use of bootstrap capacitor Cboot. Eliminating capacitor Cboot reduces the area occupied by the power supply circuitry and avoids the issues (e.g., recharging) mentioned above with respect to capacitor Cboot. Furthermore, the design of the HS level shifter 302 may be much easier because it is powered from the stable Vfloat,n domain rather than the more unstable Vboot domain.

[0059]

[0070] Additionally, the output of the DNW bias circuit 306 may be coupled to the transistor body input of the pull-down driver 326 (e.g., the PMOS body input in FIG. 3B or the body inputs of PFETs M4 and M6 in FIG. 3F). Because Vfloat,n and Vout are stable voltages (compared to the shifting Vboot domain), the output of the DNW bias circuit 306 does not need to slew up and down very quickly to track moving voltages such as VSW. Therefore, the design of the DNW bias circuit 306 may be simpler than previous implementations.

[0060]

[0071] In some embodiments, the gate driver architecture may also include another auxiliary switch S2 and control logic 348 for controlling switch S2, possibly to address additional complexities arising in, for example, the circuit diagram 340 of FIG. 3D . Switch S2 may be coupled between the gate and source of high-side transistor M0, and the output of control logic 348 may be coupled to the control input of switch S2. Switch S2 may be implemented with back-to-back NFETs, similar to the exemplary implementation of switch S1 shown in FIG. 3E . However, switch S2 may be driven by a positive voltage (e.g., Vin) from control logic 348 to close switch S2 and a negative voltage (e.g., Vout) to open switch S2. In some embodiments, control logic 348 may be part of control logic 210, while in other embodiments, control logic 348 may be physically separate from control logic 210.

[0061]

[0072] The control logic 348 may include a part of the high impedance (Hi-Z) detection circuit or be a part thereof. The high impedance (Hi-Z) detection circuit is configured to determine when the switching node 228 (or the source of transistor M0) enters a high impedance state, such as when the SMPS circuit is disabled, when the SMPS circuit is in discontinuous mode (DCM) or pulse skip mode, or when both transistors M0 and M1 are assumed to be turned off. Most of the time, switch S2 is open. However, when the gate driver enters a high impedance state and both power transistors M0 and M1 are turned off, there is a DC short circuit from the switching node 228 to ground (i.e., VSW = 0V) through the inductive element L1. In this scenario using the closed switch S1, to keep transistor M0 off, the control input of switch S1 must be higher than 0V (e.g., by at least the threshold voltage (Vth) of the back-to-back NFET). However, the control signal HS_DRV_GS_SW for switch S1 can operate in the negative voltage region (e.g., between Vout and Vfloat,n), and thus it cannot be ensured that switch S1 is closed. In other words, switch S1 may not be able to keep transistor M0 off when Vfloat,n < Vth.

[0062]

[0073] Thus, when the SMPS circuit enters DCM mode (or another high-impedance state) and, as the case may be, the control logic determines (e.g., using a zero-crossing detector in control logic 348 or based on LS_CTL from control logic 210) that low-side transistor M1 is cut off, the control logic 348 may determine that switching node 228 has entered a high-impedance state. Thus, the control logic 348 may apply a positive voltage (e.g., from the DVDD rail, input node 227 (with Vin), or another power rail powering control logic 348) to the control input of switch S2, thereby closing switch S2 and shorting the gate and source of high-side transistor M0, thus keeping transistor M0 off.

[0063]

[0074] In this case, pulling down the gate voltage of high-side transistor M0 can be thought of as involving three stages. The first stage may be to pull VSW down toward Vout using pulse generator 344, the second stage may be to short the gate of transistor M0 to its source using switch S1, and the third stage is to short the gate of transistor M0 to its source using switch S2 when it is in a high impedance state during the switching cycle. As mentioned above, switch S2 may not be triggered frequently and may remain open most of the time, but under light load conditions (and other high impedance scenarios),

[0064]

[0075] The techniques and apparatus described above (e.g., in connection with FIG. 3D ) for implementing a two-stage transition for pulling down the gate voltage of high-side transistor M0 can also be applied to other switching converter topologies, such as a buck converter. FIG. 4 is a circuit diagram 400 of an example gate driver architecture for a buck converter having a pulse generator 344 and a switch S1, in accordance with an embodiment of the present disclosure. Most of the circuit diagram 400 in FIG. 4 is similar to the circuit diagram 340 in FIG. 3D , and therefore uses the same reference numerals and will not be described again. In FIG. 4 , the LS gate drive path 349 may represent, for example, the LS level shifter 303 and the LS gate driver 305 in FIGS. 3A, 3C, and 3D .

[0065]

[0076] In a buck converter, output node 402 (having a positive output voltage Vout) is coupled to inductive element L1 and capacitive element C1, and low-side transistor M1 and the capacitive element are referenced to a reference potential node 404 (e.g., electrical ground) of the buck converter, as shown in FIG. 4. Because of these differences between a buck converter and an inverting buck-boost converter, there are some differences between the gate driver implementation for the buck converter of FIG. 4 and the gate driver implementation for the inverting buck-boost converter of FIG. 3D. For example, HS level shifter 302, pulse generator 344, and HS pull-down gate driver 326 each have a power supply input coupled between input node 227 (having Vin) and reference potential node 404. Therefore, the HS_DRV_GS_SW and HS_DRV_PD signals swing between Vin and 0V, rather than between Vfloat,n and Vout. Also, because Vin is a higher positive voltage than Vout and the common mode voltage for the buck converter is Vout, there is no need to include switch S2 and control logic 348 to detect a high impedance state and floating rail generator 301. Furthermore, there is no need to include floating rail generator 301 because Vin is already available and provides a stable voltage to power the components in the high-side pull-down path. Furthermore, there is no need to use a bootstrap capacitor.

[0066]

[0077] In this case, high-side pullup gate driver 324 can use CBST to turn on the transistor, as described above. When transistor M0 is to be turned off, a two-stage approach is used: pulse generator 344 generates a pulse with amplitude Vin in the HS_DRV_PD signal, which turns on an n-type transistor in pull-down driver 326 and creates a discharge path for the gate of transistor M0 to be pulled down toward 0V. When the gate voltage of transistor M0 falls sufficiently below Vin, HS_DRV_GS_SW at Vin can close switch S1, shorting the gate and source of transistor M0 and turning off this high-side transistor.

[0067]

[0078] As presented above, certain aspects of the present disclosure provide a switched mode power supply (SMPS) circuit. The SMPS circuit generally includes a high-side n-channel transistor, a segmented gate driver (also called a "split driver") for the high-side n-channel transistor, and a two-stage pull-down path. The first stage can pull down to the output (or ground), and the second stage can pull down to a switching node.

[0068] Exemplary Operations for Providing Power

[0079] 5 is a flow diagram of example operations 500 for supplying power according to an embodiment of the present disclosure. The operations 500 may be performed by a switched mode power supply (SMPS) circuit having a pulse generator and one or more auxiliary switches, such as the SMPS circuits having circuit diagrams 340 and 400 including the pulse generator 344 and switches S1 and S2 of FIGS. 3D and 4.

[0069]

[0080] The operations 500 may begin by pulling down the gate voltage of a high-side transistor (e.g., transistor M0) in the SMPS circuit in block 502. Once the gate voltage is pulled down to a certain voltage level (e.g., a threshold voltage below Vfloat,n or Vin), a first switch (e.g., switch S1) is closed in block 504, effectively shorting the gate and source of the high-side transistor and turning it off.

[0070]

[0081] According to one aspect, the pull-down in block 502 involves generating a pulse (e.g., at HS_DRV_PD) to turn on an n-type transistor (not shown) in a pull-down gate driver (e.g., HS pull-down gate driver 326). In one aspect, the SMPS circuit includes an inverting buck-boost converter, and the pull-down gate driver may be referenced to the output voltage (e.g., Vout) of the inverting buck-boost converter. In this case, the pulse is generated from a pulse generator (e.g., pulse generator 344), and the pulse generator and pull-down gate driver may receive power at a floating voltage (e.g., Vfloat,n) from a floating power supply (e.g., floating rail generator 301), which may be referenced to the output voltage of the inverting buck-boost converter, and the specified voltage level may be a transistor threshold voltage (Vth) lower than the floating voltage of the floating power supply. In another aspect, the SMPS circuit includes a buck converter, and the pull-down gate driver may be referenced to a reference potential for the buck converter. In this case, the pulse may be generated from the pulse generator. The pulse generator and pull-down gate driver can receive power at an input voltage (e.g., Vin) from an input voltage source, where the input voltage source is referenced to a reference potential for the buck converter (e.g., electrical ground of 0V), and the specified voltage level is a transistor threshold voltage (e.g., Vth) lower than the input voltage of the input voltage source.

[0071]

[0082] According to an aspect, the operations 500 may further include receiving a control signal (e.g., HS_DRV_GS_SW) from a level shifter (e.g., HS level shifter 302). In this case, the pulse generator may be a one-shot pulse generator, and generating may involve triggering generation of the pulse based on a rising edge of the control signal from the level shifter.

[0072]

[0083] According to an embodiment, the operations 500 may further include determining whether the SMPS circuit is in discontinuous conduction mode (DCM), whether the source of the high-side transistor is in a high-impedance (Hi-Z) state, or whether the SMPS circuit is disabled. Based on the determination, a second switch (e.g., switch S2) may be closed to short the gate of the high-side transistor to the source.

[0073] Exemplary Embodiments

[0084] In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below.

[0074]

[0085] Aspect 1: A switched mode power supply (SMPS) circuit comprising: a high-side transistor; a pull-down gate driver having an output coupled to a gate of the high-side transistor; a pulse generator having an output coupled to an input of the pull-down gate driver; and a first switch coupled between the gate and source of the high-side transistor.

[0075]

[0086] Aspect 2: The SMPS circuit of aspect 1, further comprising: a first level shifter having an output coupled to the input of the pulse generator.

[0076]

[0087] Aspect 3: The SMPS circuit of aspect 2, wherein the output of the first level shifter is further coupled to a control input of the first switch.

[0077]

[0088] Aspect 4: The SMPS circuit of any one of Aspects 1 to 3, further comprising: a second switch coupled between the gate and source of the high-side transistor; and control logic having an output coupled to a control input of the second switch.

[0078]

[0089] Aspect 5: The SMPS circuit of aspect 4, wherein the control logic is configured to close the second switch when at least one of the SMPS circuit is in discontinuous conduction mode (DCM), when the source of the high-side transistor is in a high impedance state, or when the SMPS circuit is disabled.

[0079]

[0090] Aspect 6: The SMPS circuit of any one of Aspects 2 to 5, wherein the SMPS circuit comprises an inverting buck-boost converter including a high-side transistor, the inverting buck-boost converter further comprising an input voltage node coupled to a drain of the high-side transistor, an output voltage node, and a low-side transistor having a drain coupled to a source of the high-side transistor at a switching node and having a source coupled to the output voltage node, the SMPS circuit further comprising a voltage source coupled between the output voltage node and a floating power supply rail, the first level shifter, the pulse generator, and the pull-down gate driver each having a first power supply input coupled to the floating power supply rail and a second power supply input coupled to the output voltage node.

[0080]

[0091] Aspect 7: The SMPS circuit of aspect 6, wherein the SMPS circuit further comprises a pull-up gate driver having an output coupled to a gate of the high-side transistor, and a second level shifter having an output coupled to an input of the pull-up gate driver, the second level shifter and the pull-up gate driver each having a first power supply input coupled to a power supply rail referenced to the input voltage node, and a second power supply input coupled to the input voltage node.

[0081]

[0092] Aspect 8: The SMPS circuit of aspect 6 or 7, wherein the pulse generator is configured to output a pulse having a width greater than a transition of a gate voltage at the gate of the high-side transistor from an input voltage at the input voltage node to an output voltage at the output voltage node.

[0082]

[0093] Aspect 9: The SMPS circuit of any one of Aspects 6 to 8, wherein the SMPS circuit lacks a bootstrap capacitor selectively coupled between the floating power rail and the switching node.

[0083]

[0094] Aspect 10: The SMPS circuit of any one of aspects 6 to 9, wherein the first switch is implemented as back-to-back n-channel transistors such that the first switch is configured to be closed when the gate voltage of the high-side transistor is lower than the voltage of the floating power supply rail by at least the threshold voltage of one of the back-to-back n-channel transistors.

[0084]

[0095] Embodiment 11: The SMPS circuit of any one of embodiments 1 to 10, further comprising a deep n-well bias circuit having an output coupled to a transistor body input of the pull-down gate driver.

[0085]

[0096] Aspect 12: An SMPS circuit according to any one of aspects 1 to 3, wherein the SMPS circuit comprises a step-down converter including a high-side transistor and having an input voltage node coupled to the drain of the high-side transistor, and the first level shifter, pulse generator, and pull-down gate driver each have a first power supply input coupled to the input voltage node and a second power supply input coupled to a reference potential node of the SMPS circuit.

[0086]

[0097] Aspect 13: The SMPS circuit of aspect 12, wherein the SMPS circuit further comprises a pull-up gate driver having an output coupled to a gate of the high-side transistor, and a second level shifter having an output coupled to an input of the pull-up gate driver, the second level shifter and the pull-up gate driver each having a first power supply input coupled to a power supply rail referenced to the input voltage node, and a second power supply input coupled to the input voltage node.

[0087]

[0098] Aspect 14: The SMPS circuit of aspect 12 or 13, wherein the first switch is implemented as back-to-back n-channel transistors, and the first switch is configured to be closed when the gate voltage of the high-side transistor is lower than the voltage of the input voltage node by at least a threshold voltage of one of the back-to-back n-channel transistors.

[0088]

[0099] Aspect 15: The SMPS circuit of any one of aspects 2 to 14, wherein the pulse generator comprises a one-shot pulse generator configured to output a pulse that is triggered based on a rising edge of the output signal from the first level shifter.

[0089]

[0100] Aspect 16: A power management integrated circuit (PMIC) including at least a portion of the SMPS circuit according to any one of aspects 1 to 15.

[0090]

[0101] Aspect 17: A method of supplying power, comprising: pulling down a gate voltage of a high-side transistor in a switched mode power supply (SMPS) circuit; and, when the gate voltage is pulled down to a particular voltage level, closing a first switch to effectively short-circuit the gate and source of the high-side transistor, turning off the high-side transistor.

[0091]

[0102] Embodiment 18: The method of embodiment 17, wherein the pulling down includes generating a pulse to turn on an n-type transistor in a pull-down gate driver.

[0092]

[0103] Embodiment 19: The method of embodiment 18, wherein the SMPS circuit comprises an inverting buck-boost converter, and wherein the pull-down gate driver is referenced to the output voltage of the inverting buck-boost converter.

[0093]

[0104] Aspect 20: The method of aspect 19, wherein the pulse is generated from a pulse generator, the pulse generator and the pull-down gate driver receive power from a floating power supply at a floating voltage, the floating power supply is referenced to the output voltage of the inverting buck-boost converter, and the specific voltage level is a transistor threshold voltage lower than the floating voltage of the floating power supply.

[0094]

[0105] Embodiment 21: The method of embodiment 18, wherein the SMPS circuit comprises a buck converter, and the pull-down gate driver is referenced to a reference potential of the buck converter.

[0095]

[0106] Aspect 22: The method described in aspect 21, wherein the pulse is generated from a pulse generator, the pulse generator and the pull-down gate driver receive power at an input voltage from an input voltage source, the input voltage source being referenced to a reference potential of the step-down converter, and the specific voltage level being a transistor threshold voltage lower than the input voltage of the input voltage source.

[0096]

[0107] Aspect 23: The method of aspect 22, further comprising receiving a control signal from a level shifter, wherein the pulse generator comprises a one-shot pulse generator, and generating comprises triggering generation of a pulse based on a rising edge of the control signal from the level shifter.

[0097]

[0108] Aspect 24: The method of any one of aspects 17 to 23, further comprising: determining whether the SMPS circuit is in discontinuous conduction mode (DCM), the source of the high-side transistor is in a high impedance state, or the SMPS circuit is disabled; and, based on the determination, closing a second switch to short the gate of the high-side transistor to the source.

[0098] Additional Considerations

[0109] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions, which may include various hardware and / or software components and / or modules, including, but not limited to, circuits, application-specific integrated circuits (ASICs), or processors. Generally, when operations are illustrated in figures, the operations may have corresponding equivalent means-plus-function components that are similarly numbered.

[0099]

[0110] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, database, or another data structure), ascertaining, etc. "Determining" can also include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. "Determining" can also include resolving, selecting, choosing, establishing, etc.

[0100]

[0111] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. By way of example, "at least one of a, b, or c" is intended to encompass a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or a, b, and c in any other order).

[0101]

[0112] The methods disclosed herein include one or more steps or actions for achieving the described method. The steps and / or actions of those methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0102]

[0113] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. High-side transistor and The input voltage node coupled to the drain of the high-side transistor, Output voltage node, A low-side transistor having a drain coupled to the source of the high-side transistor in the switching node, and a source coupled to the output voltage node, An inverting buck-boost converter equipped with A pull-down gate driver having an output coupled to the gate of the high-side transistor, wherein the pull-down gate driver references the output voltage of the inverting buck-boost converter. A pulse generator having an output coupled to the input of the pull-down gate driver, A first switch coupled between the gate and source of the high-side transistor, A first level shifter having an output coupled to the input of the pulse generator, A voltage source coupled between the output voltage node and the floating power rail and Equipped with, A switch-mode power supply (SMPS) circuit in which the first level shifter, the pulse generator, and the pull-down gate driver each have a first power input coupled to the floating power rail and a second power input coupled to the output voltage node.

2. The SMPS circuit according to claim 1, wherein the output of the first level shifter is further coupled to the control input of the first switch.

3. A second switch coupled between the gate and the source of the high-side transistor, A control logic having an output coupled to the control input of the second switch, The SMPS circuit according to claim 1, further comprising the following:

4. The SMPS circuit according to claim 3, wherein the control logic is configured to close the second switch when the SMPS circuit is in discontinuous conduction mode (DCM), when the source of the high-side transistor is in a high impedance state, or when the SMPS circuit is disabled.

5. The SMPS circuit, A pull-up gate driver having an output coupled to the gate of the high-side transistor, A second level shifter having an output coupled to the input of the pull-up gate driver, The second level shifter and the pull-up gate driver each have a first power input coupled to a power rail referenced to the input voltage node and a second power input coupled to the input voltage node. The SMPS circuit according to claim 1.

6. The SMPS circuit according to claim 1, wherein the pulse generator is configured to output a pulse having a width greater than the transition of the gate voltage at the gate of the high-side transistor from the input voltage at the input voltage node to the output voltage at the output voltage node.

7. The SMPS circuit according to claim 1, wherein the SMPS circuit lacks a bootstrap capacitor selectively coupled between the floating power rail and the switching node.

8. The SMPS circuit according to claim 1, wherein the first switch is implemented as a back-to-back n-channel transistor, and is configured to close when the gate voltage of the high-side transistor is lower than the voltage of the floating power rail by at least the threshold voltage of one of the back-to-back n-channel transistors.

9. The SMPS circuit according to claim 1, further comprising a deep n-well bias circuit having an output coupled to the transistor body input of the pull-down gate driver.

10. A power management integrated circuit (PMIC) comprising at least a portion of the SMPS circuit described in claim 1.

11. A method of supplying electricity, Pulling down the gate voltage of the high-side transistor in the switch-mode power supply (SMPS) circuit described in claim 1, wherein the pull-down includes generating a pulse in the pulse generator for turning on the n-type transistor in the pull-down gate driver, When the gate voltage is pulled down to a specific voltage level lower than the floating voltage of the floating power source referenced to the output voltage at the output voltage node, the first switch is closed to effectively short-circuit the gate and source of the high-side transistor and turn off the high-side transistor. A method that includes this.

12. The determination of whether the SMPS circuit is in discontinuous conduction mode (DCM), whether the source of the high-side transistor is in a high impedance state, or whether the SMPS circuit is disabled, Based on the above determination, the second switch is closed in order to short-circuit the gate of the high-side transistor to the source, The method according to claim 11, further comprising:

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