Counting mode determination circuit and counting mode determination method

Abstract

The present disclosure generally relates to a counting mode determination circuit configured to determine, for at least one imaging element, a photon count in a first photon counting mode of at least two sequentially applied photon counting modes in a standard operating mode, and to skip a second photon counting mode of the at least two photon counting modes if the photon count in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operating mode.

Description

[Technical Field]

[0001] The present disclosure generally relates to a counting mode determination circuit and a counting mode determination method for determining a photon counting mode. [Background technology]

[0002] Photon counting methods are commonly known. Such techniques may rely on the use of photodiodes such as SPADs (single photon avalanche diodes).

[0003] SPADs can be biased in Geiger mode and have large gain for counting (single photons), allowing them to be used in low light conditions.

[0004] Furthermore, it is known to combine SPAD-based photon counting with high dynamic range photodetection by employing two different exposure times, for example, a long exposure and a short exposure.

[0005] Although techniques for photon counting exist, it is generally desirable to provide a counting mode determination circuit and method. Summary of the Invention [Means for solving the problem]

[0006] According to a first aspect, the present disclosure provides a method for detecting a number of photons in a first photon counting mode of at least two sequentially applied photon counting modes in a standard operation mode for at least one image sensor; Provided is a counting mode determination circuit configured to skip a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from a standard operating mode.

[0007] According to a second aspect, the present disclosure provides a method for detecting a number of photons in a first photon counting mode of at least two sequentially applied photon counting modes in a standard operating mode for at least one image sensor; A counting mode determination method is provided that includes skipping a second photon counting mode of at least two photon counting modes if the number of photons in a first photon counting mode exceeds a predetermined threshold, thereby deviating from a standard operating mode.

[0008] Further aspects are set out in the dependent claims, the drawings and the following description.Embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which: FIG. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a simplified diagram of a pixel circuit including a SPAD and a counter. [Figure 2a] An example of a general diagram of a two-pixel arrangement where counters are not shared is shown. [Figure 2b] 1 shows an example of a general diagram of a two pixel arrangement where the counter is shared for the first SPAD. [Figure 2c] 1 shows an example of a general diagram of a two pixel arrangement where the counter is shared for the second SPAD. [Figure 3] 10 illustrates an embodiment of a counter mode sequence according to a standard operating mode of an imaging device in accordance with the present disclosure. [Figure 4] 10 is a graph of a Poisson distribution that can be used as the light distribution of a SPAD. [Figure 5] 1 illustrates one embodiment of a counting mode decision circuit according to the present disclosure. [Figure 6] 1 illustrates, in block diagram form, one embodiment of a counting mode determination method according to the present disclosure. [Figure 7] 1 illustrates a block diagram of a further embodiment of a counting mode determination method according to the present disclosure, where two LCBL modes are performed and the SCBL mode is skipped. [Figure 8]10 illustrates in block diagram form a further embodiment of a counting mode determination method according to the present disclosure, where the number of photons is not sufficient and therefore the counting mode is not skipped; DETAILED DESCRIPTION OF THE INVENTION

[0010] Before providing a detailed description of the embodiment starting with FIG. 1, a general description will be provided.

[0011] As mentioned in the introduction, photon counting based on SPADs (Single Photon Avalanche Diodes) is generally known, and it is also known to combine it with HDR (High Dynamic Range) photodetection. Due to the ability of SPADs to detect the environment, it has been recognized that HDR can potentially be realized with SPADs.

[0012] However, it is recognized that Geiger bias in SPADs can cause them to trigger too frequently, resulting in high power consumption.

[0013] It has therefore been recognised that it may be desirable to provide circuits and methods that combine the two techniques of single photon counting and high dynamic range photodetection, and that combinations may be possible by determining when to skip one of the two modes, or by skipping single exposures in different counting modes.

[0014] Furthermore, it is recognized that due to the trend towards miniaturization of SPAD pixels, unnecessary circuitry needs to be avoided. Also, to further reduce pixel size, the counter length may need to be made smaller so as not to occupy too much space on the chip / sensor. Therefore, it is recognized that pixels can share counters, thereby reducing the number of counters and reducing pixel size.

[0015] Accordingly, some embodiments relate to a counting mode determination circuit configured to, for at least one imaging element, determine a number of photons in a first photon counting mode of at least two photon counting modes that are applied sequentially in a standard operating mode, and skip a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operating mode.

[0016] The circuitry relates to any entity or multiple entities that can be used to generate signals so that counting and determination according to the present disclosure can be performed. For example, the circuitry may be based on a processor, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array). Different types of such entities may also be used to perform the present disclosure, such as a processor including at least one CPU and one GPU, between which tasks may be distributed. Furthermore, the circuitry may include corresponding wiring and / or connections for transmitting signals, as is commonly known. For example, the present disclosure may be applied to a camera system. Accordingly, the present disclosure also relates to a sensor, camera, and / or photodetection system that includes a counting mode determination circuit according to the present disclosure.

[0017] The circuitry can be configured to determine a counting mode, i.e., a mode indicating how to count photons that may be incident on the imager (e.g., SPAD (single photon avalanche diode), APD (avalanche photodiode), etc.). For example, if it is known in advance not to count too many photons (below a predetermined threshold), a "low photon count" counting mode may be applied. In such a mode, a photon counter with a low bit length may be used. On the other hand, if the ambient light is high (i.e., above a predetermined threshold), a "high photon count" mode may be applied, in which a photon counter with a high bit length may be used.

[0018] In some embodiments, the circuit is configured to determine the number of photons in a first photon counting mode of at least two photon counting modes. In a standard operating mode, these two modes may (usually) be applied sequentially, i.e., the first photon counting mode may be applied first (e.g., a high photon counting mode), and then the second photon counting mode may be applied (e.g., a low photon counting mode). Such a standard operating mode may be based on an approach of first performing a coarse photon number estimate and then a fine photon number estimate, etc.

[0019] In some embodiments, the number of photons in the first counting mode may be sufficiently high (or low) such that the second photon counting mode is not applied, i.e., is skipped, as opposed to the standard operating mode.

[0020] In some embodiments, the at least two photon counting modes may include a long counter bit length (LCBL) mode and a short counter bit length (SCBL) mode, as described above.

[0021] It should be noted that there may also be other counting modes, such as medium bit length, very short or very long bit length modes, etc. Furthermore, there may be sub-modes of each "main" mode, such as LCBL A mode, LCBL B mode, SCBL A mode, SCBL B mode, etc., which may be determined based on external circumstances, in addition or alternatively, apart from different counter bit lengths.

[0022] Furthermore, the sequential execution of modes should not be construed as requiring that the SCBL mode necessarily follow the first LCBL mode: for example, an LCBL mode may be applied, an intermediate mode may be applied, and then a SCBL mode may be applied, and yet the SCBL mode may be skipped based on photon counting of the SCBL mode.

[0023] Furthermore, if two LCBL modes are applied, the SCBL mode may be skipped over the first of them, and so on.

[0024] However, the present disclosure is not limited to the above case. For example, in low light conditions, it may be sufficient to perform only low bit length measurements (e.g., SCBL mode) and skip high bit length measurements (e.g., LCBL mode) if the counter is not saturated.

[0025] In some embodiments, the first photon counting mode is based on an LCBL mode, as described herein, and the second photon counting mode comprises an SCBL mode.

[0026] In some embodiments, the LCBL mode is based on at least two counters shared for at least one imager.

[0027] According to the present disclosure, (re)configurable counters can be used. For example, in the simplest case of two counters and two imagers (e.g., SPADs), each of the two imagers can have a counter assigned to it in SCBL mode. However, in LCBL mode, the two counters may be assigned to only one of the imagers, and the other imager may not have a counter. In such an embodiment, the bit length can be increased by connecting two counters in series.

[0028] However, the present disclosure is not limited to this case. For example, in order to avoid sacrificing resolution as in the above example, multiple (at least two) counters may be used for one image sensor, and a long counter bit length may be realized for each image sensor. In such a case, at least two short counters may be reconfigurable as long counters, or a short counter and a long counter may be provided, and these two counters may be switchable.

[0029] In some embodiments, at least one imager is based on a single-photon avalanche diode, as described herein. In general, the present disclosure can be applied by any circuit that provides counting of (single) photons.

[0030] In some embodiments, in SCBL mode, the two counters are configured to count photons of at least two different imagers as described herein.

[0031] In some embodiments, the predetermined threshold is based on a standard deviation from the photon count, as described with reference to FIG.

[0032] In some embodiments, the circuit further includes a logic element configured to generate a skip signal to skip the SCBL mode if the counting mode decision circuit indicates that the two LCBL modes exceed a predetermined threshold when operating in two consecutive LCBL modes.

[0033] In some embodiments, the logic element is further configured to store a logic value in the memory, the logic value indicating the result of the comparison of two successive LCBL modes.

[0034] However, it should be noted that an element other than the logic element may be used to generate the skip signal and / or store the logic value, and such another element may use a signal from the logic element, but may be separate from the logic element.

[0035] In some embodiments, the logic element is an exclusive OR (NOR) gate.

[0036] Some embodiments relate to a counting mode determination method as described herein that includes, for at least one imager, in a standard operating mode, determining a number of photons in a first photon counting mode of at least two sequentially applied photon counting modes, and skipping a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operating mode.

[0037] This method can be performed by a counting mode decision circuit according to the present disclosure.

[0038] In some embodiments, the at least two photon counting modes include a long counter bit length (LCBL) mode and a short counter bit length (SCBL) mode, as described herein. In some embodiments, the first photon counting mode is based on the LCBL mode, as described herein, and the second photon counting mode includes the SCBL mode. In some embodiments, the LCBL mode is based on at least two counters shared for at least one imager, as described herein. In some embodiments, the at least one imager is based on a single-photon avalanche diode, as described herein. In some embodiments, in the SCBL mode, the two counters are configured to count photons of at least two different imagers, as described herein. In some embodiments, the predetermined threshold is based on a standard deviation from the photon count, as described herein. In some embodiments, when the counting mode determination method is based on two consecutive LCBL modes, the counting mode determination method further includes generating a skip signal to skip the SCBL mode if the two LCBL modes indicate a count exceeding a predetermined threshold, as described herein. In some embodiments, the method further includes storing a logic value in a memory, the logic value indicating a result of a comparison of two successive LCBL modes as described herein. In some embodiments, generating the skip signal is performed based on an exclusive OR (NOR) gate.

[0039] The methods described herein are also, in some embodiments, implemented as a computer program that, when executed on a computer and / or processor, causes the computer and / or processor to perform the method. In some embodiments, a non-transitory computer-readable recording medium having stored thereon a computer program product that, when executed by a processor, such as the processors described above, causes the methods described herein to be performed is also provided.

[0040] It should be noted that an image sensor may be provided that includes or is connectable to circuitry according to the present disclosure, but this may not be limited to any sensor type. Thus, according to the present disclosure, the image sensor may be based on a single layer sensor, a stacked sensor, a backside illuminated sensor, a frontside illuminated sensor, etc.

[0041] Furthermore, the SPADs of the present disclosure may be externally clocked or non-externally clocked SPADs.

[0042] Furthermore, the circuitry and SPAD(s) may be provided on the same wafer or on different (stacked) wafers, and the polarity of the SPADs should not be construed as binding, as anodic or cathodic detection may be performed.

[0043] Signals EN_A and EN_B (see FIG. 2 or FIG. 5) are not intended to limit the disclosure in this regard and may be any signal, such as an external clock signal to the SPAD.

[0044] The mode may depend on the control of the SPAD. For example, in non-external clock control mode, SCBL mode may mean short exposure, and LCBL mode may mean long exposure.

[0045] On the other hand, SCBL in external clock control mode may mean long exposure, and LCBL mode may mean short exposure.

[0046] For example, if the SPAD is configured to trigger only once within a clock period, the SCBL may correspond to a long exposure. However, if the SPAD is configured to trigger multiple times within a clock period, the SCBL may correspond to a short exposure and the LCBL may correspond to a long exposure.

[0047] Returning to FIG. 1, a simplified diagram of a pixel circuit 1 including a SPAD 2 and a counter 3 is shown.

[0048] In this embodiment, the SPAD 2 is biased in Geiger mode so that it is configured to generate a pulse at its anode, i.e. so-called events, in the SPAD 2. This pulse is filtered by a comparator / inverter 4 (or other interface circuit) and then the events are counted by a counter 3.

[0049] For simplicity, SPAD2 is depicted as a passive quench structure, but it should be noted that it may be an active quench, an external clock-controlled quench, or other types of quench. Furthermore, the present disclosure is not limited to SPADs. For example, an APD or any other imaging element may be used to generate digital events in a similar manner. Furthermore, counter 3 is simplified by a counter block. Counter 3 may be based on a ripple counter, an LFSR (linear feedback shift register) counter, or any other circuit capable of accumulating events generated by SPAD2.

[0050] As mentioned above, counter sharing within a macropixel is utilized in some embodiments when high photon counts are expected. This corresponds to long exposure times in traditional multi-frame HDR (high dynamic range) techniques or long exposure times in non-externally controlled SPAD photon counting sensors. In externally clocked SPAD sensors, shorter exposure times can result in higher counts due to the higher external clock frequency, and this mode is sometimes referred to as long counter bit length (LCBL) mode. Therefore, a short exposure time with non-externally clocked control or a long exposure time with externally clocked control is sometimes referred to as SCBL (short counter bit length) mode.

[0051] Figure 2a shows an example of a general diagram of a two-pixel array 10. EN_A and EN_B represent signals for enabling / disabling SPAD_A (EN_A) and SPAD_B (EN_B), respectively. Counter_A and Counter_B share counts for SPAD_A (Counter_A) and SPAD_B (Counter_B), respectively. It should be understood that the counters are configurable, as will be explained with reference to Figures 2B and 2C.

[0052] Figure 2b shows a serial connection of counter_A and counter_B, where both counters are connected to SPAD_A (counter_A is connected to SPAD_A, and counter_B is connected to counter_A). Therefore, SPAD_B is not used in this embodiment.

[0053] Figure 2c shows another case where SPAD_A is not used because a counter is connected to SPAD_B.

[0054] Figure 3 shows one embodiment of a counter mode sequence 20 according to the standard operating mode of the imaging device. The letters below each mode refer to the counter configurations of Figures 2a-2c. That is, in Figure 3, (a) corresponds to the counter configuration of Figure 2a, (b) corresponds to the counter configuration of Figure 2b, and (c) corresponds to the counter configuration of Figure 2c.

[0055] Thus, first, counting of SPAD_B is done in LCBL mode A, then counting of SPAD_A is done in LCBL mode B, and then counting of both SPADs is done in SCBL mode.

[0056] To determine whether SCBL mode should be skipped, i.e., whether there is a deviation from the standard operating mode, we first describe some assumptions for an embodiment in which the counter length of each SPAD is 4 bits in SCBL mode and therefore 8 bits in LCBL mode.

[0057] For example, if the count in LCBL mode is 01000000 (binary) or greater (i.e., 64 decimal), the expected noise may correspond to at least one standard deviation. The corresponding distribution graph is shown in Figure 4. For SPADs, a Poisson distribution is assumed, but the present disclosure can be applied to any statistical distribution.

[0058] Therefore, one standard deviation is equivalent to 8 counts (because it is the square root of the counts).

[0059] If we are very confident, we can assume 6 standard deviations for the noise signal. Therefore, a high-confidence count could be equivalent to 64-6*√64=16 (64 minus 6 times the square root of 64 equals 16), which means that in 4-bit SCBL mode, the counter will saturate (also known as "hot"). Therefore, we can avoid SCBL counting and output 1111 according to our current assumptions, thereby saving power.

[0060] Therefore, in this embodiment, the photon number threshold is 64.

[0061] However, other assumptions for the standard deviation can be made depending on the circumstances and the respective counter bit length, as described herein.

[0062] 5 shows an embodiment of a counting mode decision circuit 40 according to the present disclosure, in which the left part (up to the counters) corresponds to the circuit described with reference to Figures 2a to 2c, with multiplexers MUX1 A and MUX1 B provided to interconnect the counters in order to establish their reconfigurability. Counters A and B are each 4-bit counters with bits Q0 to Q7, i.e. counter A has bits Q0 to Q3 and counter B has bits Q4 to Q7.

[0063] In this embodiment, a NOR gate is set after the output of counter B to monitor the outputs of the counters in LCBL Mode A and LCBL Mode B. The NOR gate is configured to output a logic zero if Q3*Q2 is greater than or equal to 01 (binary) or 10 (binary) or 11 (binary).

[0064] Furthermore, the output of the NOR gate is stored in memory cell 41 or 42, i.e., latched, and processed by other circuits to generate signals EN_A and EN_B. The two MSBs (most significant bits) of Q7 and Q6 are 01, 10, or 11 in LCBL mode A or LCBL mode B, and the output of the NOR gate is 0. This output is stored in a memory cell and combined with other possible control signals by additional circuits to control EN_A and EN_B, respectively. Since the corresponding NOR output is 0, EN_A or EN_B is 0, and the SPAD is disabled in the next SCBL mode.

[0065] If the two MSBs of Q7 and Q6 are 00, the output of the NOR gate is 1. This logical value is also stored in the memory cell and used to enable the SPAD device in the next SCBL mode, since no hot pixels are detected. In this way, meaningless counting in the SCBL is avoided, thereby saving power. Naturally, during the read phase, the data in the memory cell can be read to know the state of the SCBL count. For example, if it is decided to skip the SCBL mode, the counter data may contain only (logical) 1s; in such a case, it is not necessary to read such part of the data, and the complete 1 can be added directly by the host.

[0066] FIG. 6 illustrates in block diagram form a counting mode determination method 50 according to the present disclosure.

[0067] At 51, the photon count is determined for the LCBL mode imager as described herein.

[0068] At 52, the SCBL mode is skipped because the photon count exceeds a predetermined threshold.

[0069] 7 illustrates in block diagram form a counting mode decision method 60 according to the present disclosure, in which two LCBL modes are performed and then the SCBL mode is skipped based on the logic decision of a NOR gate as described herein.

[0070] At 61, the photon counts are determined for the imager in two successive LCBL modes as described herein.

[0071] At 62, a skip signal is generated based on the logic decision of the NOR gate, which indicates that the number of photons is sufficient to skip the SCBL mode.

[0072] At 62, SCBL mode is skipped.

[0073] FIG. 8 illustrates in block diagram form a counting mode determination method 70 according to the present disclosure where the number of photons is insufficient.

[0074] At 71, the photon counts for the imagers in two successive LCBL modes are determined and compared in a NOR gate as described herein.

[0075] At 72, the logic value of the NOR gate is stored in memory as described herein.

[0076] It should be appreciated that the embodiments describe the method in an exemplary order of method steps. However, the particular ordering of the method steps is provided for illustrative purposes only and should not be construed as binding, and variations in the ordering of the method steps may be apparent to one of ordinary skill in the art.

[0077] It should be noted that the division of circuitry 40 into units is done for illustrative purposes only, and the present disclosure is not limited to any particular division of functionality among particular units. For example, control circuitry 40 may be implemented by respective programmed processors, field programmable gate arrays (FPGAs), etc.

[0078] All units and entities described in this specification and recited in the accompanying claims may, unless otherwise stated, be implemented as integrated circuit logic on a chip, for example, and the functions provided by such units and entities may, unless otherwise stated, be implemented by software.

[0079] To the extent that the embodiments of the present disclosure described above are implemented, at least in part, using software-controlled data processing apparatus, it will be understood that computer programs providing such software control, and transmission, storage, or other media on which such computer programs are provided, are also contemplated as aspects of the present disclosure.

[0080] The present technology can also be configured as described below. (1) determining, for at least one image sensor, in a standard operating mode, a number of photons in a first photon counting mode of at least two sequentially applied photon counting modes; a counting mode determination circuit configured to skip a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operating mode. (2) The counting mode determination circuit according to (1), wherein the at least two photon counting modes include a long counter bit length (LCBL) mode and a short counter bit length (SCBL) mode. (3) The counting mode determination circuit according to (2), wherein the first photon counting mode is based on the LCBL mode and the second photon counting mode includes the SCBL mode. (4) The counting mode determination circuit according to (2) or (3), wherein the LCBL mode is based on at least two counters shared for the at least one imaging element. (5) The counting mode determination circuit according to (4), wherein the at least one imaging element is based on a single-photon avalanche diode. (6) The counting mode determination circuit according to (4) or (5), wherein in the SCBL mode, the two counters are configured to count photons for at least two different imaging elements. (7) A counting mode determination circuit according to any one of (1) to (6), wherein the predetermined threshold is based on a standard deviation from the number of photons. (8) The counting mode determination circuit according to any one of (2) to (7), further comprising a logic element configured to generate a skip signal for skipping the SCBL mode when the counting mode determination circuit indicates that the two LCBL modes exceed the predetermined threshold when operating in two consecutive LCBL modes. (9) The counting mode decision circuit of (8), wherein the logic element is further configured to store a logic value in memory, the logic value indicating the result of a comparison of two successive LCBL modes. (10) The counting mode determination circuit according to (8) or (9), wherein the logic element is an exclusive OR (NOR) gate. (11) determining, for at least one image sensor, a number of photons in a first photon counting mode of the at least two sequentially applied photon counting modes in a standard operating mode; skipping a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from a standard operating mode. (12) The counting mode determination method according to (11), wherein the at least two photon counting modes include a long counter bit length (LCBL) mode and a short counter bit length (SCBL) mode. (13) The counting mode determination method according to (12), wherein the first photon counting mode is based on the LCBL mode and the second photon counting mode includes the SCBL mode. (14) The counting mode determination method according to (12) or (13), wherein the LCBL mode is based on at least two counters shared for at least one imaging element. (15) The counting mode determination method according to (14), wherein the at least one imaging element is based on a single-photon avalanche diode. (16) The counting mode determination method according to (14) or (15), wherein in the SCBL mode, the two counters are configured to count photons for at least two different imaging elements. (17) A counting mode determination method according to any one of (11) to (16), wherein the predetermined threshold is based on a standard deviation from the number of photons. (18) A counting mode determination method according to any one of (12) to (17), wherein when the counting mode determination method is based on two consecutive LCBL modes, the counting mode determination method further comprises generating a skip signal to skip the SCBL mode if the two LCBL modes indicate that they exceed the predetermined threshold. (19) The counting mode determination method according to (18), further comprising storing the logic value in a memory, the logic value indicating the result of a comparison of two successive LCBL modes. (20) A counting mode determination method according to (18) or (19), wherein the skip signal is generated based on an exclusive OR (NOR) gate. (21) A computer program comprising a program code that, when executed on a computer, causes the computer to perform any one of the methods described in (11) to (20). (22) A non-transitory computer-readable recording medium storing a computer program product that, when executed by a processor, causes the method according to any one of (11) to (20) to be performed.

Claims

1. determining, for at least one image sensor, in a standard operating mode, a number of photons in a first photon counting mode of at least two sequentially applied photon counting modes; a counting mode decision circuit configured to skip a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from the standard operating mode.

2. 2. The counting mode decision circuit of claim 1, wherein the at least two photon counting modes include a long counter bit length (LCBL) mode and a short counter bit length (SCBL) mode.

3. 3. The counting mode determination circuit of claim 2, wherein the first photon counting mode is based on the LCBL mode and the second photon counting mode includes the SCBL mode.

4. The counting mode decision circuit of claim 2 , wherein the LCBL mode is based on at least two counters shared for the at least one image sensor.

5. 5. The counting mode determination circuit of claim 4, wherein the at least one imaging element is based on a single photon avalanche diode.

6. The counting mode determination circuit of claim 4 , wherein in the SCBL mode, the two counters are configured to count photons for at least two different image sensors.

7. 2. The counting mode decision circuit of claim 1, wherein the predetermined threshold is based on a standard deviation from the photon count.

8. 3. The counting mode decision circuit of claim 2, further comprising: a logic element configured to generate a skip signal to skip the SCBL mode when the counting mode decision circuit operates in two consecutive LCBL modes and indicates that the two LCBL modes exceed the predetermined threshold.

9. 9. The counting mode decision circuit of claim 8, wherein the logic element is further configured to store a logic value in a memory, the logic value indicating a result of a comparison of two successive LCBL modes.

10. 9. The counting mode decision circuit of claim 8, wherein the logic element is an exclusive OR (NOR) gate.

11. determining, for the at least one image sensor, in a standard operating mode, a number of photons in a first photon counting mode of the at least two sequentially applied photon counting modes; skipping a second photon counting mode of the at least two photon counting modes if the number of photons in the first photon counting mode exceeds a predetermined threshold, thereby deviating from a standard operating mode.

12. 12. The counting mode determination method of claim 11, wherein the at least two photon counting modes include a long counter bit length (LCBL) mode and a short counter bit length (SCBL) mode.

13. 13. The counting mode determination method of claim 12, wherein the first photon counting mode is based on the LCBL mode and the second photon counting mode includes the SCBL mode.

14. The counting mode determination method of claim 12 , wherein the LCBL mode is based on at least two counters shared for at least one image sensor.

15. 15. The counting mode determination method of claim 14, wherein the at least one imaging element is based on a single photon avalanche diode.

16. The counting mode determination method of claim 14 , wherein in the SCBL mode, the two counters are configured to count photons for at least two different image sensors.

17. The counting mode determination method of claim 11 , wherein the predetermined threshold is based on a standard deviation from the photon count.

18. 13. The counting mode determination method of claim 12, wherein when the counting mode determination method is based on two consecutive LCBL modes, the counting mode determination method further comprises generating a skip signal to skip the SCBL mode if the two LCBL modes indicate a value exceeding the predetermined threshold.

19. 20. The counting mode determination method of claim 18, further comprising: storing the logic value in a memory, the logic value indicating a result of a comparison of two consecutive LCBL modes.

20. 20. The counting mode determining method of claim 18, wherein the skip signal is generated based on an exclusive OR (NOR) gate.

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