Frequency Mixing

Abstract

An apparatus for mixing signals is disclosed. In an exemplary embodiment, the apparatus includes a mixer circuit having a plurality of local oscillator nodes, a first node corresponding to a first frequency, and a plurality of second nodes corresponding to a second frequency. The mixer circuit includes a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes. The mixer circuit has a plurality of switches including a first switch, a second switch, a third switch, and a fourth switch. The plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes. The first switch and the second switch are coupled between the plurality of capacitors and the first node. The first switch and the second switch are disposed between the fourth switch and the third switch.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] The present disclosure relates generally to signal communication or processing using electronic devices, and more particularly to mixer circuits that can be used for frequency conversion. [Background technology]

[0002]

[0002] Electronic devices include traditional computing devices such as desktop computers, notebook computers, smartphones, wearable devices such as smart watches, internet servers, etc. Electronic devices also include other types of computing devices, such as personal voice assistants (e.g., smart speakers), wireless access points or routers, thermostats and other automatic control devices, robotics, automotive electronics, devices embedded in other machines such as refrigerators and industrial tools, Internet of Things (IoT) devices, medical devices, etc. These various electronic devices provide services related to productivity, communication, social interaction, security, health and safety, remote management, entertainment, transportation, and information dissemination. Thus, electronic devices play a vital role in modern society.

[0003] Many of the services provided by electronic devices in today's interconnected world rely, at least in part, on electronic communications. Electronic communications can include those exchanged between two or more electronic devices using wireless or wired signals transmitted over one or more networks, such as the Internet, a Wi-Fi network, or a cellular network. Thus, electronic communications can include wireless or wired transmission and reception. To transmit and receive communications, electronic devices can use transceivers, such as wireless transceivers designed for wireless communication.

[0004]

[0004] Thus, electronic communications may be realized by propagating signals between two wireless transceivers in two different electronic devices. For example, a smartphone may use a wireless transmitter to transmit wireless signals over the air to a base station as part of uplink communications to support mobile services. The smartphone may use a wireless receiver to receive wireless signals transmitted from a base station over the air as part of downlink communications to enable mobile services. With a smartphone, mobile services may include voice and video calls, participating in social media interactions, sending messages, watching movies, sharing videos, performing searches, using map information or navigation instructions, finding friends, engaging in location-based services in general, sending money, obtaining other services such as ridesharing, and the like.

[0005] Many of these mobile services rely, at least in part, on the transmission or reception of wireless signals between two or more electronic devices. As a result, researchers, electrical engineers, and electronic device designers strive to develop wireless transceivers that can effectively use wireless signals to provide these and other mobile services. Summary of the Invention

[0006] To transmit or receive wireless signals, a wireless transceiver or radio-frequency (RF) front end may include a transmit chain or a receive chain that processes a propagated signal. Part of the signal processing may include converting the signal from a first frequency to a second frequency. A mixer circuit may perform the frequency conversion using a local oscillator signal from a local oscillator (LO). The mixer circuit may use multiple switches to combine a first signal at a first frequency with the local oscillator signal to generate a second signal at a second frequency. In the case of differential signaling at the input and / or output of the mixer circuit, the multiple switches may be four. To address noise from the local oscillator, this specification describes how multiple switches may be symmetrically arranged on a substrate. For example, the first switch and the second switch may be arranged on different sides of a line of symmetry. Additionally or alternatively, the third and fourth switches can be positioned opposite the first and second switches such that the first and second switches are "sandwiched" between the third and fourth switches along an axis that lies in the plane of the substrate, the axis being perpendicular to the line of symmetry. Furthermore, area reduction and layout simplification can be facilitated by employing coupling capacitors and / or bias resistors that are each shared between at least two of the multiple switches. In such cases, the local oscillator signal or bias signal can propagate through a given capacitor or resistor, respectively, to reach at least two switches that share the capacitor or resistor. These and other implementations are described herein.

[0007]

[0007] In one exemplary aspect, an apparatus for frequency mixing is disclosed. The apparatus includes a mixer circuit. The mixer circuit includes a plurality of local oscillator nodes, a first node corresponding to a first frequency, and a plurality of second nodes corresponding to a second frequency. The mixer circuit also includes a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes. The mixer circuit further includes a plurality of switches including a first switch, a second switch, a third switch, and a fourth switch. The plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes. The first switch and the second switch are coupled between the plurality of capacitors and the first node. The first switch and the second switch are disposed between the fourth switch and the third switch.

[0008]

[0008] In one exemplary aspect, an apparatus for frequency mixing is disclosed. The apparatus includes a mixer circuit. The mixer includes a plurality of local oscillator nodes, a first node corresponding to a first frequency, and a plurality of second nodes corresponding to a second frequency. The mixer circuit also includes a plurality of capacitors and a plurality of switches. The plurality of capacitors are coupled between the plurality of local oscillator nodes and the plurality of second nodes. The plurality of switches include a first switch, a second switch, a third switch, and a fourth switch. The plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes. The first switch and the second switch are coupled between the plurality of capacitors and the first node, and the third switch and the fourth switch are coupled to each other via a floating node. The mixer circuit further includes means for increasing symmetry-dependent linearity.

[0009] In one exemplary aspect, an apparatus for frequency mixing is disclosed. The apparatus includes a mixer circuit. The mixer circuit includes a first local oscillator node, a second local oscillator node, and a first node corresponding to a first frequency. The mixer circuit also includes a first capacitor, a second capacitor, and second and third nodes, each corresponding to the second frequency. The mixer circuit additionally includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is coupled between the first capacitor and the second node, and the first switch is further coupled between the first capacitor and the first node. The second switch is coupled between the second capacitor and the third node, and the second switch is further coupled between the second capacitor and the first node. The third switch is coupled between the first capacitor and the third node. The fourth switch is coupled between the second capacitor and the second node, the first capacitor is coupled between the first local oscillator node and the first and third switches, and the second capacitor is coupled between the second local oscillator node and the fourth and second switches.

[0010] In one exemplary aspect, a method for mixing signals is disclosed. The method includes receiving a first signal at a first switch and a second switch via a first node, the first signal corresponding to a first frequency. The method also includes receiving a positive local oscillator signal at a first switch and a third switch via a first capacitor, and receiving a negative local oscillator signal at a second switch and a fourth switch via a second capacitor. The method further includes mixing the first signal, the positive local oscillator signal, and the negative local oscillator signal using the first switch, the second switch, the third switch, and the fourth switch to generate a second signal corresponding to a second frequency. The method further includes providing the second signal from the first switch, the second switch, the third switch, and the fourth switch via a plurality of second nodes. [Brief explanation of the drawings]

[0011] [Figure 1] 1 illustrates an environment having an exemplary electronic device having a wireless interface device that includes at least one exemplary mixer circuit. [Figure 2]

[0012] 1 is a schematic diagram illustrating an example radio frequency (RF) front end and an example transceiver, each of which may include at least one mixer circuit. [Figure 3]

[0013] FIG. 1 is a schematic diagram illustrating an example of multiple receive chains that may each include at least one frequency converter as part of a wireless interface device. [Figure 4]

[0014] 1 is a schematic diagram illustrating an exemplary frequency converter including a mixer circuit and a local oscillator. [Figure 5]

[0015] 1 is a schematic diagram illustrating an example mixer circuit including multiple nodes, multiple switches, and multiple capacitors. [Figure 6]

[0016] 1 is a schematic diagram illustrating an example implementation of a plurality of switches including two switches symmetrically coupled to a node with respect to a line of symmetry. [Figure 7]

[0017] FIG. 1 is a circuit diagram illustrating an example mixer circuit including multiple nodes, multiple switches, multiple capacitors, and multiple resistors. [Figure 8]

[0018] 1 is a flow diagram illustrating an example process for mixing signals and / or operating a mixer circuit. DETAILED DESCRIPTION OF THE INVENTION

[0012] Introduction and Overview

[0019] To facilitate the transmission and reception of wireless signals, electronic devices may use wireless interface devices including wireless transceivers and / or radio frequency (RF) front ends. Electronic devices communicate using wireless signals using EM signaling at various frequencies within a portion of the electromagnetic (EM) spectrum. These wireless signals may travel between two electronic devices oscillating at specific frequencies, such as kilohertz (kHz), megahertz (MHz), or gigahertz (GHz). However, the EM spectrum is a finite resource that limits the number of signals that can be communicated simultaneously in any given spatial area. There are already billions of electronic devices that use this limited resource. To enable more simultaneous communications using EM signaling, the finite EM spectrum can be shared between electronic devices. The EM spectrum can be shared using, for example, frequency division multiplexing (FDM) and / or time division multiplexing (TDM) techniques.

[0013]

[0020] Techniques for FDM or TDM may involve separating the EM spectrum into different frequency bands and constraining communications to occur within the assigned frequency bands. EM signals in different frequency bands may be communicated simultaneously within the same area without significantly interfering with each other. To transmit a signal within a target frequency band, a transceiver may apply a mixer to the signal to upconvert a relatively low frequency to reach the target frequency band. To recover information carried by a signal received in the target frequency band, the transceiver may apply a mixer to the received signal to downconvert it from the target frequency band to a lower frequency.

[0014]

[0021] To perform the frequency conversion, the mixer circuit operates in conjunction with a local oscillator to generate a local oscillator signal. The mixer circuit "combines" (e.g., multiplies) an input signal with the local oscillator signal to generate an output signal. The mixer circuit may be configured to have a higher frequency than the input signal for frequency upconversion as part of processing a signal to be transmitted in a transmit chain. Alternatively, the mixer circuit may be configured to have a lower frequency than the input signal for frequency downconversion as part of processing a received signal in a receive chain. The frequency of the output signal depends, at least in part, on the frequency of the local oscillator signal provided by the local oscillator.

[0015]

[0022] Although local oscillators contribute to the frequency conversion process, they can introduce noise into this process via the local oscillator signal. Local oscillators can be coupled to different types of mixers, such as double balanced mixers or single balanced mixers. Double balanced mixers use balanced signals (e.g., differential signaling) for both the input and output signals. In contrast, single balanced mixers use at least one unbalanced signal (e.g., single-ended signaling) for either the input or output signal.

[0016]

[0023] In some frequency conversion situations, a double balanced mixer can perform better than a single balanced mixer, for example, in terms of handling noise injected by a local oscillator signal. Balanced signals at the input and output of the mixer can cancel the injected noise to at least some extent. However, a double balanced mixer may occupy a significantly larger area for frequency conversion than a single balanced mixer. In other words, a single balanced mixer may occupy a relatively smaller area than a double balanced mixer. The smaller area is partly due to the omission of a transformer, which typically occupies a relatively large space, from the unbalanced side of a single balanced mixer.

[0017]

[0024] Unfortunately, the unbalanced signal of a single balanced mixer may handle injected noise less well than the two balanced signals of a double balanced mixer. Therefore, the poor noise handling of a single balanced mixer competes with the smaller area occupied by a single balanced mixer, which can be a significant advantage in certain implementations. Furthermore, unbalanced signaling can significantly simplify layout and routing. Consuming less area and allowing simplified signal routing on a board can mean a smaller or lower-cost device, including smaller and cheaper.

[0018]

[0025] Furthermore, as the amount of frequency bands in which wireless interface devices are expected to operate increases, smaller area and simplified routing layouts may become increasingly important. As noted above, the range of frequencies in which devices are expected to communicate is increasing to enable faster communications with higher bandwidths and allow more devices to simultaneously share the finite EM spectrum. In addition to different frequency bands, electronic devices may be expected to handle different access protocols, including those associated with various wireless standards such as license-assisted access (LAA). These different frequency bands and access protocols increase the number of transmit and / or receive paths in electronic devices, such as increasing the amount of transmit and / or receive chains. When each such path potentially includes at least one mixer circuit, the difference in area and layout between a double balanced mixer and a single balanced mixer may have an even greater impact.

[0019]

[0026] Therefore, the use of a single balanced mixer can significantly reduce the size and / or cost of wireless interface devices, and therefore the size and / or cost of their corresponding electronic devices. This specification describes exemplary approaches using a single balanced mixer to at least partially compensate for noise injected by a local oscillator signal provided by a local oscillator of a frequency converter. For example, component symmetry can be increased to reduce the noise figure. Additionally or alternatively, components can be shared to further simplify layout and signal routing. Implementing one or more of these techniques can enable a single balanced mixer, with its size and cost advantages, to be used instead of a double balanced mixer.

[0020]

[0027] Generally, a mixer circuit uses a plurality of switches to combine a first signal at a first frequency with a local oscillator signal at a local oscillator frequency to generate a second signal at a second frequency. The second frequency is different from the first frequency. The plurality of switches may include three or more switches, such as four switches. In some implementations, to address noise from the local oscillator signal, at least a portion of the plurality of switches may be arranged symmetrically with respect to one another on the substrate. For example, a first and second switch of the plurality of switches may be arranged on opposite sides of a line of symmetry. Additionally or alternatively, a third and fourth switch of the plurality of switches may be arranged on either side of the first and second switches such that the first and second switches are “sandwiched” between the third and fourth switches along an axis that is in the plane of the substrate. The axis may be at least substantially perpendicular to the line of symmetry. Furthermore, the first and second switches “sandwiched” by the third and fourth switches may be coupled to the same node. This same node may correspond to the input or output of a mixer circuit and may be configured to carry a single-ended, unbalanced signal.

[0021]

[0028] In another implementation, area reduction and layout simplification can be facilitated by employing coupling capacitors and / or bias resistors each shared between at least two switches of the plurality of switches. With respect to the local oscillator, the local oscillator signal can propagate through a given capacitor to reach at least two switches of the plurality of switches. With respect to the power distribution network, the bias signal (e.g., a direct-current (DC) voltage) can propagate through a given resistor to reach at least two switches. In certain cases, the at least two switches are not adjacent to each other, such as the first switch and the third switch in some depicted examples. When the plurality of switches are implemented with field-effect transistors (FETs), the local oscillator signal and the bias signal can be coupled to gate terminals of the FETs. These and other implementations are described herein.

[0022] Illustrative examples

[0029] FIG. 1 illustrates an exemplary environment 100 having an electronic device 102 with a wireless interface device 120 including at least one exemplary mixer circuit 130. This specification describes exemplary implementations of the mixer circuit 130, which may be part of the device's transceiver, radio-frequency front-end (RFFE), or the like. In the environment 100, the exemplary electronic device 102 communicates with a base station 104 over a wireless link 106. In FIG. 1, the electronic device 102 is shown as a smartphone. However, the electronic device 102 may be implemented as any suitable computing device or other electronic device. Examples of devices that may be implemented as the electronic device 102 include a cellular base station, a broadband router, an access point, a cellular or mobile phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, and a server computer. Other examples of devices that may be implemented as electronic device 102 include network-attached storage (NAS) devices, smart appliances, vehicle-based communication systems, Internet of Things (IoT) devices, sensors or security devices, asset trackers, fitness management devices, wearable devices such as intelligent glasses or smart watches, wireless power devices (transmitters or receivers), medical devices, etc.

[0023]

[0030] The base station 104 communicates with the electronic device 102 via a wireless link 106, which may be implemented as any suitable type of wireless link that carries communication signals. While the base station 104 is shown as a base station tower of a cellular wireless network, it may represent or be implemented as another device, such as a satellite, a terrestrial broadcast tower, an access point, a peer-to-peer device, a mesh network node, a fiber optic line interface, or another electronic device as generally described above. Thus, the wireless link 106 may extend between the electronic device 102 and the base station 104 in any of a variety of manners.

[0024]

[0031] The wireless link 106 may include a downlink of data or control information communicated from the base station 104 to the electronic device 102. The wireless link 106 may also include an uplink of other data or control information communicated from the electronic device 102 to the base station 104. The wireless link 106 may be implemented using any suitable communication protocol or standard. Examples of such protocols and standards include fourth generation (4G) and 5G. th Generation, 4G), 5th generation (5 th Generation, 5G), 6th generation (6 th Third Generation Partnership Projects (3G) and other cellular standards rd Examples of standards that may be used include the Long-Term Evolution (LTE) standard of the Third Generation Partnership Project (3GPP), an IEEE 802.11 standard such as an 802.11g, ac, ax, ad, aj, or ay standard (e.g., Wi-Fi 6 or WiGig), an IEEE 802.16 standard (e.g., WiMAX), a Bluetooth standard, an ultra-wideband (UWB) standard (e.g., IEEE 802.15.4), etc. In some implementations, the wireless link 106 may provide power wirelessly, and the electronic device 102 or the base station 104 may include a power source.

[0025]

[0032] As shown for some implementations, the electronic device 102 may include at least one application processor 108 and at least one computer-readable storage medium 110 (CRM 110). The application processor 108 may include any type of processor, such as a central processing unit (CPU) or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored by the CRM 110. The CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media (e.g., disks), magnetic media (e.g., disks or tapes), etc. In the context of the present disclosure, the CRM 110 is implemented to store instructions 112, data 114, and other information for the electronic device 102, and therefore, the CRM 110 does not include a transitory propagated signal or carrier wave.

[0026]

[0033] The electronic device 102 may also include one or more input / output (I / O) ports 116 and at least one display 118. The I / O ports 116 enable data exchange or interaction with other devices, networks, or users. The I / O ports 116 may include serial ports (e.g., Universal Serial Bus (USB) ports), parallel ports, audio ports, infrared (IR) ports, camera or other sensor ports, etc. The display 118 may be embodied as a display screen or projection that presents graphical images provided by other components of the electronic device 102, such as a user interface (UI) associated with an operating system, program, or application. Alternatively or additionally, the display 118 may be implemented as a display port or virtual interface through which graphical content of the electronic device 102 is communicated or presented.

[0027]

[0034] Electronic device 102 further includes at least one wireless interface device 120 and at least one antenna 122. The exemplary wireless interface device 120 provides connectivity to respective networks and peer devices via a wireless link, which may be configured similarly or differently from wireless link 106. Wireless interface device 120 may facilitate communication over any suitable type of wireless network, such as a wireless local area network (LAN) (wireless LAN, WLAN), a wireless personal-area-network (PAN) (wireless PAN, WPAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide-area-network (WAN) (wireless WAN, WWAN), and / or a navigation network (e.g., the North American Global Positioning System (GPS), another Satellite Positioning System (SPS), or a Global Navigation Satellite System (GNSS)). In the context of the exemplary environment 100, the electronic device 102 may communicate various data and control information bidirectionally with the base station 104 via the wireless interface device 120. However, the electronic device 102 may also communicate directly with other peer devices, alternative wireless networks, etc. Also, as noted above, the electronic device 102 may alternatively be implemented as the base station 104 or another device described herein.

[0028]

[0035] As shown in FIG. 1 , the wireless interface device 120 may include at least one communications processor 124, at least one transceiver 126, and at least one radio frequency front-end (RFFE) 128. These components process data information, control information, and signals associated with communicating information for the electronic device 102 via the antenna 122. The communications processor 124 may be implemented as at least part of a system-on-chip (SoC), as a modem processor, or as a baseband radio processor (BBP) that enables a digital communications interface for data, voice, messaging, or other uses of the electronic device 102. The communications processor 124 may include a digital signal processor (DSP) or one or more signal processing blocks (not shown) for encoding and modulating data for transmission and for demodulating and decoding received data. In addition, the communications processor 124 may also manage (e.g., control or configure) aspects or operations of the transceiver 126, the RF front end 128, and other components of the wireless interface device 120 to implement various communications protocols or techniques.

[0029]

[0036] In some cases, the application processor 108 and the communication processor 124 may be integrated into a single module or integrated circuit (IC), such as an SoC. However, the application processor 108, the communication processor 124, or the processor generally may be operably coupled to one or more other components, such as the CRM 110 or the display 118, to enable control of or other interaction with various components of the electronic device 102. For example, at least one processor 108 or 124 may use components of the wireless interface device 120 to display one or more graphical images on a display screen implementation of the display 118 based on one or more wireless signals communicated (e.g., transmitted or received) via at least one antenna 122. Furthermore, the application processor 108 or the communication processor 124, including combinations thereof, may be implemented using digital circuitry that implements the logic or functionality described herein. Additionally, the communications processor 124 may also include or be associated with memory (not separately shown), such as the same CRM 110 or another CRM, for storing data and processor-executable instructions (e.g., code).

[0030]

[0037] As shown, the wireless interface device 120 may include at least one mixer circuit 130, described below. More specifically, the transceiver 126 may include at least one mixer circuit 130-1, or the RF front-end 128 may include at least one mixer circuit 130-2 (optionally, in accordance with the "inclusive and disjunctive" interpretation of the word "or" permitted herein, including that both components may have at least one mixer circuit 130). The transceiver 126 may also include circuitry and logic for filtering, switching, amplification, channelization, frequency conversion, etc.

[0031]

[0038] The frequency conversion function may include frequency upconversion or downconversion, performed through a single conversion operation (e.g., using a direct conversion architecture) or through multiple conversion operations (e.g., using a superheterodyne architecture). The transceiver 126 may perform such frequency conversion (e.g., frequency translation) by using mixer circuitry 130-1 and an associated local oscillator (not shown in FIG. 1). Generally, the transceiver 126 may include filters, switches, amplifiers, mixers, etc. for routing and conditioning signals to be transmitted or received via the antenna 122.

[0032]

[0039] In addition to the mixer circuit 130-1, the transceiver 126 may include an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC) (not shown in FIG. 1). In operation, the ADC can convert an analog signal to a digital signal, and the DAC can convert a digital signal to an analog signal. In general, the ADC or DAC can be implemented as part of the communications processor 124, as part of the transceiver 126, or separately from both (e.g., as another part of the SoC or as part of the application processor 108).

[0033]

[0040] The components or circuitry of the transceiver 126 may be implemented in any suitable manner, such as with combined transceiver logic or separately as respective transmitter and receiver entities. In some cases, the transceiver 126 may be implemented using multiple or different sections to implement transmit and receive operations, respectively (e.g., using separate transmit and receive chains, as shown in FIG. 2). Although not shown in FIG. 1, the transceiver 126 may also include logic for performing in-phase / quadrature (I / Q) operations, such as combining, phase correction, modulation, and demodulation.

[0034]

[0041] The RF front end 128 may also include one or more mixers, such as mixer circuit 130-2, one or more filters, one or more switches, or one or more amplifiers to condition signals received via the antenna 122 or to condition signals to be transmitted via the antenna 122. The RF front end 128 may also include a local oscillator, a phase shifter (PS), a peak detector, a power meter, a gain control block, an antenna tuning circuit, an N-plexer, a balun, etc. Configurable components of the RF front end 128, such as some phase shifters, automatic gain controllers (AGCs), or reconfigurable versions of the mixer circuit 130, may be controlled by the communications processor 124 to implement communications in various modes, using different frequency bands, or using beamforming. In some implementations, the antenna 122 is implemented as at least one antenna array including multiple antenna elements. Thus, as used herein, "antenna" may refer to at least one separate or independent antenna, at least one antenna array including multiple antenna elements, or a portion of an antenna array (e.g., an antenna element), depending on the context or implementation.

[0035]

[0042] 1 , an exemplary mixer circuit 130 is shown as mixer circuit 130-1 as part of the transceiver 126, as mixer circuit 130-2 as part of the RF front end 128, etc. However, the described implementations of the mixer circuit 130 generally may additionally or alternatively be employed in other portions of the wireless interface device 120 or in other portions of the electronic device 102. As mentioned above, the mixer circuit 130 may be included in electronic devices other than a mobile phone, such as a base station 104. Also, in a base station (or a mobile phone using a superheterodyne architecture), for example, a mixer for an intermediate frequency (IF) section of the wireless interface device 120 may be implemented using the mixer circuit 130 described herein. Other electronic device devices in which the mixer circuit 130 may be used include laptops, vehicle communication hardware, wireless access points, wearable devices, etc., as described herein.

[0036]

[0043] In an exemplary implementation, mixer circuit 130 may include one or more switches 132-1, ..., 132-S, one or more capacitors 134-1, ..., 134-C, and one or more nodes 136-1, ..., 136-N. The variables "S," "C," and "N" are positive integers that may be the same or different from one another. Although certain components are shown as part of the exemplary mixer circuit 130 in FIG. 1, a given mixer circuit may have more, fewer, or different components. Exemplary frequency mixers and their operation are described below with reference to FIGS. 4-8.

[0037]

[0044] By employing one or more aspects of the architectures and techniques described herein, the mixer circuit 130 can use symmetrical component placement to enhance linearity. For example, a linearity measurement that relies on symmetry, called the second-order intercept point (IP2 or IIP2), can improve by approximately 5 to 10 decibels (dB) in some implementations. This improvement can counter at least some of the noise introduced by the associated local oscillator. The noise handling allows the use of a single balanced mixer in certain situations, thereby eliminating the need for a transformer and therefore reducing the area consumed by a frequency converter that includes the mixer. In example implementations, sharing capacitors or resistors can also reduce wire count or simplify signal routing (including both wire count reduction and simplified signal routing).

[0038]

[0045] These advantages are multiplied by the number of transmit or receive chains that use the single balanced mixer described herein instead of a double balanced mixer. Exemplary schematics and circuit implementations of mixer circuits that may be realized in accordance with the described implementations are shown in Figures 5-7. However, this specification will now describe an exemplary implementation of a transceiver and RF front end with reference to Figure 2, and then will describe an exemplary signal path and frequency converter with reference to Figures 3 and 4.

[0039]

[0046] FIG. 2 is a schematic diagram 200 illustrating an example RF front end 128 and an example transceiver 126, each of which may include at least one mixer circuit 130. FIG. 2 also illustrates an antenna 122 and a communications processor 124. The communications processor 124 communicates one or more data signals to other components, such as the application processor 108 of FIG. 1, for further processing at 224 (e.g., for processing at the application level). As shown, the circuit 200 may include a mixer circuit 130-1, a mixer circuit 130-2, a mixer circuit 130-3, or a mixer circuit 130-4, and may include one to four such mixer circuits. However, the circuit 200 may include a different number of frequency mixers (e.g., more or fewer), may include mixers that are differently coupled to each other, may include mixers in different locations, may include mixers implemented as part of a frequency converter, etc.

[0040]

[0047] As shown from left to right, in an exemplary implementation, the antenna 122 is coupled to an RF front end 128, which is coupled to a transceiver 126. The transceiver 126 is coupled to a communications processor 124. The exemplary RF front end 128 includes at least one signal propagation path 222. The at least one signal propagation path 222 may include at least one mixer circuit 130, such as mixer circuit 130-2 and mixer circuit 130-3. The exemplary transceiver 126 includes at least one receive chain 202 (or receive path 202) and at least one transmit chain 252 (or transmit path 252). Although only one RF front end 128, one transceiver 126, and one communications processor 124 are shown in the circuit 200, the electronic device 102, or the wireless interface device 120 of the electronic device 102, may include multiple instances of any or all of such components. Also, although only certain components are explicitly shown in FIG. 2 and are shown coupled together in a particular manner, the transceiver 126 or RF front end 128 may include other unillustrated components (e.g., switches or diplexers), more or fewer components, differently coupled component arrangements, etc.

[0041]

[0048] In some implementations, the RF front end 128 couples the antenna 122 to the transceiver 126 via a signal propagation path 222. In operation, the signal propagation path 222 carries signals between the antenna 122 and the transceiver 126. During or as part of the signal propagation, the signal propagation path 222 conditions the propagating signal, such as with mixer circuit 130-2 or mixer circuit 130-3. This enables the RF front end 128 to couple a wireless signal 220 from the antenna 122 to the transceiver 126 as part of a receive operation. The RF front end 128 also enables a transmit signal to be coupled from the transceiver 126 to the antenna 122 as part of a transmit operation to emit the wireless signal 220. Although not explicitly shown in FIG. 2 , the RF front end 128 or the signal propagation path 222 of the RF front end 128 may include one or more other components, such as another mixer, a filter, an amplifier (e.g., a power amplifier (PA) or a low-noise amplifier (LNA)), an N-plexer, a phase shifter, a diplexer, one or more switches, etc.

[0042]

[0049] In some implementations, the transceiver 126 may include at least one receive chain 202, at least one transmit chain 252, or at least one receive chain 202 and at least one transmit chain 252. The receive chain 202 may include, from left to right, a low-noise amplifier 204 (LNA 204), a filter circuit 206, a mixer circuit 130-1 for frequency downconversion, and an ADC 210. The transmit chain 252 may include a power amplifier 254 (PA 254), a filter circuit 256, a mixer circuit 130-4 for frequency upconversion, and a DAC 260. However, the receive chain 202 or the transmit chain 252 may include other components electrically or electromagnetically coupled anywhere along the depicted receive and transmit chains, such as additional amplifiers or mixers, multiple filters, one or more buffers, or at least one local oscillator.

[0043]

[0050] The receive chain 202 is coupled between a signal propagation path 222 of the RF front end 128 and the communications processor 124, e.g., via a low-noise amplifier 204 and an ADC 210, respectively. The transmit chain 252 is coupled between the signal propagation path 222 and the communications processor 124, e.g., via a power amplifier 254 and a DAC 260, respectively. The transceiver 126 may also include at least one phase-locked loop (PLL) 232 (PLL 232) coupled to the mixer circuit 130-1 or the mixer circuit 130-4. For example, the transceiver 126 may include one PLL 232 per transmit / receive chain pair, one PLL 232 per transmit chain and one PLL 232 per receive chain, multiple PLLs 232 per chain, etc.

[0044]

[0051] As shown along the signal propagation direction of a particular exemplary implementation of the receive chain 202, the antenna 122 is coupled to the low-noise amplifier 204 via signal propagation path 222 and its mixer circuit 130-3, which is coupled to the filter circuit 206. The filter circuit 206 is coupled to the mixer circuit 130-1, which is coupled to the ADC 210. The ADC 210 is then coupled to the communications processor 124. As shown along the signal propagation direction of a particular exemplary implementation of the transmit chain 252, the communications processor 124 is coupled to the DAC 260, which is coupled to the mixer circuit 130-4. The mixer circuit 130-4 is coupled to the filter circuit 256, which is coupled to the power amplifier 254. The power amplifier 254 is coupled to the antenna 122 via the signal propagation path 222 using the mixer circuit 130-2 of the signal propagation path 222. Although only one receive chain 202 and one transmit chain 252 are explicitly shown, the electronic device 102 or the transceiver 126 of the electronic device 102 may include multiple instances of either or both components. Although the ADC 210 and the DAC 260 are illustrated as being separately coupled to the communications processor 124, the ADC 210 and the DAC 260 may share a bus or other means for communicating with the processor 124.

[0045]

[0052] As part of an exemplary signal reception operation, mixer circuit 130-3 (if present) in signal propagation path 222 downconverts the received signal (e.g., to an intermediate frequency (IF)) and forwards the downconverted signal to low-noise amplifier 204. Low-noise amplifier 204 accepts the downconverted signal from RF front-end 128 and provides an amplified signal to filter circuit 206 based on the accepted signal. Filter circuit 206 filters the amplified signal and provides the filtered signal to mixer circuit 130-1. Mixer circuit 130-1 performs a frequency downconversion operation on the filtered signal to downconvert from one frequency to a lower frequency (e.g., from IF to baseband frequency (BBF) if mixer circuit 130-3 is present, or from radio frequency (RF) to IF or BBF if mixer circuit 130-3 is not present). The mixer circuit 130-1 can perform frequency downconversion in a single conversion step or through multiple conversion steps using at least one PLL 232. The mixer circuit 130-1 can provide the downconverted analog signal to the ADC 210 for ADC conversion, and then forward it to the communications processor 124 as a digital signal.

[0046]

[0053] As part of an exemplary signal transmission operation, the DAC 260 converts a digital signal received from the communications processor 124 to an analog signal. The mixer circuit 130-4 accepts a BBF or IF analog signal from the DAC 260. The mixer circuit 130-4 upconverts the analog signal to a higher frequency, such as an IF or RF, to generate a higher-frequency signal using the signal generated by the PLL 232 to have a target synthesis frequency. The mixer circuit 130-4 provides the RF or other upconverted signal to the filter circuit 256. The filter circuit 256 filters the upconverted IF or RF signal and provides the filtered signal to the power amplifier 254. Thus, after filtering by the filter circuit 256, the power amplifier 254 amplifies the filtered signal and provides the amplified signal to the signal propagation path 222 for signal conditioning. The RF front end 128 may, for example, use mixer circuit 130-2 in signal propagation path 222 to provide the RF signal to antenna 122 for emission as wireless signal 220 if the amplified signal is at IF.

[0047]

[0054] The exemplary implementations of the mixer circuit 130 described herein may be employed in any one or more of the exemplary mixer circuits 130-1, 130-2, 130-3, or 130-4 in the transceiver 126 or RF front-end 128, or in other mixers (not shown in FIG. 2 ) of the electronic device 102. However, the circuit 200 illustrates only some examples for the transceiver 126 and RF front-end 128. In some cases, various components illustrated in the figures using separate schematic blocks or circuit elements may be manufactured or packaged in different and separate manners. For example, one physical module may include components of the RF front-end 128 and some components of the transceiver 126, while another physical module may combine the communications processor 124 with the remaining components of the transceiver 126. Furthermore, in some cases, the antenna 122 may be packaged with at least some components of the RF front-end 128 or the transceiver 126.

[0048]

[0055] In alternative implementations, one or more components may be physically or logically "shifted" to a different portion of the wireless interface device 120 and / or incorporated into a different module compared to the illustrated circuit 200. For example, the low noise amplifier 204 or the power amplifier 254 may alternatively or additionally be located within the RF front end 128. Similarly, the ADC 210 or the DAC 260 may alternatively be located within the communications processor 124.

[0049]

[0056] FIG. 3 is a schematic diagram 300 illustrating an example of multiple receive chains that may each include at least one frequency converter as part of a wireless interface device. As shown, the wireless interface device 120 (e.g., of FIGS. 1 and 2) may include multiple receive chains 202-1, 202-2, ..., 202-R, where "R" represents a positive integer. Each receive chain 202 includes at least one frequency converter 302. In FIG. 3, "F" frequency converters 302-1, 302-2, ..., 302-F are shown, where "F" represents a positive integer. For example, the first receive chain 202-1 includes the first frequency converter 302-1, the second receive chain 202-2 includes the second frequency converter 302-2, and the "Rth" receive chain 202-R includes the "Fth" frequency converter 302-F.

[0050]

[0057] In some implementations, each respective receive chain 202 corresponds to a respective frequency range 304, such as a first frequency range 304-1, a second frequency range 304-2, and an “Mth” frequency range 304-M. Additionally or alternatively, each respective receive chain 202 may correspond to a respective wireless standard or communication protocol. Examples include a receive chain 202 for a mid-to-high band (MHB) frequency range 304, a receive chain 202 for a millimeter wave (mmW) frequency band 304, a receive chain 202 for a combined LAA and New Radio-Unlicensed (NR-U) access scheme, etc. The values ​​of the variables “R,” “F,” and “M” may be the same or different from one another.

[0051]

[0058] While only a receive chain is shown in FIG. 3 , the wireless interface device 120 may additionally or alternatively include multiple transmit chains, such as multiple instances of the transmit chain 252 (of FIG. 2 ). Each receive chain 202 or transmit chain 252 may include a respective frequency converter or multiple frequency converters, or may share the frequency converter 202 with one or more other chains. Furthermore, although the frequency converter 302 is shown in FIG. 3 as part of the receive chain and described above as part of the receive chain or the transmit chain (or part of both), the frequency converter 302 may be implemented separately from either chain. Additionally, or alternatively, the frequency converter 302 may be implemented as part of the RF front end 128. The RF front end 128 may also include at least a portion of the receive chain 202 or the transmit chain 252.

[0052]

[0059] FIG. 4 is a schematic diagram 400 illustrating an exemplary frequency converter 302 including a mixer circuit 130 and a local oscillator 402. As shown, the mixer circuit 130 is coupled to the local oscillator 402 (LO 402). In an exemplary implementation, the mixer circuit 130 includes an input interface 412, an output interface 414, and a control interface 416 (or LO interface 416). The local oscillator 402 generates a local oscillator signal 404 (LO signal 404). The local oscillator signal 404 may be implemented as a balanced signal or a differential signal, as shown in FIGS. 5 and 6. The local oscillator 402 transmits or provides the local oscillator signal 404 to the mixer circuit 130 via at least one local oscillator node 410 (LO node 410). The mixer circuit 130 receives or accepts the local oscillator signal 404 via a control interface 416.

[0053]

[0060] The mixer circuit 130 receives or accepts a first signal 406 via an input interface 412. The mixer circuit 130 can generate a second signal 408 based on the local oscillator signal 404 and the first signal 406 by performing a mixing operation (e.g., a multiplication operation). The mixer circuit 130 transmits or provides the second signal 408 via an output interface 414. The first signal 406 corresponds to a first frequency 418-1, and the second signal 408 corresponds to a second frequency 418-2 that is different from the first frequency 418-1. Thus, the frequency converter 302 (e.g., the mixer circuit 130 together with the local oscillator 402 or at least the local oscillator signal 404 from the local oscillator 402) converts a signal having the first frequency 418-1 into another signal having the second frequency 418-2.

[0054]

[0061] The frequency converter 302 can perform frequency up-conversion or frequency down-conversion. In some cases, the first signal 406 corresponds to an input signal of the frequency converter 302 or its mixer circuit 130, and the second signal 408 corresponds to an output signal of the frequency converter 302 or its mixer circuit 130. In the case of frequency up-conversion, the second frequency 418-2 of the second signal 408 is greater (e.g., higher) than the first frequency 418-1 of the first signal 406. In the case of frequency down-conversion, the second frequency 418-2 of the second signal 408 is less (e.g., lower) than the first frequency 418-1 of the first signal 406. However, in other implementations, the second signal may correspond to the input signal and the first signal may correspond to the output signal, depending on the configuration of the unidirectional mixer circuit or the mode of the bidirectional mixer circuit.

[0055]

[0062] FIG. 5 is a schematic diagram illustrating an example mixer circuit 130 including multiple nodes, multiple switches, and multiple capacitors. Referring also to FIG. 1, the mixer circuit 130 may include multiple switches 132-1, ..., 132-S, multiple capacitors 134-1, ..., 134-C, and multiple nodes 136-1, ..., 136-N. As shown for the example mixer circuit 130 of FIG. 5, there are four switches, so "S" may equal 4. There are two capacitors, so "C" may equal 2. There are seven identified nodes, so "N" may equal 7. However, each of these components may have more or fewer instances than shown in FIG. 5 or described herein.

[0056]

[0063] In an exemplary implementation, the plurality of switches 132-1, ..., 132-S may include at least a first switch 132-1, a second switch 132-2, a third switch 132-3, and a fourth switch 132-4. The plurality of capacitors 134-1, ..., 134-C may include a first capacitor 134-1 and a second capacitor 134-2. Referring also to FIG. 4 , the at least one local oscillator node 410 may be implemented using multiple local oscillator nodes, such as a first local oscillator node 410-1 and a second local oscillator node 410-2. The multiple local oscillator nodes may support a differential signaling implementation of the local oscillator signal 404. Thus, the first local oscillator node 410-1 and the second local oscillator node 410-2 may comprise a positive local oscillator node and a negative local oscillator node. Additionally, the local oscillator signal 404 may include a plus LO signal 404+ and a minus LO signal 404-, which may also be referred to as a first local oscillator signal and a second local oscillator signal.

[0057]

[0064] The mixer circuit 130 may also include a first node 506 and a plurality of second nodes 508-1 and 508-2. The first node 506 may correspond to a first frequency 418-1, for example, based on the frequency of a signal across the first node 506. The plurality of second nodes 508-1 and 508-2 may correspond to a second frequency 418-2. The plurality of second nodes 508-1 and 508-2 may collectively carry a differential signal. Thus, the plurality of second nodes 508-1 and 508-2 may also be referred to as a positive second node 508-1 and a negative second node 508-2. The mixer circuit 130 may further include at least one bias node 510 and at least one floating node 512. The bias node 510 may provide at least one bias signal, such as a gate bias voltage, to the plurality of switches 132-1 through 132-4. The floating nodes 512 enable the mixer circuit 130 to implement a single balanced mixer architecture. Although each of the particular nodes is shown and described with a particular quantity, each node may have more or fewer instances.

[0058]

[0065] As shown, the plurality of capacitors 134-1 and 134-2 are coupled between the plurality of local oscillator nodes 410-1 and 410-2 and the plurality of second nodes 508-1 and 508-2. The plurality of switches 132-1 through 132-4 are coupled between the plurality of capacitors 134-1 and 134-2 and the plurality of second nodes 508-1 and 508-2. The first switch 132-1 and the second switch 132-2 are coupled between the plurality of capacitors 134-1 and 134-2 and the first node 506. Furthermore, the third switch 132-3 and the fourth switch 132-4 are coupled to each other via a floating node 512.

[0059]

[0066] The first capacitor 134-1 may be coupled between the first local oscillator node 410-1 and the first and third switches 132-1 and 132-3. The second capacitor 134-2 may be coupled between the second local oscillator node 410-2 and the second and fourth switches 132-2 and 132-4. At least one bias node 510 may be coupled to the first and third switches 132-1 and 132-3 and the second and fourth switches 132-2 and 132-4. Examples of bias nodes are further described below with reference to FIG. 7.

[0060]

[0067] In exemplary operation, the first node 506 may provide a first signal, such as the first signal 406 (also of FIG. 4 ) corresponding to a first frequency 418-1, to the mixer circuit 130. The plurality of second nodes 508-1 and 508-2 may accept a second signal, such as the second signal 408 (also of FIG. 4 ) corresponding to a second frequency 418-2, from the mixer circuit 130. Alternatively, the plurality of second nodes 508-1 and 508-2 may provide the second signal 408 to the mixer circuit 130, and the first node 506 may accept the first signal 406 from the mixer circuit 130. In some cases, the first signal 406 may be implemented as an unbalanced signal, and the second signal 408 may be implemented as a balanced signal.

[0061]

[0068] In some implementations, one or more of the components shown in FIG. 5 are disposed on a substrate 514, such as a semiconductor material like silicon. The substrate 514 defines a plane in which multiple axes may exist. As shown, a first axis 504-1 and a second axis 504-2 lie within the plane defined by the substrate 514. The first axis 504-1 and the second axis 504-2 are at least substantially perpendicular to one another. A line of symmetry 502 (LOS 502) may also lie within the plane 514. At least some of the illustrated components may be disposed substantially symmetrically about the line of symmetry 502 or with respect to the line of symmetry 210. In some cases, the line of symmetry 502 may be at least substantially parallel to an axis 504, such as the second axis 504-2. This may include the line of symmetry 502 being collinear with the second axis 504-2 or being parallel to it to the extent permitted by the given process technology (e.g., within 10 degrees, within 5 degrees, or within 1 degree).

[0062]

[0069] In the exemplary aspect, the first switch 132-1 and the second switch 132-2 are disposed between the fourth switch 132-4 and the third switch 132-3. The first switch 132-1 and the second switch 132-2 are coupled to the first node 506 for communicating information-related signaling, such as the first signal 406. In contrast, the fourth switch 132-4 and the third switch 132-3 are coupled to the floating node 512. In this regard, the fourth switch 132-4 and the third switch 132-3 can operate as “dummy switches” with respect to the first node 506 or the first signal 406.

[0063]

[0070] In another aspect, the first switch 132-1 can be disposed on the substrate 514 between the fourth switch 132-4 and the second switch 132-2. Furthermore, the second switch 132-2 can be disposed on the substrate 514 between the first switch 132-1 and the third switch 132-3. In a particular aspect related to symmetry, the first switch 132-1 and the fourth switch 132-4 are symmetrically disposed on a first side of the line of symmetry 502 (e.g., the upper side as shown in FIG. 5 ), and the second switch 132-2 and the third switch 132-3 are symmetrically disposed on a second side of the line of symmetry 502 (e.g., the lower side as shown in FIG. 5 ). Similarly, the second capacitor 134-2 can be disposed on the first side of the line of symmetry 502, and the first capacitor 134-1 can be disposed on the second side of the line of symmetry 502.

[0064]

[0071] Additionally or alternatively, the first switch 132-1, the second switch 132-2, the third switch 132-3, and the fourth switch 132-4 may be arranged on the substrate in the plane 514 along a line (not shown in FIG. 5, but see FIG. 7) that is at least substantially parallel to the first axis 504-1. This may include the line being collinear with the first axis 504-1 or parallel to the extent permitted by a given manufacturing technique. An example of this arrangement is described below with reference to FIG. 6.

[0065]

[0072] In an example implementation in which the local oscillator 402 (of FIG. 4) provides a differential local oscillator signal 404, the multiple local oscillator nodes may include a plus local oscillator node 410-1 and a minus local oscillator node 410-2. The first capacitor 134-1 may be coupled between the plus local oscillator node 410-1 and the first switch 132-1, and the first capacitor 134-1 may also be coupled between the plus local oscillator node 410-1 and the third switch 132-3. The second capacitor 134-2 may be coupled between the minus local oscillator node 410-2 and the fourth switch 132-4, and the second capacitor 134-2 may also be coupled between the minus local oscillator node 410-2 and the second switch 132-2.

[0066]

[0073] 6 is a schematic diagram 600 illustrating an exemplary implementation of a plurality of switches 132-1 through 132-4, including two switches symmetrically coupled to a node (e.g., first node 506). FIG. 6 also illustrates a substrate 514 and two axes that lie in a plane defined by the substrate 514. The two axes are a first axis 504-1 and a second axis 504-2. A line of symmetry 502 extends at least substantially parallel to the second axis 504-2 in the plane of the substrate 514.

[0067]

[0074] In an exemplary implementation, the plurality of switches 132-1 through 132-4 are arranged in the plane of the substrate 514 along a line 602. The line 602 is at least substantially parallel to the first axis 504-1 and at least substantially perpendicular to the line of symmetry 502. As shown, the first switch 132-1 and the second switch 132-2 are symmetrically coupled to a first node 506 along or across the line of symmetry 502. Each of the first switch 132-1 and the second switch 132-2 may include multiple transistors, represented by the letter "M" in FIGS. 6 and 7. Although eight transistors are shown in each of the first switch 132-1 and the second switch 132-2, each switch 132 may be formed from more or fewer transistors, including one transistor.

[0068]

[0075] For clarity, the plurality of second nodes 508-1 and 508-2 are omitted from Figure 6. Furthermore, each of the third switch 132-3 and the fourth switch 132-4 may also include one or more transistors. Furthermore, although a particular symmetrical arrangement of the first switch 132-1 and the second switch 132-2 with respect to the first node 506 and the line of symmetry 502 is shown in Figure 6, the first switch 132-1 and the second switch 132-2 may be symmetrically arranged on the substrate in different ways.

[0069]

[0076] FIG. 7 is a circuit diagram 700 illustrating an exemplary mixer circuit including multiple nodes, multiple switches, multiple capacitors, and multiple resistors. Circuit diagram 700 provides an exemplary circuit-level implementation of the schematic diagram of FIG. 5. In contrast to FIG. 5, multiple switches 132-1 through 132-4 are each illustrated using at least one transistor M. As shown, first switch 132-1 is implemented using at least one transistor M1, second switch 132-2 is implemented using at least one transistor M2, third switch 132-3 is implemented using at least one transistor M3, and fourth switch 132-4 is implemented using at least one transistor M4.

[0070]

[0077] The second signal 408 is implemented as a differential signal including a first instance of the second signal 408-1 and a second instance of the second signal 408-2. These signals may also be referred to as the positive second signal 408-1 and the negative second signal 408-2. A differential signal may be implemented, for example, as two complementary signals or as two signals with opposite polarity. In an exemplary operation, the second signal 408-1 may propagate through the second node 508-1 (which may be referred to as the positive second node 508-1), and the second signal 408-2 may propagate through the second node 508-2 (which may be referred to as the negative second node 508-2).

[0071]

[0078] In further contrast to FIG. 5, at least one bias node 510 is implemented as a first bias node 510-1 and a second bias node 510-2. A bias signal 704 is provided to each transistor M to bias transistors M1-M4. The bias signal may be, for example, a DC voltage from a power distribution network node. Examples of power distribution network nodes include power supply nodes such as a power rail and ground nodes such as a ground plane. In some cases, the bias signal 704 may be split into a first bias signal 704-1 and a second bias signal 704-2.

[0072]

[0079] Each respective bias signal 704 may be provided to at least one transistor M via at least one resistor 702 (e.g., a bias resistor). In the case of separate bias signals, the at least one resistor 702 may be implemented using separate resistors from a plurality of resistors. For example, the mixer circuit 130 may bias the first transistor M1 and the third transistor M3 with a first bias signal 704-1 via a first resistor 702-1. The mixer circuit 130 may also bias the second transistor M2 and the fourth transistor M4 with a second bias signal 704-2 via a second resistor 702-2.

[0073]

[0080] Generally, each switch 132 can be implemented with at least one transistor. The transistors can be realized using any one or more of several transistor types. Exemplary transistor types include field effect transistors (FETs), junction FETs (JFETs), metal-oxide-semiconductor FETs (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), etc. Manufacturers can manufacture FETs as n-channel or p-channel transistor types, and BJTs as NPN or PNP transistor types.

[0074]

[0081] Each transistor may include at least one control terminal and one or more channel terminals. In a FET transistor, the control terminal may correspond to the gate terminal, and the channel terminal may correspond to the source or drain terminal. In a BJT transistor, the control terminal may correspond to the base terminal, and the channel terminal may correspond to the emitter or collector terminal.

[0075]

[0082] To bias each transistor M, a bias signal 704 is provided to a respective control terminal of each transistor M. In FIG. 7, each transistor M is realized as an n-channel FET having a gate terminal, a drain terminal, and a source terminal. Multiple bias signals 704-1 and 704-2 are coupled to the gate terminals of one or more transistors. For example, a first bias signal 704-1 may be coupled through a first resistor 702-1 to the gate terminals of the first transistor M1 and the third transistor M3. Similarly, a second bias signal 704-2 may be coupled through a second resistor 702-2 to the gate terminals of the second transistor M2 and the fourth transistor M4. Although the transistors are shown as n-channel FETs in FIG. 7, the mixer circuit may be implemented with p-channel FETs, any type of BJT, combinations thereof, etc.

[0076]

[0083] As shown for a particular implementation, the multiple bias nodes can include a first bias node 510-1 and a second bias node 510-2, and the multiple bias resistors can include a first resistor 702-1 and a second resistor 702-2. The first resistor 702-1 can be coupled between the first bias node 510-1 and a first switch 132-1 (e.g., a first transistor M1), and the first resistor 702-1 can also be coupled between the first bias node 510-1 and a third switch 132-3 (e.g., a third transistor M3). The second resistor 702-2 may be coupled between the second bias node 510-2 and the fourth switch 132-4 (e.g., the fourth transistor M4), and the second resistor 702-2 may also be coupled between the second bias node 510-2 and the second switch 132-2 (e.g., the second transistor M2).

[0077]

[0084] In an exemplary implementation, each transistor M is coupled between two nodes via a respective channel terminal. For example, the first transistor M1 may be coupled between the first node 506 and a first instance of the second node 508-1 (e.g., the positive second node 508-1). The second transistor M2 may be coupled between the first node 506 and a second instance of the second node 508-2 (e.g., the negative second node 508-2). The third transistor M3 may be coupled between the floating node 512 and a second instance of the second node 508-2 (e.g., the negative second node 508-2). The fourth transistor M4 may be coupled between the floating node 512 and the first instance of the second node 508-1 (e.g., the positive second node 508-1).

[0078]

[0085] Next, exemplary couplings to different terminals of the transistors forming the plurality of switches 132-1 through 132-4 will be described. In a particular exemplary coupling, the first capacitor 134-1 is coupled between the first local oscillator node 410-1 and the respective control terminals (e.g., gate terminals in the case of a FET implementation) of the first switch 132-1 and the third switch 132-3 (e.g., the first transistor M1 and the third transistor M3). The second capacitor 134-2 is coupled between the second local oscillator node 410-2 and the respective control terminals (e.g., gate terminals in the case of a FET implementation) of the fourth switch 132-4 and the second switch 132-2 (e.g., the transistor M4 and the transistor M2).

[0079]

[0086] In another exemplary coupling, a first resistor 702-1 of the plurality of resistors is coupled between the first bias node 510-1 and a respective control terminal (e.g., a gate terminal in a FET implementation) of the first switch 132-1 and the third switch 132-3. A second resistor 702-2 of the plurality of resistors is coupled between the second bias node 510-2 and a respective control terminal (e.g., a gate terminal in a FET implementation) of the fourth switch 132-4 and the second switch 132-2.

[0080]

[0087] In yet another exemplary coupling, the first switch 132-1 and the second switch 132-2 are coupled to the first node 506 via respective first terminals of a first terminal type of a given transistor type. The third switch 132-3 and the fourth switch 132-4 are coupled to each other (e.g., through the floating node 512) via respective first terminals of the first terminal type. Furthermore, a second node 508-1 of the plurality of second nodes 508-1 and 508-2 is coupled to the fourth switch 132-4 and the first switch 132-1 via respective second terminals of the second terminal type. Another second node 508-2 of the plurality of second nodes 508-1 and 508-2 is coupled to the second switch 132-2 and the third switch 132-3 via respective second terminals of the second terminal type. These terminal types may correspond to channel terminals. As shown for the illustrated FET, the first terminal type may correspond to the drain terminal of transistor M, and the second terminal type may correspond to the source terminal of transistor M.

[0081]

[0088] In a particular implementation, the first switch 132-1 (e.g., including the first transistor M1) and the second switch 132-2 (e.g., including the second transistor M2) are disposed on a substrate between the fourth switch 132-4 (e.g., including the fourth transistor M4) and the third switch 132-3 (e.g., including the third transistor M3). The first switch 132-1 (e.g., including the first transistor M1) and the second switch 132-2 (e.g., including the second transistor M2) are coupled to the same node (e.g., the first node 506) to communicate (e.g., receive / accept or transmit / provide) the same signal (e.g., the first signal 406) carrying user information or application-level information (as opposed to the oscillating signal 404, which does not contain user information or application-level information).

[0082]

[0089] This provides a mechanism for increasing the symmetry-dependent linearity of the mixer circuit 130. The mechanism for increasing the symmetry-dependent linearity can be further enhanced by symmetrically arranging the switches. For example, the first switch 132-1 and the fourth switch 132-4 can be arranged on a first side of the symmetry line 502, and the second switch 132-2 and the third switch 132-3 can be arranged on a second side of the symmetry line 502.

[0083]

[0090] The area consumption of the mixer circuit 130 can be reduced by implementing a mechanism for sharing one or more components. For example, each capacitor 134 of the plurality of capacitors can be shared across two or more switches of the plurality of switches. For example, the first capacitor 134-1 of the plurality of capacitors 134-1 and 134-2 can be shared across the first switch 132-1 and the third switch 132-3 of the plurality of switches 132-1 through 132-4. As another example, each resistor 702 of the plurality of resistors can be shared across two or more switches of the plurality of switches. For example, the second resistor 702-2 of the plurality of resistors 702-1 and 702-2 can be shared across the second switch 132-2 and the fourth switch 132-4 of the plurality of switches 132-1 through 132-4. This sharing can also simplify layout or routing (including both), further reducing area consumption.

[0084]

[0091] 8 is a flow diagram illustrating an example process 800 for mixing signals and / or operating a mixer circuit. Process 800 includes five blocks 802-810 that specify operations that may be performed for the method.

[0085]

[0092] In block 802, a first signal is received at a first switch and a second switch via a first node, where the first signal corresponds to a first frequency. For example, the mixer circuit 130 can receive the first signal 406 at the first switch 132-1 and the second switch 132-2 via a first node 506, where the first signal 406 corresponds to a first frequency 418-1. For example, the first transistor M1 and the second transistor M2 can receive the first signal 406 at their respective first channel terminals as part of the receive chain 202 or the transmit chain 252. Here, the first signal 406 can be a single-ended signal on the unbalanced side of a single-balanced implementation of the mixer circuit 130.

[0086]

[0093] In block 804, a positive local oscillator signal is received at the first switch and the third switch via a first capacitor. For example, the mixer circuit 130 may receive the positive local oscillator signal 404+ at the first switch 132-1 and the third switch 132-3 via the first capacitor 134-1. In some cases, the first transistor M1 and the third transistor M3 may receive the positive local oscillator signal 404+ at their respective gate terminals via the first capacitor 134-1. Thus, the first transistor M1 and the third transistor M3 may "share" the first capacitor 134-1 to reduce the area occupied by the mixer circuit 130, including simplifying layout and routing. The first transistor M1 and the third transistor M3 may share a bias resistor instead of having two separate bias resistors.

[0087]

[0094] In block 806, the negative local oscillator signal is received at the second switch 132-2 and the fourth switch 132-4 via a second capacitor. For example, the mixer circuit 130 may receive the negative local oscillator signal 404- at the second switch 132-2 and the fourth switch 132-4 via the second capacitor 134-2. In some cases, the second transistor M2 and the fourth transistor M4 may receive the negative local oscillator signal 404- at their respective gate terminals via the second capacitor 134-2. Thus, the second transistor M2 and the fourth transistor M4 share the second capacitor 134-2. The second transistor M2 and the fourth transistor M4 may also share a bias resistor. For example, to support linearity-dependent performance parameters, the first transistor M1 and the second transistor M2 may be disposed on the substrate 514 between the third transistor M3 and the fourth transistor M4.

[0088]

[0095] In block 808, the first signal, the plus local oscillator signal, and the minus local oscillator signal are mixed using the first switch, the second switch, the third switch, and the fourth switch to generate a second signal, where the second signal corresponds to a second frequency. For example, the mixer circuit 130 can mix the first signal 406, the plus local oscillator signal 404+, and the minus local oscillator signal 404− using the first switch 132-1, the second switch 132-2, the third switch 132-3, and the fourth switch 132-4 to generate the second signal 408, where the second signal 408 corresponds to a second frequency 418-2. To do this, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be turned on and off by plus or minus the oscillator signal 404+ or 404− and may use a mathematical operation to combine the first signal 406 with the oscillator signal 404 to generate a second signal 408 having a frequency different from the frequency of the first signal 406. With the third switch 132-3 and the fourth switch 132-4 not receiving an input signal (and coupled to each other), the third switch 132-3 and the fourth switch 132-4 may be operated as dummy switches, at least with respect to the first signal 406.

[0089]

[0096] In block 810, the first switch, the second switch, the third switch, and the fourth switch provide a second signal via a plurality of second nodes. For example, the mixer circuit 130 can provide the second signal 408 via a plurality of second nodes 508-1 and 508-2 from the first switch 132-1, the second switch 132-2, the third switch 132-3, and the fourth switch 132-4. Thus, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can output the second signal 408 at each second channel terminal as part of the frequency converter 302. Here, the second signal 408 can include a positive second signal 408-1 and a negative second signal 408-2 to realize a differential signal on the balanced side of a single-balanced implementation of the mixer circuit 130.

[0090]

[0097] FIG. 8 is a flow diagram illustrating an example process or method related to mixing signals and / or operating a mixer circuit. The processes are described in the form of a set of blocks that specify operations that may be performed. However, the operations are not necessarily limited to the order shown in the figures or described herein, as the operations may be performed in alternative orders or in a fully or partially overlapping manner. Also, more, fewer, and / or different operations may be performed to perform each process or alternative processes. The operations represented by the illustrated blocks of each process may be performed by an electronic device, such as the electronic device 102 or its wireless interface device 120 of FIG. 1. More specifically, the operations of each process may be performed by the mixer circuit 130 of the transceiver 126 or the RF front end 128, independently or in conjunction with other components.

[0091] Implementation Examples

[0098] This section describes some aspects of example implementations and / or example configurations related to the devices and / or processes presented above.

[0092]

[0099] Exemplary Embodiment 1: An apparatus comprising: A mixer circuit, a plurality of local oscillator nodes; a first node corresponding to a first frequency; a plurality of second nodes corresponding to a second frequency; a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes; a plurality of switches including a first switch, a second switch, a third switch, and a fourth switch, wherein the plurality of switches are coupled between the plurality of capacitors and a plurality of second nodes, the first switch and the second switch are coupled between the plurality of capacitors and the first node, and the first switch and the second switch are disposed between the fourth switch and the third switch; mixer circuit, An apparatus comprising:

[0093]

[0100] Exemplary Embodiment 2: the third switch and the fourth switch are coupled to each other via a floating node; 10. The apparatus of exemplary embodiment 1.

[0094]

[0101] Exemplary Embodiment 3: a first node configured to provide a first signal corresponding to a first frequency to the mixer circuit; a plurality of second nodes configured to receive a second signal corresponding to a second frequency from the mixer circuit; 2. The apparatus of any one of exemplary embodiments 1 to 2.

[0095]

[0102] Exemplary Embodiment 4: the first signal comprises an unbalanced signal; the second signal comprises a balanced signal; 10. The apparatus of exemplary embodiment 3.

[0096]

[0103] Exemplary Embodiment 5: a first switch disposed on the substrate between the fourth switch and the second switch; a second switch disposed on the substrate between the first switch and the third switch; 5. The apparatus of any one of exemplary embodiments 2 to 4.

[0097]

[0104] Exemplary Embodiment 6: the first switch and the fourth switch are symmetrically arranged on a first side of a line of symmetry, and the second switch and the third switch are symmetrically arranged on a second side of the line of symmetry; 6. The apparatus of any one of exemplary embodiments 2 to 5.

[0098]

[0105] Exemplary Embodiment 7: the substrate defines a plane; the plane includes a first axis and a second axis, the first axis being substantially perpendicular to the second axis, and the second axis being at least substantially parallel to the line of symmetry; the first switch, the second switch, the third switch, and the fourth switch are arranged on the substrate in a plane along a line at least substantially parallel to the first axis; 10. The apparatus of exemplary embodiment 6.

[0099]

[0106] Exemplary Embodiment 8: the plurality of capacitors includes a first capacitor and a second capacitor; a first capacitor disposed on a second side of the line of symmetry; a second capacitor disposed on the first side of the line of symmetry; 8. The apparatus of exemplary embodiment 6 or 7.

[0100]

[0107] Exemplary Embodiment 9: the plurality of local oscillator nodes includes a first local oscillator node and a second local oscillator node; a first capacitor coupled between the first local oscillator node and the first switch and the third switch; a second capacitor coupled between the second local oscillator node and the second switch and the fourth switch; 10. The apparatus of exemplary embodiment 8.

[0101]

[0108] Exemplary Embodiment 10: the plurality of local oscillator nodes includes a positive local oscillator node and a negative local oscillator node; the plurality of capacitors includes a first capacitor and a second capacitor; a first capacitor coupled between the positive local oscillator node and the first switch; a first capacitor coupled between the positive local oscillator node and the third switch; a second capacitor coupled between the negative local oscillator node and the fourth switch; a second capacitor coupled between the negative local oscillator node and the second switch; 10. The apparatus of any one of exemplary embodiments 1 to 9.

[0102]

[0109] Exemplary Embodiment 11: The mixer circuit is a plurality of bias nodes including a first bias node and a second bias node; a plurality of bias resistors including a first resistor and a second resistor; Equipped with a first resistor coupled between the first bias node and the first switch; a first resistor coupled between the first bias node and the third switch; a second resistor coupled between the second bias node and the fourth switch; a second resistor coupled between the second bias node and the second switch; 11. The apparatus of any one of exemplary embodiments 1 to 10.

[0103]

[0110] Exemplary Embodiment 12: a local oscillator coupled to a plurality of local oscillator nodes; Further provided with the mixer circuit is configured to convert the frequency of the signal between the first frequency and the second frequency; 12. The apparatus of any one of exemplary embodiments 1 to 11.

[0104]

[0111] Exemplary Embodiment 13: at least one transmit chain comprising a mixer circuit; the mixer circuit is configured to perform frequency upconversion; 13. The apparatus of any one of exemplary embodiments 1 to 12.

[0105]

[0112] Exemplary Embodiment 14: at least one receive chain including a mixer circuit; the mixer circuit is configured to perform frequency downconversion; 14. The apparatus of any one of exemplary embodiments 1 to 13.

[0106]

[0113] Exemplary Embodiment 15: a wireless interface device comprising at least one receive chain; A display screen; at least one processor operatively coupled to the display screen and to at least a portion of the wireless interface device, the at least one processor configured to present one or more graphical images on the display screen based on one or more wireless signals communicated using a mixer circuit of the wireless interface device; 15. The apparatus of Exemplary Embodiment 14, further comprising:

[0107]

[0114] Exemplary Embodiment 16: An apparatus, comprising: A mixer circuit, a plurality of local oscillator nodes; a first node corresponding to a first frequency; a plurality of second nodes corresponding to a second frequency; a plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes; a plurality of switches including a first switch, a second switch, a third switch, and a fourth switch, the plurality of switches being coupled between a plurality of capacitors and a plurality of second nodes, the first switch and the second switch being coupled between the plurality of capacitors and the first node, and the third switch and the fourth switch being coupled to each other via a floating node; Multiple switches and a means for increasing symmetry-dependent linearity; a mixer circuit comprising: An apparatus comprising:

[0108]

[0115] Exemplary Embodiment 17: The means for increasing symmetry-dependent linearity comprises: means for symmetrically disposing the first switch and the fourth switch on a first side of a line of symmetry and for symmetrically disposing the second switch and the third switch on a second side of the line of symmetry; Including, 17. The apparatus of exemplary embodiment 16.

[0109]

[0116] Exemplary Embodiment 18: means for sharing each capacitor of the plurality of capacitors across two or more switches of the plurality of switches; 18. The apparatus of Example 16 or 17, further comprising:

[0110]

[0117] Exemplary Embodiment 19: a plurality of resistors coupled to a plurality of switches; means for sharing each resistor of the plurality of resistors across two or more switches of the plurality of switches; 19. The apparatus of any one of Exemplary Embodiments 16 to 18, further comprising:

[0111]

[0118] Exemplary Embodiment 20: An apparatus, comprising: A mixer circuit, a first local oscillator node and a second local oscillator node; a first node corresponding to a first frequency; a second node and a third node, each corresponding to a second frequency; a first capacitor and a second capacitor; a first switch coupled between the first capacitor and the second node, the first switch further coupled between the first capacitor and the first node; a second switch coupled between the second capacitor and the third node, the second switch further coupled between the second capacitor and the first node; a third switch coupled between the first capacitor and a third node; a fourth switch coupled between the second capacitor and the second node; Equipped with a first capacitor coupled between the first local oscillator node and the first switch and the third switch, and a second capacitor coupled between the second local oscillator node and the fourth switch and the second switch; mixer circuit, An apparatus comprising:

[0112]

[0119] Exemplary Embodiment 21: further comprising a local oscillator; a first local oscillator node coupled between the local oscillator and the first capacitor; a second local oscillator node coupled between the local oscillator and the second capacitor; 21. The apparatus of exemplary embodiment 20.

[0113]

[0120] Exemplary Embodiment 22: a first capacitor coupled between the first local oscillator node and the control terminal of each of the first switch and the third switch; a second capacitor coupled between the second local oscillator node and the control terminal of each of the fourth switch and the second switch; 22. The apparatus of exemplary embodiment 20 or 21.

[0114]

[0121] Exemplary Embodiment 23: further comprising a first resistor and a second resistor; a first resistor coupled between the first bias node and a control terminal of each of the first switch and the third switch; a second resistor coupled between the second bias node and the control terminal of each of the fourth switch and the second switch; 23. The apparatus of exemplary embodiment 22.

[0115]

[0122] Exemplary Embodiment 24: a first switch and a second switch coupled to a first node via respective first terminals of a first terminal type; the third switch and the fourth switch are coupled to each other via respective first terminals of a first terminal type; 24. The apparatus of exemplary embodiment 22 or 23.

[0116]

[0123] Exemplary Embodiment 25: a second node coupled to the fourth switch and the first switch via respective second terminals of a second terminal type; a third node coupled to the second switch and the third switch via respective second terminals of a second terminal type; 25. The apparatus of any one of exemplary embodiments 22 to 24.

[0117]

[0124] Exemplary Embodiment 26: the first terminal type includes the drain terminal of the transistor; the second terminal type includes a source terminal of the transistor; 26. The apparatus of exemplary embodiment 25.

[0118]

[0125] Exemplary Embodiment 27: the first switch and the second switch are disposed between the fourth switch and the third switch; 27. The apparatus of any one of exemplary embodiments 20 to 26.

[0119]

[0126] Exemplary Embodiment 28: Further comprising a substrate; a first switch disposed on the substrate between the fourth switch and the second switch; a second switch disposed on the substrate between the first switch and the third switch; the first switch and the fourth switch are symmetrically arranged on a first side of a line of symmetry lying in a plane defined by the substrate, and the second switch and the third switch are symmetrically arranged on a second side of the line of symmetry; 28. The apparatus of any one of exemplary embodiments 20 to 27.

[0120]

[0127] Exemplary Embodiment 29: A method for mixing signals, comprising: receiving a first signal at a first switch and a second switch via a first node, the first signal corresponding to a first frequency; receiving a local oscillator signal at a first switch and a third switch through a first capacitor; receiving the negative local oscillator signal at the second switch and the fourth switch through a second capacitor; mixing the first signal, plus the local oscillator signal, and minus the local oscillator signal using a first switch, a second switch, a third switch, and a fourth switch to generate a second signal, the second signal corresponding to a second frequency; providing a second signal from the first switch, the second switch, the third switch, and the fourth switch through a plurality of second nodes; A method comprising:

[0121]

[0128] Exemplary embodiment 30: operating the third switch and the fourth switch as dummy switches for the first signal; 30. The method of exemplary embodiment 29, further comprising:

[0122] conclusion

[0129] As used herein, the terms "couple," "coupled," or "coupling" refer to a relationship between two or more components that are in operative communication with each other to implement some function or achieve some capability described herein. Coupling can be achieved, for example, using physical lines, such as metal traces or wires, or electromagnetic coupling, such as a transformer. Coupling can include direct coupling or indirect coupling. Direct coupling refers to connecting discrete circuit elements through the same node without any intervening elements. Indirect coupling refers to connecting discrete circuit elements through one or more other devices or other discrete circuit elements, including two or more different nodes.

[0123]

[0130] The term "node" (including, for example, a "first node" or a "local oscillator node") represents at least a point of electrical connection between two or more components (e.g., circuit elements). While a node may be visually represented in a drawing as a single point, a node may represent a connection portion of a physical circuit or network having approximately the same electrical potential at or along the connection portion between two or more components. In other words, a node may represent at least one of multiple points along a conductive medium (e.g., a wire or trace) that exists between electrically connected components. Similarly, a "terminal" may represent one or more points having at least approximately the same electrical potential relative to an input or output of a component (e.g., a transistor).

[0124]

[0131] The terms "first," "second," "third," and other numerically related indicators are used herein to identify or distinguish from one another similar or similar items within a given context, such as a particular implementation, a single drawing, a given component, or a claim. Thus, a first item in one context may be different from a first item in another context. For example, an item identified as a "first node" in one context may be identified as a "second node" in another context. Similarly, a "first capacitor" or a "first switch" in one claim may be recited as a "second capacitor" or a "third switch," respectively, in a different claim (e.g., in a separate claim set).

[0125]

[0132] Unless the context dictates otherwise, use of the word "or" herein may be considered as use of "inclusive or," or as a term permitting the inclusion or application of one or more items associated by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A," only "B," or both "A" and "B"). Also, as used herein, phrases referring to "at least one of" a list of items refer to any combination of those items, including single members. For example, "at least one of a, b, or c" is intended to include a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c). Furthermore, items depicted in the accompanying drawings and terms discussed in this specification may refer to one or more items or terms, and therefore, reference may be made interchangeably to the singular or plural forms of the items and terms in this specification.

[0126]

[0133] Although implementations for frequency mixing have been described in terms of particular features and / or methods, the subject matter of the appended claims is not necessarily limited to the particular features or methods described. Rather, the particular features and methods are disclosed as example implementations for frequency mixing.

Claims

1. It is a device, It is a mixer circuit, Multiple local oscillator nodes, A first node corresponding to a first frequency, Multiple second nodes corresponding to the second frequency, A plurality of capacitors coupled between the plurality of local oscillator nodes and the plurality of second nodes, The system comprises a plurality of switches, including a first switch, a second switch, a third switch, and a fourth switch, wherein the plurality of switches are coupled between the plurality of capacitors and the plurality of second nodes, the first switch and the second switch are coupled between the plurality of capacitors and the first node, and the first switch and the second switch are arranged between the fourth switch and the third switch. Mixer circuit, Equipped with, An apparatus in which the third switch and the fourth switch are coupled to each other via a floating node.

2. The first node is configured to provide the mixer circuit with a first signal corresponding to the first frequency. The plurality of second nodes are configured to receive a second signal corresponding to the second frequency from the mixer circuit. The apparatus according to claim 1.

3. The first signal includes an unbalanced signal, The second signal includes a balanced signal, The apparatus according to claim 2.

4. The first switch is positioned on the substrate between the fourth switch and the second switch. The second switch is positioned on the substrate between the first switch and the third switch. The apparatus according to claim 1.

5. The first switch and the fourth switch are arranged symmetrically on the first side of the line of symmetry, and the second switch and the third switch are arranged symmetrically on the second side of the line of symmetry. The apparatus according to claim 4.

6. The aforementioned substrate defines a plane, The plane includes a first axis and a second axis, the first axis is substantially perpendicular to the second axis, and the second axis is at least substantially parallel to the line of symmetry. The first switch, the second switch, the third switch, and the fourth switch are arranged on the substrate in the plane along a line that is at least substantially parallel to the first axis. The apparatus according to claim 5.

7. The plurality of capacitors include a first capacitor and a second capacitor, The first capacitor is located on the second side of the line of symmetry, The second capacitor is located on the first side of the line of symmetry. The apparatus according to claim 5.

8. The plurality of local oscillator nodes include a first local oscillator node and a second local oscillator node, The first capacitor is coupled between the first local oscillator node, the first switch, and the third switch. The second capacitor is coupled between the second local oscillator node and the second switch and the fourth switch. The apparatus according to claim 7.

9. The plurality of local oscillator nodes include positive local oscillator nodes and negative local oscillator nodes, The plurality of capacitors include a first capacitor and a second capacitor, The first capacitor is coupled between the positive local oscillator node and the first switch. The first capacitor is coupled between the positive local oscillator node and the third switch. The second capacitor is coupled between the negative local oscillator node and the fourth switch. The second capacitor is coupled between the negative local oscillator node and the second switch. The apparatus according to claim 1.

10. The mixer circuit described above, Multiple bias nodes, including a first bias node and a second bias node, Multiple bias resistors including a first resistor and a second resistor, Equipped with, The first resistor is coupled between the first bias node and the first switch. The first resistor is coupled between the first bias node and the third switch. The second resistor is coupled between the second bias node and the fourth switch. The second resistor is coupled between the second bias node and the second switch. The apparatus according to claim 9.

11. The system further comprises local oscillators coupled to the plurality of local oscillator nodes, The mixer circuit is configured to convert the frequency of the signal between the first frequency and the second frequency. The apparatus according to claim 1.

12. The system further comprises at least one transmission chain, which includes the aforementioned mixer circuit. The mixer circuit is configured to perform frequency upconversion. The apparatus according to claim 1.

13. The system further comprises at least one receiving chain, which includes the aforementioned mixer circuit. The mixer circuit is configured to perform frequency down-conversion. The apparatus according to claim 1.

14. A wireless interface device comprising the aforementioned at least one receiving chain, Display screen and At least one processor operably coupled to the display screen and at least a portion of the wireless interface device, configured to present one or more graphical images on the display screen based on one or more wireless signals communicated using the mixer circuit of the wireless interface device, The apparatus according to claim 13, further comprising the following:

15. A method for mixing signals, Receiving a first signal at a first switch and a second switch via a first node, wherein the first signal corresponds to a first frequency. The first capacitor receives the positive local oscillator signal at the first switch and the third switch, The second capacitor is used to receive the negative local oscillator signal at the second and fourth switches, Using the first switch, the second switch, the third switch, and the fourth switch, a second signal is generated by mixing the first signal, the positive local oscillator signal, and the negative local oscillator signal, wherein the second signal corresponds to a second frequency. The first switch, the second switch, the third switch, and the fourth switch provide the second signal via a plurality of second nodes, The third switch and the fourth switch are operated as dummy switches in response to the first signal, Includes, A method in which the third switch and the fourth switch are coupled to each other via a floating node.

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