Semiconductor device and manufacturing method

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33), and a first electrode (31), wherein the semiconductor body (2) comprises a first region (21) that is a source or emitter region, and a well region (22) located adjacent to the first region (21), wherein the first region (21) is of a first conductivity type and the well region (22) is of a different second conductivity type, the well region (22) is separated from the gate electrode (33) by a gate insulating layer (4), the first region (21) is in electrical contact with the first electrode (31), at least one current limiting region (5) is present in the first region (21), and the at least one current limiting region (5) is a sub-region of the first region (21) that has reduced conductivity.

Description

[Technical Field]

[0001] A semiconductor device is provided, as well as a method for manufacturing such a semiconductor device. [Background technology]

[0002] The documents US Patent Application Publication No. 2017 / 0243970, US Patent Application Publication No. 2017 / 0229535, and US Patent Application Publication No. 2015 / 0108564 refer to semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved is to provide a semiconductor device having an improved tradeoff between conduction losses and short circuit withstand capability SCWT. [Means for solving the problem]

[0004] This object is achieved, inter alia, by a semiconductor device and a method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] For example, the semiconductor devices described herein may include one or more current-confining regions that are subregions of a source region or an emitter region, the subregions being irradiated such that more crystal lattice defects are present in the subregion than in the remainder of the source region or emitter region, and therefore the at least one current-confining region has a reduced electrical conductivity compared to the remainder of the source region or emitter region. S increases. This R S The increase in r does not significantly hinder device performance in normal operation, but improves short circuit behavior.

[0006] According to at least one embodiment, a semiconductor device includes a semiconductor body, a gate electrode, and a first electrode. For example, the semiconductor body is made of a wide bandgap semiconductor material such as SiC, Ga2O3, or GaN. However, the semiconductor body may alternatively be made of silicon, or Si for short. The electrodes may also be made of at least one metal or a highly doped and / or ohmic conductive semiconductor material such as poly-Si.

[0007] According to at least one embodiment, the semiconductor body comprises a first region, for example, the first region is a source region or an emitter region.

[0008] According to at least one embodiment, the semiconductor body includes a well region. The well region is located adjacent to the first region. That is, the first region can contact the well region and thus be in direct physical contact with the well region. The channel region is a portion of the well region and may have the same doping concentration. During operation, electrons flow in the channel region from the source region to the drift region along the gate insulating layer. In operation of the semiconductor device, the channel region may be that portion of the well region adjacent to the gate insulating layer.

[0009] According to at least one embodiment, the first region is of a first conductivity type and the well region is of a different second conductivity type. For example, the first conductivity type may be n-conductivity and the second conductivity type may be p-conductivity, or vice versa. Hereinafter, the first conductivity type will be referred to as n-conductivity; therefore, if the first conductivity type were instead p-conductivity, the doping relationships described below would have to be reversed.

[0010] According to at least one embodiment, the well region is adjacent to the gate electrode and separated from the gate electrode by a gate insulating layer, which may be directly between the gate electrode and the well region.

[0011] According to at least one embodiment, the first region is in electrical contact with a first electrode, e.g., a source electrode or an emitter electrode. Thus, the first electrode can contact the semiconductor body in at least the first region. For example, the well can be electrically contacted by the first electrode or by a separate electrode.

[0012] According to at least one embodiment, the first region includes one or more current-limiting regions. The at least one current-limiting region is a subregion of the first region with reduced electrical conductivity. For example, the first region and the at least one current-limiting region are made of the same base material, such as SiC. However, the at least one current-limiting region has more defects in its crystal lattice than the rest of the first region, so the electrical conductivity of the at least one current-limiting region is intentionally lower than the rest of the first region.

[0013] In at least one embodiment, a semiconductor device comprises a semiconductor body, a gate electrode, and a first electrode; the semiconductor body comprises a first region and a well region located adjacent to the first region, the first region being of a first conductivity type and the well region being of a different second conductivity type; the well region is adjacent to the gate electrode and separated from the gate electrode by a gate insulating layer; the first region is in electrical contact with a first electrode; - the first region has at least one current limiting region; at least one current-limiting region is a sub-region of the first region of reduced electrical conductivity;

[0014] Thus, the present application describes, for example, a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a junction-gate field-effect transistor (JFET) based on silicon carbide (SiC) material, in which at least one subregion of the source or emitter region is damaged by irradiation to reduce its electrical conductivity, improving the trade-off between conduction losses and short-circuit capability.

[0015] SiC MOSFETs are currently available from several vendors. Offered in either planar or trench cell designs, SiC MOSFETs offer competitive static losses, fast dynamic performance, and sufficient reliability. In terms of fault handling capability, SiC MOSFETs still fall short of the typical industry standard value of about 10 μs exhibited by their Si counterparts. This is usually associated with a strong trade-off between conduction losses and short-circuit withstand voltage (SCWT). SCWT and on-state device resistance, R DS,on One approach for the best trade-off between S The best way to do this is to use

[0016] Thus, for example, a SiC MOSFET is described herein in which a portion of the source region is subjected to an irradiation process. When using an appropriate mask, such as an SiO2 mask or an Al mask, n + Irradiation of electrons, protons, or neutrons in the source reduces the mobility and therefore the source resistance R S This results in the formation of defects that increase the resistivity, e.g., by 10 in at least one current-limiting region. -2 ~10 7 It can be varied to be in the Ωcm range.

[0017] Thus, in at least one proposed current-limiting region, current flows through a more resistive and / or constricted path. This effect reduces the source resistance R S The value of R increases. SIncreasing the value of σ increases the saturation current I during a short circuit, or SC for short. SAT The depth d of the irradiated area and its length L change during conduction under nominal conditions, i.e., R DS,on It can be suitably designed to achieve the desired effect on SC current while ignoring its effect on the total resistance between source and drain in the on-state, also called the resistance between source and drain.

[0018] According to at least one embodiment, the semiconductor device is a power device. This means, for example, that the semiconductor device is configured for a maximum current through the well region of at least 10 A or at least 50 A. Optionally, the maximum current is at most 500 A or at most 1.5 kA. Alternatively or additionally, the semiconductor device is configured for a maximum voltage between the source and drain or between the emitter and collector of at least 0.6 kV or at least 1.2 kV. Optionally, the maximum voltage can be at most 6.5 kV.

[0019] According to at least one embodiment, from a top perspective of the semiconductor body, the gate electrode and the first electrode overlap the first region. Here and hereinafter, "top view" may refer to a view perpendicular to the top surface of the semiconductor body to which the first electrode is attached and on which the first region is located.

[0020] According to at least one embodiment, the at least one current confinement region is spaced apart from the gate electrode and / or the first electrode when viewed from above the semiconductor body, e.g., the at least one current confinement region is spaced apart from the gate electrode and the first electrode when viewed from above.

[0021] According to at least one embodiment, the at least one current-limiting region is located in the assigned first region with mirror symmetry, e.g., within manufacturing tolerances. That is, when viewed from above the semiconductor body, the first region and the at least one current-limiting region have a mirror symmetry axis, e.g., with respect to the shape of the first region and the at least one current-limiting region. When viewed from above, the mirror symmetry axis may extend parallel to the gate electrode and / or the first electrode and / or may be located between the gate electrode and the first electrode. Otherwise, when viewed from above, a non-mirror symmetric arrangement of the at least one current-limiting region in the assigned first region is also possible.

[0022] According to at least one embodiment, the first region extends completely between the at least one current confinement region and the first electrode and between the at least one current confinement region and the gate electrode, i.e., there is a portion of the first region between the at least one current confinement region and the respective electrode, e.g., at the top surface of the semiconductor body, when viewed from above the semiconductor body.

[0023] Alternatively, from a top view of the semiconductor body, the at least one current confinement region may be partially covered by the gate electrode or the at least one current confinement region contacts the gate electrode.

[0024] According to at least one embodiment, the at least one current-limiting region is located between the first electrode and the gate electrode, for example, all of the at least one current-limiting region is disposed between said electrodes.

[0025] According to at least one embodiment, when viewed in a cross-section of the semiconductor body, the first region extends completely around the at least one current limiting region in a direction toward the well region. This can mean that the first region is integrated into the well region and / or that the at least one current limiting region is integrated into the first region. For example, when viewed in cross-section, in this case, a portion of the first region is completely around the at least one current limiting region, so that there is no straight connecting line in the semiconductor body from the at least one current limiting region to the well region without crossing the first region.

[0026] The term "cross-section of the semiconductor body" can refer to a cross-section through the first region, through the current confinement region, or through at least one of the current confinement regions, through the gate electrode, e.g., in a direction perpendicular to the top surface of the semiconductor body and / or perpendicular to the direction of the main extent of the gate electrode.

[0027] According to at least one embodiment, the at least one current-limiting region is completely embedded in the first region when viewed through a cross-section of the semiconductor body, e.g., the first region completely surrounds the at least one current-limiting region when viewed through a cross-section of the semiconductor body.

[0028] According to at least one embodiment, for example, when viewed from a cross-section of the semiconductor body, the at least one current-confining region completely penetrates the first region. Thus, the at least one current-confining region can be as deep as the first region or deeper than the first region. In other words, the at least one current-confining region penetrates the first region in a direction perpendicular to the top surface of the semiconductor body. The at least one current-confining region can begin directly at the top surface or can begin away from the top surface within the first region.

[0029] According to at least one embodiment, the volume of at least one current-limiting region is at least 5%, or at least 10%, or at least 20%, or at least 40%, or at least 60% of the total volume of the associated first region. Alternatively or additionally, said percentage is at most 95%, or at most 85%, or at most 75%. For example, said percentage is at least 40% and at most 85%.

[0030] For example, the at least one current-limiting region increases the electrical resistance through the first region between the first electrode and the channel region by at least 1.1 times, or at least 1.5 times, or at least 2 times, or at least 5 times. Alternatively or additionally, the factor is at most 100, or at most 25, or at most 15, or at most 10, or at most 5. For example, the factor is greater than or equal to 2 and less than or equal to 10. The electrical resistance through the first region can refer to the normal operating current for which the semiconductor device is designed in the on-state. These factors refer to a device that does not have at least one current-limiting region in the first region but is otherwise identical in structure within manufacturing tolerances.

[0031] According to at least one embodiment, the conductivity of the at least one current-limiting region is at least 0.1%, or at least 1%, or at least 5% of the conductivity of the remainder of the first region, or alternatively or additionally, said value is at most 95%, or at most 80%, or at most 20%, or at most 10%.

[0032] According to at least one embodiment, the crystal lattice in the at least one current-confining region has at least two times, or at least five times, or at least ten times more defects than the remainder of the first region. Alternatively or additionally, the multiple is at most 10 3or at most 100, or at most 10. Thus, in the at least one current limiting region, there is a higher defect density than in the remainder of the first region, achieved by irradiating the at least one current limiting region.

[0033] For example, the at least one current-confining region reduces an effective cross-sectional area for current flow in the first region from the first electrode to the well region adjacent the gate insulating layer, i.e., the channel region, by a factor of at least 1.5, or at least 2, or at least 5. Alternatively or additionally, the factor is at most 100, or at most 15, or at most 10, or at most 5, or at most 2. For example, the factor is 2 or more and 10 or less.

[0034] Effective cross-sectional area A of current flow eff may be the minimum value of the local electrical resistance r integrated over an area A of a cross section through the first region perpendicular to the principal direction of current flow.

[0035]

number

[0036] According to at least one embodiment, the at least one current-limiting region is aligned with and terminates in the first region. Thus, the top surface may be flat across the first region and the at least one current-limiting region, with both the at least one current-limiting region and the remainder of the first region terminating at the top surface. In other words, the first region and the current-limiting region form a flat surface and are aligned with each other.

[0037] According to at least one embodiment, the semiconductor body further comprises a drift region, the drift region being of the first conductivity type and having, for example, a lower maximum doping concentration compared to the first region and the well region.

[0038] According to at least one embodiment, the semiconductor body further comprises a second region. For example, the second region is a drain region or a collector region. In the case of a drain region, the second region is also of the first conductivity type, but, for example, has a higher maximum doping concentration than the drift region. In the case of a collector region, the second region is of the second conductivity type.

[0039] According to at least one embodiment, the drift region is located between the well region and the second region, such that the first region is separated from the second region by the well region.

[0040] According to at least one embodiment, the semiconductor device further comprises a second electrode, e.g., a collector electrode or a drain electrode, which can be located on a side of the second region remote from the drift region and / or remote from the first region.

[0041] According to at least one embodiment, when viewed from a top perspective of the semiconductor body, the gate electrode and the first electrode each extend along a straight line, and if there are multiple first electrodes and / or gate electrodes, there can be multiple straight lines along which the first electrodes and / or gate electrodes extend.

[0042] According to at least one embodiment, the first region extends parallel to the gate electrode and / or the first electrode, and thus the semiconductor device can be a stripe design including multiple rectilinear stripes of the gate electrode and / or the first electrode.

[0043] According to at least one embodiment, when viewed from above the semiconductor body, the gate electrode and / or the first electrode each comprise a plurality of subsections. For example, the subsections correspond to unit cells. The unit cells can be arranged, for example, in a regular two-dimensional grid. The semiconductor body can extend continuously across all the unit cells and comprise a plurality of first regions arranged accordingly. Thus, the semiconductor device can have a cellular design comprising a plurality of cells, each having a first electrode, a corresponding gate electrode, and a corresponding first region with at least one current-limiting region.

[0044] According to at least one embodiment, the semiconductor device has a planar design, i.e., the gate insulating layer and the gate electrode are applied to a planar section of the top surface of the semiconductor body, and the first region and the at least one current-limiting region can be located on the top surface.

[0045] According to at least one embodiment, the semiconductor device has a trench design. Thus, the gate insulating layer and gate electrode are partially or completely disposed in a trench within the semiconductor body. For example, the depth of the trench begins at the top surface of the semiconductor body and exceeds the depth of the well region. In this case, the first region and at least one current-limiting region can be located at the top surface.

[0046] According to at least one embodiment, there is exactly one current limiting region within a first region. In the case of multiple first regions, there can be a one-to-one assignment between the first regions and the current limiting regions.

[0047] Alternatively, there may be multiple current-limiting regions in the first region. In the case of multiple first regions, there may be multiple current-limiting regions per first region. The current-limiting regions of each one of the first regions, or of just one first region, are spaced apart from one another when viewed from above the semiconductor body.

[0048] When viewed from above the semiconductor body, the or each one of the current limiting regions can be completely surrounded by the respectively assigned first region.

[0049] According to at least one embodiment, the current-limiting regions are arranged along a stripe or along multiple stripes. Additionally, optionally, the current-limiting regions are arranged along a column or along multiple columns when viewed from above, with the stripes and columns oriented perpendicular to each other. In the case of multiple first regions, this can be true for each of the first regions, with each of the first regions being assigned to multiple current-limiting regions.

[0050] According to at least one embodiment, when viewed from above the semiconductor body, the current-constraining regions are shaped as at least one of a triangle, a square, a rectangle, a hexagon, and a circle. When viewed from above, all of the current-constraining regions may have the same shape and / or area content. Otherwise, and for each first region, current-constraining regions of different shapes and / or sizes may be combined with one another.

[0051] There is also provided a method for manufacturing a semiconductor device, by which a semiconductor device is manufactured as shown in relation to at least one of the above-described embodiments. Accordingly, features of the semiconductor device are also disclosed in relation to the method, and vice versa.

[0052] In at least one embodiment, the manufacturing method is for manufacturing a semiconductor device, and the method includes, for example, in the listed order: providing a semiconductor body; forming a first region and a well region in a semiconductor body; applying a mask layer to the semiconductor body; - irradiating at least one portion of a first region defined by a mask layer with at least one of x-rays, electrons, protons, neutrons, or ions, thereby creating at least one current-restriction region in the irradiated at least one portion; - applying a gate insulating layer and a gate electrode and a first electrode to the semiconductor body; Includes:

[0053] The dose for irradiating the at least one portion can be used as a design parameter to adjust the resistance of the at least one current-limiting region, and therefore the first region, to achieve a desired effect. For example, in the case of electron irradiation, the dose can be 10 10 cm -2 ~10 17 cm -2 and / or up to 10% of the maximum doping concentration of the first region. In the case of proton irradiation, for example, the dose may be 10 8 cm -2 ~10 14 cm -2 It could be.

[0054] The shape of the at least one current-limiting region, as viewed from above on the top surface, is defined by the mask layer, while the depth of the at least one current-limiting region depends on the thickness of the mask layer and the energy used for the irradiation, e.g., from a minimum of 116 keV for electrons or from a minimum of 200 keV for protons and neutrons. Only one type of irradiation, e.g., electron irradiation, can be present, or different types of irradiation can be combined with each other.

[0055] According to at least one embodiment, the method further includes forming one or more plug regions in the semiconductor body, the at least one plug region being of the second conductivity type and having a maximum doping concentration greater than a maximum doping concentration of the well region, the at least one plug region being for electrically contacting the well region, for example, by a first electrode.

[0056] According to at least one embodiment, the first region extends deeper into the semiconductor body than the at least one plug region.

[0057] According to at least one embodiment, creating the first region includes two different doping steps, such that, when viewed in cross section, the doping profile of the first region is stepped, i.e., the first region can widen toward the top surface.

[0058] The semiconductor devices and methods described herein will be explained in more detail below by way of exemplary embodiments with reference to the drawings. Like elements in the individual figures are designated by like reference numerals. However, the relationships between elements are not shown to scale, and rather, individual elements may be shown exaggeratedly large to aid understanding. [Brief explanation of the drawings]

[0059] [Figure 1] 1 is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 4] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 5] 1 is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 6] 1 is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 7] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 8] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 9]1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 10] 1 is a schematic diagram of a simulated electrical characteristic of an exemplary embodiment of a semiconductor device described herein compared to a corresponding semiconductor device without at least one current-constraining region. [Figure 11] 1 is a schematic diagram of a simulated electrical characteristic of an exemplary embodiment of a semiconductor device described herein compared to a corresponding semiconductor device without at least one current-constraining region. [Figure 12] 1 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device described herein. [Figure 13] 1A-1D are schematic cross-sectional views of method steps of exemplary embodiments of methods described herein. [Figure 14] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; [Figure 15] 1 is a schematic top view of an exemplary embodiment of a semiconductor device described herein; DETAILED DESCRIPTION OF THE INVENTION

[0060] 1 shows an exemplary embodiment of a semiconductor device 1. The semiconductor device 1 comprises a semiconductor body 2, for example made of SiC. The semiconductor body 2 includes a first region 21, a well region 22, and a drift region 23. Additionally, a plug region 25 for electrically contacting the well region 22 is present.

[0061] The semiconductor device 1 further includes a gate electrode 33 separated from the semiconductor body 2 by a gate insulating layer 4. Additionally, there is a first electrode 31 in electrical contact with the first region 21 and the plug region 25. The gate insulating layer 4 and the first electrode 31 are located on a top surface 20 of the semiconductor body 2. The top surface 20 is planar. The gate electrode 33 and the first electrode 31 may each extend along a straight line perpendicular to the cross section shown in FIG. 1 . The gate insulating layer 4 may be made of a metal oxide, a semiconductor oxide, a metal nitride, and / or a semiconductor nitride. For example, the gate insulating layer 4 includes one or more of the following materials: SiO2, Si3N4, Al2O3, YO3, ZrO2, HfO2, La2O3, Ta2O5, and TiO2.

[0062] For example, first region 21 and drift region 23 are n-doped, and well region 22 and plug region 25 are p-doped. If semiconductor device 1 is an insulated gate bipolar transistor (IGBT) or a reverse conducting insulated gate bipolar transistor (RC-IGBT), first region 21 is an emitter region and first electrode 31 is an emitter electrode. If semiconductor device 1 is a junction gate field effect transistor (JFET), a metal-insulator-semiconductor field effect transistor (MISFET), or a metal-oxide-semiconductor field effect transistor (MOSFET), first region 21 is a source region and first electrode 31 is a source electrode.

[0063] The first region 21 includes a current-limiting region 5. The current-limiting region 5 is made of the same material as the rest of the first region, for example, SiC. However, due to irradiation of the portion of the first region 21 that constitutes the current-limiting region 5, the current-limiting region 5 has a reduced electrical conductivity compared to the rest of the first region 21.

[0064] Thus, Figure 1 illustrates the basic concept of the proposed semiconductor device 1. After source activation, a region, namely at least one current-limiting region 5, is irradiated. Its width is defined by the mask design, while the depth of this region 5 depends on the thickness of the mask and the energy used for irradiation. During irradiation, for example, some point defects are formed. These defects can form electrically active levels within the band gap, such as EH1, Z1 / 2, EH3, EH4, EH5, and EH6 / 7, as compared to G. Alfieri et al., "Annealing behavior between room temperature and 2000°C of deep level defects in electron-irradiated n-type 4H silicon carbide," Journal of Applied Physics 98, 043518 (2005), doi:10.1063 / 1.2009816, and Alfieri et al., "Isothermal Annealing Study of the EH1 and EH3 Levels in n-type 4H-SiC," J.Phys.:Condens.Matter 32, 4657'3 (2020), doi:10.1088 / 1361-648X / abaeaf. These levels trap charge carriers and reduce their mobility. The lower the mobility, the lower the source resistance R S The value of becomes larger.

[0065] The current confinement region 5 extends along a straight line parallel to the gate electrode 33 and the first electrode 31. The current confinement region 5 is located directly at the top surface 20, like the first region 21. The depth of the first region 21 into the semiconductor body 2 exceeds the depth of the current confinement region 5 into the semiconductor body 2 starting from the top surface 20. The first region 21 is present, in cross section, all around the current confinement region 5, towards the well region 22 in which the first region 21 is embedded.

[0066] For example, the at least one current-limiting region 5 is arranged in a mirror-symmetric manner within the first region 21 when viewed from above and when viewed in a cross section. For example, when viewed from above the top surface 20, the current-limiting region 5 is arranged symmetrically within the first region 21 and between the electrodes 31, 33. Thus, a line of mirror symmetry M can exist with respect to the current-limiting region 5 and the first region 21.

[0067] The at least one current-restricting region 5 may have different shapes and depths and may also be uniform or non-uniform along a direction perpendicular to the cross section of FIG. 1, see also FIGS. 2-9 below.

[0068] In the proposed at least one current-restriction region 5, the current flows through a more resistive and / or constricted path. This effect is due to the source resistance R S or a corresponding increase in the value of the emitter resistance R S Increasing the value of increases the saturation current I during short circuit conditions. SAT The depth d of the current-limiting region 5 along the cross section of FIG. 1 parallel to the upper surface 20 and its length L are determined by the following equation: DS,on can be appropriately designed to achieve the desired effect on short circuit current while continuing to neglect its effect on

[0069] For example, the effective channel contact-to-contact path length Leff of the carriers is the minimum value of the local resistance r along all possible paths S having an incremental element s within the first region 21 including at least one current-limiting region 5.

[0070]

number

[0071] The semiconductor device 1 in Fig. 1 has a planar design. In contrast to that, the semiconductor device 1 in Fig. 2 has a trench design. The gate electrode 33 and the gate insulating layer 4 are therefore at least partially located in a trench into the semiconductor body 2. Accordingly, the top surface 20 is not planar, in contrast to the case in Fig. 1, since it is penetrated by the trench. The gate electrode 33, for example, starts from the top surface 20 and extends deeper into the semiconductor body 2 than the well region 22.

[0072] 2 further shows that the multiple first regions 21, and therefore the current-limiting regions 5, are arranged symmetrically, for example, with respect to the gate electrode 33. The multiple units shown in FIG. 2 can be adjacent to each other along a direction parallel to the top surface 20, resulting in multiple stripes of the first electrode 31 extending perpendicular to the gate electrode 33 and the projection plane of FIG. 2 and parallel to each other.

[0073] This symmetrical arrangement of FIG. 2, see also FIG. 14, and / or the trench design of FIG. 2 can be applied to all other embodiments as well.

[0074] One current-limiting region 5 per first region 21 in Fig. 2 has the same design as in Fig. 1, i.e., a trough with a rectangular parallelepiped shape. According to Fig. 2, the trough has sharp edges and corners, while according to Fig. 1, the trough has rounded edges and corners. Both designs are possible in all embodiments, depending on the manufacturing process of the at least one current-limiting region 5.

[0075] 2 shows that there is a second electrode 32 and that the semiconductor body 2 comprises a second region 24. For example, the second region 24 is a substrate in which the other regions 23, 22, 21, 25 are formed by growth and / or doping, such as ion implantation. In the case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode and the second region is a collector region of the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is a drain electrode and the second region is a drain region of the same doping type as the first region. Analogously, this is true for all other embodiments of the semiconductor device 1.

[0076] Furthermore, according to Fig. 2, the plug region 25 starts from the top surface 20 and reaches deeper into the semiconductor body 2 than the first region 21. Otherwise, with reference to Fig. 1, the plug region 25 can have the same depth as the first region 21, or it can be shallower or deeper than the first region 21. In all embodiments, both possibilities can apply.

[0077] As in FIG. 1, in FIG. 2 at least one current-confining region 5 per first region 21 is spaced apart from the first electrode 31 , from the gate electrode 33 and from the gate insulating layer 4 .

[0078] For example, the maximum doping concentration of the first region 21, the second region 24, and the at least one plug region 25 is at least 1×10 18 cm -3 Or at least 5 x 10 18 cm -3 Or at least 1×10 19 cm -3 and / or at most 5 × 10 20 cm -3 Or at most 2 x 10 20 cm -3 Or at most 1×10 20 cm -3 Furthermore, the maximum doping concentration of the well region 22, and therefore the channel region adjacent to the gate insulating layer 4, is at least 5×10 16cm -3 Or at least 1×10 17 cm -3 and / or at most 5 × 10 19 cm -3 Or at most 5 x 10 18 cm -3 Depending on the voltage class of the semiconductor device 1, the maximum doping concentration of the drift region 23 may be at least 1×10 11 cm -3 Or at least 1×10 12 cm -3 Or at least 1×10 13 cm -3 and / or at most 1 × 10 17 cm -3 Or at most 5 x 10 16 cm -3 Or at most 1×10 16 cm -3 For example, the thickness of the gate insulating layer 4 may be 10 nm to 250 nm or 80 nm to 150 nm. These parameters may also be applied individually or collectively to all other embodiments.

[0079] Otherwise, the same may be true for Figure 2 as for Figure 1, and vice versa.

[0080] 3 and 4, as in FIG. 1, there is one current-limiting region 5 per first region 21. The current-limiting regions 5 may be arranged with mirror symmetry within the first region 25, with the axis of mirror symmetry extending perpendicular to the top surface 20.

[0081] 1, according to FIGS. 3 and 4, the current-limiting region 5 extends beyond the gate insulating layer 4 as well as the gate electrode 33. Such an arrangement is also possible in all other exemplary embodiments. Alternatively, in contrast to what is shown in FIGS. 3 and 4, the current-limiting region 5 may be located non-mirror-symmetrically within the first region 21, so that the current-limiting region 5 ends away from the gate insulating layer 4 and therefore does not extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0082] According to FIG. 3, the current-limiting region 5 is formed as a shallow trough within the first region 21, which is also formed as a trough. The depth d of the current-limiting region 5 is, for example, 10% to 90% or 40% to 80% of the depth D of the first region 21. The first region 21 and the plug region 25 may have the same depth, for example, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 μm and / or at most 2 μm.

[0083] According to FIG. 4 , the current-confining region 5 is formed as a deep trough in the first region 21, formed as two troughs one above the other, with the trough adjacent to the top surface 20 having a larger extent parallel to the projection plane of FIG. 4 . Again, the depth d of the current-confining region 5 can reach 10% to 90% or 40% to 80% of the depth D of the entire first region 21. Due to the design with two stacked troughs, the first region 21 can extend deeper into the semiconductor body 2 than the plug region 25. The plug region 25 can be, for example, as deep as the trough of the first region 21 adjacent to the top surface 20, within manufacturing tolerances. For example, the depth D of the first region 21 is at least 2 μm and / or at most 4 μm.

[0084] For example, first the troughs adjacent to the upper surface 20 are formed with corresponding doping, and then the doping for the troughs further away from the upper surface 20 is provided, for example, by using different energies in the ion implantation process. Thus, the troughs in Fig. 4 have a stepped design when viewed in cross section. Otherwise, in the configuration of Fig. 4, deep troughs having a rectangular shape with rounded corners, as depicted in Fig. 3, for example, are also possible.

[0085] Both designs with shallow or deep first regions 21 shown in Figures 3 and 4 are possible in all other embodiments.

[0086] For example, the length L of the current-limiting region 5 is 10% to 90%, 40% to 80%, or 50% to 70% of the width B of the first region 21. This is also possible in all other embodiments.

[0087] Otherwise, the same may be true for Figures 3 and 4 as for Figures 1 and 2, and vice versa.

[0088] 5-7, there are multiple current-limiting regions 5 per first region 21. With respect to the parameters d, D, B, and L described above for the case of a single current-limiting region 5 per first region 21, the same applies to the case of multiple current-limiting regions 5 per first region 21, where L corresponds to the total width of all respective current-limiting regions 5, compare for example FIG. 6. With multiple current-limiting regions 5, there are more design parameters to achieve an optimized first region.

[0089] For one current confinement region 5 in a direction perpendicular to the gate electrode 33 and / or first electrode 31, referring to FIG. 5, the total width L is the same as the width W of the individual insulating current confinement region 5 shown in FIG. 4.

[0090] However, according to Figure 5, there is one stripe of current-limiting region 5 extending parallel to electrodes 31, 33. From a top perspective, current-limiting region 5 is rectangular or square in shape, optionally with rounded corners, each having a width W and a length range V. For example, V is between 0.5L and 100L, or between 0.5L and 10L, or between 0.7L and 5L.

[0091] For example, the distance Zs between adjacent current-constraining regions 5 along a stripe is 10% to 75% or 10% to 40% of the width W and / or length V. Individual current-constraining regions 5 within a stripe can be spaced equidistantly or at different distances from each other than those shown in FIG. 5. These aspects may also apply individually or collectively to all other embodiments.

[0092] Other than as shown, the current-limiting region 5 does not have to be square in shape when viewed from above, but may be rectangular, hexagonal, regular or irregular polygonal, or circular in shape when viewed from above, as well as all other embodiments.

[0093] 5 to 7, all of the current-limiting regions 5 in each first region 21 have the same shape. This is not necessarily essential; that is, current-limiting regions 5 of different shapes may be combined within one first region 21.

[0094] There can be N stripes of current-limiting regions 5 between the electrodes 31, 33, where N is a natural number greater than or equal to 2. For example, N is at most 10 or at most 4. According to the example of FIG. 6, N is 2. For example, 0.1 B / N≦W≦0.99 B / N, 0.4 B / N≦W≦0.95 B / N, or 0.7 B / N≦W≦0.90 B / N may apply. Alternatively or additionally, the distance Zt between adjacent current-limiting regions 5 in the transverse direction perpendicular to the stripes is 10% to 75% or 10% to 40% of the length range V. Alternatively or additionally, for example, 0.1 B / N≦V≦100 B / N, 0.4 B / N≦V≦10 B / N, or 0.7 B / N≦V≦5 B / N may apply. The current-limiting regions 5 can be arranged equidistantly parallel and perpendicular to the electrodes 31, 33.

[0095] 6, all N stripes have the same number of current-limiting regions 5, so that in each case, K current-limiting regions 5 are adjacent to each other in a direction parallel to the stripes, forming a regular array of N×K current-limiting regions 5, all of which have the same shape.

[0096] However, this is not required. That is, current-constraint regions 5 of different shapes and sizes can be combined with each other, and there can be a different number K of current-constraint regions 5 per stripe and / or a different number N of current-constraint regions 5 in the direction parallel to the width L. For example, there can be current-constraint regions 5 of different widths W, such that, as an example, rows parallel to the direction along the width L having a single wide current-constraint region 5 alternate with rows having multiple narrower current-constraint regions 5.

[0097] In Figure 7, N is shown to be 3. Optionally, the stripes furthest from the first electrode 31 reach beyond the gate insulating layer 4. However, other than as shown in Figure 7, all stripes may be further from the gate electrode 33, for example, when viewed from above the top surface 20.

[0098] Each of the stripes in Figure 7 can be made up of multiple current-restriction regions 5, as in Figures 5 and 6, or there is only a single current-restriction region 5 per stripe, as in Figures 1-4, and similarly for all other embodiments.

[0099] The current-limiting regions 5 in Figures 5-7 are of shallow design, for example, compared to Figure 3 above. It is also possible that all or some of the current-limiting regions 5 per first region 21 are of deep design, as depicted in connection with Figure 4.

[0100] Otherwise, the same may be true for Figures 5-7 with respect to Figures 1-4, and vice versa.

[0101] 8, the current-limiting region 5 penetrates completely through the first region 21 from the top surface 20 to the well region 22. Therefore, all current from the first electrode 31 to the channel region of the well region 22 adjacent to the gate insulating layer 4 must flow through the lower conductivity current-limiting region 5, ignoring possible small currents around the current-limiting region 5 that pass through the portion of the well region 22 away from the top surface 20 of the current-limiting region 5.

[0102] Due to its length parallel to the projection plane of FIG. 8 and due to the conductivity of the current-limiting region 5, the resistance of the first region 21 can be adjusted particularly precisely.

[0103] Otherwise, the same may be true for Figure 8 as for Figures 1-7, and vice versa.

[0104] 9, the current-constraining region 5 is completely embedded in the remainder of the first region 21. That is, the first region 21 is all around the current-constraining region 5. It is therefore possible for the current-constraining region 5 to extend beyond the gate electrode 33. Other than as shown, the current-constraining region 5 may not extend underneath the gate electrode 33.

[0105] For example, the layer thickness of the first region 21 around the entire current-limiting region 5 has a thickness of at least 5% or at least 10% and / or at most 30% or at most 45% of the total thickness of the first region 21 together with the incorporated current-limiting region 5.

[0106] The design of FIG. 9 is also possible with multiple current-limiting regions 5 per first region 21, for example, compare FIGS. 5-7, or with deep current-limiting regions 5, for example, compare FIG.

[0107] Otherwise, the same may be true for Figure 9 as for Figures 1-8, and vice versa.

[0108] 10 and 11 show the gate-source voltage V of the semiconductor device 1 of FIG. 8 compared to the corresponding reference MOSFET design 9 without the current-limiting region. GS Simulated isothermal power J at 15V and 300K D Against V DS , and the drain-source voltage V DS = 600V and V GS,Swing 8 shows an electrothermal short circuit waveform at −5 V / +15 V. In the semiconductor device 1 corresponding to FIG. 8, the quotient d / D of the depth d of the current limiting region 5 and the depth D of the first region 21 is 1. The quotient L / B of the length L of the current limiting region 5 and the width B of the first region 21 is 0.5.

[0109] Maximum saturation current during short circuit I SAT,peak The realized reduction in the on-state resistance R DS,on Note that the increase in I is greater than the increase in I. The energy received by the device during a short circuit is SAT Since the maximum value of .DELTA..times ...

[0110] 12 shows a method for manufacturing a semiconductor device 1. In method step S1, a semiconductor body 2 is provided. For example, the semiconductor body 2 provides a drift region 23. Then, in method step S2, a first region 21 and a well region 22 are formed in the semiconductor body 2 and a plug region 25.

[0111] Next, in step S3, at least one mask layer is provided on the top surface 20 of the semiconductor body 2. Furthermore, in step S4, at least one portion of the first region 21 defined by the mask layer is irradiated with at least one of X-rays, electrons, protons, neutrons, or ions, resulting in the creation of at least one current-confining region 5 in the at least one irradiated portion. Then, in step S5, a gate insulating layer 4, a gate electrode 33, and a first electrode 31 are applied to the semiconductor body 2, and optionally also to a second electrode 32.

[0112] In a further step not shown, the mask layer may be partially or completely removed and the semiconductor device 1 may be completed.

[0113] The method steps S1 to S5 do not necessarily have to be performed in the order presented. Method step S5 is illustrated in more detail in Figure 13. As can be seen from Figure 13, in this step S5, optionally, no electrodes have been applied yet. It is also possible for the gate insulating layer 4 to be applied immediately after the irradiation step, which is symbolized in Figure 13 by the gate insulating layer 4 being represented by a dashed line.

[0114] 13, a mask layer 6, for example made of silicon dioxide, is applied to the upper surface 20 and structured to represent at least one current limiting region 5. In the region of the at least one current limiting region 5, radiation R can pass through the mask layer 6 to reach the first region 21. In other parts of the semiconductor body 2, radiation R may not be able to reach the semiconductor body 2.

[0115] In contrast to what is shown in FIG. 13, it is also possible to have the upper surface 20 completely free of the mask layer 6 in the region of at least one current-limiting region 5 .

[0116] For example, the radiation R may consist of electrons, protons, or neutrons with energies greater than about 0.1 MeV. Such irradiation may damage the crystal lattice of the material of the first region 21, resulting in the generation of many point defects. Besides increasing the defect density, it may alternatively or additionally be possible to neutralize the doping of the first region 21, for example by counterdoping, so that the radiation R may also consist of ions.

[0117] An example of a semiconductor device 1 is shown in a top view in Figure 14. It can be seen that the stripes of gate electrode 33 are, for example, symmetrically located between the two stripes of the first electrode 31 halves and therefore between the two stripes of the first region 21 having the current-limiting region 5. The structure in Figure 14 corresponds to a unit cell that can be multiplied so that multiple unit cells can be placed adjacent to each other.

[0118] This stripe design is equally applicable to the embodiments of Figures 1 and 3-9, and Figure 2 already shows a symmetrical design of this kind.

[0119] Otherwise, the same may be true for Figure 14 with respect to Figures 1-13, and vice versa.

[0120] 15, the semiconductor device 1 may also have a cellular design when viewed from above, such that rectangular or square unit cells can be produced. For example, a unit cell has a first electrode 31 at its center, surrounded by a gate electrode 33. Such unit cells can be arranged two-dimensionally, such that the semiconductor device 1 can include many such unit cells.

[0121] Otherwise, the same may be true for FIG. 15 as for FIG. 14, and vice versa.

[0122] Components shown in the figures exemplarily follow one another directly in the specified order, unless otherwise indicated. Components that are not touching in the figures are exemplarily spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the depicted components relative to one another are accurately reproduced in the figures.

[0123] The invention described herein is not limited by the description based on the exemplary embodiments, but rather the invention encompasses any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly named in the claims or exemplary embodiments. [Explanation of symbols]

[0124] List of Reference Numbers 1. Semiconductor devices 2. Semiconductor body 20 top surface of semiconductor body 21 First region (source region or emitter region) 22 well area 23 Drift Region 24 Second region (drain region or collector region) 25 plug area 31 First electrode (source electrode or emitter electrode) 32 Second electrode (drain electrode or collector electrode) 33 gate electrode 4 Gate insulating layer 5 Current Limit Area 6 Mask Layer 9 Comparative Examples of Semiconductor Devices B Width of the first region d Depth of the current limiting region D Depth of the first region E1 First example of a semiconductor device E2 First example of a semiconductor device E3 First example of a semiconductor device L Length of the current limiting area M Mirror symmetry line R Radiation S.. Method Step T Time in μs J D A / cm 2 current density in the drain region of a unit V DS Voltage between the drain and source electrodes in V V Length range of current limiting area W Width of the insulation current limiting area Zs: Distance between current-limiting regions along the stripe Zt: Distance between current-restricted regions in the transverse direction

Claims

1. A semiconductor device (1) comprising a semiconductor body (2), a gate electrode (33) and a first electrode (31), the semiconductor body (2) comprises a first region (21) which is a source region or an emitter region and a well region (22) located adjacent to the first region (21), the first region (21) being of a first conductivity type and the well region (22) being of a different second conductivity type, - said well region (22) is adjacent to said gate electrode (33) and is separated from said gate electrode (33) by a gate insulating layer (4); - said first region (21) is in electrical contact with said first electrode (31), which may be a source or emitter electrode; - there is at least one current limiting region (5) in said first region (21); - said at least one current limiting region (5) is a sub-region of said first region (21) with reduced electrical conductivity; Semiconductor device (1).

2. When viewed from above the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap the first region (21), and the at least one current limiting region (5) is spaced apart from the gate electrode (33) and the first electrode (31). A semiconductor device (1) according to the preceding claims.

3. When viewed from above the semiconductor body (2), the first region (21) extends completely between the at least one current limiting region (5) and the first electrode (31) and between the at least one current limiting region (5) and the gate electrode (33), and the at least one current limiting region (5) is located between the first electrode (31) and the gate electrode (33). A semiconductor device (1) according to any one of the preceding claims.

4. When viewed in a cross section of the semiconductor body (2) through the first region (21) and the gate electrode (33), the first region (21) extends completely around the at least one current limiting region (5) in a direction towards the well region (22), so that the first region (21) is embedded in the well region (22) and the at least one current limiting region (5) is embedded in the first region (21). A semiconductor device (1) according to any one of the preceding claims.

5. the at least one current limiting region (5) is completely integrated into the first region (21), so that, when viewed in a cross-section of the semiconductor body (2), the first region (21) is located entirely around the at least one current limiting region (5); A semiconductor device (1) according to the preceding claims.

6. the at least one current limiting region (5) completely penetrates the first region (21), so that the at least one current limiting region (5) is at the same depth as the first region (21) or deeper than the first region (21); A semiconductor device (1) according to any one of claims 1 to 3.

7. the volume of said at least one current-limiting region (5) is at least 10% and at most 95% of the total volume of said first region (21); A semiconductor device (1) according to any one of the preceding claims.

8. the conductivity of said at least one current-limiting region (5) is between 5% and 90% of the conductivity of the remainder of said first region (21); the crystal lattice in said at least one current confinement region (5) has at least twice as many defects as the remainder of said first region (21); A semiconductor device (1) according to any one of the preceding claims.

9. the semiconductor body (2) further comprises a drift region (23) of the first conductivity type and also comprises a second region (24) which is a drain or collector region, the drift region is located between the well region (22) and the second region (24); The semiconductor device (1) further comprises a second electrode (32) which is a collector electrode or a drain electrode, the second electrode (32) being located on a side of the second region (24) away from the drift region (23); The semiconductor body (2) is made of SiC, A semiconductor device (1) according to any one of the preceding claims.

10. When viewed from above the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, and the first region (21) extends parallel to the gate electrode (33) and the first electrode (31), or When viewed from above the semiconductor body (2), the gate electrode (33) and the first electrode (31) each comprise a plurality of subsections arranged along at least one arrangement line, and the first region (21) extends between adjacent subsections of the gate electrode (33) and the first electrode (31). A semiconductor device (1) according to any one of the preceding claims.

11. the gate insulating layer (41) and the gate electrode (33) are designed to be applied on a planar section of the upper surface (20) of the semiconductor body (2), and the first region (21) is located on the upper surface (20); A semiconductor device (1) according to any one of the preceding claims.

12. a trench design in which the gate insulating layer (41) and the gate electrode (33) are at least partially disposed in a trench in the semiconductor body (2), the depth of the trench exceeding the depth of the well region (22) and starting from the upper surface (20) of the semiconductor body (2), and the first region (21) is located on the upper surface (20); A semiconductor device (1) according to any one of claims 1 to 10.

13. There is exactly one current limiting region (5) within the first region (21), A semiconductor device (1) according to any one of the preceding claims.

14. a plurality of the current limiting regions (5) are present in the first region (21), and the current limiting regions (5) are spaced apart from one another when viewed from above the semiconductor body (2); A semiconductor device (1) according to any one of claims 1 to 10.

15. A manufacturing method for a semiconductor device (1) according to any one of the preceding claims, said method comprising: - providing said semiconductor body (2); - forming said first region (21) and said well region (22) in said semiconductor body (2); - applying a mask layer (6) to said semiconductor body (2); - irradiating at least one portion of said first region (21) defined by said mask layer (6) with at least one of X-rays, electrons, protons, neutrons or ions, so that said at least one current-limiting region (5) is created in said at least one irradiated portion; - applying said gate insulating layer (41) and said gate electrode (33) and said first electrode (31) to said semiconductor body (2); A manufacturing method comprising:

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