Multiphase buck-boost converter

Abstract

The multi-phase buck-boost converter (101) includes a first half-bridge circuit (107), a second half-bridge circuit (115), a third half-bridge circuit (111), and a control circuit (130). The first half-bridge circuit is coupled to a first inductor terminal (123). The second half-bridge circuit is coupled to a second inductor terminal (127). The third half-bridge circuit is coupled to a third inductor terminal (125), a system voltage terminal (104), and a battery terminal (106). The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in a buck mode to operating in a buck-boost mode based on an off-time of the first half-bridge circuit being less than a specific time.

Description

[Technical Field]

[0001] Rechargeable batteries, such as lithium-ion batteries, are widely used to power portable electronic devices. Examples of portable electronic devices that use rechargeable batteries include smartphones, laptop computers, tablet computers, power tools, etc. Rechargeable batteries require some form of battery charging system. A battery charging system transfers power from a power source, such as an AC wall plug, to the battery. The charging process involves processing and regulating the voltage and current from the power source so that the voltage and current supplied to the battery meet the charging specifications of the particular battery. For example, if the voltage or current supplied to the battery is too high, the battery may be damaged or even explode. On the other hand, if the voltage or current supplied to the battery is too low, the charging process may take an undesirably long time. The battery charging system may include a DC-DC converter to generate the appropriate charging voltage. Summary of the Invention

[0002] In one example, a multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to the third inductor terminal and a system voltage terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in a buck mode to operating in a buck-boost mode based on an off-time of the first half-bridge circuit being less than a specific time.

[0003] In another example, a multi-phase buck-boost converter includes an input voltage terminal, an output voltage terminal, a first inductor terminal, a second inductor terminal, a third inductor terminal, a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to the input voltage terminal and the first inductor terminal. The second half-bridge circuit is coupled to the input voltage terminal and the second inductor terminal. The third half-bridge circuit is coupled to the output voltage terminal and the third inductor terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to operate the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a buck converter based on an on-time of the first half-bridge circuit being shorter than a first specific time. The control circuit is also configured to operate the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a buck-boost converter based on the off-time of the first half-bridge being shorter than a second particular time, and the control circuit is also configured to operate the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit as a boost converter based on the off-time of the first half-bridge circuit being shorter than a third particular time.

[0004] In yet another example, a computer system includes a processor, a battery, and a battery charging circuit. The battery is coupled to the processor and configured to power the processor. The battery charging circuit is coupled to the battery and includes a multi-phase buck-boost converter. The multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to the third inductor terminal, a system voltage terminal, and a battery terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in a buck mode to operating in a buck-boost mode based on the off-time of the first half-bridge circuit being less than a first specific time. The control circuit is also configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operating in the buck-boost mode to operating in the boost mode based on the off-time of the first half-bridge circuit being shorter than a second specified time. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an example multi-phase buck-boost converter applied in a battery charging circuit.

[0006] [Figure 2] 2 is an example state diagram illustrating transitions between operating modes in the multi-phase buck-boost converter of FIG. 1.

[0007] [Figure 3] 2 is an example timing diagram of buck mode operation in the multi-phase buck-boost converter of FIG. 1;

[0008] [Figure 4]2 is a graph of an example buck mode switching cycle for the multi-phase buck-boost converter of FIG. 1.

[0009] [Figure 5] 2 is an example timing diagram of the boost mode operation of the multi-phase buck-boost converter of FIG. 1.

[0010] [Figure 6] 2 is a graph of an example boost mode switching cycle for the multi-phase buck-boost converter of FIG. 1;

[0011] [Figure 7] 2 is an example timing diagram of the buck-boost mode of operation in the multi-phase buck-boost converter of FIG. 1.

[0012] [Figure 8] 2 is a graph of an example buck-boost mode switching cycle in the multi-phase buck-boost converter of FIG. 1;

[0013] [Figure 9] 2 is an example graph of the output voltage and inductor current of the buck-boost converter of FIG. 1 as it transitions from buck mode to buck-boost mode to boost mode.

[0014] [Figure 10] 2 is a block diagram of an exemplary computer system including the battery charging circuit of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0015] In many battery-powered devices, the voltage received to charge the battery can be higher or lower than the battery voltage. To accommodate such a range of charging voltages, a battery charger may include a buck-boost DC-DC converter that steps up or down the charging voltage. To increase output power and reduce circuit volume, some battery charging circuits include a multi-phase DC-DC converter (e.g., a dual-phase DC-DC converter). A multi-phase DC-DC converter includes multiple inductors and reduces the current per inductor compared to a single-phase DC-DC converter. Multi-phase conversion is usually applied in step-down conversion, where higher power is delivered.

[0016] Some dual-phase buck-boost DC-DC converters use eight transistor switches, which increases circuit area, wiring difficulty, and cost. Implementations using six transistor switches do not provide true buck-boost operation and operate properly only when the charging voltage is outside a specified voltage range (dead zone) of the battery voltage (a specified amount greater or less than the battery voltage). The usefulness of such implementations is limited. Also, in six-transistor implementations, the input or output ripple current can increase when operating in boost mode due to the reduced effective inductance caused by paralleling the multiple phase inductors.

[0017] The battery charging circuit described herein includes a multiphase buck-boost DC-DC converter implemented with six transistor switches. The example DC-DC converter operates over a wide input voltage range without dead zones and reduces circuit area and cost compared to an eight-transistor implementation. In buck-boost mode, switching is sequenced to equalize inductor currents between phases. More specifically, when one inductor de-integrates, the other inductor de-integrates, and then boost integration is permitted. When operating in buck-boost mode, the switching duty cycle is adjusted to ensure a smooth transition from buck mode to buck-boost mode and back to boost mode (i.e., to prevent unwanted transitions between modes). Some implementations of the DC-DC converter switch at a higher frequency (e.g., higher than when operating in buck mode) when operating in boost mode to reduce input and output current ripple.

[0018] 1 is a block diagram of an exemplary multi-phase buck-boost converter 101 applied in a battery charging circuit 100. The battery charging circuit 100 includes a battery terminal 106 and a pass transistor 120. The multi-phase buck-boost converter 101 includes an input voltage terminal 102, an output voltage terminal 104, an inductor terminal 123, an inductor terminal 125, an inductor terminal 127, a half-bridge circuit 107, a half-bridge circuit 111, a half-bridge circuit 115, and a controller 122. The controller 122 includes a converter control circuit 130. A switching node 109 of the half-bridge circuit 107 is coupled to the inductor terminal 123 and a first terminal of the inductor 126. A switching node 113 of the half-bridge circuit 111 is coupled to the inductor terminal 125, a second terminal of the inductor 126, and a first terminal of the inductor 128. A switching node 117 of the half-bridge circuit 115 is coupled to the inductor terminal 127 and a second terminal of the inductor 128. Half-bridge circuit 107 includes high-side transistor 108 and low-side transistor 110. Half-bridge circuit 111 includes high-side transistor 112 and low-side transistor 114. Half-bridge circuit 115 includes high-side transistor 116 and low-side transistor 118. High-side transistor 108, low-side transistor 110, high-side transistor 112, low-side transistor 114, high-side transistor 116, low-side transistor 118, and pass transistor 120 may be n-channel field-effect transistors (NFETs). High-side transistor 108, high-side transistor 112, high-side transistor 116, and pass transistor 120 may be p-channel FETs (PFETs) in some examples.

[0019] The drain of high-side transistor 108 is coupled to input voltage terminal 102. The gate of high-side transistor 108 is coupled to converter control circuit 130. The source of high-side transistor 108 is coupled to switching node 109. The drain of low-side transistor 110 is coupled to switching node 109. The gate of low-side transistor 110 is coupled to converter control circuit 130. The source of low-side transistor 110 is coupled to ground terminal. The drain of high-side transistor 116 is coupled to input voltage terminal 102. The gate of high-side transistor 116 is coupled to converter control circuit 130. The source of high-side transistor 116 is coupled to switching node 117. The drain of low-side transistor 118 is coupled to switching node 117. The gate of low-side transistor 118 is coupled to converter control circuit 130. The source of low-side transistor 118 is coupled to ground terminal. The drain of high-side transistor 112 is coupled to output voltage terminal 104. The gate of high-side transistor 112 is coupled to converter control circuit 130. The source of high-side transistor 112 is coupled to switching node 113. The drain of low-side transistor 114 is coupled to switching node 113. The gate of low-side transistor 114 is coupled to converter control circuit 130. The source of low-side transistor 114 is coupled to a ground terminal.

[0020] Converter control circuit 130 controls switching in half-bridge circuit 107, half-bridge circuit 111, and half-bridge circuit 115 to implement buck mode, buck-boost mode, and boost mode operation. When the voltage at input voltage terminal 102 is substantially greater than the voltage at output voltage terminal 104, converter control circuit 130 alternately switches half-bridge circuit 107 and half-bridge circuit 115 180 degrees out of phase to implement buck mode operation. Within the half-bridge circuits, high-side and low-side transistors are switched back and forth. The minimum difference between the voltage at input voltage terminal 102 and the voltage at output voltage terminal 104 to enter buck mode is determined by the maximum duty cycle of the buck converter and the resistive voltage drop of the field-effect transistors (FETs) and inductors, which varies based on the inductor current. An exemplary maximum duty cycle may be approximately 97%. In buck mode, converter control circuit 130 turns off low-side transistor 114 and turns on high-side transistor 112 to connect inductor 126 and inductor 128 to output voltage terminal 104. In buck mode, converter control circuit 130 switches half-bridge circuits 107 and 115 at a frequency (f0) selected to reduce inductor ripple and improve conversion efficiency.

[0021] When the voltage at the input voltage terminal 102 is substantially less than the voltage at the output voltage terminal 104, the converter control circuit 130 switches the half-bridge circuit 111 to implement boost mode operation. The minimum difference between the voltage at the output voltage terminal 104 and the voltage at the input voltage terminal 102 to enter boost mode is determined by the minimum duty cycle of the boost converter. The converter control circuit 130 turns on the high-side transistors 108 and 116 and turns off the low-side transistors 110 and 118 during boost mode operation. When operating in boost mode, the converter control circuit 130 may switch the half-bridge circuit 111 at a frequency higher than f0 to reduce inductor current ripple. For example, in some implementations, the converter control circuit 130 may switch the half-bridge circuit 111 at 2f0. In some examples, the converter control circuit 130 may switch the half-bridge circuit 111 at a lower frequency to improve efficiency.

[0022] When the difference between the voltage at input voltage terminal 102 and the voltage at output voltage terminal 104 is less than the minimum voltage for entering buck mode and the difference between the voltage at output voltage terminal 104 and the voltage at input voltage terminal 102 is less than the minimum voltage for entering boost mode, converter control circuit 130 sequentially switches half-bridge circuit 107, half-bridge circuit 111, and half-bridge circuit 115 to implement buck-boost mode operation. Converter control circuit 130 alternately switches half-bridge circuit 107 and half-bridge circuit 115 to equalize the currents in inductor 126 and inductor 128.

[0023] A battery 124 is coupled to the battery terminal 106. A pass transistor 120 controls the flow of current to the battery 124 for charging and from the battery 124 for powering a load coupled to the output voltage terminal 104. The drain of the pass transistor 120 is coupled to the output voltage terminal 104. The gate of the pass transistor 120 is coupled to a controller 122. The source of the pass transistor 120 is coupled to the battery terminal 106. The controller 122 controls the pass transistor 120 to enable charging of the battery 124.

[0024] 2 is an exemplary state diagram illustrating transitions between operating modes in multi-phase buck-boost DC-DC converter 101. When operating in buck mode, converter control circuit 130 monitors the off-time (the time that low-side transistor 110 or low-side transistor 118 is turned on) of half-bridge circuits 107 and 115. If the off-time of half-bridge circuits 107 and 115 is shorter than a predefined buck-boost transition time, converter control circuit 130 transitions multi-phase buck-boost DC-DC converter 101 from buck mode to buck-boost mode. Otherwise, converter control circuit 130 continues operating multi-phase buck-boost DC-DC converter 101 in buck mode. The predefined buck-boost transition time is set to be greater than the smallest possible pulse of the converter. In a multiphase buck-boost DC-DC converter 101 implementation using silicon FETs, this value can be in the range of tens of nanoseconds, but it can be higher for very high power converters and lower for high frequency, highly integrated converters.

[0025] When operating in buck-boost mode, the converter control circuit 130 monitors the off-times of the half-bridge circuits 107 and 115 (the time the low-side transistor 110 or the low-side transistor 118 is turned on). If the off-times of the half-bridge circuits 107 and 115 are shorter than a predefined boost transition time, the converter control circuit 130 transitions the multi-phase buck-boost DC-DC converter 101 from buck-boost mode to boost mode. The predefined boost transition time may be similar to the predefined buck-boost transition time described above. In buck-boost mode, the converter control circuit 130 monitors the on-times of the half-bridge circuits (the time the low-side transistor 114 is turned on). If the on-time of the half-bridge circuit 111 is shorter than a predefined buck transition time, the converter control circuit 130 transitions the multi-phase buck-boost DC-DC converter 101 from buck-boost mode to buck mode. The predefined buck transition time may be similar to the predefined buck-boost transition time described above. If the off-time of half-bridge circuit 107 and half-bridge circuit 115 is not shorter than the predefined boost transition time and the on-time of half-bridge circuit 111 is not greater than the predefined buck transition time, converter control circuit 130 continues to operate multi-phase buck-boost DC-DC converter 101 in buck-boost mode.

[0026] When operating in boost mode, converter control circuit 130 also monitors the on-time of half-bridge circuit 111 (the time that low-side transistor 114 is turned on). If the on-time of half-bridge circuit 111 is shorter than a predefined time (similar to the predefined buck-boost transition time described above), converter control circuit 130 transitions multi-phase buck-boost DC-DC converter 101 from boost mode to buck-boost mode. Otherwise, converter control circuit 130 continues to operate multi-phase buck-boost DC-DC converter 101 in boost mode.

[0027] 3 is an example timing diagram of buck mode operation in multi-phase buck-boost DC-DC converter 101. The switching cycles of half-bridge circuit 107 and half-bridge circuit 115 are offset by approximately 180° relative to each other, as indicated by inductor current 146 and inductor current 148. Converter control circuit 130 generates complementary high-side drive signal 134 and low-side drive signal 136 to control high-side transistor 108 and low-side transistor 110, respectively. High-side drive signal 134 turns on high-side transistor 108, and low-side drive signal 136 turns off low-side transistor 110, charging inductor 126. Low-side drive signal 136 turns on low-side transistor 110, and high-side drive signal 134 turns off high-side transistor 108, discharging inductor 126. Converter control circuit 130 generates complementary high-side drive signal 144 and low-side drive signal 142 to control high-side transistor 116 and low-side transistor 118, respectively. High-side drive signal 144 turns on high-side transistor 116, and low-side drive signal 142 turns off low-side transistor 118, charging inductor 128. Low-side drive signal 142 turns on low-side transistor 118, and high-side drive signal 144 turns high-side transistor 116 off, discharging inductor 128. Converter control circuit 130 generates high-side drive signal 140 and low-side drive signal 138 to control high-side transistor 112 and low-side transistor 114. In buck mode, high-side drive signal 140 turns on high-side transistor 112, and low-side drive signal 138 turns low-side transistor 114 off.

[0028] 4 is a graph of an example buck mode switching cycle. The duration of a switching cycle is shown as Ts. Ton indicates the time when high-side transistor 108 is on and low-side transistor 110 is off, or when high-side transistor 116 is on and low-side transistor 118 is off. Toff indicates the time when low-side transistor 110 is on and high-side transistor 108 is off, or when low-side transistor 118 is on and high-side transistor 116 is off. In buck mode, the transfer function of multi-phase buck-boost DC-DC converter 101 can be expressed as follows: V OUT / V IN =T ON / T S where: V OUT is the voltage at the output voltage terminal 104, and V IN is the voltage at the input voltage terminal 102, and T S and T ON is as shown in Figure 4.

[0029] 5 is an example timing diagram of boost mode operation in multi-phase buck-boost DC-DC converter 101. In boost mode, high-side drive signal 134 turns on high-side transistor 108, high-side drive signal 144 turns on high-side transistor 116, low-side drive signal 136 turns off low-side transistor 110, and low-side drive signal 142 turns off low-side transistor 118. Converter control circuit 130 switches half-bridge circuit 111 to increase the voltage at output voltage terminal 104. Low-side drive signal 138 turns on low-side transistor 114, and high-side drive signal 140 turns off high-side transistor 112, charging inductors 126 and 128. High-side drive signal 140 turns on high-side transistor 112, and low-side drive signal 138 turns off low-side transistor 114, discharging inductors 126 and 128. The switching frequency of low-side drive signal 138 and high-side drive signal 140 may be higher (e.g., twice as high) than the switching frequency of high-side drive signal 134, low-side drive signal 136, low-side drive signal 142, or high-side drive signal 144 in buck mode to compensate for the reduced inductance due to parallel inductors 126 and 128.

[0030] 6 is a graph of an example boost mode switching cycle. The duration of a switching cycle is represented as Ts. Ton indicates the time that low-side transistor 114 is on and high-side transistor 112 is off. Toff indicates the time that high-side transistor 112 is on and low-side transistor 114 is off.

[0031] 7 is an example timing diagram of buck-boost mode operation in multi-phase buck-boost DC-DC converter 101. In buck-boost mode, converter control circuit 130 sequences the switching of half-bridge circuit 107, half-bridge circuit 115, and half-bridge circuit 111. A buck-boost switching cycle begins with the performance of a boost integration cycle. During the boost integration cycle, low-side drive signal 138 turns on low-side transistor 114, high-side drive signal 140 turns off high-side transistor 112, high-side drive signal 134 turns on high-side transistor 108, low-side drive signal 136 turns off low-side transistor 110, high-side drive signal 144 turns on high-side transistor 116, and low-side drive signal 142 turns off low-side transistor 118. The boost integration cycle charges inductors 126 and 128. During a first time interval after the boost cycle, a first buck de-integration cycle is performed in half-bridge circuit 107 or half-bridge circuit 115. For example, during the first buck de-integration cycle, high-side transistor 108 is turned off, low-side transistor 110 is turned on, high-side transistor 116 is turned on, and low-side transistor 118 is turned off. During a second time interval after the first buck de-integration cycle, a second buck de-integration cycle is performed in one of half-bridge circuits 107 and 115 that did not perform the first de-integration cycle. For example, during the second buck de-integration cycle, low-side transistor 118 is turned on, high-side transistor 116 is turned off, high-side transistor 108 is turned on, and low-side transistor 110 is turned off. In this way, inductors 126 and 128 are charged simultaneously during the boost cycle and discharged sequentially during the buck de-integration cycle. In two adjacent buck-boost cycles, the de-integration cycles alternate: in the first buck-boost cycle, half-bridge circuit 107 performs a buck de-integration cycle before half-bridge circuit 115 performs a de-integration cycle; in the second buck-boost cycle (immediately after the first buck-boost cycle), half-bridge circuit 115 performs a buck de-integration cycle before half-bridge circuit 107 performs a de-integration cycle.The alternating operation averages the current between half-bridge circuit 107 and half-bridge circuit 115. The timing of the de-integration is set by a modulator in converter control circuit 130, which adjusts the timing to regulate the output current and voltage. If the current or voltage is too high, the de-integration time is increased. This can be achieved with a pulse width modulator (PWM) ramp, a control signal, and a comparator.

[0032] 8 is a graph of an example buck-boost mode switching cycle in a multi-phase buck-boost DC-DC converter 101. The first buck-boost switching cycle is represented as Ts_bb_1 and the second (subsequent) buck-boost switching cycle is represented as Ts_bb_2. Ton indicates the time (portion of the buck-boost mode switching cycle) that the boost integration cycle is active. Toff (Toffa and Toffb) indicates the time that the buck de-integration is active.

[0033] The buck-boost transfer function is expressed as follows: TIFF2025533022000002.tif3462

[0034] At the operating mode transition point, a given control signal produces the same output voltage in buck, boost, and buck-boost modes. Converter control circuit 130 achieves this by increasing the slope of the PWM ramp generated in converter control circuit 130 in buck-boost mode. Increasing the slope of the ramp increases both the Ton and Toff times in buck-boost mode. The Ton and Toff signals are generated by two ramps and combined with the control signal and a comparator. When the ramp is above the control signal, the Ton and Toff signals are high. As the slope of the PWM ramp is increased, the width of both the Ton and Toff signals increases. Because the buck-boost cycle includes a boost cycle, the cycle time in buck-boost mode may differ from the cycle time in buck mode. The ramp slope in buck-boost mode is adjusted to account for this difference.

[0035] In FIG. 8, current 802 represents the current flowing in inductor 126, and current 804 represents the current flowing in inductor 128 in a sequential buck-boost cycle. During interval Ton, at the beginning of Ts_bb_1 and Ts_bb_2, a boost integration cycle is performed to charge inductors 126 and 128. During interval COM1a, high-side transistor 108 is turned on and low-side transistor 110 is turned off. Similarly, during interval COM2a, high-side transistor 116 is turned on and low-side transistor 118 is turned off. COM1a and COM2a correspond to buck integration and boost de-integration. During interval Toffa, high-side transistor 108 is turned on and low-side transistor 110 is turned off to perform a buck de-integration cycle for inductor 126. During interval COM1b, after the buck de-integration cycle, high-side transistor 108 is turned on and low-side transistor 110 is turned off. Similarly, during interval Toffb, low-side transistor 118 is turned on and high-side transistor 116 is turned off to implement a buck de-integration cycle for inductor 128. By implementing Toff at different times (applying different time offsets relative to each other), converter control circuit 130 maintains dual-phase reduction of ripple current in buck-boost mode. During interval COM2b, after the buck de-integration cycle, high-side transistor 116 is turned on and low-side transistor 118 is turned off. COM1b and COM2b correspond to buck integration and boost de-integration.

[0036] At Ts_bb_1, COM1a is longer than COM2a. At Ts_bb_2, COM2a is longer than COM1a. For example, at Ts_bb_2, COM1a may be the same length as COM2a at Ts_bb_1, and COM2a may be the same length as COM1a at Ts_bb_1. By alternating the lengths of COM1 and COM2 in successive switching cycles, converter control circuit 130 ensures that the average currents in inductor 126 and inductor 128 are equal. The duty cycle of each phase may be adjusted to compensate for mismatches in propagation delays or inductor parameters to ensure uniform currents.

[0037] Figure 9 is an example graph of the output voltage and inductor current as the multi-phase buck-boost DC-DC converter 101 transitions from buck mode to buck-boost mode to boost mode. The inductor current 146, the inductor current 148, and the output voltage 150 are shown in Figure 9. Figure 9 shows that the multi-phase buck-boost DC-DC converter 101 provides seamless transitions between buck, buck-boost, and boost modes as the output voltage 150 increases, and there is no imbalance between the inductor currents 146 and 148 as the waveform currents change.

[0038] 10 is a block diagram of an example computer system 1000 including a battery charging circuit 100. The computer system 1000 includes a battery 124 and a processor 1002 coupled to the battery charging circuit 100. The processor 1002 may be a general-purpose microprocessor, a graphics processor, or a network processor, or other instruction execution device. Implementations of the computer system 1000 may include various additional components (e.g., memory, timing circuitry, communication circuitry, etc.) coupled to the processor 1002 and the battery charging circuit 100. The battery charging circuit 100 generates a voltage for charging the battery 124 and powering the processor 1002. The battery charging circuit 100 operates over a wide range of input voltages and provides seamless transitions between buck, buck-boost, and boost modes as described herein.

[0039] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with the explanation of this description. For example, if device A generates a signal that controls controlling device B to perform a certain action, (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C, such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0040] Also, in this description, the phrase "based on" means "based at least in part on." Thus, if X is based on Y, X can be a function of Y and any number of other factors.

[0041] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, or through the configuration and / or layout of hardware components, device interconnections, or a combination thereof.

[0042] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise specified, these terms are used generally to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0043] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0044] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no modification to the remaining circuit elements. For example, field-effect transistors (FETs) (such as n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in conjunction with one or more of the devices described herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0045] As used herein, a reference to a FET being "ON" means that the FET's conduction channel is present and drain current can flow through the FET. A reference to a FET being "OFF" means that the conduction channel is not present and drain current does not flow through the FET. However, an "OFF" FET may have current flowing through the transistor's body diode.

[0046] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available prior to the replacement of the component. Unless otherwise noted, a component depicted as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor described herein as a single component may instead be multiple resistors or capacitors, each of which may be multiple resistors coupled in parallel between the same nodes. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in parallel between the same nodes, as a single resistor or capacitor. For example, a resistor or capacitor illustrated and described herein as a single component may instead be multiple resistors or capacitors, each of which may be coupled in series between the same two nodes, as a single resistor or capacitor.

[0047] While some elements of the illustrated examples are included in an integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features shown as being external to the integrated circuit may be included in the integrated circuit, and / or some features shown as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) incorporated within / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0048] Use of the term "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. In this description, unless otherwise stated, "about," "approximately," or "substantially" in front of a value means within + / - 10 percent of the stated parameter.

[0049] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A device, A first half-bridge circuit coupled to the first inductor terminal and the input terminal, A second half-bridge circuit coupled to the second inductor terminal and the input terminal, A third half-bridge circuit is coupled to the third inductor terminal and the output terminal, A control circuit coupled to the earlier half-bridge circuit 1, the earlier half-bridge circuit 2, and the earlier half-bridge circuit 3, In the first section, the first inductor terminal and the second inductor terminal are connected to the input terminals of the first half-bridge circuit and the second half-bridge circuit, respectively, and the third inductor terminal of the third half-bridge circuit is connected to the ground terminal. In the second section, the first inductor terminal of the first half-bridge circuit is connected to the ground terminal, and the third inductor terminal of the third half-bridge circuit is connected to the output terminal. The control circuit is configured as follows, A device including a device.

2. The apparatus according to claim 1, The first and second sections are part of the first switching cycle, The control circuit, In the first section of the second switching cycle, the first inductor terminal and the second inductor terminal of the first half-bridge circuit and the second half-bridge circuit are connected to the input terminal, respectively, and the third inductor terminal of the third half-bridge circuit is connected to the ground terminal. In the second section of the second switching cycle, the second inductor terminal of the second half-bridge circuit is connected to the ground terminal, and the third inductor terminal of the third half-bridge circuit is connected to the output terminal. A device further configured in this way.

3. The apparatus according to claim 2, The control circuit is further configured to operate the first, second, and third half-bridge circuits in a step-down mode, a step-up mode, and a step-up / step-down mode, An apparatus in which the first, second, and third half-bridge circuits operate in the buck-boost mode during the first and second switching cycles.

4. The apparatus according to claim 1, The control circuit, The first, second, and third half-bridge circuits are operated in buck mode, boost mode, and buck-boost mode, Based on the fact that the off time of the first half-bridge circuit is shorter than a first predetermined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are transitioned from operation in the buck-down mode to operation in the buck-boost mode. Based on the fact that the off time of the first half-bridge circuit is shorter than a second predetermined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are transitioned from operation in the boost-down mode to operation in the boost mode. A device further configured in this way.

5. The apparatus according to claim 4, The apparatus further comprises a control circuit that transitions the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in the boost-down mode to operation in the buck-down mode based on the fact that the on-time of the first half-bridge circuit is shorter than a third predetermined time.

6. The apparatus according to claim 4, The apparatus further comprises a control circuit that transitions the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in the boost mode to operation in the buck-boost mode based on the fact that the on-time of the first half-bridge circuit is shorter than a third predetermined time.

7. The apparatus according to claim 4, The first half-bridge circuit includes a first high-side transistor and a first low-side transistor, the second half-bridge circuit includes a second high-side transistor and a second low-side transistor, and the third half-bridge circuit includes a third high-side transistor and a third low-side transistor. In the step-down mode, the control circuit The third high-side transistor is turned on through the switching cycle, The third low-side transistor is turned off through the aforementioned switching cycle. The first high-side transistor and the first low-side transistor are switched to each other. The second high-side transistor and the second low-side transistor are switched to each other. The switching in the second half-bridge circuit is offset by 90 degrees from the switching in the first half-bridge circuit. A device further configured in this way.

8. The apparatus according to claim 7, In the boost mode, the control circuit The first high-side transistor and the second high-side transistor are turned on through the aforementioned switching cycle. Through the aforementioned switching cycle, the first low-side transistor and the second low-side transistor are turned off. The third high-side transistor and the third low-side transistor are switched to each other. A device further configured in this way.

9. The apparatus according to claim 8, The apparatus further comprises a control circuit configured such that, in the boost mode, it switches the third high-side transistor and the third low-side transistor at a higher frequency than that at which the first high-side transistor and the first low-side transistor are switched in the buck mode.

10. The apparatus according to claim 7, In the step-up / step-down mode, the control circuit In the first interval of the switching cycle, The first high-side transistor, the second high-side transistor, and the third low-side transistor are turned on. The first low-side transistor, the second low-side transistor, and the third high-side transistor are turned off. In the second interval of the switching cycle, Turn on the first high-side transistor, the second low-side transistor, and the third high-side transistor. The second high-side transistor, the first low-side transistor, and the third low-side transistor are turned off. In the third interval of the switching cycle, The second high-side transistor, the first low-side transistor, and the third high-side transistor are turned on. The first high-side transistor, the second low-side transistor, and the third low-side transistor are turned off. A device further configured in this way.

11. A multiphase step-up / step-down converter, A first half-bridge circuit coupled between the input voltage terminal and the first inductor terminal, A second half-bridge circuit coupled between the input voltage terminal and the second inductor terminal, A third half-bridge circuit is coupled between the output voltage terminal and the third inductor terminal, A control circuit coupled to the earlier half-bridge circuit 1, the earlier half-bridge circuit 2, and the earlier half-bridge circuit 3, Based on the fact that the on-time of the first half-bridge circuit is shorter than a first predetermined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated in step-down mode. Based on the fact that the off time of the first half-bridge circuit is shorter than a second predetermined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated in boost-buck mode. Based on the fact that the off time of the first half-bridge circuit is shorter than a third predetermined time, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated in boost mode. The control circuit is configured as follows, A multiphase step-up / step-down converter, including...

12. A multiphase step-up / step-down converter according to claim 11, A multiphase buck-boost converter, further configured such that the control circuit transitions the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from the boost mode to the buck-boost mode based on the fact that the on-time of the first half-bridge circuit is shorter than a fourth predetermined time.

13. A multiphase step-up / step-down converter according to claim 11, In the step-down mode, the control circuit The third inductor terminal is connected to the output voltage terminal via the third half-bridge circuit. The above-mentioned half-bridge circuit 1 and the above-mentioned half-bridge circuit 2 are switched alternately. A multiphase step-up / step-down converter, further configured as follows.

14. A multiphase step-up / step-down converter according to claim 13, In the boost mode, the control circuit The input voltage terminal is connected to the first inductor terminal via the first half-bridge circuit. The input voltage terminal is connected to the second inductor terminal via the second half-bridge circuit. Switching the third half-bridge circuit described above, A multiphase step-up / step-down converter, further configured as follows.

15. A multiphase step-up / step-down converter according to claim 14, A multiphase buck-boost converter in which the switching frequency of the third half-bridge circuit in the boost mode is greater than the switching frequency of the first half-bridge circuit in the buck mode.

16. A multiphase step-up / step-down converter according to claim 11, In the step-up / step-down mode, the control circuit In the first part of the switching cycle, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform a boost integration cycle. In the second part of the switching cycle, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform the first buck unintegration cycle. In the third portion of the switching cycle, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform a second buck uncoupling cycle. A multiphase step-up / step-down converter, further configured as follows.

17. A multiphase step-up / step-down converter according to claim 16, The second buck unintegration cycle is performed after the first buck unintegration cycle. In the first switching cycle, the first time offsets the first buck unintegration cycle from the second buck unintegration cycle. A multiphase buck-boost converter in which, in a second switching cycle, a second time different from the first time offsets the first buck-down uncoupling cycle from the second buck-down uncoupling cycle.

18. It is a system, A first inductor coupled between the first inductor terminal and the third inductor terminal, A second inductor coupled between the second inductor terminal and the third inductor terminal, The battery is connected to the battery terminals, A battery charging circuit having an input terminal and an output terminal connected to the battery, comprising a power converter, wherein the power converter A first half-bridge circuit coupled to the first inductor terminal and the input terminal, A second half-bridge circuit coupled to the second inductor terminal and the input terminal, A third half-bridge circuit coupled to the third inductor terminal and the output terminal, A switch coupled between the output terminal and the battery terminal, A control circuit coupled to the earlier half-bridge circuit 1, the earlier half-bridge circuit 2, the earlier half-bridge circuit 3, and the switch, In the first section, the first inductor terminal and the second inductor terminal are connected to the input terminals of the first half-bridge circuit and the second half-bridge circuit, respectively, and the third inductor terminal of the third half-bridge circuit is connected to the ground terminal. In the second section, the first inductor terminal of the first half-bridge circuit is connected to the ground terminal, and the third inductor terminal of the third half-bridge circuit is connected to the output terminal. The battery charging circuit is configured as follows: The load connected to the output terminal, A system that includes this.

19. The system according to claim 18, The first and second sections are part of the first switching cycle, The control circuit, In the first section of the second switching cycle, the first inductor terminal and the second inductor terminal of the first half-bridge circuit and the second half-bridge circuit are connected to the input terminal, respectively, and the third inductor terminal of the third half-bridge circuit is connected to the ground terminal. In the second section of the second switching cycle, the second inductor terminal of the second half-bridge circuit is connected to the ground terminal, and the third inductor terminal of the third half-bridge circuit is connected to the output terminal. A system further configured in this way.

20. The system according to claim 19, The control circuit operates the first, second, and third half-bridge circuits in a step-down mode, a step-up mode, and a step-up / step-down mode. A system in which the first, second, and third half-bridge circuits operate in the buck-boost mode during the first and second switching cycles.

21. The system according to claim 18, The control circuit, The first, second, and third half-bridge circuits are operated in buck mode, boost mode, and buck-boost mode, Based on the fact that the off time of the first half-bridge circuit is shorter than a first predetermined time, the first, second, and third half-bridge circuits are transitioned from operation in the buck-down mode to operation in the buck-boost mode. Based on the fact that the off time of the first half-bridge circuit is shorter than a second predetermined time, the first, second, and third half-bridge circuits are transitioned from operation in the boost-down mode to operation in the boost mode. A system further configured in this way.

22. The system according to claim 18, The aforementioned load is a system including a processor.

23. The system according to claim 21, A system further configured such that the control circuit transitions the first, second, and third half-bridge circuits from operation in the boost-buck mode to operation in the buck mode based on the fact that the on-time of the first half-bridge circuit is shorter than a third predetermined time.

24. The system according to claim 21, The control circuit is further configured to transition the first, second, and third half-bridge circuits from operation in the boost mode to operation in the buck-boost mode based on the fact that the on-time of the first half-bridge circuit is shorter than a third predetermined time.

25. The system according to claim 21, A system in which the switching frequency of the third half-bridge circuit in the boost mode is greater than the switching frequency of the first half-bridge circuit in the buck mode.

26. The system according to claim 21, In the step-up / step-down mode, the control circuit In the first part of the switching cycle, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform a boost integration cycle. In the second part of the switching cycle, the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit are operated to perform a buck unintegration cycle. A system further configured in this way.

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