N-polarity HEMT structure with N+ contact layer

Abstract

An exemplary semiconductor device includes a III-nitride material structure, a III-nitride back barrier layer, a III-nitride channel layer on the N-face of the III-nitride back barrier layer, and an N-polar HEMT structure and a method for forming the HEMT structure. + The semiconductor device includes a gate region between the source region and the drain region, and an n-type III nitride etch stop layer in the source region. + Source contact on top of III-nitride etch stop layer and n in drain region + a drain contact on the III-nitride etch stop layer, a 2DEG in the III-nitride channel layer adjacent to the interface between the III-nitride channel layer and the III-nitride back barrier layer, and a n-type electrode between the source region and the drain region; + It includes a channel recess etched down to a III-nitride etch stop layer, a gate recess in the channel layer, and a gate contact within the gate recess.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 416,738, filed October 17, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Technical Field The present disclosure relates to semiconductor devices, and in particular to N + This paper deals with N-polar HEMT structures with contact layers.

[0003] background III-nitride semiconductor devices, such as III-nitride (III-N) high electron mobility transistors (HEMTs), are typically formed from III-nitride material structures grown in a III-polar orientation (i.e., a

[0001] orientation) on a substrate, with a III-nitride barrier layer formed on the III-nitride channel layer. In nitrogen-polar (N-polar) III-nitride HEMT devices (i.e., devices in which the III-nitride layers are oriented in a

[0001] orientation on the substrate), the III-nitride channel layer (i.e., the layer containing the 2DEG channel) is formed on the III-nitride barrier layer (hence, in N-polar III-nitride HEMTs, the barrier layer is often referred to as the "back barrier").

[0004] in-situ + N-polar HEMT structures with in-situ n +The layer is etched down to the UIDGaN channel, and the gate is placed on this etched surface. In some other examples, the channel recess is etched, and then a second recess etch is used that stops on the "gate recess" AlGaN etch stop layer. The gate recess AlGaN etch stop layer allows for precise control of the gate electrode to channel distance, but creates an electronic barrier in the contact region of the device, which is essential for in-situ n + The effect of providing a GaN contact layer is reduced.

[0005] overview This document describes the recess gate and n + An N-polar HEMT structure is described with source and drain contact layers, where a cross section taken parallel to the gate width has a gate electrode that lies on a flat surface, i.e., the gate electrode lies on a flat surface when viewed in the direction along the gate width. An exemplary semiconductor device includes a III-nitride material structure, including a III-nitride back barrier layer, a III-nitride channel layer on the N-face of the III-nitride back barrier layer, and an n-type semiconductor layer on the N-face of the III-nitride channel layer. + The semiconductor device includes a gate region between the source region and the drain region, and an n-type III nitride etch stop layer in the source region. + Source contact on top of III-nitride etch stop layer and n in drain region + a drain contact on the III-nitride etch stop layer, a 2DEG in the III-nitride channel layer adjacent to the interface between the III-nitride channel layer and the III-nitride back barrier layer, and a n-type electrode between the source region and the drain region; + It includes a channel recess etched down to a III-nitride etch stop layer, a gate recess in the channel layer, and a gate contact within the gate recess. [Brief explanation of the drawings]

[0006] [Figure 1A]FIG. 1 illustrates an exemplary semiconductor device 100 that is an N-polar HEMT with a gate electrode on a substantially flat surface when viewed along the gate width. [Figure 1B] FIG. 1 illustrates an exemplary semiconductor device 100 that is an N-polar HEMT with a gate electrode on a substantially flat surface when viewed along the gate width. [Figure 1C] FIG. 1 illustrates an exemplary semiconductor device 100 that is an N-polar HEMT with a gate electrode on a substantially flat surface when viewed along the gate width. [Figure 1D] FIG. 1 illustrates an exemplary semiconductor device 100 that is an N-polar HEMT with a gate electrode on a substantially flat surface when viewed along the gate width. [Figure 1E] FIG. 1 illustrates an exemplary semiconductor device 100 that is an N-polar HEMT with a gate electrode on a substantially flat surface when viewed along the gate width.

[0007] [Figure 2] 1 is a cross-sectional view of an exemplary epitaxial structure.

[0008] [Figure 3A] FIG. 1 shows the initial epitaxial structure. [Figure 3B] FIG. 1 shows the initial epitaxial structure. [Figure 3C] FIG. 1 shows the initial epitaxial structure. [Figure 3D] FIG. 1 shows the initial epitaxial structure. [Figure 3E] FIG. 1 shows the initial epitaxial structure.

[0009] [Figure 4A] FIG. 10 illustrates the formation of an etching mask to remove the n+ contact layer in areas outside the source and drain contact regions. [Figure 4B]FIG. 10 illustrates the formation of an etching mask to remove the n+ contact layer in areas outside the source and drain contact regions. [Figure 4C] FIG. 10 illustrates the formation of an etching mask to remove the n+ contact layer in areas outside the source and drain contact regions. [Figure 4D] FIG. 10 illustrates the formation of an etching mask to remove the n+ contact layer in areas outside the source and drain contact regions. [Figure 4E] FIG. 10 illustrates the formation of an etching mask to remove the n+ contact layer in areas outside the source and drain contact regions.

[0010] [Figure 5A] FIG. 10 illustrates etching of the n+ contact layer, stopping at the channel layer, and removal of the etching mask. [Figure 5B] FIG. 10 illustrates etching of the n+ contact layer, stopping at the channel layer, and removal of the etching mask. [Figure 5C] FIG. 10 illustrates etching of the n+ contact layer, stopping at the channel layer, and removal of the etching mask. [Figure 5D] FIG. 10 illustrates etching of the n+ contact layer, stopping at the channel layer, and removal of the etching mask. [Figure 5E] FIG. 10 illustrates etching of the n+ contact layer, stopping at the channel layer, and removal of the etching mask.

[0011] [Figure 6A] FIG. 1 illustrates masking of active areas for isolation process. [Figure 6B] FIG. 1 illustrates masking of active areas for isolation process. [Figure 6C] FIG. 1 illustrates masking of active areas for isolation process. [Figure 6D] FIG. 1 illustrates masking of active areas for isolation process. [Figure 6E] FIG. 1 illustrates masking of active areas for isolation process.

[0012] [Figure 7A] FIG. 10 shows ion implantation into non-active regions to remove the 2DEG and isolate the device. [Figure 7B] FIG. 10 shows ion implantation into non-active regions to remove the 2DEG and isolate the device. [Figure 7C] FIG. 10 shows ion implantation into non-active regions to remove the 2DEG and isolate the device. [Figure 7D] FIG. 10 shows ion implantation into non-active regions to remove the 2DEG and isolate the device. [Figure 7E] FIG. 10 shows ion implantation into non-active regions to remove the 2DEG and isolate the device.

[0013] [Figure 8A] 10A-10C illustrate the formation of a mask to define a gate recess. [Figure 8B] 10A-10C illustrate the formation of a mask to define a gate recess. [Figure 8C] 10A-10C illustrate the formation of a mask to define a gate recess. [Figure 8D] 10A-10C illustrate the formation of a mask to define a gate recess. [Figure 8E] 10A-10C illustrate the formation of a mask to define a gate recess.

[0014] [Figure 9A] FIG. 10 illustrates etching of a gate recess. [Figure 9B] FIG. 10 illustrates etching of a gate recess. [Figure 9C] FIG. 10 illustrates etching of a gate recess. [Figure 9D] FIG. 10 illustrates etching of a gate recess. [Figure 9E] FIG. 10 illustrates etching of a gate recess.

[0015] [Figure 10A] FIG. 1 illustrates gate metal deposition and removal of the etch mask from the gate recess. [Figure 10B] FIG. 1 illustrates gate metal deposition and removal of the etch mask from the gate recess. [Figure 10C] FIG. 1 illustrates gate metal deposition and removal of the etch mask from the gate recess. [Figure 10D] FIG. 1 illustrates gate metal deposition and removal of the etch mask from the gate recess. [Figure 10E] FIG. 1 illustrates gate metal deposition and removal of the etch mask from the gate recess.

[0016] [Figure 11A] FIG. 10 illustrates the deposition of source and drain contact metal across several cut lines. [Figure 11B] FIG. 10 illustrates the deposition of source and drain contact metal across several cut lines. [Figure 11C] FIG. 10 illustrates the deposition of source and drain contact metal across several cut lines.

[0017] [Figure 12A] FIG. 1 illustrates the deposition of interconnect metal. [Figure 12B] FIG. 1 illustrates the deposition of interconnect metal. [Figure 12C] FIG. 1 illustrates the deposition of interconnect metal. [Figure 12D] FIG. 1 illustrates the deposition of interconnect metal. [Figure 12E] FIG. 1 illustrates the deposition of interconnect metal.

[0018] [Figure 13A] FIG. 1 shows the initial epitaxial structure. [Figure 13B] FIG. 1 shows the initial epitaxial structure. [Figure 13C] FIG. 1 shows the initial epitaxial structure. [Figure 13D] FIG. 1 shows the initial epitaxial structure. [Figure 13E] FIG. 1 shows the initial epitaxial structure.

[0019] [Figure 14A] FIG. 10 illustrates the formation of a regrowth mask that protects the area near the active area of ​​the FET, except over the source and drain contact areas. [Figure 14B] FIG. 10 illustrates the formation of a regrowth mask that protects the area near the active area of ​​the FET, except over the source and drain contact areas. [Figure 14C] FIG. 10 illustrates the formation of a regrowth mask that protects the area near the active area of ​​the FET, except over the source and drain contact areas. [Figure 14D] FIG. 10 illustrates the formation of a regrowth mask that protects the area near the active area of ​​the FET, except over the source and drain contact areas. [Figure 14E] FIG. 10 illustrates the formation of a regrowth mask that protects the area near the active area of ​​the FET, except over the source and drain contact areas.

[0020] [Figure 15A] FIG. 10 illustrates the regrowth of an n+ GaN contact layer and the removal of the regrowth mask. [Figure 15B] FIG. 10 illustrates the regrowth of an n+ GaN contact layer and the removal of the regrowth mask. [Figure 15C] FIG. 10 illustrates the regrowth of an n+ GaN contact layer and the removal of the regrowth mask. [Figure 15D] FIG. 10 illustrates the regrowth of an n+ GaN contact layer and the removal of the regrowth mask. [Figure 15E] FIG. 10 illustrates the regrowth of an n+ GaN contact layer and the removal of the regrowth mask.

[0021] [Figure 16] FIG. 1 shows an epitaxial structure including an n+ layer as an etch stop.

[0022] [Figure 17A] FIG. 1 illustrates the process flow by showing the device structure at various stages of the process. [Figure 17B] FIG. 1 illustrates the process flow by showing the device structure at various stages of the process. [Figure 17C] FIG. 1 illustrates the process flow by showing the device structure at various stages of the process. [Figure 17D] FIG. 1 illustrates the process flow by showing the device structure at various stages of the process. [Figure 17E] FIG. 1 illustrates the process flow by showing the device structure at various stages of the process.

[0023] [Figure 18] FIG. 1 illustrates an epitaxial structure that can be used to fabricate a semiconductor device using such a stop layer.

[0024] [Figure 19] FIG. 10 shows a structure with additional doping below the AlGaN barrier.

[0025] [Figure 20] FIG. 1 illustrates a structure with a UID spacer layer.

[0026] [Figure 21] FIG. 10 illustrates AlGaN etch stop options using band diagrams.

[0027] [Figure 22]FIG. 1 shows a device structure with a thin n+ layer in the access region.

[0028] [Figure 23A] FIG. 17 shows an alternative device fabricated from the structure shown in FIG. 16. [Figure 23B] FIG. 17 shows an alternative device fabricated from the structure shown in FIG. 16. [Figure 23C] FIG. 17 shows an alternative device fabricated from the structure shown in FIG. 16. [Figure 23D] FIG. 17 shows an alternative device fabricated from the structure shown in FIG. 16. [Figure 23E] FIG. 17 shows an alternative device fabricated from the structure shown in FIG. 16.

[0029] [Figure 24A] FIG. 20 shows a device fabricated from the structure shown in FIG. 19. [Figure 24B] FIG. 20 shows a device fabricated from the structure shown in FIG. 19. [Figure 24C] FIG. 20 shows a device fabricated from the structure shown in FIG. 19. [Figure 24D] FIG. 20 shows a device fabricated from the structure shown in FIG. 19. [Figure 24E] FIG. 20 shows a device fabricated from the structure shown in FIG. 19.

[0030] [Figure 25A] FIG. 21 shows a device fabricated from the structure shown in FIG. 20. [Figure 25B] FIG. 21 shows a device fabricated from the structure shown in FIG. 20. [Figure 25C] FIG. 21 shows a device fabricated from the structure shown in FIG. 20. [Figure 25D] FIG. 21 shows a device fabricated from the structure shown in FIG. 20. [Figure 25E] FIG. 21 shows a device fabricated from the structure shown in FIG. 20.

[0031] Detailed Description This document describes an N-polarity HEMT structure comprising a recess gate and contact layers for the source and drain of n + In this case, in a cross-section parallel to the gate width, the gate electrode is located on a flat surface, i.e., when viewed in the direction along the gate width, the gate electrode is on a flat surface. As used herein, the terms "Group-III nitride" or "III-N material", "III-N layer", "III-N device", etc. mean a material or device made of a compound semiconductor material according to the chemical formula Sc v B w Al x In y Ga z N a (D) b where v + w + x + y + z is about 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, a + b is about 1, 0.9 < a ≦ 1, 0 ≦ b < 0.1, and (D) is any Group-V element other than nitrogen.

[0032] In the formation of an N-polarity Group-III nitride HEMT, it can be useful to dispose an n + contact layer (generally n + GaN) under the source and drain contacts. However, this gives rise to several complications in device manufacturing. Specifically, it may be necessary to electrically isolate all devices from the remainder of the wafer. This is generally achieved by removing the surrounding material (or at least the portion containing the device channel) by etching or by ion implanting the surrounding material to insulate it. Generally, the n + contact layer can be an n-type Group-III nitride layer having a donor concentration, for example, of at least 10 18 cm -3 on the N surface of the Group-III nitride channel layer. [[ID=三十六]]

[0033] n +Devices with a contact layer typically have the layer formed over the entire wafer (it is epitaxially grown along with the rest of the active semiconductor layers) and then patterned in the active areas of the device to remove it everywhere except the source and drain regions. + If a layer is present, the ion implantation will not sufficiently isolate this region.

[0034] Thus, the next step is to calculate n in the inactive region. + The material is removed by etching, and then either (a) etching continues down to the channel layer, or (b) ion implantation is performed on the remaining material in the non-active areas. + Because the layer is etched away, a step exists between the active and non-active areas. For the device to function properly, the subsequently deposited gate electrode must span the full width of the active area and over this step into the non-active area. However, it has been shown that allowing the gate to pass over this step creates a failure mode for the device. Therefore, n + It would be useful to have a device in which the gate, including the contact layer, is on a surface that is coplanar in both the active and non-active areas (ie, there are no such steps).

[0035] 1A-1E show an exemplary semiconductor device 100 that is an N-polar HEMT having a gate electrode on a substantially planar surface when viewed in the direction along the gate width.

[0036] 1A is a plan view of a device 100. The device 100 includes a source ohmic metal 102, a drain ohmic metal 104, an interconnect metal 106, and a gate metal 108. The device 100 includes an isolation region 110 formed, for example, by ion implantation. The device 100 includes an active channel 112 and an n-channel 114. + The GaN contact layer 114 is included.

[0037] Various cut lines are drawn representing different views of the device structure. Cut line A-A' represents a cross section of the device showing the device in the direction of current flow. Figure 1B shows the structure of device 100 along cut line A-A'. The remaining cut lines are drawn in a direction perpendicular to the current flow in the device. Figure 1B shows an optional gate dielectric material (dielectric) 116 underlying some or all of the gate metal 108.

[0038] Cut line B-B' is drawn through the center of the gate electrode at the bottom of the gate recess etch. FIG. 1C shows the structure of device 100 along cut line B-B'. Cut line C-C' is drawn through the center of the access region on the drain side of device 100. FIG. 1D shows the structure of device 100 along cut line C-C'. Cut line D-D' is drawn through the center of the n + The drain contact region is depicted showing the contact layer and ohmic metal. Figure 1E shows the structure of device 100 along cut line DD'.

[0039] 1A , which shows device 100 along cut line B-B′, the bottom (base) of gate 108 lies on a substantially flat surface. The surface is “substantially” flat in that the bottom of gate 108 lies on a flat surface, which may not be perfectly flat due to normal manufacturing imperfections. Gate 108 does not cross etched sidewalls, which can be useful, for example, to avoid non-uniformities under gate 108 that could become leakage points and cause failures. Gate 108 extends beyond the active channel into isolation region 110 without a step.

[0040] 2 is a cross-sectional view of an exemplary epitaxial structure that can be used to obtain the device 100 shown in FIGS. 1A-1E. The epitaxial structure is formed by in-situ +This document describes two exemplary methods for obtaining the device 100 shown in Figures 1A-1E.

[0041] A first exemplary process flow for manufacturing is + Starting with the epitaxial structure of FIG. 2, the following steps can be performed:

[0042] 1. Perform channel recess etching to remove the n-type layer between the source and drain. + In addition to removing the contact layer, an equal amount of material is also removed in the areas to be isolated, leaving only the source and drain contact areas of the device. + Leave.

[0043] 2. From the area to be separated + The GaN is removed and the inactive channel is isolated by ion implantation.

[0044] 3. A gate recess etch is then performed, etching both the implanted region and the active channel simultaneously.

[0045] 4. Deposition of gate metal and source and drain metal completes the device fabrication.

[0046] This process takes advantage of the fact that implanted GaN etches at the same rate as unimplanted GaN. Depending on the context, this may not always be the case. When the etch rates are different, a step occurs. This can be addressed by reversing the order of steps 2 and 3 above, etching the gate recess first, then isolating the structure with implantation after the etch is complete.

[0047] Figures 3A-12E show the device at various stages of the fabrication process, with the same cut lines as in Figures 1A-1E being used to illustrate the device structure.

[0048] 3A-3E show the initial epitaxial structure. 4A-4E show the n-type epitaxial structure in the region outside the source and drain contact regions. + 5A-5E show the formation of an etching mask to remove the contact layer. + 1 shows etching the contact layer, stopping at the channel layer, and removing the etching mask.

[0049] Figures 6A-6E show masking the active area for the isolation process, Figures 7A-7E show ion implantation into the non-active area to remove the 2DEG and isolate the devices, and Figures 8A-8E show forming a mask to define the gate recess.

[0050] Figures 9A-9E show the etching of the gate recess. Figures 10A-10E show the deposition of gate metal and removal of the etch mask from the gate recess. Optionally, gate dielectric material can be deposited. Figure 11 shows the deposition of source and drain contact metal across several cut lines.

[0051] 12A-12E show the deposition of interconnect metal. The resulting device is + It has a planar split-gate structure for a recessed-gate N-polar HEMT with a contact layer.

[0052] Another exemplary method for fabricating device 100 of FIGS. 1A-1E includes: + This involves regrowth of the contact layer. Because the regrowth is done on a wafer with most of the surface masked, the growth rate may not be as well controlled as in some conventional systems. However, by using selective area growth, the regrowth is limited to only the areas around the active area that need to be under the source and drain contacts. + The same structure can be obtained by regrowing GaN. In summary, the fabrication method includes:

[0053] 1. Define a regrowth hard mask (e.g., SiO2) that masks both the active channel and the area around the periphery of the FET, so that regrowth near the FET occurs only in places that do not need to be removed later in the process. In some instances, for example, to form a resistor as part of a circuit, or simply to fill in an area to allow selective area growth, n + Some areas of may be included in other areas of the wafer.

[0054] 2. Etch any GaN and AlGaN cap layers to expose the channel layer. The GaN and AlGaN cap layers are optional layers and if not present, this etching step does not need to be performed.

[0055] 3. Regrow n+ GaN.

[0056] 4. Isolate the FETs by implantation.

[0057] 5. Perform gate recess.

[0058] 6. Deposit gate and source / drain ohmic metal to complete the FET.

[0059] In some instances, it may be useful to swap steps 4 and 5 if the gate recess etch process has different etch rates for implanted and non-implanted layers.

[0060] Figures 13A-13E show the device structure at various stages in the fabrication process: Figures 13A-13E show the initial epitaxial structure.

[0061] 14A-14E show the formation of a regrowth mask that protects areas near the active area of ​​the FET (except over the source and drain contact areas). There may also be additional areas (not shown) away from the FET where the mask is not in place (i.e., where regrowth will occur). This may be done, for example, to increase the fill factor of the regrowth process.

[0062] 15A to 15E show n + The regrowth of the GaN contact layer and removal of the regrowth mask are shown. The remaining steps are shown in Figures 6A-12E and described above in connection with Figures 6A-12E.

[0063] The use of an in-situ n+ contact layer eliminates the need for an epitaxial regrowth step from the manufacturing process. However, challenges can arise in device fabrication due to the need for precise etching of the channel and gate recess. Two exemplary approaches to using an etch stop layer in the channel recess are described below.

[0064] Figure 16 shows the n + The epitaxial structure includes a layer containing a large number of free electrons. + The layer can pin the Fermi level to the conduction band edge, thereby minimizing the concentration of free holes required for etching to proceed. + layer ("contact layer"), + Using an etchant capable of etching GaN (such as a plasma etch), it is first etched away, stopping within the UID spacer layer. + The contact layer can have any suitable thickness (e.g., 2 to 200 nm, or 5 to 100 nm), and the UID spacer layer can have any suitable thickness (e.g., 1 to 50 nm, or 5 to 15 nm).

[0065] These etches often involve trade-offs between etch rate, surface roughness, etch profile (trenching, footing), aspect ratio effects, and uniformity, which can make it difficult to obtain a desired etch profile across the wafer. These effects tend to become more pronounced in some cases as the thickness of the layer that needs to be etched increases. + By including a subsequent selective etch that stops on the GaN etch stop layer, the surface morphology can be restored to a smooth surface with an epitaxially defined distance to the 2DEG. + Because the etch stop layer can be thin, it can be removed without significantly disturbing the surface morphology. Once the channel recess is complete, the gate recess can be performed. + The etching stop layer can have any suitable thickness (for example, 0.5 to 10 nm, or 2 to 5 nm).

[0066] 17A-17E illustrate the process flow by showing the device structure at various stages of the process. In the example shown in FIGS. 17A-17E, n + Since only the UID layer and the SiO 2 layer are used, no electron barrier is introduced. In some examples, the channel recess process includes:

[0067] 1. Perform a non-selective etch (e.g., plasma etch) to remove n + Etch the contact layer, stopping somewhere on the UID spacer layer.

[0068] 2. Etch the remaining UID spacer to remove the n + A selective etch (eg, a wet etch) is performed that stops on the spacer layer.

[0069] 3. Using either selective or non-selective etching, + Etch until the etch stop.

[0070] 4. Proceed to etching the gate recess.

[0071] Non-selective etching can suffer from trenching or footing, where the etch rate near the edge of the mask is increased or decreased compared to areas away from the edge of the mask.

[0072] Figure 17A shows the creation of a mask. Figure 17B shows the use of non-selective etching. Figure 17C shows the execution of selective etching. Figure 17D shows the + The etching is shown to be performed until the etch stop. Figure 17E shows the gate recess etch.

[0073] In some instances, the devices described herein may use an AlGaN etch stop layer (e.g., an AlGaN etch stop layer or another suitable type of layer). Typically, the etch stop layer may be an Al-containing III-nitride layer. In some cases, AlGaN etch stop layers have common drawbacks in contact structures due to the resulting electron barrier caused by polarization and bandgap differences with GaN.

[0074] In some examples, the device can include an AlGaN etch stop layer at the bottom of the n+ contact layer. For example, Figure 18 shows an epitaxial structure that can be used to fabricate a semiconductor device using such a stop layer. Figure 19 shows a structure in which doping is added below the AlGaN barrier. Figure 20 shows an example of a structure that can be used to obtain selectivity (e.g., etching UIDs but not n+ contacts). + Figure 21 shows a structure with a UID spacer layer that can be used for a wet etch that does not etch GaN. Figure 21 illustrates AlGaN etch stop options using band diagrams. Figure 21 shows three curves 2102 (Figure 18), 2104 (Figure 2), and 2106 (Figure 19).

[0075] n +2 nm of Al at the bottom of the contact layer 0.15 Ga 0.85 The addition of an N etch stop layer creates a large barrier of 0.49 eV due to the N polar orientation, which depletes electrons from below the AlGaN barrier (Figure 21, curve 2102). + This can be reduced to half (0.28 eV) by adding doping (Fig. 19, Fig. 21, curve 2106). This structure uses AlGaN as an etch stop layer first, and then the AlGaN layer and the underlying n-type GaN layer are etched during the channel recess etching. + Furthermore, in some instances, multiple techniques may be combined to achieve the desired selectivity. + The layer may exhibit a reduced etch rate due to the presence of a high free electron density and a low free hole density. Therefore, a UID spacer can be introduced on top of the AlGaN to provide etch selectivity in the two-step etch described above, as shown in Figure 20.

[0076] Figure 22 shows the thin n + 16 shows a device structure with layers that can be fabricated from the structure shown in FIG.

[0077] Figures 23A-23E show alternative devices fabricated from the structure shown in Figure 16. Figures 24A-24E show devices fabricated from the structure shown in Figure 19. Figures 25A-25E show devices fabricated from the structure shown in Figure 20.

[0078] Various devices and their material structures have been described above. However, it should be understood that they are presented by way of example only, and not by way of limitation. While embodiments have been particularly shown and described, it should be understood that various changes in form and detail may be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A semiconductor device comprising:

1. A Group III nitride material structure comprising: a III-nitride back barrier layer; a III-nitride channel layer on an N-face of the III-nitride back barrier layer and having a bandgap smaller than that of the III-nitride back barrier layer; an n-type Group III nitride layer on an N-face of the Group III nitride channel layer, wherein the n-type Group III nitride layer has a donor concentration of at least 10 １８ cm －３ a III-nitride material structure, a non-active region surrounding an active region, the active region including a gate region between a source region and a drain region, the active region including the III-nitride back barrier layer, the III-nitride channel layer, the n-type III-nitride layer, a source contact on the n-type III-nitride layer in the source region, a drain contact on the n-type III-nitride layer in the drain region, and a 2DEG in the III-nitride channel layer adjacent to an interface between the III-nitride channel layer and the III-nitride back barrier layer; the semiconductor device further includes a gate recess in the channel layer and a gate contact in the gate recess, the gate recess being formed across a width of the active region and having a portion formed in a non-active region, the gate contact being formed in the portion of the gate recess across the width of the active region and within the non-active region, the gate recess having a bottom surface, the bottom surface of the gate recess in the active region and the bottom surface of the gate recess in the non-active region being substantially coplanar.

2. 10. The semiconductor device of claim 1, wherein the n-type III-nitride layer is in the source and drain regions of the active area, but not in the gate region of the active area.

3. The semiconductor device of claim 1 , wherein the non-active region includes the III-nitride back barrier layer and the III-nitride channel layer, but does not include the n-type III-nitride layer.

4. The semiconductor device of claim 1 , wherein in the non-active area, the III-nitride channel layer and the III-nitride back barrier layer are implanted with ions.

5. The semiconductor device of claim 1 , wherein the 2DEG is not within the non-active region.

6. A semiconductor device comprising:

1. A Group III nitride material structure comprising: a III-nitride back barrier layer; a III-nitride channel layer on an N-face of the III-nitride back barrier layer and having a bandgap smaller than that of the III-nitride back barrier layer; n on the N face of the group III nitride channel layer ＋ a III-nitride material structure including a III-nitride etch stop layer; a gate region between the source and drain regions; The n ＋ a source contact on the III-nitride etch stop layer; The n ＋ a drain contact on the III-nitride etch stop layer; a 2DEG of the III-nitride channel layer adjacent to an interface between the III-nitride channel layer and the III-nitride back barrier layer; The n region between the source region and the drain region ＋ a channel recess etched down to the III-nitride etch stop layer; a gate recess in the channel layer and a gate contact in the gate recess.

7. The n ＋ 7. The semiconductor device of claim 6, wherein the III-nitride etch stop layer is 2 to 5 nm thick.

8. The n ＋ 7. The semiconductor device of claim 6, wherein the III-nitride etch stop layer is 0.5 to 10 nm thick.

9. The n ＋ The semiconductor device of claim 6 , further comprising a UID spacer layer over the III-nitride etch stop layer.

10. 10. The semiconductor device of claim 9, wherein the UID spacer layer is 5 to 15 nm thick.

11. 10. The semiconductor device of claim 9, wherein the UID spacer layer is 0.5 to 50 nm thick.

12. n on the UID spacer layer ＋ The semiconductor device of claim 9 comprising a III-nitride contact layer.

13. The n ＋ 13. The semiconductor device of claim 12, wherein the III-nitride contact layer is at least 2 nm thick.

14. The n ＋ The semiconductor device of claim 12, wherein the III-nitride contact layer is 5 to 100 nm thick.

15. a non-active region surrounding an active region, the active region including the gate region, the III-nitride back barrier layer, the III-nitride channel layer, the n ＋ 7. The semiconductor device of claim 6, comprising a III-nitride etch stop layer, the source contact, the drain contact, and the 2DEG.

16. The n ＋ The semiconductor device of claim 6 , wherein the III-nitride etch stop layer extends into one or more access areas of the semiconductor device.

17. 7. The semiconductor device of claim 6, wherein the gate recess has a bottom surface that spans the active area and the non-active area, and the bottom surface of the gate recess in the active area and the bottom surface of the gate recess in the non-active area are substantially coplanar.

18. A semiconductor device comprising:

1. A Group III nitride material structure comprising: a III-nitride back barrier layer; a III-nitride channel layer on an N-face of the III-nitride back barrier layer and having a bandgap smaller than that of the III-nitride back barrier layer; a III-nitride material structure including an Al-containing III-nitride etch stop layer on an N-face of the III-nitride channel layer; a gate region between the source and drain regions; a source contact on the Al-containing III-nitride etch stop layer in the source region; a drain contact on the Al-containing III-nitride etch stop layer in the drain region; a 2DEG of the III-nitride channel layer adjacent to an interface between the III-nitride channel layer and the III-nitride back barrier layer; a channel recess etched to the Al-containing III-nitride etch stop layer between the source region and the drain region; a gate recess in the channel layer and a gate contact in the gate recess.

19. Under the AlGaN etching stop layer ＋ 20. The semiconductor device of claim 18, comprising a layer of doping.

20. 19. The semiconductor device of claim 18, wherein the Al-containing III-nitride etch stop layer is 2 to 5 nm thick.

21. 19. The semiconductor device of claim 18, wherein the Al-containing III-nitride etch stop layer is 0.5 to 10 nm thick.

22. 20. The semiconductor device of claim 18, wherein the Al-containing III-nitride etch stop layer is comprised of AlGaN, AlInN, AlGaInN, or AlScN, or any combination thereof.

23. 20. The semiconductor device of claim 18, further comprising a UID spacer layer on the Al-containing III-nitride etch stop layer.

24. The semiconductor device of claim 23, wherein the UID spacer layer is between 5 and 15 nm thick.

25. 24. The semiconductor device of claim 23, wherein the UID spacer layer is at least 1 nm thick.

26. n on the UID spacer layer ＋ 24. The semiconductor device of claim 23, comprising a III-nitride contact layer.

27. The n ＋ 19. The semiconductor device of claim 18, wherein the III-nitride contact layer is 5 to 100 nm thick.

28. The n ＋ 20. The semiconductor device of claim 18, wherein the III-nitride contact layer is at least 2 nm thick.

29. a non-active region surrounding an active region, the active region including the gate region, the III-nitride back barrier layer, the III-nitride channel layer, the n ＋ 20. The semiconductor device of claim 18, comprising a III-nitride etch stop layer, the source contact, the drain contact, and the 2DEG.

30. 28. The semiconductor device of claim 27, wherein the gate recess has a bottom surface, and the bottom surface of the gate recess in the active area and the bottom surface of the gate recess in the non-active area are substantially coplanar.

31. 10. A method for forming the semiconductor device of claim 1, comprising: Perform channel recess etching; performing ion implantation into the III-nitride channel layer and the III-nitride back barrier layer in the non-active region; performing a gate recess etch by simultaneously etching both the implanted region and the active region; depositing a gate metal, a source metal and a drain metal.

32. 10. A method for forming the semiconductor device of claim 1, comprising: Perform channel recess etching; After performing the channel recess etching, a gate recess etching is performed; After performing the gate recess etching, performing ion implantation into the III-nitride channel layer and the III-nitride back barrier layer in the non-active region; depositing a gate metal, a source metal and a drain metal.

33. 10. A method for forming the semiconductor device of claim 1, comprising: regrowing the n-type III-nitride layer after performing the channel recess etch.

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