Apparatus for operating a hardware-based artificial neural network and method for its use and training - Patent Application 20070122997

Abstract

An apparatus for operating a hardware-based artificial neural network comprises a hardware-based artificial neural network having a plurality of electrically interconnected network nodes, each network node comprising an electronic component, the hardware-based artificial neural network having a particularly invariant hardware structure, the apparatus comprising an interfering device for coupling an interfering signal into one area of ​​the hardware-based artificial neural network, and a coupling device, the coupling device being arranged between the interfering device and the hardware-based artificial neural network and designed to transmit the interfering signal from the interfering device throughout the one area, and / or the apparatus comprising switching elements that can be individually actuated by control signals for dimming and / or switching on and off the supply voltage to the electronic components.

Description

[Technical Field]

[0001] The present invention relates to an apparatus for operating a hardware-based artificial neural network, its use, and a method for training the same. [Background technology]

[0002] Artificial intelligence can be used to detect patterns in technological applications such as image recognition or machine parameter monitoring. Artificial neural networks, which mimic the function of biological neurons, can provide artificial intelligence. These artificial neural networks can be trained with training data using evolution-based methods, where training adjusts the artificial neural networks, thereby improving their ability to perform their tasks. Individual elements of the artificial neural network are reassociated during each training iteration.

[0003] In principle, such systems can be implemented as hardware-based systems, i.e., systems in which hardware physically forms a network, or as software-based systems, particularly as virtual networks simulated or emulated on hardware portions, such as RAM memory and / or processors. In hardware-based systems, configurable electronic elements are linked together to form an artificial neural network. The number of linked elements can be reduced by tens without causing a loss in the system's performance. Furthermore, hardware-based artificial neural networks may have elements that are not connected to other parts of the network, i.e., unconnected and unused elements that cannot be reduced without degrading or losing the performance of the hardware-based artificial neural network.

[0004] To mitigate this effect, for example, Cramer, B., Stoeckel, D., Kreft, M., Wibral, M., Schemmel, J., Meier, K., Priesemann, V., “Control of criticality and computation in spiking neuromorphic networks with plasticity”, Nature Communications, 11(1)(2020) 2853, it is known to increase the signal-to-noise ratio between linked elements as much as possible, thereby increasing the number of subcomponents to thousands and the number of evolutionarily linkable connections to tens of thousands.

[0005] Compared to software-based artificial neural networks, hardware-based artificial neural networks currently have a much more limited number of elements and connections, are less trainable, and are less complex and flexible.

[0006] Known artificial neural networks are specialized for individual tasks after their training. Furthermore, software-based artificial neural networks in particular can be externally manipulated because they are formed from program code and / or the hardware they simulate or emulate is usually connected to the Internet. Therefore, the output data of an artificial neural network can be read by unauthorized persons.

[0007] Therefore, there is a need for broadly applicable, autonomous, secured, and universally applicable artificial neural networks. Summary of the Invention [Problem to be solved by the invention]

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved hardware-based artificial neural network that eliminates the aforementioned drawbacks. [Means for solving the problem]

[0009] This object is achieved by the features of the independent claims. Advantageous refinements are the subject matter of the dependent claims and the following description.

[0010] According to a first aspect, the invention relates to an apparatus for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network having a plurality of electrically interconnected network nodes, each network node comprising at least one electronic component, the hardware-based artificial neural network having, according to the invention, in particular an immutable hardware structure, the apparatus comprising at least one interfering device for injecting at least one interfering signal into at least one region of the hardware-based artificial neural network, and at least one coupling device, the coupling device being arranged between the interfering device and the hardware-based artificial neural network and designed to transmit the at least one interfering signal from the interfering device throughout the at least one region, and / or the apparatus comprising at least one switching element that can be individually actuated by at least one control signal for dimming and / or switching on / off the supply voltage to the at least one electronic component.

[0011] Hardware-based artificial neural networks are understood to include both biologically based neural networks, in which nodes typically have similar characteristics (weights, transfer functions, etc.) and are arranged in layers, and electronic circuits, in contrast to biologically based neural networks, in which the nodes of the network have different digital and / or analog circuit elements or components. These may also not be in the form of layers as in biologically based networks, but instead be stochastically connected as electronic circuits, whereby some circuit elements, for example, can use terminals provided as outputs as inputs and vice versa. From the perspective of current electronics, this results in "dumb" overall circuits that can acquire their "intelligence" through training. Therefore, hardware-based artificial neural networks can be referred to as trainable electronic networks. Circuit elements can also form the nodes of the corresponding network. Hardware-based artificial neural networks can also be referred to as physical neural networks.

[0012] In software-based artificial neural networks, the output of each node in a layer of the network is determined sequentially, whereas in hardware-based artificial neural networks, the node output is obtained simultaneously for all nodes in a layer. This means that in software-based artificial neural networks, the number of nodes affects the time required to calculate the output of the artificial neural network. However, in hardware-based artificial neural networks, the number of nodes in a layer makes no difference to the time it takes to determine the output. The time it takes to determine the output data is determined solely by the number of layers.

[0013] Electronic components are understood to mean both components that are manufactured and / or usable separately, and components that are manufactured and used simultaneously with other components, such as, for example, in the exposure of silicon wafers as part of the manufacture of semiconductor chips.

[0014] The present invention provides an apparatus for operating a hardware-based artificial neural network, in which an interfering signal is injected into at least one region of the hardware-based artificial neural network. The interfering signal is injected into the entire region, i.e., the interfering signal is present in the entire region, or the region corresponds to the region of the hardware-based artificial neural network covered by the interfering signal. The at least one region can be smaller than the entire hardware-based artificial neural network. The apparatus further includes an interfering device capable of injecting the interfering signal into the hardware-based artificial neural network. To inject the interfering signal, a coupling device is provided between the interfering device and the hardware-based artificial neural network. In one example, the coupling device may simply comprise an air-filled space between the interfering device and the hardware-based artificial neural network. The interfering signal emitted by the interfering device passes through the coupling device and is injected into the at least one region. Injecting the interfering signal increases noise in the at least one region, thereby reducing the signal-to-noise ratio during signal transmission between elements, e.g., nodes, of the hardware-based artificial neural network. Therefore, contrary to all efforts in electronic circuit implementation, instead of increasing the signal-to-noise ratio in at least one region of the hardware-based artificial neural network, a spatial and / or temporal and / or partial reduction of the signal-to-noise ratio is counterintuitively implemented. This reduction is limited to at least one region where the interference signal is injected, i.e., it is limited to some electronic components of the hardware-based artificial neural network circuit. The signal-to-noise ratio (S / N) is defined as S / N = 10 * log (effective power / noise) (expressed in decibels (dB)) or S / N = 20 * log (effective signal voltage / noise signal voltage). An easily transmittable signal has an S / N ratio greater than 15 dB, while an S / N ratio less than 10 dB is considered noisy. If the effective signal power is equal to the noise signal power, the signal becomes indistinguishable at the receiver.Alternatively or additionally, the device may include at least one switching element capable of dimming and / or switching on / off the supply voltage for electronic components, particularly for multiple nodes or portions of nodes of the hardware-based artificial neural network. The at least one switching element may be located in at least one region and may be switched by an interference signal, which may be referred to as a control signal. Thus, the switching element may be controlled via the interference signal formed as a control signal. If multiple switching elements are present, each switching element may be individually controlled by a control signal. Thus, the electronic assembly may be dimmed or switched on / off by the supply voltage. Each switching element may operate a separate electronic module. The control signals for the switching elements may form a control signal pattern across the surface of the hardware-based artificial neural network. The hardware-based artificial neural network may be trained by adjusting the control signal pattern. Therefore, using the present invention, the hardware-based artificial neural network may be trained by changing the interference signal and / or the control signal. It is not necessary to change the connections between the nodes of the hardware-based artificial neural network or the nodes themselves. Therefore, the hardware-based artificial neural network may have an unchanging hardware structure. An immutable hardware structure is understood to mean, for example, that the hardware structure has no means for physically separating the tracks between the network nodes or for changing the way the network nodes function. In this example, changes in the operating mode of the network nodes or changes in the electrical connections between the network nodes of the hardware structure can only be performed by control signals of interference signals and control voltages. The interference signals or control signals are used to change the links between the nodes or even the function of the nodes.The modification of the interference and control signals is therefore an alternative to adjusting or modifying the links between nodes of the artificial hardware-based neural network. This eliminates the need to provide a hardware-based network with modifiable links. The modification can be generated by varying the interference signal or by changing the supply voltage of individual electronic components, and the training of the artificial hardware-based neural network then shifts to modifying the control signal or signals. This provides a highly flexible hardware-based network that can be trained to perform a variety of tasks. The individual control or interference signals of the electronic components can be determined for each task. Thus, the task of the hardware-based artificial neural network can be set by introducing corresponding control or interference signals to the electronic components. This allows a single hardware-based artificial neural network to perform a wide range of tasks, such as first recognizing images and then recognizing audio data. This provides a widely applicable, autonomous, protected, and universally applicable artificial neural network.

[0015] According to one example, the hardware-based artificial neural network in at least one region may have at least one component designed to reduce the signal-to-noise ratio upon receiving at least one interference signal, wherein the interference device preferably generates an optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization interference signal, and / or the switching element preferably is designed to receive an optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization control signal.

[0016] The signal-to-noise ratio can be reduced by increasing the noise within the component. To this end, the component can be designed to be sensitive to interfering signals. For example, if an optical interfering signal is used, the noise within the component can increase during the transmission of the electrical signal within the component. The component can be located, for example, within the electrical connection between two network nodes or within one network node. Switching elements can also be controlled by control signals. The control signals can control the switching elements to dim and / or switch on / off the supply voltage.

[0017] By way of further example, the interference device may have a plurality of individually actuatable interference elements for injecting interference signals into the hardware-based artificial neural network, the interference elements preferably injecting interference signals into different regions of the hardware-based artificial neural network.

[0018] Thus, multiple regions of the hardware-based artificial neural network may be affected by an interfering signal, and these regions preferably cover the entire hardware-based artificial neural network. Because the interfering elements can be controlled independently of each other, each region of the hardware-based artificial neural network may be individually subject to its own interfering signal. These regions may overlap and / or be separated from each other.

[0019] Furthermore, a plurality of interference elements can be arranged to be distributed throughout the layer, for example, preferably in the form of an array, and the coupling device comprises a medium having a plurality of coupling elements for transmitting at least one interference signal to at least one region, the coupling elements being distributed within the layer in the same manner as the interference elements.

[0020] Thus, interference elements can be used to generate interference signal patterns, which are then transmitted to the hardware-based artificial neural network via a coupling device involving coupling elements. Because the distribution of interference elements within a layer is known, specific regions of the hardware-based artificial neural network can be targeted with interference signals. In particular, the distribution of interference elements within a layer can be designed so that the interference elements are arranged similarly to the components of the neural network, allowing specific interference signals to be injected into individual components.

[0021] Furthermore, at least some of the plurality of interference elements may be designed as resistive heaters, Peltier elements, light emitting diodes, electromagnetic emitters and / or transmitters, and / or piezoelectric components.

[0022] In a further example, at least one region can have a range that corresponds to the range of the hardware-based artificial neural network, or is designed to be smaller than the range of the hardware-based artificial neural network.

[0023] If at least one region has the same extent as the hardware-based artificial neural network, the interference or combining device can be uniformly shaped to apply the interference signal uniformly to the entire hardware-based artificial neural network. Finer structuring allows the interference signal to be injected only into different regions within a component, such as the signal input or signal output of a circuit element of the hardware-based artificial neural network. For example, if the extent of at least one region is equal to the extent of the components of the hardware-based artificial neural network, with each component assigned a region, then a separate interference signal can be injected into each component of the neural network.

[0024] Thus, the multiple combining elements can have the same structure as the multiple interference elements. Furthermore, the structure of the combining elements can correspond to the structure of the hardware-based artificial neural network. However, this does not exclude the possibility that the structure of the combining elements can be finer or coarser than the structure of the interference elements or the hardware-based artificial neural network.

[0025] According to another example, the apparatus may comprise at least one semiconductor chip comprising a hardware-based artificial neural network, preferably formed in an integrated circuit, more preferably a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0026] A neural network can be designed as a circuit on a semiconductor chip, and the nodes of the neural network can be formed as components of the circuit. In an example where elements of a neural network are designed as components of a field programmable gate array, the field programmable gate array can be configured so that the circuit structure of the elements of the field programmable gate array forms the neural network. In principle, a hardware-based artificial neural network also implemented on a field programmable gate array can be further trained. In contrast, a hardware-based artificial neural network can be hardwired on an application-specific integrated circuit and optimized in advance in other ways. However, in the present invention, training of a hardware-based artificial neural network is not required per se. This means, for example, that an integrated circuit capable of injecting interference signals and / or varying the supply voltages of individual parts of the circuit can train an artificial hardware-based neural network by modifying the interference or control signals. Even when a field programmable array is used, the array can be trained by modifying the input control or interference signals without the need to reprogram the array.

[0027] The apparatus may also include a shielding device for shielding external interference signals of the same type as the at least one interference signal, and the shielding device may surround the hardware-based artificial neural network, the combining device, and the interference device.

[0028] The shielding device may be designed, for example, as a housing that forms the outer shell of the device. Thus, the interference device, the coupling device, and the hardware-based artificial neural network are enclosed by the shielding device. The shielding device can shield external interference signals that can change the signal-to-noise ratio in an uncontrollable and unrepeatable manner. Thus, the interference signals of the interference device almost exclusively cause changes in the signal-to-noise ratio in the area of ​​the neural network.

[0029] According to further examples, it is conceivable that the apparatus further comprises at least one memory for storing at least one interference signal and / or at least one control signal used by the at least one interference device, at least one control unit for controlling the at least one interference device and / or at least one switching element, and / or at least one output unit for outputting in particular a further processed output signal of the hardware-based artificial neural network.

[0030] The memory can be used to store interference signals or control signals during and after training. For example, during the training process, all interference signals or control signals of electronic components used during training can be stored in the memory to avoid repeated training runs with the same parameters. After training, optimized control signals or control signals of electronic components can also be stored in the memory. If multiple electronic components are present, corresponding control signals or interference signals of each electronic component can be stored in the memory. Multiple control signals or interference signals can be referred to as signal patterns or signal pattern pairs. The signal patterns or signal pattern pairs can be read from the memory as needed. The memory can be designed to store multiple different signal patterns or signal pattern pairs. Each signal pattern or signal pattern pair may be trained for a separate task. For example, the type of task for each signal pattern or signal pattern pair can also be stored in the memory. For example, one signal pattern or signal pattern pair may be trained to determine the category of an image element, while another signal pattern or signal pattern pair may be trained to recognize an audio pattern.

[0031] It is also conceivable, for example, to design the interference device as a control device which provides at least one control signal to at least one switching element.

[0032] The control device can then read, for example, the control signals currently to be used from the memory and use them thereafter. For this purpose, the control device can, for example, receive a value that determines the task to be performed by the network. Based on this value, the corresponding control signal can be read from the memory, or the control signal that the control device needs to send to the switching element or elements so that the artificial hardware-based neural network can perform the task must have been read from the memory.

[0033] According to one example, the above-mentioned multiple devices may be combined in a multiple device configuration according to the preceding description, wherein the hardware-based artificial neural networks of each device are electrically connected in series and / or parallel with each other, the interference device of at least one first device of the multiple devices and a second device of the multiple devices is preferably designed as a common interference device, and the output layer of the hardware-based artificial neural network of a third device of the multiple devices is preferably also designed to control the interference device of a fourth device of the multiple devices.

[0034] The advantages, effects and improvements of the arrangement result from those of the device described above, and in this respect reference is therefore made to the foregoing description to avoid repetition.

[0035] The configuration comprises at least two devices according to the preceding description. In this configuration, the output layer of the hardware-based artificial neural network of a first device is electrically connected to, among other things, the input of an interfering device of a second device or multiple other devices. The first device can then control or influence the function of the interfering device of the second device. In this way, each device can be coupled to the interfering device of the other devices in the configuration via the electrical connection of its neural network.

[0036] According to a further example, there may be provided a system comprising a plurality of configurations according to the foregoing description, wherein a first configuration of the plurality of configurations is designed to control at least one interference device in a second configuration of the plurality of configurations.

[0037] The advantages, effects and improvements of the system result from those of the devices and arrangements described above, and in this respect reference is therefore made to the foregoing description to avoid repetition.

[0038] The first configuration may form, for example, a base layer, and the device emits an output signal, which is processed as an input signal by the device of the second configuration, for example after further processing. In this case, at least one interference device of the device of the second configuration may be coupled to the output layer of at least one device of the first configuration. This may be referred to as forward coupling. Furthermore, it is also conceivable that at least one interference device of the device of the first configuration may be coupled to the output layer of at least one device of the second configuration. This may be referred to as backward coupling.

[0039] Additionally, multiple systems can be considered subsystems and combined into a composite system, where the subsystems are coupled together in the manner described above. In this way, more complex systems with improved performance can be formed. For example, such a complex system may process different types of signals (optical and acoustic), with one subsystem processing optical signals and another processing acoustic signals.

[0040] In a second aspect, the present invention relates to a method for training an artificial neural network in an apparatus according to the preceding description, the method comprising at least the following steps: defining target output data during processing of supplied training data; supplying the training data to the hardware-based artificial neural network and injecting at least one interfering signal into at least one region of the hardware-based artificial neural network by means of at least one interfering device; obtaining output data from the hardware-based artificial neural network; determining whether there is at least one deviation between the output data and the target output data, said deviation being outside a predetermined tolerance range; terminating the method if the deviation is within the tolerance range; modifying the hardware-based artificial neural network, preferably modifying at least one interfering signal, if the deviation is outside the predetermined tolerance range; or modifying the at least one interfering signal and / or modifying at least one control signal; and repeating the above steps, in particular terminating the method and modifying the at least one interfering signal and / or modifying the at least one control signal.

[0041] The advantages, effects and improvements of the method result from those of the device described above, and in this respect reference is therefore made to the foregoing description to avoid repetition.

[0042] In a first alternative, the method is used to train a hardware-based artificial neural network in a state perturbed by an interfering device. Thus, the neural network is trained by interfering with signal transmissions in at least one region where an interfering signal is injected. In addition to changes made to the hardware-based artificial neural network, changes are also made to the at least one injected interfering signal during each training run. To this end, at least one parameter of the at least one interfering signal can be changed, such as intensity, frequency, duration, etc. Changing the at least one parameter also changes the at least one interfering signal. Thus, the method can be used to integrate an interfering device into the training of the neural network. Thus, the method can provide a trained hardware-based artificial neural network that performs better than a neural network without the interfering signal injected.

[0043] In a second alternative, training provides interference signals or control signals that allow an unchanged hardware-based artificial neural network to solve the task imposed by the training. Training is performed solely by changing at least one interference signal and / or at least one control signal until the physically unchanged hardware-based artificial neural network successfully completes training. Changes in physical connections, such as physical disconnections or reconnections between network nodes or physical changes to the network nodes themselves, are not intended, nor are they intended to be eliminated. Therefore, in this alternative, it is only necessary to find one interference signal and / or one control signal, or one pattern of interference signals and / or control signals, that allows the hardware-based artificial neural network to successfully complete training. To solve the task trained in the training process after training, it is only necessary to apply the interference signal and / or control signal, or the pattern of interference signals and / or control signals, to the hardware-based artificial neural network. Therefore, different tasks can be performed with a single hardware-based artificial neural network by correspondingly performing different training processes that can determine different interference signals and / or control signals, or patterns of interference signals and / or control signals.

[0044] According to one example, the injected interfering signal may produce a signal-to-noise ratio of 15 dB or less, preferably 10 dB or less, and more preferably 0 dB or less in at least one region.

[0045] In general, readily transmittable signals often have a signal-to-noise ratio greater than 15 dB. A signal-to-noise ratio of less than 10 dB is considered very noisy. If the effective signal power is equal to the noise signal power, the signal becomes indistinguishable at the receiver. Nevertheless, neural networks can, in principle, detect noise patterns at signal-to-noise ratios of 0 dB or less, thereby allowing even indistinguishable signals to influence the output of subsequent nodes in the neural network. The signal-to-noise ratio can also be less than 0 dB, preferably at least -40 dB, more preferably -15 dB, and even more preferably -10 dB.

[0046] For example, it is conceivable that a hardware-based artificial neural network can be maintained without changing its structure.

[0047] In another example, it is contemplated that the hardware-based artificial neural network may be trained, for example, without injecting an interfering signal, prior to the step of defining the target output data during processing of the supplied training data.

[0048] This means that, as known from the prior art, a neural network can be initially trained to obtain an initial performance, e.g., a first accuracy value for recognizing a particular pattern. Subsequent additional training with interference signal injection can exceed the initial performance, e.g., achieve a second accuracy value for detecting the particular pattern, which is greater than the first accuracy value.

[0049] According to a further example, the last obtained interference signal and / or control signal may be saved, preferably together with a marker value for identifying the target output data used, and after step (185) of terminating the method, the method is run again at least once using the same device with modified target output data and training data.

[0050] Further, for example, it is contemplated that at least one interference device may have at least a plurality of individually actuatable interference elements, each interference element designed to inject an interference signal into the hardware-based artificial neural network, each interference element preferably injecting the interference signal into a different region of the hardware-based artificial neural network, the plurality of actuatable interference elements may be actuated such that the interference signal forms a predetermined interference signal pattern on the hardware-based artificial neural network, and multiple training iterations of the hardware-based artificial neural network are preferably performed sequentially with different predefined interference signal patterns.

[0051] A predefined interference signal pattern can be used, for example, for the initial training iteration. In subsequent training runs, the interference signal pattern can be varied by varying the activity of individual or multiple individually actuatable interference elements, for example, by lowering or increasing signal strength. Because a predefined interference signal pattern can be injected initially, training can be accelerated using an interference signal pattern that has already been classified as suitable. Furthermore, the predefined interference signal pattern can also be used unchanged throughout training.

[0052] Further, for example, the interference signal and / or the control signal can be a test signal, which, when used to input predefined test data, can provide predefined output data only if no part of the hardware-based artificial neural network has been corrupted, replaced, and / or manipulated. Thus, the test signal can be used to verify whether the hardware-based artificial neural network has been compromised, e.g., modified. If the hardware-based artificial neural network to which the test data has been applied does not provide predefined output data, it can be assumed that the hardware-based artificial neural network is unable to perform its assigned task or returns incorrect or manipulated results. This can improve reliability when using the hardware-based artificial neural network.

[0053] According to a third aspect, the invention relates to the use of an apparatus according to the preceding description, the apparatus being operated sequentially with at least two different signal sets, in particular for different tasks, each signal set comprising at least one interference signal and / or control signal.

[0054] Different signal sets can be assigned to different tasks. For example, one signal set can enable a hardware-based artificial neural network to analyze an image. A second signal set may be suitable for recognizing specific objects within an image. Another signal set may solve an entirely different task, such as performing speech recognition.

[0055] The advantages and effects of the use of the device and the improvements thereof result from the advantages and effects of the device and the method described above, and in this respect reference is therefore made to the foregoing description in order to avoid repetition.

[0056] In a further example, there may be provided a method for training an artificial neural network in an arrangement according to the foregoing description, the method for training an artificial neural network in an apparatus according to the foregoing description being preferably applied to a hardware-based artificial neural network of an apparatus after the apparatus has been separately trained outside the arrangement by the method for training an artificial neural network in an apparatus according to the foregoing description.

[0057] The advantages, effects and improvements of the method for training an artificial neural network in a configuration arise from the advantages, effects and improvements of the above-described apparatus, configuration and the additional methods described above. In this respect, therefore, reference is made to the foregoing description to avoid repetition.

[0058] Using the method for training an artificial neural network within a configuration, all devices in the configuration can be matched to one another through training, improving the performance of the configuration. For this purpose, the devices in the configuration can be trained together from the beginning. Alternatively, each device can be trained individually first, so that the corresponding interfering device is not affected by the output signals of the other devices. Only in the second training run, when the devices in the configuration are matched to one another, can the interfering device be affected by the output signals of the other devices in the configuration.

[0059] In yet another example, there may be provided a method for training an artificial neural network in a system according to the foregoing description, the method for training an artificial neural network in an apparatus according to the foregoing description being applied to a hardware-based artificial neural network of the apparatus, preferably after the arrangement has been separately trained outside the system by a method for training an artificial neural network in an arrangement according to the foregoing description.

[0060] The advantages, effects and improvements of the method for training an artificial neural network in a system arise from the advantages, effects and improvements of the apparatus, arrangements, systems and other methods described above, and in this respect therefore, to avoid repetition, reference is made to the foregoing description.

[0061] In a method for training an artificial neural network in a system, different configurations of the system are coordinated with each other. In this case, the configurations can be initially trained separately without the devices of the other configurations affecting the interfering signal devices. Furthermore, in this case, before training the configuration, the devices of the configuration can be trained separately from each other without the other devices affecting the interfering devices. Alternatively, the configurations and the devices they contain can be matched with each other in a single training of the system, and the output signals of the configurations can affect the interfering devices of the other configurations. [Brief explanation of the drawings]

[0062] In the following, the invention will be explained by means of exemplary embodiments with reference to the accompanying drawings.

[0063] [Figure 1A] A schematic diagram of the apparatus is shown. [Figure 1B] A schematic diagram of the apparatus is shown. [Figure 2A] 1A and 1B show a schematic diagram of the device according to the invention in more detail. [Figure 2B] 1A and 1B show a schematic diagram of the device according to the invention in more detail. [Figure 3] 1 shows a schematic diagram of an example of a device with an FPGA chip. [Figure 4A] 4 shows a schematic diagram of a further embodiment of the example of FIG. 3. [Figure 4B] 4 shows a schematic diagram of a further embodiment of the example of FIG. 3. [Figure 5] 1 shows a schematic diagram of an example of an apparatus with two interference devices. [Figure 6] A schematic diagram of the basic structure of an FPGA chip is shown. [Figure 7] 1 shows a schematic diagram of an example of a device with a capacitive interference element. [Figure 8] 1 shows a schematic diagram of an example of a device with heating and cooling interference elements. [Figure 9] 1 shows a schematic diagram of an example of a device with a heated interference element. [Figure 10] 1 shows a schematic diagram of an example of a device with a sound-generating interference element. [Figure 11] 1 shows a schematic diagram of an example of a device with an interference element that emits electromagnetic radiation; [Figure 12] 1 shows a schematic diagram of an example of an apparatus with a pattern-generating interference signal device. [Figure 13] 1 shows a schematic diagram of a configuration involving multiple devices. [Figure 14] 1 shows a schematic diagram of a system with multiple configurations. [Figure 15] 10 shows a schematic diagram of a further example of a system for alternative modes of presentation; [Figure 16] 1 shows a schematic diagram of an example having multiple systems networked together via interference devices. [Figure 17] 10 shows a schematic diagram of a further example of the configuration of the device. [Figure 18] 1 shows a flowchart of a method for training an artificial neural network in a system. [Figure 19A] 1 shows a comparison between a conventional circuit and a hardware-based artificial neural network circuit adapted for the present invention. [Figure 19B] 1 shows a comparison between a conventional circuit and a hardware-based artificial neural network circuit adapted for the present invention. [Figure 20A] A further comparison between a conventional circuit and a hardware-based artificial neural network circuit adapted for the present invention is shown. [Figure 20B] A further comparison between a conventional circuit and a hardware-based artificial neural network circuit adapted for the present invention is shown. [Figure 21] 1 shows an array-like structure of semiconductor chips with artificial hardware-based neural networks. [Figure 22A] 1 shows an example of the arrangement as a semiconductor chip with an interference device and a switching element for the supply voltage. [Figure 22B] 1 shows an example of the arrangement as a semiconductor chip with an interference device and a switching element for the supply voltage. [Figure 22C] 1 shows an example of the arrangement as a semiconductor chip with an interference device and a switching element for the supply voltage. [Figure 23] 1 shows a schematic diagram detailing the overall system of a hardware-based artificial neural network. [Figure 24] 1 shows a device with additional peripherals. [Figure 25] 1 illustrates the layers of a hardware-based artificial neural network. [Figure 26] Serial queries of hardware-based artificial neural networks with various tasks are shown. [Figure 27] The overall structure of the device is shown. DETAILED DESCRIPTION OF THE INVENTION

[0064] 1A and 1B illustrate an apparatus, described in more detail below, with 1A showing a spatial configuration and 1B showing a cross-sectional view of the essential components of the apparatus. This example shows an FPGA chip on a control circuit board 13, whose individual components are configured and trained via an evolutionary learning process to link and form a hardware-based artificial neural network 11. This layer of the hardware-based artificial neural network 11 roughly corresponds to industrially available chip-based systems and activation mechanisms described in the prior art.

[0065] In the following, the term "FPGA" is used to represent any freely configurable electronic semiconductor chip. At a distance d, specified in more detail in the following examples, a further layer, optionally with an array-like structure, is arranged as an interference device 12, the elements of which are shown here as small spheres and can be switched on / off or adjusted in a controlled manner as interference elements. Actuation elements are not shown here.

[0066] This layer of the interference device 12 can generate interference signals in a pattern, referred to as the "interference signal layer." The interference signal layer, or elements thereof, can generate interference signals that are locally cross-coupled to at least one region of the hardware-based artificial neural network 11 via a space that is part of the coupling device 15, and the interference signal is injected into the entire region. This region thus corresponds to the region of the hardware-based artificial neural network 11 that is covered by the interference signal. The region can cover the entire network, i.e., the interference signal can be injected into the entire network. This can be done uniformly. Furthermore, for example, if multiple regions are provided, the range of the region can be assigned to a group of individual components of the FPGA, individual individual components, or only sub-regions of individual components.

[0067] Suitable interference signal array components can be miniature heating or cooling elements, optical, acoustic, resistive, electromagnetic, capacitive, mechanical, or even quantum mechanical components—anything that can be injected into an electronic circuit such as that implemented in a layer of a hardware-based artificial neural network 11 is applicable.

[0068] Through the coupling device 15, hereafter also referred to as the "coupling space," the signals generated by the interference device 12 can be cross-coupled to the layers of the hardware-based artificial neural network 11 in a pattern. Corresponding to the elements of the layers of the interference device 12, the coupling device 15 can be, for example, a medium mediating thermal, resistive, electromagnetic, capacitive, mechanical, or even quantum mechanical signal transmission. In the simplest case, it can be a homogeneous medium, such as a gas, liquid, or solid. However, in principle, the medium can comprise a combination of different materials structured vertically and / or horizontally to achieve localized effects in the direction of the layers of the hardware-based artificial neural network 11 and to match their array structure. That is, the medium of the coupling device 15 can be adapted to suit the configuration of the linkable elements of the FPGA chip, i.e., the hardware-based artificial neural network. The distance d can also be varied but is usually selected to be small compared to the surface area of ​​the layers of the hardware-based artificial neural network 11, in order to generate localized effects within the hardware-based artificial neural network 11, especially within the FPGA chip.

[0069] In contrast to the conventional use of semiconductor chips and semiconductor components, the components mounted in the layers of the hardware-based artificial neural network 11 may be partially, but not completely, shielded from external influences, whereby injection is possible only from the layers of the interference device 12.

[0070] Therefore, due to the increased sensitivity of the components of the hardware-based artificial neural network 11 to external signals, the encapsulation of the device can serve as a shielding device 14 against these very interfering signals.

[0071] In this basic configuration of the hardware-based artificial neural network 11 according to the present invention, the main components of the evolutionary learning process are the layers of the hardware-based artificial neural network 11. The layers of the interference devices 12 form higher-level but subordinate components, making this process in the layers of the hardware-based artificial neural network 11 more complex and capable of being optimized through its own evolutionary algorithm or a second evolutionary algorithm and learning process. The whole of the units 11-15 can be understood and referred to as an intelligent hardware AI system and can be called an AI basic unit.

[0072] The training process can be carried out in two variations: in the first option, the hardware-based artificial neural network 11 and the interfering device 12 can be modified simultaneously in an evolutionary process; in the second option, only the hardware-based artificial neural network 11 can be trained first, and if this training gives good results, the interfering device 12 can be added. If the apparatus comprises several hardware-based artificial neural networks 11 and several interfering devices 12, any combination can be subjected to individual and joint training according to the first or second option.

[0073] In contrast to prior art systems, by avoiding undefined interference effects, a defined separation of interfering signals by the interfering device 12 and the coupling device, highly complex systems become feasible and controllable, increasing the likelihood of achieving good training results.

[0074] Figures 2A and 2B show examples illustrating spatial relationships, with Figure 2A showing a three-dimensional exploded view and Figure 2B showing a cross section along line SS in Figure 2A.

[0075] The FPGA chip 24, on which the hardware-based artificial neural network is implemented, may be placed on a board 21 (e.g., a multi-layer PCB) for activating and configuring the FPGA via terminals 26. Configuration may be performed via a digital computer. The FPGA 24 may not be encapsulated in a shielded state, but instead be covered with a coupling medium 23 of a coupling device, followed by an interference device 22, shown here in the form of a checkerboard array with individual interference elements for locally generating an interference signal for the FPGA. The interference device 22 is then connected via terminals 27 to a board 25 for activating the interference elements. In the simplest case, any pattern can be generated by switching on and off the interference elements of the interference device, which locally act on the FPGA chip 24 via the coupling medium 23.

[0076] Regarding the distance d in FIG. 1A, in this example, it is small compared to the surface area of ​​the FPGA chip 24. Typically, the distance is between 0.1 mm and 5 mm, but preferably 0.5 mm. The geometric relationship can be seen in the cross section SS in FIG. 2B.

[0077] By way of example, the array of interference devices 22 may consist of small heating or Peltier elements coupled through a medium 23 with high thermal conductivity, such as through a metal or diamond layer. This layer may be configured as an array of columns with good and poor thermal conductivity, and the temperature pattern may be transferred to an FPGA, which may generate variable, trainable, and switchable interference signal patterns.

[0078] The first structuring degree of the interference device, which is a measure of the structuring of the distribution of interference elements, can be adapted to match the structuring of the FPGA, which in this example can be specified with a second structuring degree, i.e., can be selected to be geometrically similar. Next, in each region where the interference device injects an interference signal into the hardware-based artificial neural network implemented in the FPGA, a basic element of the FPGA is placed. In other words, one basic element of the FPGA is operated by each interference element.

[0079] However, this is not necessary, since the first degree of structuring can be equally well structured whether it is finer or coarser than the second degree of structuring, and it is preferred that the ratio between the first degree of structuring and the second degree of structuring has a value in the range of 10:1 for finer structuring and 0.1:1 for coarser structuring.

[0080] The bonding medium 23 of the bonding device can have a structuring designated by a third degree of structuring, which can also be finer or coarser than the second degree of structuring.

[0081] Figure 3 shows a compact technical configuration of the device described in Figures 1A and 1B. A semiconductor chip holder 31, e.g., ceramic with multiple contact pads, can be arranged on which an FPGA chip 32 with linkable electronic basic components 33 can be placed. Furthermore, a coupling medium 34 and an interference device 35 with an array of interference elements can be placed directly on top of it.

[0082] The entire chip can then be encapsulated 36 to shield it from external influences. In the case of electromagnetic elements in an interference device, this can be, for example, a metal encapsulation, and in the case of optical interference signals, it can be an opaque coating.

[0083] This compact chip design allows such chips to be combined on a single board to form complex structures or even stacks, as explained in the example below: This kind of chip can be used to assemble multiple AI basic units and combine them into layers and hierarchies.

[0084] 4A and 4B show schematic diagrams of exemplary combinations of compact chip systems. FIG. 4A shows the device as the AI ​​basic unit of FIG. 3, comprising an FPGA 41, a coupling medium 43 of the coupling device, and an interferometric device 42 with electrical contact pads 44. The thickness of the coupling medium can vary between 100 μm and 5 mm, preferably between 200 μm and 600 μm. Furthermore, the coupling medium can have multiple coupling elements, which can be structured or unstructured according to a third structuring degree. Structuring of the coupling medium is provided, particularly for use with signal patterns.

[0085] In Figure 4B, two devices are shown combined together. The combination of the two devices includes two FPGAs 41, which are connected to a common interference device 42 via two coupling media 43. The FPGAs are positioned head-to-head.

[0086] In a similar manner, further combinations can be realized as horizontal or vertical stacks. The advantage of using a common interferometric device for multiple FPGAs is that it reduces operational complexity.

[0087] Furthermore, during training by the FPGA, interference signal patterns can be generated that are either fixed in advance or optimized by evolutionary-based methods. Such a system also has the advantage that the upper and lower FPGAs can be exposed to different interference signal patterns in a time-separated sequence or alternating, resulting in more complex training and a more complex AI system without the need for complex switching.

[0088] Figure 5 shows a further variation, in which an FPGA 51 is placed between two coupling media 53a and 53b and two interference signal layers 52a and 52b, which provides multiple options for injecting interference signals in well-defined situations, albeit with increased device complexity.

[0089] For example, the central FPGA chip can be symmetrically injected with the same interference signal pattern from above and below. Alternatively, for example, the FPGA chips can be asymmetrically injected with the same or different interference signal patterns. Another alternative, for example, can be time-separated injections from above and below. Furthermore, for example, asymmetric interference signals can be injected alternately from above and below.

[0090] The basic principles and structure of an FPGA chip array are shown schematically in Figure 6. Because FPGAs are typically structured as an array, the representation of rows 1 to m and columns 1 to n was chosen for clarity.

[0091] Electronic elementary elements, whose positions can be identified by indices 11, 12, [...], m5, mn, can be connected to each other in a short-circuit-proof configuration via four connections A, B, C, D in each case to form a hardware-based artificial neural network, in which even incorrect wiring connections are permitted, for example, using the output of an element as an input.

[0092] As an example, elements of an FPGA can be digital or analog, as shown by the basic elements in positions 11-15 of the top row of the illustrated array. The symbols used correspond to electronic nomenclature. Analog and digital devices can be mixed. Electronic elements mn are not shielded from interference in the usual way, but may even have assemblies that are sensitive to optical, acoustic, thermal, electromagnetic, and other signals generated by interfering devices. The types of configurations used in training and evolutionary programs are conventional and will not be described in detail here.

[0093] In FIG. 7, three layers of the apparatus (hardware-based artificial neural network, coupling device, and interference device) are shown with capacitive interference.

[0094] In this example, the FPGA 71, as a hardware-based artificial neural network, has a second degree of structuring that is finer than the first and third degrees of structuring of the interference signal device 72 and the coupling device 73. The structuring of the FPGA, the interference device, and the coupling device can be of the same or different types. Therefore, it is possible to operate not only a single basic element of the FPGA, but also a group of basic elements simultaneously, or even only a sub-region of the basic elements.

[0095] The interference device 72 may, for example, comprise small metal plates or pads 72a as interference elements, embedded in an electrically insulating medium 72b. Each pad 72a can be activated by a computer program, similar to the operation of an FPGA. In the simplest example, as shown in 74, three assignments of each pad are possible: 1. application of a positive or negative voltage Ux; 2. open pad, i.e., no potential connection, where the pad seeks its potential in the chip environment itself; and 3. ground connection, allowing any charge pattern to be generated in the array.

[0096] In the example shown, the coupling devices 73 are structured in the same way, so that beneath each metal pad there is placed a high-permittivity material 73a embedded in a low-permittivity medium 73b as a coupling element. At the surface of the FPGA 71, the metal pads form local capacitors through which displacement currents can be injected into locally adjacent regions of the hardware-based artificial neural network.

[0097] In the evolutionary training process, the assignment of interference elements 72a can be changed via an evolutionary algorithm, similar to training a hardware-based artificial neural network. This means that a random assignment of input signals can first be generated and applied to the interference device 72. The input signals can then be received by an artificial neural network implemented in an FPGA. If this is correctly interpreted by the neural network at the output, the configuration of the interference device 72 remains unchanged, and the next training signal is applied to the FPGA. If the input signals are interpreted incorrectly, the assignment of some pads or interference elements is randomly changed, similar to switching connections in an FPGA. Both algorithms can be consistent, but do not have to be. This can be repeated hundreds to thousands of times (sometimes referred to as "generations" in evolutionary algorithms) to achieve the desired success rate for the entire device.

[0098] Figure 8 shows a three-layer AI chip that can generate interference signals via an array of heating and / or Peltier elements 82, which in this example represent interference elements. Temperature can be transferred from the interference elements to local elementary elements in an FPGA 81 via a coupling device 83. The elementary elements arranged as an array in FPGA locations 11-mn can be fabricated as temperature-sensitive elements according to standard semiconductor fabrication methods, or they can be designed so that they react in terms of signal behavior to small temperature differences, such as a few degrees or fractions thereof.

[0099] The coupling device 83 in this example also consists of two components: a cylinder region 83a with high thermal conductivity and a region 83b with low thermal conductivity between them. The material 83a can be a metal, such as copper or silver, or a diamond layer processed by semiconductor technology. The insulating material 83b can be a plastic material, glass, or even a ceramic material with low thermal conductivity.

[0100] The interference device 82 in this example can have multiple heating and / or cooling elements, such as small resistive elements or Peltier elements, as interference elements. In this way, any temperature pattern can be transferred to the underlying FPGA. The temperature difference can be selected within a wide range, for example, from -20°C to 100°C, but is preferably close to or below room temperature.

[0101] The structure of this AI basic unit is shown in vertical cross section SS in box 85 shown in the upper center of Figure 8. Again, the array structures of interference devices, coupling devices, and neural network layers do not need to match, i.e., the number of interference elements and coupling elements can, but does not necessarily, correspond to the number of basic electronic elements.

[0102] The generated temperature patterns are typically static, i.e., they remain constant for the operating cycle of the neural network corresponding to the decision run. However, it is also possible to generate dynamic changes over multiple decision runs of the FPGA.

[0103] The training procedure is similar to that described in FIG.

[0104] An apparatus with an interference device having only a heating element is shown in Figure 9. Otherwise, this example is configured similarly to that described in Figures 7 and 8.

[0105] 10 shows an interference device 102 having miniature acoustic transmitters as interference elements that emit acoustic signals at different frequencies, for example via vibrations. The acoustic transmitters can be piezoelectric elements, piezoelectric crystals, or miniature diaphragms that generate individually activated acoustic patterns.

[0106] In this example, the coupling device 103 may comprise an acoustic transmission area 103a (e.g., a mechanical solid-state coupling or a miniature sonotrode) and an acoustic attenuating intermediate space 103b (e.g., a sound-absorbing material, e.g., a material with very small cavities).

[0107] The FPGA 101 basic elements can be designed to be perturbed to some degree via acoustic frequencies. For example, if the FPGA basic electronic elements have an acoustic receiver component, the effect can be designed to be enhanced and more complex. This may apply to some or all of the FPGA basic elements. The advantage of using acoustics is their wide frequency range, which ranges from infrasonic frequencies through the human audible range to ultrasonic frequencies. This allows for the generation of acoustic patterns at not only one frequency, but also different frequencies.

[0108] This example graphically illustrates the expanding range of possibilities associated with introducing interference and coupling devices into a hardware-based artificial neural network. In interconnected configurations and systems, as illustrated in the following diagrams, each of these interference devices can vary in intensity as a fixed acoustic pattern, shift in frequency as a whole, change its frequency composition / spectrum, vary as a pattern, or operate in a combination of the above options.

[0109] Assuming the entire system of hardware-based artificial neural networks, interfering devices, and coupling devices is optimized for a specific frequency pattern and achieves its highest success rate with this operating pattern, modifying / detuning the interfering signal will lead to worse results. In extreme cases, the neural network will only function at specific intensity or frequency intervals. This means that for devices previously operating in a suboptimal manner, the interfering signal alone can be used to worsen or improve the device. This opens up the option of interconnecting many devices hierarchically or even non-hierarchically, which can potentially affect the success rate of the neural network and, therefore, other hardware-based artificial neural networks connected to it.

[0110] 11 shows an FPGA 111 equipped with an artificial neural network of the type already described. In this example, the interference device 112 can have as an interference element a small transmitter for high frequency electromagnetic waves up to the microwave range, which transmitter can be designed for example like an antenna, or it can transmit its signal to the FPGA via the coupling device 113 by means of a waveguide 113a as a coupling element.

[0111] Similarly, the interference device could have an infrared element or a visible or UV LED as the interference element. Furthermore, injection could be performed via an optical fiber or a small pinhole as the coupling element. As with Figure 10, this device allows for a very wide range of operation and training types.

[0112] FIG. 12 shows an alternative arrangement involving an interference device capable of generating an interference signal only in a pattern. For this purpose, the coupling device 123 may have two or more layers 123a, 123b, in which, for example, alternating transparent and opaque concentric rings are applied as a pattern, with the centers of the concentric rings of the two layers shifted relative to each other. This results in a symmetrical or asymmetrical superposition pattern. The interference device 122 may also comprise an array of light-emitting diodes. In this case, the coupling device 123 is not an array as in the previous example. Instead, the superposition pattern may define the pattern formed by the interference signal in a neural network. The FPGA chip 121 may have, for example, light-sensitive components in its electronic basic elements.

[0113] Figure 13 shows the configuration of the device as an ensemble of AI basic units corresponding to Figures 3 to 5. The FPGA chip 131 can be electrically connected to a control circuit board 135, and the interference device 132 can be electrically connected to the underside of the control circuit board 136, which is shown upside down and transparent. The coupling device 133 is located between them.

[0114] Via first actuation 139 to FPGA 131 on control circuit board 135 and second actuation 140 to interference device 132 on control circuit board 136, AI basic units 134 can be trained individually and / or jointly as previously described. If each AI basic unit 134 is trained on a different group of features, e.g., one to recognize cats, a second to recognize dogs, a third to recognize horses, etc., the configuration of Figure 13 forms a more complex AI system with higher performance / intelligence than the AI ​​basic units exhibit as individual devices.

[0115] The interference devices may also be partially electrically connected to one another as shown schematically via dashed lines 137, 138. This provides further options for overall configuration control and evolutionary training.

[0116] These connections can be used to transmit signals between interference devices 132, which can permanently change the performance of other AI elementary units, e.g., by simply injecting an interference signal into each AI elementary unit to manipulate the corresponding artificial neural network in the FPGA, as previously described. This can be done, for example, by increasing or decreasing the strength of the interference signal of the connected AI elementary unit. This means that each AI elementary unit can operate in an improved or optimal manner, such as in the device connected via dashed connection line 138, or can be detuned and degraded or switched off, such as in the device connected via connection line 137. For example, in the animal recognition example above, if half of the AI ​​elementary units can recognize animals and the other half can recognize artwork that resembles animals, such interconnections can ensure that many AI elementary units are initially controlled in a suboptimal range by the detuning of their respective interference devices, operating at, for example, 80% of their maximum performance. When an input signal (e.g., an image of a mule) is provided to the device, each AI elementary unit will classify this input signal differently.

[0117] A device capable of recognizing cats may, for example, output a 2% match rate between mules and cats, a device capable of recognizing horses may, for example, output a 90% match rate, and a device capable of recognizing art may respond with a detection range of, for example, a few percent to 60% for horse sculptures. The AI ​​base unit with the highest match rate (in this case, the device capable of recognizing horses) can switch its interference device to optimal operation. Furthermore, previously detuned interference devices of connected AI base units can also simultaneously switch to optimal interference signal mode, for example, one AI base unit for detecting wild horses, one for detecting zebras, and one for detecting equine hybrids. At the same time, through its connection to the device capable of recognizing art, it can suppress all but the device with the highest hit rate. This device with the highest hit rate in detecting art can optimally adjust its interference device and activate additional devices capable of detecting art through its connection.

[0118] This allows new iterations of the mule image to be initiated until it is determined which object in the entire system the mule comes closest to, be it an animal or an artwork.

[0119] Such a configuration has one more training layer than the AI ​​basic units, i.e., a layer of interconnection between devices, which can also be achieved through evolutionary optimization strategies.

[0120] Using multiple (at least two) configurations according to Figure 13, a complex system can be constructed, organized hierarchically or otherwise, as shown in Figure 14. While a base layer 141 with any number of AI basic units is shown, for clarity, Figure 14 shows only four devices, referenced a1-a4, which can be interconnected and activated or suppressed via electrical connections 143 between associated interference devices. In this layer, an input signal 144 can be input to all AI basic units a1-a4, for example, by connecting the device inputs in parallel.

[0121] The AI ​​basic unit with the highest recognition probability can be cross-coupled to the next higher layer 142, where an input signal 144 can now be applied to all AI basic units; for clarity, only two devices b1 and b2 are shown in layer 142, but these devices can also be partially or fully interconnected via electrical connections 143 between interfering devices. At this layer, the AI ​​basic unit with the highest recognition probability can also be determined, which can then generate an output signal 147.

[0122] Typically, the number of AI basic units can be greatest in the lowest layer and decrease toward higher layers. However, this is not required. At each layer, expanded decision categories or new links can also be created. For example, after an object is recognized, patterns can be compared in higher-level layers, and acoustic signals can be added in the next layer to reveal discrepancies that would otherwise lead to misclassification. For example, an object recognized as a cat may neigh like a horse. Such a system can have larger AI basic units in higher layers than in lower layers.

[0123] The left side of Figure 15 shows a system with a hierarchical AI structure, which consists of three layers 151, 152, 153 with inputs 154 and outputs 155, similar to Figure 14. Such complex AI interconnections are grouped below as cylinders 156 with inputs 154 and outputs 155, as shown on the right side of Figure 15, to allow for more complex structures to be represented.

[0124] Figure 16 shows a schematic representation of a more complex structure. It consists of several systems according to Figure 15, shown as cylinders 164-166. They can be oriented in layers in the same direction, but for clarity, only cylinder 164 is shown, by way of example, with inputs 161 pointing downwards and outputs 169 pointing upwards.

[0125] Systems can be arranged in domains marked with specific patterns on top of the corresponding cylinder, one pattern marking each system in the domain.

[0126] Figure 16 shows three domains that can be made up of three system types 164, 165, and 166. As can be seen in system type 166, not all systems within a domain need to be directly adjacent. Individual systems can also be located as standalone units in separate domains (not shown here). In this way, strong and weak interactions between domains can be achieved via interference devices.

[0127] Systems within a domain may receive a common input signal. Suitably, the domains may be configured so that each domain receives a different or modified input signal (e.g., a portion of the common input signal shown in Figure 16 at 161, 162, and 163).

[0128] There can be reciprocal or directed connections between systems, through which systems can stimulate or inhibit, and stimulate or inhibit, other systems. These connections typically start from the top layer, the result layer (see Figure 15). When input signals 161-163 are applied, individual systems can arrive at more complex responses faster, with different recognition probabilities than if these connections were not present.

[0129] Similar to the operation of the individual systems in Figures 14 and 15, systems within and outside the domain can be strengthened and weakened. Connections to other domains can easily be very far away, as shown, for example, by the connecting arrow from system 164a to system 164b, allowing larger system ensembles to control their activity via interference devices. These system ensembles have further layers of training in addition to those already described above.

[0130] Systems with the highest hit rate in a domain can be interconnected via the switching layer 167, and their results sent to the projection layer 168, where the results of other domains with high hit rates and the input signal can be input and displayed for comparison.

[0131] This configuration allows for the implementation of, for example, the chaos-like structures suspected to exist in the human brain. Systems correspond to the columnar structures of the cerebral cortex, and domains correspond, for example, to the visual, auditory, tactile, or olfactory cortex. Through interconnections between systems and domains, association-like modes can be created and trained, ultimately representing associations between phenomena that are not actually related to each other, such as the implementation of optical patterns in music. As can be seen, by using underlying devices, such as FPGAs with interferometric devices, interconnecting and manipulating them via the interferometric devices, linking the devices to form configurations, aggregating them into systems, and then arranging the systems into layers and domains, an overall AI system can be created, which can be made universally intelligent by running multiple evolutionary training cycles sequentially and / or simultaneously. The more extensive the system, the more complex the training structure can be.

[0132] 17A-17D show an alternative arrangement. When the interference device 172 is not located near the FPGA 171 and the interference signal is injected into multiple FPGAs in the same or similar manner, but more broadly rather than in a finer pattern than in FIGS. 1-16, the arrangement can include multiple FPGAs 171 and control circuit boards arranged in a square around a common interference device 172, which can be configured as a column, as in FIG. 17A. A group of four such FPGAs 171, or as many as eight (only seven are shown for clarity), can form an AI basic unit in conjunction with the interference device 172 and intervening coupling device 173.

[0133] Figures 17B-17D show further examples of devices in plan view, where in Figure 17B the FPGAs of the device are arranged in a triangular configuration, and in Figure 17C they are arranged in a hexagonal configuration.

[0134] FIG. 17D shows an arrangement in which FPGAs, and thus hardware-based artificial neural networks, are arranged in a rectangular chain system. The coupling medium of the coupling device 173 can be a gas or material that easily transmits the respective interference signals to the FPGA chip. Typically, it can be uniformly formed from the interference signal train 172 due to the width effect. Alternatively, it can comprise layers or other types of configurations of highly and less transparent materials. Other groupings can be implemented in a similar manner. What all of these have in common is that they can be combined into more complex configurations, systems, and ensembles, such as those described in FIGS. 13-16.

[0135] 18 shows a flow chart illustrating a method for training a system according to the foregoing description, which begins with a method 180 for training an artificial neural network in an apparatus according to the foregoing description. The apparatus of the system may be trained first.

[0136] In a first optional step 187 of method 180, the hardware-based artificial neural network of the device can be initially trained without the injection of an interfering signal. In this step, the hardware-based artificial neural network is trained to preliminary performance values.

[0137] A further step 181 can define target output data representing the desired results of processing the supplied training data by the hardware-based artificial neural network. This step can be performed at any time before the subsequent steps, and can also be performed simultaneously with or before optional step 187.

[0138] Furthermore, in step 182, the supplied training data can be used to train the hardware-based artificial neural network. To this end, the training data is input to an input layer of the neural network, and an interference device injects an interference signal into at least one region of the hardware-based artificial neural network. In this process, a portion of the nodes of the hardware-based artificial neural network, all of the nodes, or multiple nodes can be placed in at least one region.

[0139] In a further step 183, the output data of the hardware-based artificial neural network is obtained. Because the network is hardware-based, the training data is processed simultaneously by all nodes in the network layer, so that the output data is available within a few milliseconds.

[0140] Thereafter, in step 184, the deviation between the output data and the target output data is determined. If the deviation is outside a predefined tolerance, for example, if the deviation is greater than 1%, the hardware-based artificial neural network is reconfigured. At least one interfering signal can also optionally be modified. If multiple interfering signals are used, it is sufficient to modify a single interfering signal, for example, by activating an interfering element of an interfering device.

[0141] Steps 182-184 are repeated with the modified hardware-based artificial neural network and possibly the modified interference signal as inputs.

[0142] If the deviation is within the predefined tolerance, the training of the device ends at step 185 .

[0143] Once all devices have been trained with the method 180, a configuration of devices can be trained 188 with a further method. For this purpose, devices of the configuration that are coupled to each other via an interference device are trained according to steps 182 to 186. However, this does not exclude the possibility of training a configuration without previously performing the aforementioned method on the devices.

[0144] Training the configuration may proceed in a manner similar to method 180, with at least some of the interfering devices potentially being influenced or controlled by hardware-based artificial neural networks of other devices.

[0145] When all configurations of the system have been trained using method 188, the system can be trained according to method 189. For this purpose, devices or configurations of the system that are coupled to each other via interference devices are trained according to steps 182 to 186. However, this does not exclude the possibility of training the system without previously performing the aforementioned method on the configurations or devices.

[0146] Furthermore, the ensemble can be trained by first training the system as described above and then training the entire ensemble, although this does not exclude the possibility of training the ensemble without pre-training the system, configuration, and / or device.

[0147] The following describes a further exemplary embodiment in which the artificial hardware-based neural network is not modified in its structure during training. The artificial hardware-based neural network can be implemented as a semiconductor chip, the side dimensions of which can be a fraction of an inch to several inches. On the semiconductor chip, multiple analog and / or digital basic electronic circuits, each with x inputs and y outputs, can be processed in an array configuration, as in the case of previous FPGA chips, for example. Assuming a square semiconductor substrate with a side length of 2 inches and realizing the basic circuit of a complete electronic module or electronic component on a chip area of ​​2 μm × 2 μm, this results in a total number of connectable module fields exceeding 100 million. This is a number large enough to generate even very complex artificial hardware-based neural networks. However, in contrast to previous approaches, these electronic assemblies are hardwired and do not need to use all inputs and outputs. All basic circuits, i.e., each of the millions of module fields, are connected to a supply voltage, regardless of whether they are connected to a network. Assemblies are not limited to being linked to adjacent assemblies, but can also be linked to multiple assemblies.

[0148] The selected connections can be made without any circuit logic, i.e., randomly, or in a specific proportion, e.g., 40% random and 60% electronically meaningful connections, as obtained, for example, in previous artificial hardware-based neural networks after training. Alternatively, the connections between assemblies or electronic components can follow proven network patterns derived from previous artificial hardware-based neural networks, individual modeling processes, or training runs. This offers the advantage that artificial hardware-based neural networks can be mass-produced, always on identical semiconductor chips. In contrast to previous FPGA chips and other artificial hardware-based neural networks, the artificial hardware-based neural network of this exemplary embodiment cannot be trained directly, i.e., new connections cannot be added or removed in the artificial hardware-based neural network via external wiring. The highly complex switching matrices required for this purpose are no longer necessary, significantly simplifying the semiconductor system.

[0149] In this example, each electronic assembly or component may instead be provided with optically addressable components, such as photoresistors, photodiodes, and / or phototransistors, during chip processing, optionally modified in conjunction with conventional switching techniques, thereby allowing each of the millions of module fields to be influenced at one or more points via optical injection. However, components addressable via acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization signals may also be used in place of, or in addition to, optically addressable components. The discussion of this example applies equally to each of the component addressing options described above.

[0150] For example, additional light-sensitive components can be inserted to create suitable modules by replacing some of the components normally already present in the respective electronic circuits (which are not light-sensitive components). The replacement does not need to conform to any electrical logic or meaningful system.

[0151] This is shown by way of example in Figures 19A and 19B for analog circuits and in Figures 20A and 20B for digital circuits, with separate component diagrams in each case. In principle, any circuit commonly used in electronics can be used and modified in this way. The more complex the circuit, the greater the control possibilities, which in this example are optically guided.

[0152] FIG. 19A shows an instrumentation amplifier. FIG. 19B shows an exemplary modification via a photoresistor, which can replace individual or group resistors or can be added as an additional resistor. The additional photoresistor branch does not represent a significant electrical change, but it significantly affects the signal flow of the amplifier. This is a characteristic of the present invention's modification of the basic circuit of an artificial hardware-based neural network.

[0153] Similarly, all possible analog circuits commonly used in electronics are suitable for these modifications, which may include, individually or in combination, photodiodes, phototransistors, and other light-sensitive components, or components that can be addressed in other ways as described above. The appropriately modified circuits are then processed in semiconductor technology in a multi-layer design using known methods, thereby enabling the aforementioned miniaturization to produce a large number of module fields on the chip, preferably in the high millions. Then, appropriate optical injection can be introduced into elements such as transistors, resistors, etc. on the silicon chip, as well as the operational amplifier itself, which is processed in semiconductor technology. Assuming an average of 3 to 15 photoelements per basic circuit, this results in billions of possible operational options at the local semiconductor chip level on a 2-inch chip, providing more than enough variation potential for neural networks.

[0154] Figure 20B shows the corresponding modification of the digital circuit using the example of a NAND gate. Figure 20A shows a conventional circuit implemented with discrete components using diode-transistor logic technology.

[0155] A further deviation from conventional semiconductor realizations of artificial hardware-based neural networks according to the present invention is that the module fields are connected to a common supply voltage (U SS ), but are individually connected via switching elements (e.g. photoresistors, photodiodes, phototransistors or other light-insensitive elements via thyristors, field-effect transistors, etc.) that allow switching on / off and dimming the supply voltage of the corresponding electronic components of the artificial hardware-based neural network.

[0156] An array-like structure of a semiconductor chip for an artificial hardware-based neural network can be illustrated by, for example, a chip 211 with side lengths a and b of 2 inches, as shown in Figure 21. This chip 211 has module fields with light-modulating circuits 212 arranged in an n-row and m-column configuration. Each module circuit can have inputs and outputs that can be permanently connected to other modules, and can be connected in multiple layers, collectively forming a complex structure of an artificial hardware-based neural network. Typical dimensions c and d of the module fields are 1 μm to 5 μm, respectively, so a total of tens to hundreds of millions of electronic module fields or individual circuits, as shown in Figures 19A, 19B, and 20A, 20B, can easily be obtained. Processing of the individual circuits and creation of connections between electronic components across multiple layers can be performed, for example, according to conventional techniques, as can definition of input and output regions. The chip's planar surface can be optically transparent to allow light to be injected.

[0157] To provide selective manipulation of the module field of an artificial hardware-based neural network, for example, an LED array with the highest possible resolution and dimensions the same as or similar to the artificial hardware-based neural network can be used as an interference device. The interference device can be galvanically decoupled from the artificial hardware-based neural network. Such arrays can correspond to prior art arrays and, for example, can be made of indium gallium nitride. Furthermore, due to their current relatively low light output, they may be limited to pixel pitch dimensions of approximately 10 μm (fine pixel pitch LED technology). However, as evidenced by the photosensitive LCD chips in digital cameras, the size of the LED elements in the array can technically be reduced to pixel pitch dimensions in the submicrometer range (down to 50 nm), because the high light output required for large screens or displays is irrelevant in the application described here. This type of miniaturization is beneficial, but not absolutely necessary. If possible, it would be sufficient to provide very localized illumination of the surface of the artificial hardware-based neural network, individually for each photosensitive electronic component of the artificial hardware-based neural network. In contrast to display screens, for artificial hardware-based neural networks, the luminous output is less important in this configuration, which allows also to use the optical near-field effect, which allows very localized illumination in the sub-micrometer range.

[0158] Such arrays typically produce small screens, light strips, etc., so the LED elements can be activated, for example, according to conventional techniques, to produce any light pattern, with the resolution depending only on the number of pixels and the pixel pitch ratio. In addition to LEDs, other small light sources, such as OLEDs or QDOTs, can also be used in array format.

[0159] The purpose of the application described here is to generate an optical pattern with the highest possible resolution, which is usually the brightness and darkness of any wavelength sufficient to illuminate an artificial hardware-based neural network. Regardless of where the light-emitting LED elements are arranged on the photosensitive module field of the artificial hardware-based neural network, this circuit can selectively change its electrical behavior, for example, as shown in Figure 22C. For this purpose, the interference device 222 is arranged on the artificial hardware-based neural network 221, for example, at a small interval below the submillimeter range, as shown in Figure 22A. In this example, the interference device 222 has a plurality of LED elements 224 as interference elements, and only a part of the LED elements 224 is shown in Figure 22A. In order to laterally limit the light irradiation of the LED elements 224 and make it more local, a mask 411 can be arranged between the artificial hardware-based neural network 221 and the interference device 222, as shown in Figure 22B. In order to avoid difficult adjustments in this sandwich structure, the mask 411 can also be processed directly as a thin layer on the transparent surface of the artificial hardware-based neural network, especially in the range from micrometers to submicrometers. Diffractive elements and / or light of different wavelengths can also be applied, possibly in combination with an optical filter.

[0160] The reference signs in Figures 22A to C are as follows: 223 - details of the electronic module field; 224 - details of the LED elements; 228 and 410 - photosensitive components within the basic circuit field 223; 411 and 412: masks with openings 227. Figure 22B shows a cross-sectional view of one of the array fields of the interference device 222, the electronic component field of the artificial hardware-based neural network, and the control device 225 for providing a control signal to the switching element. The control device can be designed in the same way as the interference device.

[0161] The result of training an artificial hardware-based neural network is the generation of complex light patterns in an interference device via an array of LED elements, which are then input into the artificial hardware-based neural network, encoding its task for use as artificial intelligence. The large number of operations possible with millions of LED pixels and numerous light-sensitive components in the basic circuit domain of the artificial hardware-based neural network allows for a number of degrees of freedom equivalent to the number required for training the artificial hardware-based neural network (which can also be referred to as artificial intelligence) to be realized without having to modify the hardware structure of the artificial hardware-based neural network. While the technical difficulty of disconnecting and linking electrical connections between nodes in a conventional artificial hardware-based neural network is overcome by the present invention, this is replaced by the generation of individual light patterns and the introduction of numerous light-sensitive electronic components. The generation of light patterns can be performed under computer control, thus eliminating the limitations of system upscaling and training problems for the artificial hardware-based neural network. At the same time, the system is compatible with digital computers. The number of degrees of freedom can be increased by using different wavelengths of light, time-dependent signals, etc. The interference devices are galvanically decoupled in the manner described, which greatly simplifies the multi-layer construction of semiconductor components in artificial hardware-based neural networks.

[0162] To further increase the flexibility of the semiconductor chip array of the artificial hardware-based neural network and the possibility of further manipulation by purely electrical means, a switching array can be used as part of the control device, allowing for on / off switching or dimming of the supply voltage of individual basic circuit fields or electronic components of the artificial hardware-based neural network. This can be done in a separate chip system, as will be explained below using the example of a second optically galvanically isolated array, or it can be integrated in a galvanically coupled form into the semiconductor chip of the artificial hardware-based neural network.

[0163] As shown in FIG. 22A, a semiconductor chip 221 with an array of modified basic circuits 223 that are part of an artificial hardware-based neural network can be implemented in an optically transparent format on the top and bottom and placed between an interference device 222 and a control device 225, both of which can consist of LED arrays 224 and 226. The arrows indicate how the arrays can be attached to the surface of 221 from the bottom and top. A cross-sectional detail of the three-component system of interference device 222, artificial hardware-based neural network 221, and control device 225 is shown schematically in FIG. 22B. The semiconductor chip of the artificial hardware-based neural network is centrally located with its multiple layers 413, which can form the basic circuit field 223 and can include light-sensitive elements 228. The backside of the chip can have a thin opaque layer 229, which allows light from the LED array 226 of the control device 225 to reach only the light-sensitive components 410 in the supply voltage controllers of all basic circuits, but not the light-sensitive components 228 of the basic circuit layer, and vice versa for the upper optical layer of the interference device. A masking layer 412, similar to the layer 411, can also be processed or inserted on the backside, as in the case of the upper LED array. Depending on the trained pattern, LEDs 224 and 226 (only three of which are shown hatched here) can illuminate the light-sensitive components 228 of the basic circuit fields through the masking layer and, for example, illuminate the light-sensitive dimming transistor 410 from below to generate individual supply voltages. By manipulating the supply voltages of each of the millions of basic circuit fields from below via the control device, the circuits of the array of artificial hardware-based neural networks can be individually switched on, decoupled, or dimmed independently of each other.

[0164] The control device 225 can also be used to train an artificial hardware-based neural network to generate a second two-dimensional light pattern, which can greatly increase the number of possible variations across the device.

[0165] The connection, interruption or dimming of the supply voltage can be carried out via electrical switching elements, in particular phototransistors, photoresistors, photodiodes, thyristors, field-effect transistors, Zener diodes, etc., and can also be carried out in miniaturized form with conventional semiconductor processing. SS can be switched and dimmed via phototransistors T1 and T2 is shown in Fig. 22C for two basic circuit fields BS1 and BS2 of two basic circuit fields 223. A supply voltage is applied to the respective basic circuit field BS1 and / or BS2 of the artificial hardware-based neural network only if light strikes transistors T1 and / or T2.

[0166] However, the design of a control device for manipulating the supply voltage via the second optical array is also particularly advantageous, since it is also electrically isolated and coupled to the artificial hardware-based neural network. Dimming, in particular, corresponds to shifting the weights of individual basic circuit components throughout the network. Viewed in this way, the component fields of an artificial hardware-based neural network can be analogously represented as nodes in an artificial software-based neural network. Dimming can affect their weights, their on / off switching, and the addition or removal of nodes. The manipulation of the circuit's electrical behavior via optical injection can be analogously represented as linking and severing connections in an artificial software-based neural network, which is no longer possible in the artificial hardware-based neural network of this example. This example demonstrates the numerous changes that can now be achieved in highly scaled, complex networks that can be easily controlled electronically and with the aid of a computer, such as those required for artificial intelligence systems, thus eliminating the previous drawbacks of artificial hardware-based neural networks.

[0167] A schematic diagram with details of the entire system is shown in Figure 23. It includes an artificial hardware-based neural network 221 with basic circuit fields 223 shown in hatching, an interference device 222 with an LED array 224, a mask 235, a control device 226, and a supply voltage U of the individual basic circuit fields 223 of the artificial hardware-based neural network. SS 237 for controlling the switching element array 237.

[0168] Training the system can be performed by applying changes using known learning algorithms to the interference device and control device alone, but not to the artificial hardware-based neural network. To this end, LED activation can be randomly varied, new LED activations can be introduced into the pattern, and basic circuit fields can be switched off and new ones switched on or dimmed according to the learning algorithm. With a sufficient number of iterations, the artificial hardware-based neural network can learn by injecting a light pattern formed in the interference device in combination with a second light pattern, which can develop into an array pattern in the control device and affect the light-sensitive components of the artificial hardware-based neural network. Because the possible configurations of such component combinations are vast, typically in the billions, the system of the present invention, in its degrees of freedom or learning, corresponds to and avoids the physical separation and coupling of conventional hardware-based neural networks, but without the drawbacks of previous technologies.

[0169] The training methodology can be variable and operates on the principle that changes are made only if the results do not support the training goals. For example, the number and type of increments of changes per learning cycle can be varied. For example, the training procedure can use methods known in the art.

[0170] As illustrated in the examples of Figures 19A-22, training the system 7 ~10 9 Optical 2D array patterns with pixel resolution of over 10 and 10 in 2D array format 8The resulting switching patterns are of a super-high switching state. These figures reflect the vast number of ways to influence an artificial hardware-based neural network. An important advantage is that both arrays are independent of each other, and the patterns of the arrays are formed individually by training and, at the end of training, are fully defined, specifically in terms of their x- and y-coordinates, and are saved as activation patterns for the interfering and controlling devices.

[0171] As an example of training, consider an image recognition problem, such as distinguishing between wolves and dogs. Training generates two individual array patterns (one in the interference device and one in the control device), which the system correctly classifies with a high hit rate. Running the training again with other images generates other patterns, also leading to a high hit rate. Thus, the array patterns can be referred to as individual patterns. These patterns can be stored, for example, as digital images, in a separate electronics set or a connected computer. They can be later retrieved and regenerated by the interference device and the control device, allowing for repetition without changing the hardware structure of the artificial hardware-based neural network.

[0172] This is a crucial advantage, as the entire system can be retrained to distinguish between, for example, beech trees and oak trees. Two other array patterns are also obtained that are saved for later retrieval. This can be repeated for any number of training objectives. A library of array pattern combinations for the interference device and the control device is created, each paired, so that when loaded from memory and generated on the interference device and the control device, the artificial hardware-based neural network can be used accurately with respect to the distinctions it achieved in training. That is, with one pattern pair, the artificial hardware-based neural network can detect and distinguish between wolves and dogs, with another pair, it can detect and distinguish between beech trees and oak trees, and so on.

[0173] A particular advantage of the present invention over artificial software-based neural networks is that, after training is complete, the device's artificial hardware-based neural network produces results very quickly during use, without the need to run an extensive computer program. This speed advantage arises because, when an input signal is applied, multiple pulses pass through the electronic network chip at the switching speed of the electronic components, which can now typically be in the upper MHz to GHz range. Because multiple pulses are coupled forward and backward through the electronic network in parallel, but executed with delays and sometimes sequentially, results are obtained very quickly after one chip has passed—in the millisecond, microsecond, or even shorter time range.

[0174] A step towards more widely usable, potentially general AI, is made possible by being able to serially acquire any number of pattern pairs for every possible discrimination task that has been trained so far. For example, if the system is trained to have only three possible responses when given an input image to distinguish between dogs and wolves, then a certain level of general intelligence has already been achieved: 1. It's a wolf! 2. It's a dog! 3. Neither of those!

[0175] Next, to use the device as a general artificial intelligence, the user applies an image of a landscape with, for example, trees, houses, animals, and cars to the device's input, and the interference and control devices generate pattern pairs already obtained from training, using the same input image each time. The responses obtained from the device are saved for each pattern pair. For example, if it takes one millisecond to run one device, in one second, 1,000 different responses can be obtained, such as ``It's a dog,'' ``It's a beech,'' ``It's a house,'' ``It's not a fish,'' ``It's not a mountain,'' etc. Obtaining a response that confirms something already provides a description of what is shown in the image, i.e., a first interpretation. This can be considered a step towards general intelligence.

[0176] The device format according to the examples of Figures 19A-23 can be expanded for multiple, general-purpose use via peripheral devices, as shown in the example of Figure 24. 241 represents a device in which an artificial hardware-based neural network 221 is interposed, along with an interferometric device 222 as an optical array and a control device 225 as a supply voltage switching array. 242 represents an input module, through which, for example, a standardized pixel representation of an image can be input. 243 represents the activation electronics of the LED array of the interferometric device, and 244 represents an array pattern memory, which records activation data of individual training results and can generate it in the interferometric device via the activation electronics 243 as needed. Similarly, 245 represents the activation electronics of the switching device, and 246 represents a switching array pattern memory. Memories 244 and 246 can form a common memory. The results are further processed in 248, listed, displayed on a screen, or output as audio.

[0177] Even if serial queries for each incoming pattern pair are time-consuming, this is more than compensated for by other benefits. Currently, increasingly powerful artificial hardware and software-based neural networks require larger networks whose complexity increases significantly beyond linearity, which, among other reasons, leads to the limitations already discussed. The solution presented here also alleviates this problem of unmanageable complexity and cost growth, since the same artificial hardware-based neural network, whose hardware structure remains unchanged, is used to answer the most diverse questions. The technically challenging problem of network expansion is shifted to creating a large number of corresponding pattern pairs, which, from a data technology and information science perspective, is much easier than expanding hardware or software networks.

[0178] Below are estimates of the switching speed / cycle rate of the device according to FIG.

[0179] The switching time of the LEDs is less than 1 μs, with peak values ​​between 1 ns and 10 ns. In this case, the response latency of the LEDs in the array is therefore not limited by the time, but by the activation of the LED array until the complete light pattern is formed. In this example, data transmission to the array is carried out via electrical conductors. In these cases, achievable transmission speeds are currently between 1 Gbit / s and 40 Gbit / s (e.g., mass storage interfaces SATA Express, SAS-1 and SAS-3 or serial interfaces such as Serial ATA, Thunderbolt interfaces, USB4®). 10 7 Considering an LED array of pixels, the resulting switching rate for pixel patterns across the array is in the sub-ms range. For large LED screens, image refresh rates currently range from 360 fps to 1920 and 3840 fps for smaller LED displays. Using parallelization, this can be further reduced by a factor of 10, resulting in approximately 1,000 to 30,000 patterns per second. A major advantage of this device, as already mentioned, is its high speed, determined by the switching times of the electronic components and the length of the key connections within the network. Assuming switching frequencies in the MHz to GHz range (e.g., CMOS technology), the operating speed, or cycle rate, of the artificial hardware-based neural network is again in the sub-ms range. This means that an artificial hardware-based neural network can provide decisions via pattern changes at rates exceeding 1,000 per second. This rate can also be increased by parallelizing multiple devices. This brings the potential cycle rate of various device queries to 1,000 to 10,000 per second.

[0180] To enhance the security of such AI systems, manufacturers or operators can generate special pattern pairs that, when imported into the array, produce known, specific response reactions that detect that the artificial hardware-based neural network has not been modified, substituted, or otherwise manipulated, particularly in the form of a challenge-response procedure and test task, thereby enabling authentication via one or more test patterns.

[0181] Updates in AI systems can be achieved by importing further or improved pattern pairs into the corresponding memory (see Figure 24), as the semiconductor chip of the artificial hardware-based neural network can remain unchanged under these extensions.

[0182] FIG. 25 shows a device system with multiple layers. For example, an image 252 of an animal in pixel format is input to input layer 251. Layers 253 and 254 can be chips of different dimensions according to FIG. 22, which may be followed by further chips (represented by dots). For example, layer 253 may be more complex than layer 254 and have more than 1 million switching modules. Layer 254 may be less complex than layer 253 and have, for example, fewer than 10,000 switching modules. Each layer includes two LED arrays 256, 257 and 258, 259, which may have different dimensions, for example, in terms of the number of LED elements. Output layer 255 can present the result. In this example, this is the sentence "It is a lion" in text form.

[0183] Figure 26 shows the serial query of a device trained with n different LED array pattern pairs to recognize animals, faces, scenes, etc., here t1, t2, t3…t nThese can be run sequentially in chronological order, such as in the example above, or they can be run separately. The device shown performs broad category classification, so that when an image of a giraffe is input, it is given the classification "is an animal." This is followed by another device of this type that performs finer classification, such as recognizing what type of animal it is ("giraffe"), given an image of an animal. Subsequent devices are trained on giraffes and recognize that the image is, for example, the head of a particular giraffe species (e.g., "Africa, Serengeti, adult, female").

[0184] Such hierarchically cascaded devices can be used to develop systems with more complex configurations and general intelligence.

[0185] Figure 27 shows the overall structure once again, showing its parts more clearly, and summarizing the options for the influence of light on the circuit blocks of the central network electronics.

[0186] The light flux of each pixel during the operation of the central network (i.e., during processing after image capture) can be either a) constant, b) a function of time (alternating or discontinuous periodic), and / or c) stochastic (convolutive noise).

[0187] The above examples do not limit the invention in any way. On the contrary, the invention can be modified in many ways. All of the above-mentioned features of the invention, either alone or in combination with each other, can be essential to the invention.

Claims

1. An apparatus for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network (11, 24, 32, 41, 51, 71, 81, 101, 111, 121, 131, 171, 221) having a plurality of electrically interconnected network nodes, each network node comprising at least one electronic component, the hardware-based artificial neural network having a particularly immutable hardware structure, and the apparatus comprising at least one interference device (12, 22, 35, 42, 52a, 52b, 72, 82, 10) for injecting at least one interference signal into at least one region of the hardware-based artificial neural network. The apparatus comprises 2, 112, 122, 132, 172, 222, 225) and at least one coupling device (15, 23, 34, 43, 53a, 53b, 73, 83, 103, 113, 123, 133, 173), wherein the coupling device is positioned between the interference device and the hardware-based artificial neural network and is designed to transmit the at least one interference signal from the interference device to the at least one region, and / or the apparatus has at least one switching element which can be individually actuated by at least one control signal to dim and / or switch on and off a supply voltage to the at least one electronic component.

2. The apparatus according to claim 1, wherein the hardware-based artificial neural network in the at least one region has at least one component designed to reduce the signal-to-noise ratio upon receiving the at least one interference signal, the interference device preferably generates optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization interference signals, and / or the switching element is preferably designed to receive optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal, and / or ionization control signals.

3. The apparatus according to claim 1 or 2, wherein the interference device has a plurality of individually operable interference elements (72a) for injecting interference signals into the hardware-based artificial neural network, the interference elements preferably inject interference signals into different regions of the hardware-based artificial neural network.

4. The apparatus according to claim 3, wherein the plurality of interference elements are preferably arranged in the form of an array and distributed throughout the layer, and the coupling device comprises a medium having a plurality of coupling elements (73a, 83a, 103a, 113a) for transmitting the at least one interference signal to the at least one region, the coupling elements being distributed within the layer in the same manner as the interference elements.

5. The apparatus according to claim 1, wherein the at least one region is designed to have a range corresponding to the range of the hardware-based artificial neural network or to be smaller than the range of the hardware-based artificial neural network.

6. The apparatus according to claim 1, wherein the apparatus has at least one semiconductor chip, the semiconductor chip comprising the hardware-based artificial neural network.

7. The apparatus according to claim 1, comprising shielding devices (14, 36) for shielding external interference signals of the same type as the at least one interference signal, wherein the shielding devices surround the hardware-based artificial neural network, the coupling device, and the interference device.

8. The apparatus according to claim 1, further comprising: at least one memory for storing the at least one interference signal and / or the at least one control signal used by the at least one interference device; at least one control unit for controlling the at least one interference device and / or the at least one switching element; and / or at least one output unit for outputting a particularly further processed output signal of the hardware-based artificial neural network.

9. The apparatus according to claim 1, wherein the interference device is designed as a control device that provides the at least one control signal to the at least one switching element.

10. A method for training an artificial neural network in the apparatus described in claim 1, wherein the method (180) comprises at least the following steps: - Defining target output data during processing of supplied training data (181); - Supplying the training data to the hardware-based artificial neural network (182) and injecting at least one interference signal into the at least one region of the hardware-based artificial neural network by the at least one interference device; - Obtaining output data from the hardware-based artificial neural network (183); - Determining whether there is at least one deviation between the output data and the target output data (184), and determining that the deviation is outside a predetermined tolerance range; If the deviation is within the tolerance range: - To terminate the above method (185); If the deviation is outside the predetermined tolerance range: - Modifying the at least one interference signal (186), and / or modifying the at least one control signal; - A method comprising repeating steps 182 to 184 above, in particular 185 or 186 (187).

11. The method according to claim 10, wherein the injected interference signal generates a signal-to-noise ratio of 15 dB or less, preferably 10 dB or less, and more preferably 0 dB or less in the at least one region.

12. The method according to claim 10 or 11, wherein the hardware-based artificial neural network is maintained without changing its structure.

13. The method of claim 10, wherein the last acquired interference signal and / or control signal is preferably stored together with a marker value for identifying the target output data used, and after the step (185) of terminating the method, the method is performed again at least once using the same apparatus with the modified target output data and training data.

14. The method according to claim 10, wherein the interference signal and / or control signal is a test signal, and when predefined test data is input using the test signal, predefined output data is provided only if no part of the hardware-based artificial neural network is damaged, replaced, and / or manipulated.

15. The apparatus according to claim 1, wherein the apparatus is operated sequentially with at least two different signal sets, particularly for different tasks, and each signal set comprises at least one interference signal and / or control signal.

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