Semiconductor device having dummy pads and method for forming same

Abstract

In a particular aspect, a semiconductor device includes a device layer, a dummy pad, a dielectric structure extending vertically between the device layer and the dummy pad, and an interconnect structure extending vertically between the device layer and the dielectric structure, wherein the dielectric structure, the interconnect structure, and the dummy pad are superimposed.

Description

[Technical Field]

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods for fabricating same. [Background technology]

[0002] Electrostatic discharge (ESD) is the sudden release of static electricity. ESD can occur when a charged object touches an electronic device. ESD can damage semiconductor devices, for example, if they are not protected during their manufacturing and packaging. One way to prevent damage caused by ESD is to use ESD protection circuits (also known as ESD circuits), which divert the flow of ESD current by providing a low-impedance path. Summary of the Invention

[0003] In one aspect, a semiconductor device includes a device layer, a dummy pad, a dielectric structure extending vertically between the device layer and the dummy pad, and an interconnect structure extending vertically between the device layer and the dielectric structure, wherein the dielectric structure, the interconnect structure, and the dummy pad are superimposed.

[0004] In some embodiments, the semiconductor device further comprises a semiconductor layer between the dummy pad and the interconnect structure, hi some implementations, the dielectric structure comprises an isolation structure within the semiconductor layer.

[0005] In some implementations, the isolation structures have lateral dimensions greater than the lateral dimensions of the dummy pads.

[0006] In some embodiments, the semiconductor device further includes a first via contact in contact with the interconnect structure and separated from the dummy pad by an isolation structure.

[0007] In some embodiments, the first via contact comprises tungsten.

[0008] In some embodiments, the semiconductor device further includes a second via contact extending vertically in contact with the dummy pad, hi some embodiments, the dielectric structure includes a dielectric layer between the second via contact and the interconnect structure.

[0009] In some embodiments, the second via contact is separated from the interconnect structure by a dielectric layer.

[0010] In some embodiments, the second via contact comprises tungsten.

[0011] In some embodiments, the semiconductor device further comprises a bonding interface between the dummy pad and the device layer, hi some implementations, the interconnect structure comprises a bonding contact at the bonding interface.

[0012] In some embodiments, the interconnect structure further comprises a device contact between the bonding interface and the device layer, connecting the bonding interface and the device layer.

[0013] In some embodiments, the semiconductor device further includes a pad, another second via contact in contact with the pad, another first via contact in contact with the other second via contact, and another interconnect structure in contact with the other first via contact and the device layer.

[0014] In some implementations, the pads and dummy pads are coplanar and the interconnect structures and other interconnect structures are coplanar.

[0015] In another aspect, a semiconductor device includes a device layer including electrostatic discharge (ESD) circuitry and functional circuitry, a dummy pad isolated from the functional circuitry, and an interconnect structure between the device layer and the dummy pad, wherein the dummy pad is connected to the ESD circuitry through at least the interconnect structure.

[0016] In some embodiments, the semiconductor device further includes a first via contact between the dummy pad and the interconnect structure and connected to the interconnect structure.

[0017] In some embodiments, the semiconductor device further includes a semiconductor layer between the dummy pad and the first via contact, a spacer in the semiconductor layer, and a second via contact that contacts the dummy pad and extends through the spacer.

[0018] In some embodiments, the first and second via contacts comprise tungsten.

[0019] In some embodiments, the dummy pad is connected to the ESD circuitry through at least the interconnect structure and the first and second via contacts.

[0020] In some embodiments, the semiconductor device further comprises a bonding interface between the dummy pad and the device layer, hi some implementations, the interconnect structure comprises a bonding contact at the bonding interface.

[0021] In some embodiments, the interconnect structure further comprises a device contact between the bonding interface and the device layer, connecting the bonding interface and the device layer.

[0022] In yet another aspect, a method for forming a semiconductor device is provided. A device layer including functional circuitry is formed. An interconnect structure is formed on the device layer and isolated from the functional circuitry. A first via contact is formed on the interconnect structure and connected to the interconnect structure. An isolation structure is formed on the first via contact. A dummy pad is formed on the isolation structure and isolated from the first via contact by the isolation structure.

[0023] In some embodiments, other interconnect structures are formed on the device layer and connected to the functional circuitry, other first via contacts are formed on the other interconnect structures and connected to the other interconnect structures, second via contacts are formed on and in contact with the other first via contacts and extend through the isolation structures, and pads are formed on and in contact with the second via contacts.

[0024] In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, exposing the first via contact and the other first via contact, and a dielectric layer is deposited to fill the trench.

[0025] In some embodiments, to form the second via contact, a portion of the isolation structure is removed to form a hole to expose another first via contact other than the first via contact, and a metal layer is deposited to fill the hole.

[0026] In some embodiments, the metal layer comprises tungsten.

[0027] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure. [Brief explanation of the drawings]

[0028] [Figure 1] 1 illustrates a plan view of a semiconductor device with via contacts below dummy pads in accordance with some aspects of the present disclosure. [Figure 2] 1 illustrates a plan view of a semiconductor device without via contacts below the dummy pads in accordance with some aspects of the present disclosure. [Figure 3A] 1 illustrates a cross-sectional side view of a semiconductor device having a dummy pad in accordance with some aspects of the present disclosure. [Figure 3B] 1 illustrates a cross-sectional side view of a three-dimensional (3D) memory device having dummy pads and pads in accordance with some aspects of the present disclosure. [Figure 4] 1 illustrates a cross-sectional side view of another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 5] 1 illustrates a cross-sectional side view of yet another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 6A] 1 illustrates a circuit diagram of an ESD circuit in accordance with some aspects of the present disclosure. [Figure 6B] 1 illustrates a circuit diagram of an ESD circuit in accordance with some aspects of the present disclosure. [Figure 7A] 1 illustrates a manufacturing process for forming a semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 7B] 1 illustrates a manufacturing process for forming a semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 7C] 1 illustrates a manufacturing process for forming a semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 7D] 1 illustrates a manufacturing process for forming a semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 7E] 1 illustrates a manufacturing process for forming a semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 8A] 10 illustrates a manufacturing process for forming another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 8B] 10 illustrates a manufacturing process for forming another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 8C] 10 illustrates a manufacturing process for forming another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 8D] 10 illustrates a manufacturing process for forming another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 8E]10 illustrates a manufacturing process for forming another semiconductor device having dummy pads in accordance with some aspects of the present disclosure. [Figure 9] 1 is a flowchart of a method for forming a semiconductor device having dummy pads in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present disclosure will be described with reference to the accompanying drawings.

[0030] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be applied to a variety of other applications. The functional and structural features described in this disclosure can be combined, arranged, and modified with each other, and in ways not specifically shown in the drawings, such that these combinations, arrangements, and modifications are within the scope of the present disclosure.

[0031] In general, terms may be understood, at least in part, from their use in context. For example, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Furthermore, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly described, depending at least in part on the context.

[0032] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest possible manner, such that "on" not only means "directly on" something, but also includes the meaning "on" of something with an intermediate feature or layer therebetween, and "above" or "over" not only means "above" or "over" something, but can also include the meaning "above" or "over" of something without an intermediate feature or layer therebetween (i.e., directly on top of something).

[0033] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0034] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added onto the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0035] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extent that is smaller than the extent of the underlying or overlying structure. Furthermore, a layer can be a uniform or non-uniform region of a continuous structure that has a thickness that is smaller than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces between the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along tapered surfaces. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0036] In semiconductor devices, dummy pads, like regular pads (referred to herein as "pads"), can be used for wire bonding during semiconductor device packaging. However, unlike regular pads, dummy pads are electrically isolated from the functional circuitry (e.g., having transistors or memory cells) of the semiconductor device and therefore do not facilitate operation of the functional circuitry.

[0037] Although dummy pads are designed to be electrically isolated from the corresponding functional circuitry below them, ESD from the dummy pads can still cause damage to the functional circuitry if, for example, during packaging of a semiconductor device, the distance between the functional circuitry below and in contact with the dummy pad and the interconnect structure is not large enough and / or the functional circuitry is not ESD protected.

[0038] To address one or more of the aforementioned problems, the present disclosure introduces various solutions for preventing ESD damage to semiconductor devices from dummy pads. According to one aspect of the present disclosure, at least one of the via contacts in an interconnect structure below and covering the dummy pad is removed, e.g., replaced by a dielectric structure, so that ESD from the dummy pad cannot propagate to functional circuitry. In some implementations, the lateral dimensions of the isolation structure (e.g., buried shallow trench isolation (BSTI)) in the dielectric structure are larger than the lateral dimensions of the dummy pad, thereby further reducing the risk of burnout due to defects between the dummy pad and the semiconductor layer below the dummy pad. According to another aspect of the present disclosure, the dummy pad is electrically connected to an ESD circuit at least through the interconnect structure, thereby allowing ESD from the dummy pad to be mitigated by the ESD circuit.

[0039] FIG. 1 illustrates a plan view of a semiconductor device 100 with via contacts beneath dummy pads 104, according to some embodiments of the present disclosure. The semiconductor device 100 may include logic devices such as a microcontroller, a microprocessor, or an application processor; memory devices such as dynamic random access memory (DRAM), NAND or NOR flash memory, or static random access memory (SRAM); or analog devices such as operational amplifiers, timers, analog-to-digital converters (ADCs), or digital-to-analog converters (DACs). The semiconductor device 100 may include wire bond pads used to electrically connect the semiconductor device 100 to external devices. For example, the wire bond pads may be connected to a circuit board or packaging substrate (e.g., a redistribution layer) or an interposer by soldering and attaching gold or aluminum wires. Thus, the wire bond pads can serve as bond sites on the semiconductor device 100. The semiconductor device 100 may also include functional circuits (e.g., as part of its device layers) configured to perform the functions of the semiconductor device, such as transistors for logic devices, memory cells for memory devices, or resistors, capacitors, and inductors for analog devices.

[0040] In some embodiments, wire bond pads include regular pads (also known as pads) 102 and dummy pads 104, depending on whether the wire bond pads are electrically connected to any functional circuitry, i.e., whether the wire bond pads also facilitate operation of the corresponding functional circuitry (e.g., transmitting / receiving electrical signals to / from a functional device). For example, each pad 102 may be electrically connected to a corresponding functional circuitry to facilitate operation of the functional circuitry, while each dummy pad 104 may not be electrically connected to any functional circuitry and therefore does not facilitate operation of any functional circuitry. As shown in FIG. 1 , in some embodiments, either pad 102 or dummy pad 104 is in contact with one or more via contacts therebelow that form part of an interconnect structure overlying pad 102 / dummy pad 104. It is understood that an interconnect structure overlying pad 102 may connect pad 102 to a corresponding functional circuitry, while an interconnect structure overlying dummy pad 104 may not connect dummy pad 104 to any functional circuitry. In some embodiments, described in more detail below, the interconnect structure overlying the dummy pad 104 may connect the dummy pad 104 to ESD circuitry to reduce the risk of ESD damage from the dummy pad 104 to functional circuitry near the interconnect structure overlying the dummy pad 104.

[0041] 2 illustrates a plan view of a semiconductor device 200 without via contacts below the dummy pads 104, according to some aspects of the present disclosure. The semiconductor device 200 is similar to the semiconductor device 100, except that at least one of the via contacts below the dummy pads 104 is removed and replaced with, for example, a dielectric structure. As a result, according to some embodiments described in detail below, ESD from the dummy pads 104 can be isolated by the dielectric structure before reaching any functional circuitry via the interconnect structure covering the dummy pads 104.

[0042] 3A illustrates a cross-sectional side view of a semiconductor device 300 having a dummy pad 330, according to some aspects of the present disclosure. The semiconductor device 300 may be an example of the semiconductor device 200. As illustrated in FIG. 3A, the semiconductor device 300, according to some embodiments, is a bonded chip including a first structure 302 and a second structure 304 stacked on top of each other in different planes in the vertical direction (e.g., the z-direction). According to some embodiments, the first and second structures 302 and 304 are bonded at a bonding interface 306 therebetween.

[0043] As shown in FIG. 3A , first structure 302 can include a substrate 308, which can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, substrate 308 includes single crystal silicon, which is a portion of the wafer on which first structure 302 is fabricated, either at its original thickness or thinned. In some embodiments, first substrate 302 includes, for example, polysilicon, a semiconductor layer that replaces a portion of the wafer on which first structure 302 is fabricated. Note that x-, y-, and z-axes are included in FIGS. 1 , 2 , and 3A to further illustrate the spatial relationships of components within semiconductor devices 100, 200, and 300. The substrate 308 of the semiconductor device 300 includes two sides extending laterally within the x-y plane: a top surface on the front side of the wafer on which device layers 310 can be formed, and a bottom surface on the back side of the wafer opposite the front side. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether one component (e.g., a layer or device) of the semiconductor device 300 is "above," "above," "below," or "below" another component (e.g., a layer or device) is determined relative to the substrate 308 of the semiconductor device 300 in the z-direction (a vertical direction perpendicular to the x-y plane) when the substrate 308 is positioned at the lowest plane of the semiconductor device 300 in the z-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0044] As shown in FIG. 3A , the first structure can include a device layer 310 over a substrate 308. In some implementations, the device layer 310 includes functional circuitry 312. In some implementations, the semiconductor device 300 is a NAND flash memory device in which memory cells are formed in an array of NAND memory strings, and the functional circuitry 312 is peripheral circuitry (also known as control and sensing circuitry) that facilitates operation of the NAND memory strings and includes any suitable digital, analog, and / or mixed-signal circuitry. For example, the peripheral circuitry can include one or more of: a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., subcircuit) of the aforementioned functional circuitry, or any active or passive component (e.g., transistor, diode, resistor, or capacitor) of the circuitry. The functional circuitry 312 can use, for example, complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented in a logic process in any suitable technology node.

[0045] In some implementations, the first structure 302 further includes an interconnect layer 311 above the device layer 310 to transfer electrical signals to and from the device layer 310. As shown in FIG. 3A , the interconnect layer 311 can reside vertically between the bonding interface 306 and the device layer 310 (including the functional circuitry 312). The interconnect layer 311 can include multiple interconnects (also referred to herein as “contacts”), including horizontal lines and via contacts. The term “interconnect” as used herein can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer 311 can further include one or more interlayer dielectric (ILD) layers (also known as “inter-metal dielectric (IMD) layers”) in which the horizontal lines and via contacts can be formed. That is, the interconnect layer 311 can include horizontal lines and via contacts in multiple ILD layers. Although not shown in FIG. 3A , it is understood that the functional circuitry 312 in the device layer 310 may be electrically connected to any other suitable functional circuitry via interconnects in the interconnect layer 311. The interconnects in the interconnect layer 311 may include conductive materials, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer 311 may include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 311 include device contacts 316, for example, in the metal 3-5 (M3-M5) layers. The device contacts 316 may include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials.

[0046] 3A , the first structure 302 can further include a bonding layer 313 in contact with the interconnect layer 311 at the bonding interface 306 and above the interconnect layer 311. The bonding layer 313 can include a plurality of bonding contacts 318 and a dielectric that electrically isolates the bonding contacts 318. The bonding contacts 318 can include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some embodiments, the bonding contacts 318 of the bonding layer 313 include Cu. The remaining regions of the bonding layer 313 can be formed of a dielectric, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contact 318 and the surrounding dielectric within the bonding layer 313 can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive), and can simultaneously obtain a metal-metal (e.g., Cu-Cu) bond and a dielectric-dielectric (e.g., SiO2 to SiO2) bond.

[0047] As shown in FIG. 3A , the second structure 304 may include a bonding layer 315 at the bonding interface 306, e.g., on the opposite side of the bonding interface 306 from the bonding layer 313 of the first structure 302. The bonding layer 315 may include a plurality of bonding contacts 320 and a dielectric that electrically insulates the bonding contacts 320. The bonding contacts 320 may include a conductive material such as Cu. The remaining regions of the bonding layer 315 may be formed of a dielectric material such as silicon oxide. The bonding contacts 320 and the surrounding dielectric within the bonding layer 315 may be used for hybrid bonding. In some embodiments, the bonding interface 306 is where the bonding layers 313 and 315 meet and bond. In practice, the bonding interface 306 may be a layer having a certain thickness that includes the top surface of the bonding layer 313 of the first structure 302 and the bottom surface of the bonding layer 315 of the second structure 304.

[0048] As shown in FIG. 3A , the second structure 304 can further include an interconnect layer 323 above the bonding layer 315 to transfer electrical signals. The interconnect layer 323 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Although not shown in FIG. 3A , in some examples, the interconnects in the interconnect layer 323 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 323 can further include one or more ILD layers in which horizontal lines and via contacts can be formed. The interconnects in the interconnect layer 323 can include conductive materials, including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 323 can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 323 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (reduced defects, e.g., voids) among conductive metal materials.

[0049] 3A, the second structure 304 can further include a semiconductor layer 326 above the interconnect layer 323. The semiconductor layer 326 can include a semiconductor material. In some implementations, the semiconductor layer 326 is a thinned silicon substrate having single crystal silicon. In some implementations, the semiconductor layer 326 is a deposited polysilicon layer that replaces at least a portion of the silicon substrate having single crystal silicon. It is understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the semiconductor layer 326. It is also understood that in some examples, the semiconductor layer 326 can include multiple vertical semiconductor layers with dielectric layers formed therebetween.

[0050] 3A , the second structure 304 may further include a pad-out layer 327 above the semiconductor layer 326. The pad-out layer 327 may include a dummy pad 330, one or more ILD layers 332 (e.g., a silicon oxide layer and a silicon nitride layer), and a protective layer 334 (e.g., a polyimide layer) on the top surface of the semiconductor device 300. The pad-out layer 327 and the interconnect layer 323 may be formed on either side of the semiconductor layer 326. In some implementations, an opening 336 is formed through the protective layer 334 and the ILD layer 332 in the pad-out layer 327 to expose the dummy pad 330, thereby allowing wire bonding to be performed on the top surface of the dummy pad 330.

[0051] Consistent with the scope of the present disclosure, the semiconductor device 300 may include a dielectric structure between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., the z direction in FIG. 3A ). The dielectric structure may extend laterally (e.g., the y direction in FIG. 3A ) and vertically (e.g., the z direction in FIG. 3A ). In some implementations shown in FIG. 3A , the dielectric structure includes an isolation structure 328, such as a BSTI, within the semiconductor layer 326. For example, the isolation structure 328 may include silicon oxide. The semiconductor device 300 may also include an interconnect structure 314 between the device layer 310 and the dielectric structure (e.g., the isolation structure 328 in FIG. 3A ) in the vertical direction (e.g., the z direction in FIG. 3A ). The interconnect structure 314 may extend in the vertical direction (e.g., the z direction in FIG. 3A ). The semiconductor layer 326 may be disposed between the dummy pad 330 and the interconnect structure 314 in the vertical direction. 3A, according to some embodiments, the isolation structures 328, interconnect structures 314, and dummy pads 330 are overlaid and are considered corresponding structures in this disclosure. In other words, for each dummy pad 330, the semiconductor device 300 may include a corresponding overlay isolation structure 328 and interconnect structure 314.

[0052] 3A , interconnect structure 314 can include bond contacts 320 and 318 in bonding layers 315 and 313, and device contact 316 in interconnect layer 311 of first structure 302. According to some embodiments, device contact 316 is disposed between bond interface 306 and device layer 310, and bond interface 306 is disposed vertically between dummy pad 330 and device layer 310. It is understood that in some embodiments, interconnect structure 314 can further include interconnect 322 in interconnect layer 323 of second structure 304.

[0053] 3A , the second structure 304 of the semiconductor device 300 can further include a via contact 324 extending vertically within the interconnect layer 323. The via contact 324 can include W. In some implementations, the via contact 324 contacts the interconnect structure 314 but is separated from the dummy pad 330 by an isolation structure 328. Thus, even if the device contact 316 of the interconnect structure 314 is not far enough from the functional circuit 312 in the device layer 310 to prevent ESD damage to the functional circuit 312 through the interconnect structure 314 and the via contact 324, the isolation structure 328 between the dummy pad 330 and the via contact 324 can still prevent ESD from propagating from the dummy pad 330 to the via contact 324. In some embodiments, the thickness (e.g., thickness in the vertical direction) of isolation structure 328 is between 500 nm and 1000 nm (e.g., 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, any range bounded at the lower end by any of these values, or any range defined by any two of these values).

[0054] In some implementations, the lateral dimension (e.g., in the y direction in FIG. 3A ) of the isolation structure 328 is larger than the lateral dimension (e.g., in the y direction in FIG. 3A ) of the dummy pad 330. As a result, even if defects may form in the semiconductor layer 326, the increased size of the isolation structure 328 (e.g., BSTI) can reduce the risk of burn-in between the dummy pad 330 and the semiconductor layer 326. In some implementations, the distance d between the edge of the dummy pad 330 and the isolation structure 328 in the lateral direction (e.g., the y direction in FIG. 3A ) is greater than 1 μm, for example, between 1 μm and 5 μm (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, any range bounded at the bottom by any of these values, or any range defined by any two of these values).

[0055] 3B illustrates a cross-sectional side view of a three-dimensional memory device 301 having dummy pads 330 and pads 346 in accordance with some aspects of the present disclosure. The three-dimensional memory device 301 may be an example of the semiconductor device 300 of FIG. 3A, such as a NAND flash memory device. For ease of explanation, components that are the same as those described above with respect to FIG. 3A are not repeated.

[0056] As shown in FIG. 3B , three-dimensional memory device 301 can further include pad 346, via contact 344 below and in contact with pad 346, via contact 342 below and in contact with via contact 344, and interconnect structure 340 below and in contact with via contact 342. According to some embodiments, pad 346, via contacts 344 and 342, and interconnect structure 340 are stacked. As described in detail below with respect to the manufacturing process, pad 346 and dummy pad 330 can be formed by the same process and are coplanar. Similarly, interconnect structure 314 and interconnect structure 340 can be formed by the same process and are coplanar, and via contact 324 and via contact 342 can be formed by the same process and are coplanar. According to some embodiments, via contact 344 extends through isolation structure 328 (e.g., BSTI) to connect pad 346 and via contact 342. Thus, unlike dummy pad 330 and interconnect structure 314, which are electrically isolated by isolation structure 328, pad 346 can be electrically connected to interconnect structure 340 through via contacts 344 and 342. Similar to via contact 324, via contacts 344 and 342 can include W.

[0057] 3B, device layer 310 may further include functional circuitry 312 electrically connected to interconnect structure 314, distinct from functional circuitry 338, which is electrically isolated from interconnect structure 340. As a result, pad 346 may be electrically connected to functional circuitry 338 in device layer 310 through via contacts 344 and 342 and interconnect structure 340, thereby facilitating operation of functional circuitry 338. Although not shown, it is understood that device layer 310 may further include ESD circuitry electrically connected to functional circuitry 338 and interconnect structure 340 to avoid ESD damage from pad 346.

[0058] In some embodiments, three-dimensional memory device 301 further includes a memory cell array, such as an array of NAND memory strings 350, above junction interface 306 in second structure 304. In some embodiments, NAND memory strings 350 are disposed vertically between semiconductor layer 326 and junction interface 306. In some embodiments, semiconductor layer 326 is disposed above memory stack 348 and in contact with the sources of NAND memory strings 350. In some embodiments, each NAND memory string 350 is a “charge trap” type NAND memory string including any suitable channel structure. It is understood that NAND memory strings 350 are not limited to “charge trap” type NAND memory strings and may, in other examples, be “floating gate” type NAND memory strings.

[0059] According to some embodiments, each NAND memory string 350 extends vertically through multiple pairs, each including a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stack structure, e.g., memory stack 348. The memory stack 348 and the via contacts 324 and 342 may be coplanar. Thus, the via contacts 324 and 342 may also be referred to as "array contacts" because they are coplanar with the memory cell array in the memory stack 348. According to some embodiments, the interleaved conductive and dielectric layers in the memory stack 348 alternate vertically. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The adhesion layer may include a conductive material, such as titanium nitride (TiN), which can improve adhesion between the gate electrode and the gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line and terminate in one or more staircase structures in the memory stack 348.

[0060] According to some embodiments, compared to pad 346, which is electrically connected to corresponding interconnect structure 340 through two via contacts 344 and 342, dummy pad 330 is separated from via contact 324 by isolation structure 328. In other words, according to some embodiments, one of the two via contacts covering dummy pad 330 (i.e., the one that is coplanar with via contact 344) is replaced by isolation structure 328 to ensure electrical isolation between dummy pad 330 and interconnect structure 314 and avoid ESD damage to functional circuit 312, even if the distance between interconnect structure 314 and functional circuit 312 is too close without ESD circuit protection of functional circuit 312.

[0061] To isolate the dummy pad 330 from the interconnect structure 314, one or both of the two via contacts covering the dummy pad 330 can be replaced with a dielectric structure. Instead of removing the via contact in contact with the dummy pad 330 as shown in FIGS. 3A and 3B , in other examples, the other via contact (e.g., 324) in contact with the interconnect structure 314 can be removed to achieve the same result. FIG. 4 shows a cross-sectional side view of another semiconductor device 400 having a dummy pad 330 in accordance with some aspects of the present disclosure. The semiconductor device 400 may be another example of the semiconductor device 200. For ease of explanation, the same components as those described above with respect to FIG. 3A are not repeated.

[0062] Consistent with the scope of the present disclosure, the semiconductor device 400 may include a dielectric structure between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., the z direction in FIG. 4 ). The dielectric structure may extend laterally (e.g., the y direction in FIG. 4 ) and vertically (e.g., the z direction in FIG. 4 ). In some implementations shown in FIG. 4 , the dielectric structure includes a dielectric layer 401 within the interconnect layer 323. For example, the dielectric layer 401 may include silicon oxide. The semiconductor device 400 may also include an interconnect structure 314 between the device layer 310 and the dielectric structure (e.g., the dielectric layer 401 in FIG. 4 ) in the vertical direction (e.g., the z direction in FIG. 4 ). The interconnect structure 314 may extend in the vertical direction (e.g., the z direction in FIG. 4 ). As shown in FIG. 4 , according to some implementations, the dielectric layer 401, the interconnect structure 314, and the dummy pad 330 are superimposed and are considered corresponding structures in the present disclosure. In other words, for each dummy pad 330 , the semiconductor device 400 may include a corresponding overlay dielectric layer 401 and interconnect structure 314 .

[0063] Unlike the semiconductor device 300 of FIG. 3A , the semiconductor device 400 may further include a via contact 402 that contacts an underlying dummy pad 330. In some embodiments, the via contact 402 extends vertically (e.g., in the z-direction in FIG. 4 ) through the isolation structure 328. The via contact 402 may include a W. Because the via contact 402 also penetrates the semiconductor layer 326, in some examples it may be referred to as a “through-silicon via (TSV).” However, in contrast to the semiconductor device 300 of FIG. 3A , which includes a via contact 324 that is above and in contact with the interconnect structure 314, according to some embodiments, the semiconductor device 400 does not include the via contact 324, but instead includes a dielectric layer 401 between the via contact 402 and the interconnect structure 314. That is, the via contact 402 may be separated from the interconnect structure 314 by the dielectric layer 401. Thus, even if the device contact 316 of the interconnect structure 314 is not far enough from the functional circuit 312 in the device layer 310 to prevent ESD damage to the functional circuit 312 through the interconnect structure 314, the dielectric layer 401 between the interconnect structure 314 and the via contact 402 can still prevent ESD from propagating from the dummy pad 330 to the interconnect structure 314. In some implementations, the thickness (e.g., thickness in the vertical direction) of the isolation structure 328 is between 1000 nm and 2000 nm (e.g., 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, 1900 nm, 2000 nm, any range bounded at the bottom by any of these values, or any range defined by any two of these values).

[0064] In some implementations, the lateral dimension (e.g., in the y direction in FIG. 4 ) of the isolation structure 328 is larger than the lateral dimension (e.g., in the y direction in FIG. 4 ) of the dummy pad 330. As a result, even if defects may form in the semiconductor layer 326, the increased size of the isolation structure 328 (e.g., BSTI) can reduce the risk of burn-in between the dummy pad 330 and the semiconductor layer 326. In some implementations, the distance d between the edge of the dummy pad 330 and the isolation structure 328 in the lateral direction (e.g., the y direction in FIG. 4 ) is greater than 1 μm, for example, between 1 μm and 5 μm (e.g., 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, any range bounded at the bottom by any of these values, or any range defined by any two of these values).

[0065] Although not shown, it is understood that in some examples, both via contacts 324 and 402 covering dummy pad 330 can be removed and replaced with, for example, isolation structure 328 and dielectric layer 401, thereby isolating dummy pad 330 from interconnect structure 314 by isolation structure 328 and dielectric layer 401 to prevent ESD damage from dummy pad 330 to functional circuit 312.

[0066] 5 illustrates a cross-sectional side view of yet another semiconductor device 500 having dummy pads 330 in accordance with some aspects of the present disclosure. The semiconductor device 500 may be an example of the semiconductor device 100. As illustrated in FIG. 5 , the semiconductor device 500 is a bonded chip including a first structure 302 and a second structure 304 stacked on top of each other in different planes in the vertical direction (e.g., the z-direction). According to some embodiments, the first and second structures 302 and 304 are bonded at a bonding interface 306 therebetween.

[0067] 5, first structure 302 may include a substrate 308, which may include silicon (e.g., single crystal silicon), SiGe, GaAs, Ge, SOI, or any other suitable material. In some embodiments, substrate 308 includes single crystal silicon, which may be a portion of the wafer on which first structure 302 is fabricated, either at its original thickness or thinned. In some embodiments, first substrate 302 includes polysilicon, for example, a semiconductor layer that replaces a portion of the wafer on which first structure 302 is fabricated.

[0068] As shown in FIG. 5 , the first structure can include a device layer 310 over a substrate 308. In some implementations, the device layer 310 includes functional circuitry 312 and ESD circuitry 502. In some implementations, the semiconductor device 500 is a NAND flash memory device in which memory cells are formed in an array of NAND memory strings, and the functional circuitry 312 is peripheral circuitry (also known as control and sensing circuitry) that facilitates operation of the NAND memory strings and includes any suitable digital, analog, and / or mixed-signal circuitry. For example, the peripheral circuitry can include one or more of: a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an input / output circuit, a charge pump, a voltage source or voltage generator, a current or voltage reference, any portion (e.g., sub-circuit) of the aforementioned functional circuitry, or any active or passive component (e.g., transistor, diode, resistor, or capacitor) of the circuitry. The functional circuitry 312 can use, for example, CMOS technology, which can be implemented in a logic process in any suitable technology node.

[0069] The ESD circuit 502 can use ESD suppression components to reduce ESD voltages below a certain limit. These components can be connected in parallel to vulnerable lines. When an ESD strike occurs, the ESD diodes can break down to create a low-impedance path, limiting peak voltages and currents by diverting current flow to ground. In one example, as shown in FIG. 6A, the ESD circuit 502 can include a resistor R, a capacitor C, and a transistor Q. The resistor R and the capacitor C can form a resistor-capacitor circuit (RC circuit), and the transistor Q can be a discharge transistor. When an electrostatic signal is input to the electrostatic terminal A, the output terminal of the resistor-capacitor circuit can become a logic high level, which can turn on the transistor Q and conduct ESD through the transistor Q. In another example, as shown in FIG. 6B, the ESD circuit 502 can include a resistor R, a capacitor C, a transistor Qa, a transistor Qb, and a transistor Qc. The resistor R and the capacitor C can form an RC circuit, the transistor Qa and the transistor Qb can form an inverter, and the transistor Qc can be a discharge transistor. When an electrostatic signal is input to the electrostatic terminal A, the output terminal of the resistor-capacitor circuit becomes a logic low level, the output terminal of the inverter becomes a logic high level, the transistor Qc turns on, and ESD can be conducted through the transistor Qc.

[0070] As shown in FIG. 5 , in some implementations, the first structure 302 further includes an interconnect layer 311 above the device layer 310 to transfer electrical signals to and from the device layer 310. The interconnect layer 311 can reside vertically between the bond interface 306 and the device layer 310 (including the functional circuitry 312 and the ESD circuitry 502). The interconnect layer 311 can include multiple interconnects and one or more ILD layers. That is, the interconnect layer 311 can include horizontal lines and via contacts in multiple ILD layers. Although not shown in FIG. 5 , it is understood that the functional circuitry 312 in the device layer 310 can be electrically connected to any other suitable functional circuitry through the interconnects in the interconnect layer 311. The interconnects in the interconnect layer 311 can include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The ILD layers in the interconnect layer 311 may include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 311 include device contacts 316, for example, in the metal 3-5 (M3-M5) layers. The device contacts 316 may include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials.

[0071] 5, the first structure 302 can further include a bonding layer 313 at and above the bonding interface 306 in contact with the interconnect layer 311. The bonding layer 313 can include a plurality of bonding contacts 318 and a dielectric that electrically isolates the bonding contacts 318. The bonding contacts 318 can include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. In some embodiments, the bonding contacts 318 of the bonding layer 313 include Cu. The remaining regions of the bonding layer 313 can be formed of a dielectric, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contact 318 and the surrounding dielectric within the bonding layer 313 can be used for hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive), and can simultaneously obtain a metal-metal (e.g., Cu-Cu) bond and a dielectric-dielectric (e.g., SiO2 to SiO2) bond.

[0072] As shown in FIG. 5 , the second structure 304 may include a bonding layer 315 at the bonding interface 306, for example, on the opposite side of the bonding interface 306 from the bonding layer 313 of the first structure 302. The bonding layer 315 may include a plurality of bonding contacts 320 and a dielectric that electrically insulates the bonding contacts 320. The bonding contacts 320 may include a conductive material such as Cu. The remaining regions of the bonding layer 315 may be formed of a dielectric material such as silicon oxide. The bonding contacts 320 and the surrounding dielectric within the bonding layer 315 may be used for hybrid bonding. In some embodiments, the bonding interface 306 is where the bonding layers 313 and 315 meet and bond. In practice, the bonding interface 306 may be a layer having a certain thickness that includes the top surface of the bonding layer 313 of the first structure 302 and the bottom surface of the bonding layer 315 of the second structure 304.

[0073] As shown in FIG. 5 , the second structure 304 can further include an interconnect layer 323 above the bonding layer 315 to transfer electrical signals. The interconnect layer 323 can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. Although not shown in FIG. 5 , in some examples, the interconnects in the interconnect layer 323 also include local interconnects, such as bit line contacts and word line contacts. The interconnect layer 323 can further include one or more ILD layers in which horizontal lines and via contacts can be formed. The interconnects in the interconnect layer 323 can include conductive materials, including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer 323 can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some implementations, the interconnects in the interconnect layer 323 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (reduced defects, e.g., voids) among conductive metal materials.

[0074] 5, second structure 304 can further include a semiconductor layer 326 above interconnect layer 323. Semiconductor layer 326 can include a semiconductor material. In some implementations, semiconductor layer 326 is a thinned silicon substrate having single crystal silicon. In some implementations, semiconductor layer 326 is a deposited polysilicon layer that replaces at least a portion of the silicon substrate having single crystal silicon. It is understood that in some examples, trench isolation and doped regions (not shown) may also be formed in semiconductor layer 326. It is also understood that in some examples, semiconductor layer 326 may include multiple vertical semiconductor layers with dielectric layers formed therebetween.

[0075] 5, the second structure 304 may further include a pad-out layer 327 above the semiconductor layer 326. The pad-out layer 327 may include a dummy pad 330, one or more ILD layers 332 (e.g., a silicon oxide layer and a silicon nitride layer), and a protective layer 334 (e.g., a polyimide layer) on the top surface of the semiconductor device 500. The pad-out layer 327 and the interconnect layer 323 may be formed on either side of the semiconductor layer 326. In some implementations, an opening 336 is formed through the protective layer 334 and the ILD layer 332 in the pad-out layer 327 to expose the dummy pad 330, thereby allowing wire bonding to be performed on the top surface of the dummy pad 330.

[0076] Consistent with the scope of the present disclosure, the semiconductor device 500 may include an interconnect structure 314 between the device layer 310 and the dummy pad 330 in the vertical direction (e.g., the z-direction in FIG. 5 ), where the dummy pad 330 is connected to the ESD circuit 502 in the device layer 310 via at least the interconnect structure 314. Meanwhile, according to some embodiments, the dummy pad 330 is separated from the functional circuit 312 in the device layer 310. The interconnect structure 314 may extend in the vertical direction (e.g., the z-direction in FIG. 5 ). The semiconductor layer 326 may be disposed between the dummy pad 330 and the interconnect structure 314 in the vertical direction. As shown in FIG. 5 , according to some embodiments, the interconnect structure 314 and the dummy pad 330 are overlaid and are considered corresponding structures in the present disclosure. In other words, for each dummy pad 330, the semiconductor device 500 may include a corresponding overlay interconnect structure 314.

[0077] 5 , interconnect structure 314 can include bond contacts 320 and 318 in bonding layers 315 and 313, and device contact 316 in interconnect layer 311 of first structure 302. According to some embodiments, device contact 316 is disposed between bond interface 306 and device layer 310, and bond interface 306 is disposed vertically between dummy pad 330 and device layer 310. It is understood that in some embodiments, interconnect structure 314 can further include interconnect 322 in interconnect layer 323 of second structure 304.

[0078] As shown in FIG. 5 , the second structure 304 of the semiconductor device 500 may further include a via contact 324 extending vertically within the interconnect layer 323. The via contact 324 may include W. In some embodiments, the via contact 324 is in contact with the interconnect structure 314. That is, the via contact 324 may be disposed between the dummy pad 330 and the interconnect structure 314 and connected to the interconnect structure 314. The second structure 304 of the semiconductor device 500 may further include a spacer 504 within the semiconductor layer 326 and a via contact 402 extending vertically through the spacer 504. The spacer 504 may include a dielectric material such as silicon oxide or silicon nitride. In some embodiments, the via contact 402 is in contact with the dummy pad 330 and the via contact 324 at opposite ends. That is, the via contact 402 may electrically connect the dummy pad 330 and the via contact 324. The via contact 402 may also include W. As a result, the dummy pad 330 can be electrically connected to the ESD circuit 502 in the device layer 310 through at least the interconnect structure 314 and the via contacts 324 and 402. Therefore, ESD from the dummy pad 330 can be propagated to and mitigated by the ESD circuit 502 to prevent its damage to the functional circuit 312.

[0079] 7A-7E illustrate a manufacturing process for forming a semiconductor device having dummy pads according to some embodiments of the present disclosure. FIGS. 8A-8E illustrate a manufacturing process for forming another semiconductor device having dummy pads according to some embodiments of the present disclosure. FIG. 9 illustrates a flowchart of a method 900 for forming a semiconductor device having dummy pads according to some embodiments of the present disclosure. Examples of semiconductor devices depicted in FIGS. 7A-7E, 8A-8E, and 9 include semiconductor devices 300, 301, and 400 depicted in FIGS. 3A, 3B, and 4. FIGS. 7A-7E, 8A-8E, and 9 are collectively described below. It is understood that the steps illustrated in method 900 are not exhaustive, and that other steps can be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in a different order than that depicted in FIG. 9.

[0080] Referring to FIG. 9, method 900 begins at step 902, where a device layer including functional circuits is formed. As shown in FIGS. 7A and 8A, a device layer 710 including functional circuits 712 and 738 is formed on a silicon substrate 708 having single-crystal silicon. The functional circuits 712 and 738 can be formed by multiple processes, including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical-mechanical polishing (CMP), and any other suitable process. In some embodiments, doped regions are formed in the silicon substrate 708 by, for example, ion implantation and / or thermal diffusion to function as wells and source / drain regions of transistors in the functional circuits 712 and 738. In some embodiments, isolation regions (e.g., shallow trench isolation (STI)) are also formed in the silicon substrate 708 by wet / dry etching and thin film deposition.

[0081] 9, the method 900 proceeds to step 904, where an interconnect structure is formed on the device layer and separated from the functional circuitry. In some embodiments, another interconnect structure is formed on the device layer and connected to the functional circuitry. The interconnect structure and the other interconnect structure can be formed by the same process.

[0082] 7A and 8A, an interconnect layer 711 is formed above the device layer 710. The interconnect layer 711 can include MEOL and / or BEOL interconnects within multiple ILD layers, such as device contacts 716, to provide electrical connection with functional circuitry 738 but not with functional circuitry 712. That is, device contacts 716 can connect to functional circuitry 738 but be decoupled from functional circuitry 712. In some implementations, the interconnect layer 711 includes multiple ILD layers and interconnects formed in multiple processes. For example, the interconnects within the interconnect layer 711 can include conductive material deposited by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The fabrication process for forming the interconnects can also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The ILD layer and interconnects shown in Figures 7A and 7B may be collectively referred to as interconnect layer 711. In some implementations, the interconnects, such as device contacts 716, in interconnect layer 711 comprise Cu, which has a relatively low resistivity among conductive metallic materials.

[0083] As shown in FIGS. 7A and 8A , a bonding layer 713 is formed above the interconnect layer 711. The bonding layer 713 can include a plurality of bonding contacts 718 surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the top surface of the interconnect layer 711 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The bonding contacts 718 that pass through the dielectric layer and contact the interconnects in the interconnect layer 711 can then be formed by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion layer, a barrier layer, and / or a seed layer before depositing the conductor. For example, an adhesion layer can improve the adhesion of a conductor to avoid defects, a barrier layer can prevent metal ions (e.g., Cu ions) from diffusing from the conductor to other structures to cause contamination, and a seed layer can facilitate the deposition of a conductor (e.g., Cu) in a contact hole to improve deposition quality and speed.

[0084] As shown in FIGS. 7A and 8A, a stack structure such as a memory stack 748 including alternating conductive and dielectric layers is formed on a silicon substrate 726. To form the memory stack 748, in some embodiments, a dielectric stack (not shown) including alternating sacrificial layers (not shown) and dielectric layers is formed on the silicon substrate 726. In some embodiments, each sacrificial layer includes a layer of silicon nitride, and each dielectric layer includes a layer of silicon oxide. The interleaved sacrificial and dielectric layers can be formed by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The memory stack 748 can then be formed by replacing the sacrificial layers with conductive layers using a gate replacement process, e.g., wet / dry etching of the sacrificial layers selective to the dielectric layers, and filling the resulting recesses with the conductive layers. In some embodiments, each conductive layer includes a metal layer, such as a layer of W. It will be appreciated that in some examples, memory stack 748 may be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process. In some implementations, a pad oxide layer comprising silicon oxide (e.g., thermally grown local oxidation of silicon (LOCOS)) is formed between memory stack 748 and silicon substrate 726.

[0085] 7A and 8A, NAND memory strings 750 are formed, each extending vertically through the memory stack 748. In some embodiments, the fabrication process for forming the NAND memory string 750 includes forming a channel hole in the silicon substrate 726 through the memory stack 748 (or dielectric stack) using dry etching and / or wet etching, such as deep reactive ion etching (DRIE), and then filling the channel hole with multiple layers, such as memory films (e.g., tunneling layer, storage layer, and blocking layer) and semiconductor layers, using a thin film deposition process, such as ALD, CVD, PVD, or any combination thereof. It is understood that the details of fabricating the NAND memory string 750 may vary depending on the type of channel structure of the NAND memory string 750, and therefore will not be detailed for ease of explanation.

[0086] As shown in FIGS. 7A and 8A , a bonding layer 715 is formed above the memory stack 748. The bonding layer 715 can include a plurality of bonding contacts 720 surrounded by a dielectric. In some implementations, a dielectric layer is deposited on the top surface of the memory stack 748 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. The bonding contacts 720 can then be formed through the dielectric layer by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing an adhesion layer, a barrier layer, and / or a seed layer before depositing the conductor.

[0087] As shown in FIGS. 7A and 8A , a silicon substrate 726 and components formed thereon (e.g., a memory stack 748 and a NAND memory string 750 formed therethrough) are flipped upside down. The downward-facing bonding layer 715 is bonded, i.e., face-to-face, with the upward-facing bonding layer 713, thereby forming a bonding interface 706. That is, the silicon substrate 708 and components formed thereon can be bonded face-to-face with the silicon substrate 726 and components formed thereon, such that the bonding contacts 718 of the bonding layer 713 contact the bonding contacts 720 of the bonding layer 715 at the bonding interface 706. In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and / or a thermal treatment, is applied to the bonding surfaces before bonding. In some embodiments, the silicon substrate 726 is thinned after bonding to form a thinned silicon substrate, also referred to herein as a semiconductor layer 726.

[0088] As a result of bonding, e.g., hybrid bonding, bond contacts 718 and 720 on either side of bond interface 706 can intermix. After bonding, bond contacts 718 in bonding layer 713 and bond contacts 720 in bonding layer 715 can align and contact each other to form two interconnect structures 714 and 740. Interconnect structure 714 or 740 can include bond contacts 718 and 720 across bond interface 706 and device contact 716. As shown in Figures 7A and 8A, interconnect structure 714 is formed on device layer 710 and is separated from functional circuitry 712, while interconnect structure 740 is formed on device layer 710 and is connected to functional circuitry 738.

[0089] 9, the method 900 proceeds to step 906, where a first via contact is formed on and connected to the interconnect structure. In some embodiments, another first via contact is formed on and connected to another interconnect structure. The first via contact and the other first via contact may be formed by the same process.

[0090] As shown in FIG. 7A , prior to bonding, via contacts 724 and 742 are formed, for example, by the same process as forming word line contacts through memory stack 748. Via contacts 724 and 742 can then be formed through the dielectric layer by first patterning contact holes through the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., W). In some implementations, filling the contact holes includes depositing an adhesion layer, a barrier layer, and / or a seed layer before depositing the conductor. After bonding, via contact 724 can be connected to and formed on interconnect structure 714, as shown in FIG. 7A . Similarly, via contact 742 can be connected to and formed on interconnect structure 740.

[0091] 9, the method 900 proceeds to step 908, where an isolation structure is formed over the first via contact. In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, exposing the first via contact and the other first via contact, and a dielectric layer is deposited to fill the trench.

[0092] 7A, a portion of semiconductor layer 726 is removed to expose one end of via contacts 724, 742 to form trench 727. Trench 727 can be formed by etching semiconductor layer 726 using, for example, dry etching and / or wet etching, to remove a portion of semiconductor layer 726 that covers via contacts 724 and 742 until via contacts 724 and 742 are exposed.

[0093] As shown in Figure 7B, a dielectric layer is filled within trench 727 (shown in Figure 7A). For example, a dielectric layer, such as silicon oxide, may be deposited to fill trench 727 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. Thus, as shown in Figure 7B, isolation structures 728 may be formed over via contacts 724 and 742 as part of the deposited dielectric layer.

[0094] In some embodiments, a second via contact is formed on and in contact with the other first via contact and extending through the isolation structure. To form the second via contact, in some embodiments, a portion of the isolation structure is removed to form a hole to expose the other first via contact but not the first via contact, and a metal layer is deposited to fill the hole. The metal layer can include W.

[0095] As shown in FIG. 7C , hole 746 is formed by removing a portion of isolation structure 728 to expose one end of via contact 742, but not via contact 724. Hole 746 may be formed by etching isolation structure 728 using, for example, dry etching and / or wet etching, to selectively remove the portion of isolation structure 728 that covers via contact 742, but not via contact 724, until the via contact 742 is exposed. First, an etching mask may be patterned using a photolithography process to expose only the portion of isolation structure 728 that covers via contact 742, but not via contact 724. The etching mask may then protect the portion of isolation structure 728 that covers via contact 724 during the etching process. It will be understood that in some examples, other holes 746 may also be formed by the same process that forms hole 747, for example, to expose components within memory stack 748, such as the source end of a slit structure or NAND memory string 750.

[0096] As shown in FIG. 7D , hole 746 (shown in FIG. 7C ) is filled with a metal layer, such as W. For example, a metal layer, such as W, may be deposited to fill hole 746 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. Accordingly, via contact 744 may be formed through isolation structure 728 over and in contact with via contact 742, as shown in FIG. 7D . In contrast, no via contact may be formed over and in contact with via contact 724, as shown in FIG. 7D . It will be understood that in some examples, other via contacts 749 may also be formed over and in contact with components in memory stack 748, such as the source end of a slit structure or a NAND memory string 750, by the same process that forms via contact 744.

[0097] 9, the method 900 proceeds to step 910, where a dummy pad is formed on the isolation structure and separated from the first via contact by the isolation structure. In some embodiments, a pad is formed on and in contact with the second via contact. The dummy pad and the pad can be formed by a similar process.

[0098] 7D, a pad layer 729, such as aluminum, is deposited on the via contacts 744. For example, a metal layer, such as aluminum, can be deposited on the via contacts 744 and 749 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0099] As shown in FIG. 7E, pad layer 729 (shown in FIG. 7D ) is patterned to form dummy pads 730 and pads 745. Pads 745 may be formed on and in contact with via contacts 744 and may therefore be electrically connected to functional circuitry 738 in device layer 710 through via contacts 744 and 742 and interconnect structure 740. In contrast, dummy pads 730 may be formed on and separated from via contacts 724 by isolation structure 728. Thus, dummy pads 730 may be electrically separated from interconnect structure 714. To form dummy pads 730 and pads 745, pad layer 729 may be subjected to a patterning process (e.g., photolithography and dry / wet etching of pad layer 729). A dielectric layer 732 (e.g., comprising silicon nitride) and a protective layer 734 (e.g., comprising polyimide) can then be formed over the dummy pads 730 and 745, followed by a patterning process to form openings 736 and 746 through the dielectric layer 732 and the protective layer 734 to expose the dummy pads 730 and 745, respectively.

[0100] It is understood that in some instances, a dielectric layer is formed over the interconnect structure, distinct from step 906 where a first via contact is formed on and connected to the interconnect structure.

[0101] 8A, a dielectric layer 801 is formed on interconnect structure 714. That is, according to some embodiments, via contacts 742 are formed only on interconnect structure 740 and connected to interconnect structure 714, but are not formed in or connected to the interconnect structure.

[0102] In some embodiments, an isolation structure is formed on the other first via contact. In some embodiments, to form the isolation structure, a portion of the semiconductor layer is removed to form a trench, exposing the other first via contact, and a dielectric layer is deposited to fill the trench.

[0103] 8A, trench 727 is formed by removing a portion of semiconductor layer 726 to expose one end of via contact 742. Trench 727 can be formed by etching semiconductor layer 726 using, for example, dry etching and / or wet etching, to remove a portion of semiconductor layer 726 that covers via contact 742 until via contact 742 is exposed.

[0104] As shown in Figure 8B, a dielectric layer is filled within trench 727 (shown in Figure 8A). For example, a dielectric layer, such as silicon oxide, may be deposited to fill trench 727 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. Thus, isolation structure 728 may be formed over via contact 742 as part of the deposited dielectric layer, as shown in Figure 8B.

[0105] In some embodiments, a second via contact is formed that extends through the isolation structure. In some embodiments, another second via contact is formed on and connected to the other first via contact and extends through the isolation structure. To form the second via contact and the other second via contact, in some embodiments, a portion of the isolation structure is removed to form a hole that penetrates the isolation structure, and a metal layer is deposited to fill the hole. The metal layer can include W.

[0106] 8C , holes 746 and 802 are formed by removing portions of isolation structure 728. Hole 746 can expose one end of via contact 742, and hole 802 can be aligned with interconnect structure 714. Holes 746 and 802 can be formed, for example, by etching isolation structure 728 using dry etching and / or wet etching to selectively remove the portion of isolation structure 728 covering via contact 742 and the portion of isolation structure 728 aligned with interconnect structure 714 until exposing via contact 742. An etch mask can first be patterned using a photolithography process to expose the portion of isolation structure 728 covering via contact 742 and the portion of isolation structure 728 aligned with interconnect structure 714. It will be understood that in some examples, other holes 747 can also be formed by the same process that forms holes 746 and 802 to expose components in memory stack 748, such as the source end of a slit structure or NAND memory string 750.

[0107] As shown in FIG. 8D , holes 746 and 802 (shown in FIG. 8C ) are filled with a metal layer, such as W. For example, a metal layer, such as W, can be deposited to fill holes 746 and 802 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. Accordingly, via contact 744 can be formed over and in contact with via contact 742 through isolation structure 728, as shown in FIG. 8D . Another via contact 804 can be formed through isolation structure 728 to land on dielectric layer 801 and over interconnect structure 714, as shown in FIG. 8D . It will be understood that in some examples, another via contact 749 can also be formed over and in contact with a component in memory stack 748, such as the source end of a slit structure or a NAND memory string 750, by the same process that forms via contacts 744 and 804.

[0108] In some embodiments, a dummy pad is formed on and in contact with a second via contact. In some embodiments, a pad is formed on and in contact with another second via contact. The dummy pad and the pad can be formed by a similar process.

[0109] 8D, a pad layer 729, such as aluminum, is deposited on the via contacts 744 and 804. For example, a metal layer, such as aluminum, can be deposited on the via contacts 744, 804, and 749 by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0110] As shown in FIG. 8E, pad layer 729 (shown in FIG. 8D ) is patterned to form dummy pads 730 and pads 745. Pads 745 may be formed on and in contact with via contacts 744 and thus may be electrically connected to functional circuitry 738 in device layer 710 through via contacts 744 and 742 and interconnect structure 740. Dummy pads 730 may be formed on and in contact with via contacts 804. However, dummy pads 730 and via contacts 804 may be separated from interconnect structure 714 by dielectric layer 801. Thus, dummy pads 730 may be electrically separated from interconnect structure 714. A patterning process (e.g., photolithography and dry / wet etching of pad layer 729) may be performed on pad layer 729 to form dummy pads 730 and pads 745. Subsequently, a dielectric layer 732 (e.g., comprising silicon nitride) and a protective layer 734 (e.g., comprising polyimide) can be formed on the dummy pad 730 and the pad 745, and then a patterning process can be performed to form openings 736 and 746 that penetrate the dielectric layer 732 and the protective layer 734, exposing the dummy pad 730 and the pad 745, respectively.

[0111] The foregoing descriptions of specific embodiments may be readily modified and / or adapted for a variety of applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0112] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. a device layer; A dummy pad and a dielectric structure extending vertically between the device layer and the dummy pad; an interconnect structure extending in the vertical direction between the device layer and the dielectric structure, wherein the dielectric structure, the interconnect structure, and the dummy pad are superimposed; A semiconductor device comprising:

2. a semiconductor layer between the dummy pad and the interconnect structure; the dielectric structure comprises an isolation structure within the semiconductor layer; The semiconductor device of claim 1 .

3. The semiconductor device of claim 2 , wherein the isolation structure has a lateral dimension greater than a lateral dimension of the dummy pad.

4. The semiconductor device of claim 2 or 3, further comprising a first via contact in contact with the interconnect structure and separated from the dummy pad by the isolation structure.

5. The semiconductor device of claim 4 , wherein the first via contact comprises tungsten.

6. a second via contact extending in the vertical direction and contacting the dummy pad; the dielectric structure comprises a dielectric layer between the second via contact and the interconnect structure. The semiconductor device of claim 1 .

7. The semiconductor device of claim 6 , wherein the second via contact is separated from the interconnect structure by the dielectric layer.

8. The semiconductor device of claim 6 or 7, wherein the second via contact comprises tungsten.

9. The semiconductor device of claim 1 , further comprising a bonding interface between the dummy pad and the device layer, the interconnect structure comprising a bonding contact at the bonding interface.

10. The semiconductor device of claim 9 , wherein the interconnect structure further comprises a device contact between the bond interface and the device layer.

11. Pads and another second via contact contacting the pad; another first via contact in contact with the another second via contact; another interconnect structure contacting the other first via contact and the device layer; The semiconductor device according to claim 1 , further comprising:

12. the pad and the dummy pad are on the same plane; the interconnect structure and the other interconnect structure are coplanar; The semiconductor device of claim 11.

13. a device layer comprising electrostatic discharge (ESD) circuitry and functional circuitry; a dummy pad separated from the functional circuit; an interconnect structure between the device layer and the dummy pad, the dummy pad being connected to the ESD circuitry through at least the interconnect structure; A semiconductor device comprising:

14. The semiconductor device of claim 13 , further comprising a first via contact between the dummy pad and the interconnect structure and connected to the interconnect structure.

15. a semiconductor layer between the dummy pad and the first via contact; spacers within the semiconductor layer; a second via contact contacting the dummy pad and extending through the spacer; The semiconductor device of claim 14 further comprising:

16. 16. The semiconductor device of claim 15, wherein the first and second via contacts comprise tungsten.

17. 17. The semiconductor device of claim 15 or 16, wherein the dummy pad is connected to the ESD circuitry through at least the interconnect structure and the first and second via contacts.

18. 18. The semiconductor device of claim 16 or 17, further comprising a bonding interface between the dummy pad and the device layer, the interconnect structure comprising a bonding contact at the bonding interface.

19. 20. The semiconductor device of claim 18, wherein the interconnect structure further comprises a device contact between the bond interface and the device layer.

20. 1. A method for forming a semiconductor device, comprising: forming a device layer comprising functional circuitry; forming an interconnect structure on the device layer that is isolated from the functional circuitry; forming a first via contact on the interconnect structure, the first via contact being connected to the interconnect structure; forming an isolation structure on the first via contact; forming a dummy pad on the isolation structure, the dummy pad being separated from the first via contact by the isolation structure; A method comprising:

21. forming other interconnect structures on the device layer that are connected to the functional circuitry; forming another first via contact on the other interconnect structure, the first via contact being connected to the other interconnect structure; forming a second via contact on the other first via contact, the second via contact contacting the other first via contact and extending through the isolation structure; forming a pad on the second via contact to contact the second via contact; 21. The method of claim 20, further comprising:

22. forming the isolation structure includes: removing a portion of the semiconductor layer to form a trench and expose the first via contact and the other first via contact; depositing a dielectric layer to fill the trench; 22. The method of claim 21, comprising:

23. The step of forming the second via contact includes: removing a portion of the isolation structure to form a hole to expose the other first via contact but not the first via contact; depositing a metal layer to fill the hole; 22. The method of claim 21, comprising:

24. 24. The method of claim 23, wherein the metal layer comprises tungsten.

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