Local VDD and VSS power supply through dummy gate with gate tie-down and associated benefits

Abstract

The integrated circuit structure includes a power supply rail formed on the backside of the semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, the gate being of a type that is powered down by a power supply coupled from the power supply rail through the gate to the first frontside BEOL wire layer. A method of forming the integrated circuit structure includes forming a power supply rail on the backside of the semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type that is powered down by a power supply coupled from the power supply rail through the gate to the first frontside BEOL wire layer.

Description

[Technical Field]

[0001] The present invention relates generally to semiconductors, and more particularly to local VDD and VSS power supplies through dummy gates with gate tie-downs. [Background technology]

[0002] In semiconductor devices fabricated using a backside power distribution network (BSPDN), there are several areas that can be improved. For example, source / drain (S / D) epitaxial silicon (epi) areas may need to be connected to the backside through via-to-buried power rail (VBPR). As another example, and due to VBPR, separate S / D epitaxial silicon areas may only have access to one signal track above them (e.g., near the back end of line (BEOL) area).

[0003] Regarding VBPR and similar technologies, consider "Buried Power Rails and Back-side Power Grids: Arm CPU Power Delivery Network Design Beyond 5nm" by Divya Prasad et al., from the 2019 IEEE International Electron Devices Meeting (IEDM), which states the following about the Power Delivery Network (PDN): "A 3D integration technique is proposed to implement a powered backside PDN using tiny ('micro') through-silicon vias (μTSVs) located on buried rails to completely remove the overhead of power tap cells and the entire PDN from the front side (thereby decoupling the sharing of routing resources between signal and power delivery)." " and discusses multiple technologies, stating, "Three power rail technologies are considered in this study: traditional front-side (FS) PDN, front-side with buried power rails (FS-BPR), and back-side power delivery with buried power rails (BS-BPR)." FS-BPR and BS-BPR do not address the above issues and require many additional process steps. Summary of the Invention

[0004] This section is intended to be illustrative and not limiting.

[0005] In one exemplary embodiment, the integrated circuit structure includes a power supply rail formed on the backside of the semiconductor wafer and a front-side back-end-of-line (BEOL) wire layer connected to the power supply rail through a gate. The gate is of a type that is powered off by a power supply coupled from the power supply rail through the gate to a first front-side BEOL wire layer. This provides access to power and / or ground in the front-side BEOL wire layer without using vias to the backside power rail, thereby freeing up space to allow some source / drain (S / D) epitaxial regions to contact multiple signal tracks, one of which may be in a currently unaccessed area, and also allowing other S / D regions to be powered from tracks above them. The impact on manufacturing is minimal, and the technique can be combined with current techniques used in different locations on the semiconductor wafer, allowing both conventional and new structures to be used on the same wafer.

[0006] Another example is an integrated circuit structure according to the foregoing, wherein the gate is a first gate and the power supply rail is a first power supply rail. The integrated circuit structure further comprises a second power supply rail formed on the backside of the semiconductor wafer and another front-side BEOL wire layer connected to the second power supply rail through a second gate, the second gate being of a type that is powered down by a power supply coupled from the second power supply rail through the second gate to the another front-side BEOL wire layer. This allows multiple routing of power supplies to the front-side BEOL wire layer.

[0007] Another example is the integrated circuit structure according to the previous paragraph, where the first gate is an n-type gate, the power supply for the first gate is ground, and the second gate is a p-type gate, and the power supply for the first gate is power. Furthermore, the first and second gates may be formed adjacent to each other and separated by a gate cut formed between at least the adjacent first and second gates. This allows both power and ground to be routed, for example, to a front-side BEOL wire layer using adjacent gates.

[0008] Another example is an integrated circuit structure further comprising a front-side BEOL wire connected to one or more source / drain epitaxy silicon areas of a corresponding transistor. An additional example is an integrated circuit structure according to the previous sentence, where the front-side BEOL wire is connected to one or more source / drain epitaxy silicon areas of a corresponding transistor using one or more corresponding vias. An additional example is an integrated circuit structure according to the first sentence of this paragraph, where the front-side BEOL wire layer is connected to the front-side BEOL wire. What these provide is the ability for source / drain regions to access multiple signal tracks, including a signal track in an N2N (n-type to n-type) semiconductor area or a P2P (p-type to p-type) semiconductor area and another signal track in an NFET or PFET (respectively) area.

[0009] Another example is a method of forming an integrated circuit structure, comprising forming a power supply rail on the backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a front-side back-end-of-line (BEOL) wire layer connected to the power supply rail through the gate, the gate being of a type that is powered off by a power supply coupled from the power supply rail through the gate to a first front-side BEOL wire layer. This provides access to power and / or ground in the front-side BEOL wire layer without using vias-to-backside power rails, thereby freeing up space to allow some source / drain (S / D) epitaxial regions to contact multiple signal tracks, one of which may be in a currently unaccessed area, and also allowing other S / D regions to be powered from tracks above them. The impact on manufacturing is minimal, and this technique can be combined with current techniques used at different locations on the semiconductor wafer, allowing both conventional and new structures to be used on the same wafer.

[0010] Another example is the method according to the preceding paragraph, wherein forming a gate in the semiconductor wafer further comprises forming a plurality of gates on a substrate of the semiconductor wafer, and forming the plurality of gates includes performing gate patterning to pattern a plurality of gates on the substrate, of which the gate is one; performing source / drain epitaxy to form source / drain regions for the plurality of gates; performing interlayer dielectric deposition to cover at least the source / drain regions; and at least partially isolating the plurality of gates; and forming a front-side back-end-of-line (BEOL) wire layer, including forming BEOL interconnects; and bonding a carrier wafer to the substrate on which the plurality of gates are formed.

[0011] Another method comprises the method of the preceding paragraph, wherein forming a gate in the semiconductor wafer further comprises forming backside gate tie-down vias at edges of the gates and filling the backside gate tie-down vias with conductive material simultaneously as the conductive material forming the gates is formed, the method further comprises forming gate via contacts to connect the gates including the gate tie-down vias to a front-side back end of line (BEOL) wire layer, and the method further comprises connecting a power supply rail to the gate tie-down vias.

[0012] Another exemplary method further comprises forming source / drain contacts that contact and extend beyond corresponding source / drain regions to provide access to one of a signal track in a region between two doped regions of the same type and a signal track in a doped region.

[0013] What they provide is the ability for the source / drain regions to access multiple signal tracks, including a signal track that is in an N2N (n-type to n-type) semiconductor area or a P2P (p-type to p-type) semiconductor area and another signal track that is in an NFET or PFET (respectively) area.

[0014] Another method further comprises connecting one or more source / drain regions of a corresponding one or more others of the plurality of gates requiring power to one or more corresponding front-side BEOL wires, the one or more corresponding front-side BEOL wires being connected to a front-side back-end-of-line (BEOL) wire layer.

[0015] Another method comprises a method, wherein the gate is a first gate and the power supply rail is a first power supply rail, the method further comprising forming a second power supply rail formed on a back side of the semiconductor wafer, and forming another front-side BEOL wire layer connected to the second power supply rail through a second gate, the second gate being of a type that is powered down by a power supply coupled from the second power supply rail through the second gate to the another front-side BEOL wire layer, wherein the first gate is an n-type gate, the power supply for the first gate is ground, and the second gate is a p-type gate, and the power supply for the first gate is power.

[0016] A further method comprises the method of the preceding paragraph, except that forming the first and second gates comprises forming the first and second gates adjacent to one another, and the method comprises forming and filling a gate cut between the adjacent first and second gates.

[0017] These examples provide access to power and / or ground in the front-side BEOL wire layers without using vias to back-side power rails, thereby freeing up space to allow some source / drain (S / D) epitaxial regions to contact multiple signal tracks, one of which may be in a currently unaccessed area, and also allowing other S / D regions to be powered from tracks above them.

[0018] Furthermore, these methods can be combined with current techniques used at different locations on a semiconductor wafer, which means, for example, that current designs do not have to be modified to implement current improvements. [Brief explanation of the drawings]

[0019] [Figure 1A] FIG. 1 illustrates an example of a conventional POR integrated circuit structure. [Figure 1B]FIG. 1 illustrates an example of an integrated circuit structure according to an exemplary embodiment of the present disclosure.

[0020] [Figure 2A] 1 is a cross-sectional view X of the integrated circuit structure after forming NS and STI. [Figure 2B] 1 is a cross-sectional view Y1 of the integrated circuit structure after forming NS and STI. [Figure 2C] 1 is a cross-sectional view Y2 of the integrated circuit structure after forming NS and STI. [Figure 2D] FIG. 1 shows a top view layout of an integrated circuit structure and illustrates where cross sections X, Y1, and Y2 exist within this layout.

[0021] [Figure 3A] 1 is a cross-sectional view X of an integrated circuit structure after depositing and patterning an OPL and forming a gate tie-down opening. [Figure 3B] 4 is a cross-sectional view Y1 of the integrated circuit structure after depositing and patterning an OPL and forming gate tie-down openings. [Figure 3C] 4 is a cross-sectional view Y2 of the integrated circuit structure after depositing and patterning an OPL and forming gate tie-down openings. [Figure 3D] FIG. 1 shows a top view layout of an integrated circuit structure and illustrates where cross sections X, Y1, and Y2 exist within this layout.

[0022] [Figure 4A] Cross section X of the integrated circuit structure after OPL / HM removal, dummy gate formation, SiGe55 removal, BDI / spacer formation, NS recess, inner spacer formation, S / D epi formation, ILD deposition, and CMP. [Figure 4B] Cross-sectional view Y1 of the integrated circuit structure after removing OPL / HM, forming dummy gate, removing SiGe 55, forming BDI / spacer, recessing NS, forming inner spacers, forming S / D epi, depositing ILD, and performing CMP. [Figure 4C]Cross section Y2 of the integrated circuit structure after removing OPL / HM, forming dummy gate, removing SiGe55, forming BDI / spacer, recessing NS, forming inner spacers, forming S / D epi, depositing ILD, and performing CMP. [Figure 4D] FIG. 1 shows a top view layout of an integrated circuit structure and illustrates where cross sections X, Y1, and Y2 exist within this layout.

[0023] [Figure 5A] 1 is a cross-sectional view X of the integrated circuit structure after forming the gate cut. [Figure 5B] 4 is a cross-sectional view Y1 of the integrated circuit structure after forming the gate cut. [Figure 5C] 4 is a cross-sectional view Y2 of the integrated circuit structure after forming the gate cut. [Figure 5D] FIG. 1 shows a top view layout of an integrated circuit structure and illustrates where cross sections X, Y1, and Y2 exist within this layout.

[0024] [Figure 6A] 1 is a cross-sectional view X of an integrated circuit structure after removing the dummy gate, releasing the SiGe, and forming a replacement HKMG. [Figure 6B] 1 is a cross-sectional view Y1 of the integrated circuit structure after removing the dummy gate, releasing the SiGe, and forming a replacement HKMG. [Figure 6C] 4 is a cross-sectional view Y2 of the integrated circuit structure after removing the dummy gate, releasing the SiGe, and forming a replacement HKMG. [Figure 6D] FIG. 1 shows a top view layout of an integrated circuit structure and illustrates where cross sections X, Y1, and Y2 exist within this layout.

[0025] [Figure 7A] 1 is a cross-sectional view X of an integrated circuit structure after performing a MOL process to form a lower BEOL with VDD / VSS local supplies from dummy gate tie-downs. [Figure 7B]1 is a cross-sectional view Y1 of an integrated circuit structure after performing a MOL process to form a lower BEOL with VDD / VSS local supplies from dummy gate tie-downs. [Figure 7C] 10 is a cross-sectional view Y2 of the integrated circuit structure after performing the MOL process to form a lower BEOL with VDD / VSS local supplies from the dummy gate tie-downs.

[0026] [Figure 8A] 1 is a cross-sectional view X of an integrated circuit structure after forming more BEOL levels and bonding a carrier wafer. [Figure 8B] 4 is a cross-sectional view Y1 of the integrated circuit structure after forming more BEOL levels and bonding a carrier wafer. [Figure 8C] 4 is a cross-sectional view Y2 of the integrated circuit structure after forming more BEOL levels and bonding a carrier wafer.

[0027] [Figure 9A] 1 is a cross-sectional view X of the integrated circuit structure after flipping the wafer, removing the substrate, and stopping on the etch stop layer. [Figure 9B] 4 is a cross-sectional view Y1 of the integrated circuit structure after flipping the wafer, removing the substrate, and stopping on the etch stop layer. [Figure 9C] 4 is a cross-sectional view Y2 of the integrated circuit structure after flipping the wafer, removing the substrate, and stopping on the etch stop layer.

[0028] [Figure 10A] 1 is a cross-sectional view X of the integrated circuit structure after removal of the etch stop layer and removal of the remaining Si. [Figure 10B] 4 is a cross-sectional view Y1 of the integrated circuit structure after removing the etch stop layer and removing the remaining Si. [Figure 10C] 4 is a cross-sectional view Y2 of the integrated circuit structure after removing the etch stop layer and removing the remaining Si.

[0029] [Figure 11A] 1 is a cross-sectional view X of an integrated circuit structure after forming a backside ILD and forming a backside power rail. [Figure 11B] 4 is a cross-sectional view Y1 of the integrated circuit structure after forming a backside ILD and forming a backside power rail. [Figure 11C] 4 is a cross-sectional view Y2 of the integrated circuit structure after forming a backside ILD and forming a backside power rail.

[0030] [Figure 12A] 1 is a cross-sectional view X of the integrated circuit structure after forming a backside power distribution network layer. [Figure 12B] 4 is a cross-sectional view Y1 of the integrated circuit structure after forming the backside power distribution network layer. [Figure 12C] 4 is a cross-sectional view Y2 of the integrated circuit structure after forming the backside power distribution network layer.

[0031] [Figure 13A] FIG. 1 illustrates an example of a conventional POR integrated circuit structure. [Figure 13B] FIG. 1 illustrates an example of an integrated circuit structure according to an exemplary embodiment of the present disclosure.

[0032] [Figure 14] FIG. 10 provides a detailed top view layout of S / D contacts, VBPR, and VA. DETAILED DESCRIPTION OF THE INVENTION

[0033] Abbreviations that may be found in the specification and / or drawings are defined below at the end of the Detailed Description section.

[0034] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are example embodiments provided to enable any person skilled in the art to make or use the invention and do not limit the scope of the invention, which is defined by the claims.

[0035] This disclosure relates to front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL). An introduction to these concepts is presented next. FEOL includes processing of the active portion of the chip, i.e., the transistors that reside on the bottom of the chip. BEOL is the final stage of processing and refers to the metal layer interconnects that reside on the top portion of the chip. FEOL and BEOL are tied together by the MOL. The MOL is typically made up of metal structures that serve as contacts to the source, drain, and gate of the transistors. These structures connect to local interconnect layers in the BEOL.

[0036] Architectures that comprise the FEOL can include gate-all-around (GAA) nanosheet, forksheet, and complementary field-effect transistor (CFET) devices. These device architectures affect the local interconnect layer and require different BEOL materials (e.g., ruthenium (Ru), molybdenum (Mo), and metal alloys) and different integration schemes (e.g., hybrid metallization, semi-damascene, and hybrid height with zero-via structures). Vias-to-backside power rails (VBPRs) are part of the power distribution network and can be used in the MOL to route some terminals of transistors to the backside power distribution network to help reduce congestion in the lower BEOL.

[0037] Now that an introduction to the FEOL, MOL, and BEOL has been provided, as noted above, there are several areas in which semiconductor devices formed using backside power distribution networks (BSPDNs) can be improved. These are illustrated by figures and described below, but the following are challenges with conventional techniques: Source / drain (S / D) epitaxial silicon (epi) areas may need to be connected to the backside through via-to-backside power rails (VBPRs), and / or other S / D epitaxial silicon areas may only have access to one signal track above (e.g., near the back-end-of-line (BEOL) area). Furthermore, access to signal tracks within N2N or P2P regions typically does not exist. Therefore, gate tie-down to the backside power rail provides an opportunity to locally redesign the routing by powering from a dummy gate with a gate tie-down. These challenges are addressed herein, and a semiconductor device diagram illustrating a conventional POR (process of record) is described.

[0038] Consider Figure 1A, an example of a conventional POR integrated circuit structure 1. As indicated by reference numeral 10, S / D epi (epitaxial silicon area) 50 has access to only one signal track 55 above (e.g., near the BEOL layer). As indicated by reference numeral 15, S / D epi area 60 must be connected to the backside through VBPR 65, which is connected to VSS area 66. Due to the presence of the VBPR at the cell boundary (between S / D epi 50 and 60), the source / drain contacts (CA) on S / D epi 50 cannot freely extend into the cell boundary region to access other signal tracks above.

[0039] In contrast, Figure 1B is an example of integrated circuit structure 2 of an exemplary embodiment of the present specification. As indicated by reference numeral 20, S / D epitaxial layer 50 has free access to two signal tracks indicated by reference numeral 75. The tracks shown as connected to signal lines using via VA and contact CA are inside the N2N or P2P region. As indicated by reference numeral 30, S / D epitaxial layer 60 is powered from above by local VSS 25.

[0040] Techniques for eliminating VBPR for either or both VDD and VSS are described herein, which involve forming and using "dummy" gates to provide a bridge from the backside power supply rails to the frontside BEOL wiring. As will be described in further greater detail below, such dummy gates 1130 can be seen at least in FIG. 11B. A "dummy" gate is a gate that is turned off and not used as an active gate. Thus, the advantages described in the previous paragraph are made possible by the dummy gates described in this paragraph (and in further greater detail below).

[0041] Additionally, there are manufacturing advantages, one of which is that because the gates are already formed, it takes only a few additional steps to create one or more gates with corresponding gate tie-downs, which then provides the advantages described above and herein.

[0042] Additionally, the techniques herein are fully compatible with POR processes (e.g., as illustrated by FIG. 1A), meaning that the new features herein (including those in FIG. 1B) can be added without modifying the POR structure; in fact, both the POR structure and the new structure can be fabricated on the same semiconductor wafer.

[0043] These improvements address the shortcomings discussed above.

[0044] Thus, an integrated circuit structure may include:

[0045] a) At a minimum, a power supply rail formed on the backside of the wafer.

[0046] b) The backside power rail is connected to the local frontside BEOL wire through a gate.

[0047] Additional examples include:

[0048] 1) A local front-side BEOL wire can supply power to at least one S / D epitaxial silicon area.

[0049] 2) The backside power rail can be connected to the gate through a gate tie-down.

[0050] 3) The local front side BEOL wire can connect to the gate through the gate via contact.

[0051] 4) The N-type gate can be separated from the P-type gate by an N2P gate cut.

[0052] 5) An N-type (or P-type) gate connected to the backside power supply can be isolated from another N-type (or P-type) active gate not connected to the backside power supply by an N2N (or P2P) gate cut.

[0053] As an overview of an exemplary embodiment, an exemplary process flow for, for example, at least partially forming integrated circuit structure 2 is set forth as follows.

[0054] 1) Form backside gate tie-down vias at the edge of the gate and fill the vias with dummy gates.

[0055] 2) Gate patterning, S / D epi, ILD filling, and gate cut are formed.

[0056] 3) Form gate via contacts to connect the dummy gates with gate tie-down vias to the local M1 wires.

[0057] 4) Connect some S / Ds that require power to the local M1 wire.

[0058] 5) Form BEOL interconnects and bond carrier wafer.

[0059] 6) Invert the wafer and remove the substrate.

[0060] 7) Form the backside power rail that connects to the gate tie-down via.

[0061] As further described in the following text and corresponding figures, an overview of an exemplary semiconductor device may include:

[0062] The following figures illustrate exemplary process flows, for example, for the methods described above and for forming integrated circuit structure 2.

[0063] 2A, 2B, and 2C are different cross-sectional views X, Y1, and Y2, respectively, of integrated circuit structure 2 after forming NS and STI, while FIG. 2D shows a top view layout 100 of integrated circuit structure 2 and indicates where cross-sectional views X, Y1, and Y2 exist within this layout.

[0064] FIG. 2D shows multiple NFET regions 140 and PFET regions 130 formed in conjunction with appropriately doped and patterned nanosheets (called active regions RX) along with backside power rails for VSS region 110 and VDD region 120 (see FIG. 4C). There are also three rows of gate regions 115, five per row except for the presence of dummy gate (called PC) regions 117. Note that in FIGS. 2A, 2B, and 2C, the PC regions 115, VSS region 110, and VDD region 120 have not yet been formed. Note that the terms "region" and "area" are sometimes used interchangeably herein; they both refer to three-dimensional structures in a semiconductor.

[0065] 2A, 2B, and 2C show a silicon (Si) substrate 105 having an etch-stop layer 175, such as SiGe, and another silicon substrate 106 formed on the etch-stop layer 175. The stack 150 includes a layer of a first semiconductor material 160 (e.g., 55% SiGe) formed on the upper surface of the substrate 106, followed by alternating layers of a second semiconductor material 161 (e.g., 25% SiGe) and a third semiconductor material 162 (e.g., silicon, such as monocrystalline silicon). The third semiconductor material 162 will be used in the gate to form the channel. These figures show that the stack 150 is covered with a hard mask (HM) 155, and that the regions 130 and 140 for the PFET and NFET regions, respectively, are formed (e.g., by etching), as is the STI region 180 (e.g., by deposition after etching). The stack 150 can be considered a nanosheet, formed by multiple thin sheets of material.

[0066] Although Figure 2D shows gate area 115 and dummy gate area 117, these are not actually formed until later, i.e., Figures 2A, 2B, and 2C do not show the gate.

[0067] 3A, 3B, and 3C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after depositing and patterning a masking layer (such as an OPL) and forming gate tie-down openings, while FIG. 3D shows a top view layout of the integrated circuit structure and indicates where cross-sectional views X, Y1, and Y2 reside within this layout.

[0068] In comparison to FIG. 2B , FIG. 3B shows gate tie-down openings 220. FIGS. 3A, 3B, and 3C show an OPL coating 210 covering the exposed surfaces of the PFET fin 130, NFET fin 140, silicon substrate 106, STI areas 180, and HM 155. The OPL coating 210 may be a carbon polymer or the like. Gate tie-down openings 220 are formed in the OPL coating 210 and STI areas 180 in FIG. 3B by conventional lithography and etching processes to provide openings 220 on a single side of each PFET area 130 and NFET area 140, through the corresponding STI areas 180, and into the silicon substrate 106. The gate tie-down openings 220 will form gate tie-downs to the VSS and VDD areas 110 and 120 after multiple process steps described below.

[0069] 4A, 4B, and 4C are different cross sections X, Y1, and Y2, respectively, of the integrated circuit structure after OPL / HM removal, dummy gate formation, SiGe 55 removal, BDI / spacer formation, nanosheet recess, inner spacer formation, S / D epi formation, ILD deposition, and CMP, while FIG. 4D shows the top view layout of the integrated circuit structure and indicates where cross sections X, Y1, and Y2 reside within this layout.

[0070] As can be seen, the OPL coating 210 and HM 155 have been removed. FIG. 4A shows the gate area 115 and dummy gate area 117 formed, while FIG. 4B shows a cross-sectional view of the dummy gate area 117. The gate area 115 and dummy gate area 117 may be formed of a material 490 such as poly-Si or amorphous Si. (Note that a thin layer of SiO2 may be present between the material 490 and the nanosheet stack 150; this is not shown and is deposited and appropriately modified using known techniques.) Reference numeral 220 indicates where the gate tie-down opening previously existed. The SiGe 55% layer 160 in the stack 150 has been removed, and a BDI (bottom dielectric isolation) layer 420 is in its place (see FIG. 4B). Figure 4A also shows that BDI layer 420 underlies the channel region and S / D regions 410, and that ILD layer 440 covers S / D epi region 410. Figure 4C shows that the previous nanosheet material in stack 150 has been removed, how BDI layer 420 surrounds the three layers of S / D epi region 410, and that S / D epi region 410 has been formed. ILD layer 440 has been deposited. After etching back SiGe layer 161 and then depositing material 420 in these areas, inner spacers 430 are formed, for example, from an insulating material.

[0071] Figures 5A, 5B, and 5C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after forming the gate cut, while Figure 5D shows a top view layout of the integrated circuit structure and indicates where cross-sectional views X, Y1, and Y2 reside within this layout. Figures 5B and 5D show gate cut 510 formed and filled with a dielectric material such as SiO2, SiN, SiBCN, SiOCN, SiOC, and the like.

[0072] FIGS. 6A, 6B, and 6C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after removing the dummy gate, releasing the SiGe, and forming a replacement high-k metal gate, while FIG. 6D shows a top-view layout of the integrated circuit structure and indicates where cross-sectional views X, Y1, and Y2 reside within this layout. Dummy gate area 117 is still shown, but material 490 within this area has been removed. SiGe 25% layer 161 has been released, so that second semiconductor material layer 162 still remains and is used in the channel region. Gate areas 115 and 117 have had their material replaced from material 490 with high-k metal gate layer 690. High-k metal gate layer 690 is formed by removing a gate dielectric layer, e.g., HfO2, HfSiO2, etc. x , HfAlO x , HfLaO x , ZrO x and the like, and work function metals such as TiN, TiC, TiAl, TiAlC and the like, and optional conductive metals such as W, or Co, or Al, which may be deposited by conformal deposition, as is known.

[0073] 7A through 12C use the layout 100 shown in FIG. 6D and cross-sectional views X, Y1, and Y2.

[0074] 7A, 7B, and 7C are different cross-sectional views X, Y1, and Y2, respectively, of an integrated circuit structure after performing a MOL process and forming a lower BEOL with VDD / VSS local supplies from dummy gate tie-downs. FIG. 7A shows that as part of the MOL process, contacts 710 (CA) are formed above S / D epi regions 410 in ILD layer 440 to S / D epitaxial regions 410. Additionally, in FIGS. 7A, 7B, and 7C, ILD layer 440 has been formed (e.g., as part of the lower BEOL formation), and vias A 720 and B 730 have been formed. As part of the lower BEOL formation, in FIG. 7A, local Vss 740 (to VB 720 and VB 730) has been added, and signal track 760 (using the M1 metal layer) has been added to VB 730. Multiple signal tracks 760 are shown in Figure 7B, with local VSS 740 connected to VB 730, in addition to local VDD 750, which is shown connected to VB 730. In Figure 7B, some of the signal tracks 760 are connected to vias, such as VB 730. Figure 7C also shows two contacts CA710 to individual regions, which are S / D epitaxial regions 410, and vias VA720 that lead to contacts CA710 and then to the corresponding signal tracks 760 or local VSS 740.

[0075] The local VSS 740 or VDD 750 is part of the BEOL (within M1) that provides ground or power, respectively, to only a few nearby transistors, hence the name "local" (as opposed to "global"). A more detailed definition is as follows: The local VSS / VDD is a segment of M1 wire that provides power only to transistors within 10 contacted poly pitches (CPP).

[0076] As shown by reference numeral 780, the introduction of local VSS 740 and / or local VDD 750 allows direct power supply to the S / Ds and allows nearby S / D epitaxial regions access to signal tracks within the N2N, P2P regions. That is, the introduction of local VSS 740-1 allows via VA 720-1 coupled to local VSS 740-1 to be used to directly supply power to S / D epitaxial region 410-1 (rather than having to connect to backside VSS through VBPR as shown, for example, in FIG. 1A). Furthermore, nearby S / D epitaxial region 410-2 has access to signal track 760-1 between the two NFET regions (see FIG. 6D and NFET area 140, or FIG. 14 and N2N). Additionally, CA710-1 above S / D epi410-2 allows this epi410-2 to be connected to either signal track 760-1 (using via VA720-2) or signal track 760-2 (using a via not shown).

[0077] Figures 8A, 8B, and 8C are different cross-sectional views X, Y1, and Y2, respectively, of an integrated circuit structure after forming more BEOL levels and bonding a carrier wafer. Figures 8A, 8B, and 8C are the same as Figures 7A, 7B, and 7C, respectively, but with the addition of BEOL layers 820 and carrier wafer 810. Carrier wafer 810 is bonded to BEOL layers 820. Reference numeral 800 denotes a semiconductor wafer being processed.

[0078] Figures 9A, 9B, and 9C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after flipping the wafer, removing the substrate, and stopping on the etch stop layer. Figures 9A, 9B, and 9C are the same as Figures 8A, 8B, and 8C, respectively, except that wafer 800 has been flipped for processing and substrate 105 has been removed by etching down to etch stop layer 175.

[0079] 10A, 10B, and 10C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after etch stop layer removal and remaining Si removal. These views show that etch stop layer 175 has been removed as well as silicon substrate 106 down to STI layer 180 and BDI layer 420. Region 1010 of gate metal layer 690 will become the gate tie-down and was formed by a process that began with the formation of gate tie-down opening 220 in FIG. 3B.

[0080] 11A, 11B, and 11C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after forming the backside ILD and forming the backside power rails. A BILD layer 1110 is formed over the STI area 180 and exposed areas of the BDI layer 420. The BILD layer 1110 is patterned (see FIGS. 11B and 11C), and conductive material is deposited to form the VSS region 110, ground rail 1160-1, and VDD region 120, power rail 1160-2. Region 1010 of gate metal layer 690 now becomes gate tie-downs 1010-1 and 1010-2. Note that gate tie-downs 1010-1 and 1010-2 may be considered vias and may be formed using techniques for forming such vias.

[0081] Furthermore, since VSS and VDD are both power supplies, the ground rail 1160-1 and the power rail 1160-2 may be generalized into the power supply rail 1160. That is, VSS is the power supply for the NFET, and VDD is the power supply for the PFET.

[0082] Two dummy gates 1130 are shown: an N-type dummy gate 1130-1 and a P-type dummy gate 1130-2. The N-type dummy gate 1130-1 uses the NFET area 140, and the P-type dummy gate 1130-2 uses the PFET area 130. The N-type dummy gate 1130-1 and the P-type dummy gate 1130-2 are separated from each other by at least a gate cut 510-1, although other techniques for separation may be used. The N-type dummy gate 1130-1 may be separated from an N-type active gate 1140-1 (which has a gate that forms a corresponding NFET using the S / D regions of the corresponding NFET area 140) by a gate cut 510-2. Note that the gate 1140-1 in this example is inactive (e.g., there is no via VB connected to the channel region), but in other examples this gate may be active. The P-type dummy gate 1130-2 may be separated from the P-type active gate 1140-2 (which has a channel formed in the gate region and uses the corresponding PFET area 130 to form the corresponding PFET) by a gate cut 510-3.

[0083] A gate tie-down means that the device is turned off by its gate. For an NFET, it needs to be turned off by adding a VSS power supply to the gate. This is how, for example, an N-type dummy gate 1130-1 is constructed using ground rail 1160-1. For a PFET, it needs to be turned off by adding a VDD power supply to the gate to turn it off. This is how, for example, a P-type dummy gate 1130-2 is constructed using power rail 1160-2.

[0084] As shown, the ground rail 1160-1 and its corresponding gate 1130-1, and the power rail 1160-2 and its corresponding gate 1130-2 are adjacent. Note that there could be two adjacent ground rails 1160-1 and corresponding gates 1130-1, or two adjacent power rails 1160-1 and corresponding gates 1130-2, if desired, although the dummy gate 117 would need to span two NFET or two PFET regions, respectively, rather than one NFET and one PFET region as in the above example.

[0085] 12A, 12B, and 12C are different cross-sectional views X, Y1, and Y2, respectively, of the integrated circuit structure after forming the backside power distribution network layer. For FIGS. 11A, 11B, and 11C, a BSPDN layer 1210 is formed on the exposed surfaces of the BILD layer 1110, the VSS region 110, and the VDD region 120.

[0086] FIG. 13A is an example of a conventional POR integrated circuit structure taken from cross-section Y3 of FIG. 14, while FIG. 13B is an example of an integrated circuit structure of an exemplary embodiment of the present disclosure. FIG. 13A is the same as FIG. 1A but is repeated for ease of reference. FIG. 13A is an example of a conventional POR integrated circuit structure 1. As indicated by reference numeral 10, S / D epi (epitaxial silicon area) 50 has access to only one signal track 55 above (e.g., near the BEOL layer). As indicated by reference numeral 60, S / D epi area 60 must be connected to the backside through VBPR 65, which is connected to VSS area 66. Note that, as indicated by FIGS. 13A, 13B, and 14, the techniques herein are fully compatible with POR processes. That is, the new features of the present disclosure can be added without modifying the POR structure.

[0087] FIG. 13B is FIG. 1B, but updated with the reference numbers used in the previous figures, starting with FIG. 2A. It is taken from cross-sectional view Y2 shown in FIG. 14. As shown in FIG. 13B, integrated circuit structure 2 illustrates an exemplary embodiment of the present specification. As indicated by reference numeral 20, S / D epitaxial layer 410-2 has free access to two signal tracks 760-1 and 760-2, indicated by reference numeral 75. In this example, via VA720-1 is used to access signal track 760-1, but signal track 760-2 is also readily accessible instead. In this example, signal track 760-1 is in the N2N region (see also FIG. 14), but it could also be in the P2P region (see FIG. 14), providing additional opportunities for signal routing. As indicated by reference numeral 30, S / D epitaxial layer 410-1 is powered from above by local VSS 740-1 (through via VA720-2). These improvements address the shortcomings discussed above with respect to FIG. 13A.

[0088] Turning now to FIG. 14, this figure provides a detailed top-view layout of the S / D contacts, VBPR, and VA. As shown in previous figures, cross sections X, Y1, and Y2 are shown in FIG. 14. Cross section Y3, used in FIG. 13A, is also shown. The NFET and PC regions are shown, including gate metal layer 690. The VSS region 110, VDD region 120, PFET region 130, and NFET region 140 are shown. The gate cut 510 is shown. The dummy PC area 117 is also shown. The local VSS region 740 is above via VA720-2, which contacts and overlies CA710-2, and via VA720-1 is above contact CA710-1, both of which are within the N2N region (VA720-1 is entirely within the N2N region, and CA710-1 is partially within this region). See also FIG. 7C, for example, which shows the Y2 cross section.

[0089] The local VDD region 750 is shown in Figure 14, and the three gate cuts 510 along cross section Y1 can be seen in Figure 7B, as can the local VDD (connected to underlying via VB 730, not shown in Figure 14). The local VDD region 750 is above via VA1420-2 (similar to 720-2), which contacts and is above CA1410-2 (similar to 710-2), and via VA1420-1 (similar to 720-1) is above contact CA1410-1 (similar to 710-1), both of which are within the P2P region (VA1420-1 is completely within the P2P region, and CA1410-1 is partially within this region).

[0090] The foregoing description has set forth numerous specific details, such as particular structures, components, materials, dimensions, process steps, and techniques, to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be understood by those skilled in the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or process steps may be omitted or not described to avoid obscuring the presented embodiments. When an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, it will be understood that it may be directly above the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly above" or "directly above" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will also be understood that it may be directly below or below the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0091] Additionally, as used herein, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "upper," "below," "beneath," "below," "over," "parallel," "vertical," and the like are intended to describe the relative positions as they are oriented and depicted in the drawings (unless otherwise indicated), and terms such as "contacting," "in direct contact," "abutting," "directly adjacent," "immediately adjacent," and the like are intended to indicate that at least one element is in physical contact with another element (with no other elements separating the depicted element). The term "laterally" is used herein to describe the relative positions of elements, more particularly to indicate that an element is disposed to the side of another element as opposed to above or below it, as those elements are oriented and depicted in the drawings. For example, an element disposed laterally adjacent to another element would be next to that other element, an element disposed immediately laterally adjacent to another element would be immediately adjacent to that other element, and an element that laterally surrounds another element would be adjacent to and bounded by the outer sidewall of that other element. In the following claims, the corresponding structure, material, acts, and equivalents of all means or step-plus-function elements are intended to include any structure, material, or acts for performing the function in combination with other claimed elements that are specifically claimed.

[0092] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, their practical applications, or technical improvements over techniques found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0093] The following abbreviations that may be found in the specification and / or drawings are defined as follows:

[0094] BDI Bottom Dielectric Isolation

[0095] BEOL Back End of Line

[0096] BILD backside interlayer dielectric

[0097] BSPDN Backside Power Distribution Network

[0098] CA source / drain contacts

[0099] CPP Contacted Poly Pitch

[0100] epi epitaxial silicon (area)

[0101] HM Hard Mask

[0102] ILD Interlayer Dielectric

[0103] M1 First metal layer

[0104] MOL Middle of the Line

[0105] N2N n-type (NFET) to n-type (NFET) semiconductor area

[0106] N2P n-type to p-type semiconductor region

[0107] NFET n-type field effect transistor

[0108] NS nanosheet

[0109] OPL optical planarization layer

[0110] P2P p-type (PFET) to p-type (PFET) semiconductor area

[0111] PC Gate Area

[0112] PFET p-type field effect transistor

[0113] POR Process of Record

[0114] RX Active Area

[0115] S / D Source / Drain

[0116] S / D epi Source / drain epitaxy

[0117] STI Shallow Trench Isolation

[0118] VBPR Via-to-Backside Power Rail

Claims

1. a power supply rail formed on the backside of the semiconductor wafer; and a front-side back-end-of-line (BEOL) wire layer connected to the power supply rail through a gate, the gate being of a type that is powered down by a power source coupled from the power supply rail through the gate to a first front-side BEOL wire layer; 1. An integrated circuit structure comprising:

2. 10. The integrated circuit structure of claim 1, further comprising a front-side BEOL wire connected to one or more source / drain epitaxy silicon areas of a corresponding transistor.

3. 3. The integrated circuit structure of claim 2, wherein the front-side BEOL wires are connected to the one or more source / drain epitaxy silicon areas of corresponding transistors using one or more corresponding vias.

4. 3. The integrated circuit structure of claim 2, wherein the front-side BEOL wire layer is connected to the front-side BEOL wire.

5. 2. The integrated circuit structure of claim 1, wherein the power supply rail connects to the gate through a gate tie-down via that electrically connects the power supply rail to a portion of the gate.

6. 10. The integrated circuit structure of claim 1, wherein the front-side BEOL wire layer connects to the gate through a gate via contact.

7. the gate is a first gate and the power supply rail is a first power supply rail; The integrated circuit structure comprises: a second power supply rail formed on the backside of the semiconductor wafer; and another front-side BEOL wire layer connected to the second power supply rail through a second gate, the second gate being of a type that is powered down by a power source coupled from the second power supply rail through the second gate to the another front-side BEOL wire layer; The integrated circuit structure of claim 1 further comprising:

8. the first gate is an n-type gate, the power supply for the first gate is ground, and the second gate is a p-type gate, and the power source for the first gate is electric power; 8. The integrated circuit structure of claim 7.

9. 8. The integrated circuit structure of claim 7, wherein said first and second gates are formed adjacent to one another and separated by a gate cut formed between at least said adjacent first and second gates.

10. 10. The integrated circuit structure of claim 9, wherein the first gate is formed at least partially in a first doped region of a first type, the second gate is formed at least partially in a second doped region of a second type, and the gate cut is formed in a region between the first and second doped regions.

11. 2. The integrated circuit structure of claim 1, further comprising source / drain contacts that contact corresponding source / drain regions in the doped regions and extend beyond the source / drain regions to provide access to one of a signal track in a region between the doped region and another doped region of the same type and a signal track within the doped region.

12. 2. The integrated circuit structure of claim 1, wherein gates connected to a power supply rail formed on the backside are separated from adjacent active gates not connected to the power supply rail formed on the backside by a gate cut.

13. the gate connected to the power supply rail formed on the backside and the adjacent active gate are of the same type and are at least partially formed within respective ones of two doped regions of this same type; and the gate cut between the gate connected to the power supply rail formed on the backside and the adjacent active gate is formed in a region between the two doped regions of the same type; 13. The integrated circuit structure of claim 12.

14. forming a power supply rail on the backside of the semiconductor wafer; forming a gate in the semiconductor wafer; and forming a front-side back-end-of-line (BEOL) wire layer connected to the power supply rail through the gate, the gate being of a type that is powered down by a power source coupled from the power supply rail through the gate to a first front-side BEOL wire layer; 1. A method of forming an integrated circuit structure, comprising:

15. The step of forming the gate in the semiconductor wafer further comprises forming a plurality of gates on a substrate of the semiconductor wafer, the step of forming the plurality of gates comprising: performing gate patterning to pattern a plurality of gates on a substrate, the gate being one of the gates; performing source / drain epitaxy to form source / drain regions for the plurality of gates; performing an interlayer dielectric deposition to cover at least the source / drain regions and at least partially separate the plurality of gates; and forming a front-side back-end-of-line (BEOL) wire layer, including forming a BEOL interconnect; and bonding a carrier wafer to the substrate on which the plurality of gates are formed.

15. The method of claim 14, comprising:

16. forming the gate in the semiconductor wafer further comprises forming a backside gate tie-down via at an edge of the gate and filling the backside gate tie-down via with a conductive material simultaneously with the conductive material forming the gate being formed; The method further comprises forming a gate via contact to connect the gate including the gate tie-down via to the front-side back end of line (BEOL) wire layer; and The method further comprises connecting the power supply rail to the gate tie-down via.

16. The method of claim 15.

17. 16. The method of claim 15, further comprising connecting one or more source / drain regions of a corresponding one or more others of the plurality of gates requiring power to one or more corresponding front side BEOL wires, the one or more corresponding front side BEOL wires being connected to the front side back end of line (BEOL) wire layer.

18. the gate is a first gate and the power supply rail is a first power supply rail; The method comprises: forming a second power supply rail formed on the backside of the semiconductor wafer; and forming another front-side BEOL wire layer connected to the second power supply rail through a second gate, the second gate being of a type that is powered down by a power source coupled from the second power supply rail through the second gate to the another front-side BEOL wire layer; Furthermore, the first gate is an n-type gate, the power supply for the first gate is ground, and the second gate is a p-type gate, and the power source for the first gate is electric power; 16. The method of claim 15.

19. 20. The method of claim 18, wherein forming the first and second gates comprises forming the first and second gates adjacent to one another, the method comprising forming and filling a gate cut between the adjacent first and second gates.

20. 16. The method of claim 15, further comprising forming source / drain contacts that contact and extend beyond corresponding source / drain regions to provide access to one of a signal track in a region between two doped regions of the same type and a signal track in the doped region.

Images