3D Memory Device Wordlines with Reduced Blocking Layer Damage

Abstract

The method includes obtaining a base structure for a three-dimensional (3D) memory device, forming a blocking layer on the base structure comprising a high-k dielectric material, and forming word lines for the 3D memory device on the blocking layer using an atomic layer deposition (ALD) process, the word lines comprising molybdenum.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to the fabrication of electronic devices. In particular, embodiments of the present disclosure relate to three-dimensional (3D) memory device wordlines with reduced blocking layer damage. [Background technology]

[0002] An electronic device manufacturing apparatus may include multiple chambers, such as process chambers and load lock chambers. Such an electronic device manufacturing apparatus may use a robotic device in a transfer chamber configured to transport substrates between the multiple chambers. In some instances, multiple substrates are transported together. Process chambers may be used in an electronic device manufacturing apparatus to perform one or more processes on a substrate, such as a deposition process and an etching process. Gases are flowed through the process chamber for many processes. Electronic devices, such as semiconductor devices, are manufactured by performing a series of operations, which may include deposition, oxidation, photolithography, ion implantation, etching, etc., to form many patterned layers. Summary of the Invention

[0003] According to one embodiment, a method is provided that includes obtaining a base structure for a three-dimensional (3D) memory device, forming a blocking layer on the base structure comprising a high-k dielectric material, and forming word lines for the 3D memory device on the blocking layer using an atomic layer deposition (ALD) process, the word lines comprising molybdenum.

[0004] According to one embodiment, a three-dimensional (3D) memory device is provided. The 3D memory device includes a blocking layer and word lines including molybdenum disposed on the blocking layer. The blocking layer includes a high-k dielectric material that is resistant to damage from atomic layer deposition (ALD) chemistry used to form the molybdenum in the word lines.

[0005] In the figures of the accompanying drawings, the present disclosure is illustrated by way of example, and not by way of limitation. In these figures, like reference numerals refer to like elements. It should be noted that different references to "one" or "an" embodiment in the present disclosure do not necessarily refer to the same embodiment, but rather that such references mean at least one. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram of an exemplary portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 2] FIG. 1 illustrates an exemplary deposition process that can be used to form at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3A] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3B] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3C] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3D] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3E] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3F] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 3G] FIG. 1 illustrates an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 4] 1 is a graph illustrating the difference in threshold voltage (Vt) shift in volts (V) after 1000 program / erase (P / E) cycles for various combinations of word line materials and blocking layer materials according to some embodiments. [Figure 5] 1 is a graph illustrating leakage current in amperes (A) as a function of equivalent oxide thickness (EOT) in nanometers (nm) for various combinations of word line materials and blocking layer materials according to some embodiments. [Figure 6] FIG. 1 illustrates an exemplary portion of a three-dimensional (3D) memory device, according to some embodiments. [Figure 7A] 1 is a flow diagram of an exemplary method for fabricating word lines of a three-dimensional (3D) memory device with reduced blocking layer damage, according to some embodiments. [Figure 7B] 1 is a flow diagram of an exemplary method for fabricating word lines of a three-dimensional (3D) memory device with reduced blocking layer damage, according to some embodiments. [Figure 7C] 1 is a flow diagram of an exemplary method for fabricating word lines of a three-dimensional (3D) memory device with reduced blocking layer damage, according to some embodiments. [Figure 7D] 1 is a flow diagram of an exemplary method for fabricating word lines of a three-dimensional (3D) memory device with reduced blocking layer damage, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0007] In some memory devices, such as non-conjunction (NAND) flash memory devices (“NAND memory devices”), word lines are the components responsible for reading, writing, and erasing data. NAND memory can be organized into a hierarchical structure including blocks, pages, and cells. Cells, which store data as an electrical charge, are the smallest unit of data storage in NAND memory devices. These cells are grouped into pages, and pages are further grouped into blocks. Word lines can be used to address and select specific rows of cells in the memory array. In NAND memory devices, each cell is essentially a floating-gate transistor or a charge-trapping transistor. Cells may be organized into a grid-like structure with rows and columns.

[0008] The basic operating principles of 3D NAND memory devices are similar to those of planar (2D) NAND memory devices, including the role of word lines. However, 3D NAND technology introduces a significant change in the physical architecture of the memory cells. Instead of laying out memory cells flat on a silicon substrate, 3D NAND memory devices contain a vertically arranged stack of layers of memory cells, thereby effectively creating a 3D structure.

[0009] A 3D NAND memory device may include multiple word lines extending from the first layer of the layer stack to the last layer of the layer stack. Each word line may be connected to a respective set of cells (a "page"), where each cell of the set of cells is contained within a respective layer of the layer stack. More specifically, the word lines may be connected to the control gates of the cells. The 3D NAND memory device may further include multiple bit lines arranged perpendicular to the word lines, where each bit line is connected to a respective set of cells (a "string"). More specifically, the bit lines may be connected to the drains of the cells. The 3D NAND memory device may include additional components such as source lines and select gates (e.g., source select gates and drain select gates). In some 3D NAND memory devices, the word lines are formed of tungsten (W) and / or titanium nitride (TiN).

[0010] Similar to 2D NAND memory devices, to read data from a set of cells (a "page") in a 3D NAND memory device, a read voltage is applied to word lines connected to the set of cells, and the data is read via connected bit lines. To write or program data onto a set of cells, data is placed on the bit lines and a program voltage is applied to the word lines, causing electrons to tunnel into the floating gate or charge trapping layer of the cells (depending on the specific type of 3D NAND memory device). Data is erased by applying an erase voltage to the substrate high enough to release stored charge. Thus, read and program operations are performed at the page level, while erase operations are performed at the block level.

[0011] In some embodiments, a 3D NAND memory device includes a blocking layer. The blocking layer acts as a barrier to prevent electrons stored in a cell's charge storage layer (e.g., a floating gate or a charge trapping layer) from leaking out. In doing so, the blocking layer acts as an insulator that helps maintain the stored charge. For example, the blocking layer can be formed from a dielectric material. One example of a dielectric material used to form the blocking layer is aluminum oxide (Al2O3). Al2O3 is a dielectric material with a dielectric constant of approximately 7.8. Therefore, the blocking layer can contribute to the overall reliability and performance of the cell by ensuring that the charge stored in the cell remains stable and is not affected by disturbances from neighboring cells or external factors. The blocking layer can also act as a barrier to prevent impurities, such as chlorine and fluorine, from diffusing into the charge storage layer.

[0012] As discussed above, during program and erase operations, charges move into and out of the charge storage layer through a process called tunneling. A blocking layer may cooperate with the tunneling layer to control this tunneling process. The tunneling layer is a thin insulating layer that separates the channel layer from the charge storage layer, where data is stored in the form of electric charges. The primary function of the channel layer is to serve as a conductive path for current to flow through the memory cell during read, program, and erase operations. Essentially, the channel layer connects the source and drain regions of the memory cell transistor, allowing current to flow through those regions when appropriate voltages are applied. For example, during programming, electrons can tunnel through the tunneling layer via the channel layer and be trapped in the charge storage layer. During erasure, electrons can tunnel in the opposite direction through the tunneling layer and exit through the channel layer.

[0013] In some embodiments, a 3D NAND memory device includes a charge-blocking layer. The charge-blocking layer may be used, for example, in a charge-trapping flash (CTF) memory cell. In a conventional floating-gate flash memory cell, data is stored by injecting electrons into a conductive floating gate. In contrast, a CTF memory cell uses a charge-trapping layer to store electrons, and the charge traps are insulated by surrounding dielectric materials, one of which is a charge-blocking layer. The charge-blocking layer may act as a barrier to prevent electrons stored in the charge-trapping layer from leaking into the control gate or other surrounding materials.

[0014] The change from a planar 2D architecture to a 3D vertically stacked architecture can enable significant advantages, including higher capacity, better performance, and lower power consumption. One benefit of 3D NAND is that it allows for significant scaling and increased storage density without the need to reduce the size of the cells. This is achieved by increasing the number of layers in the stack.

[0015] To improve storage density, the number of cell layers in 3D memory devices continues to increase. To compensate for the overall thickness of the memory cells as the number of memory cell layers increases, the pitch (e.g., vertical pitch) and thickness of the word lines can be scaled down to reduce the aspect ratio of the vertical channel structure of the 3D NAND memory device. Furthermore, the reduction in word line thickness also increases the resistance and / or resistivity of the word lines. Therefore, materials used to form word lines that can achieve lower resistance or resistivity at thinner thicknesses than W and / or TiN can be beneficial to continue scaling down the word line pitch as the number of memory cell layers increases.

[0016] In some embodiments, one candidate to replace W and / or TiN as a word line material is molybdenum (Mo). For example, Mo has low resistance or resistivity characteristics and can be formed using low barrier thickness (e.g., barrier-free) deposition. Mo may be deposited to form word lines using any suitable deposition process. One such deposition process is an atomic layer deposition (ALD) process. However, at least some ALD chemistries (e.g., solid Mo precursors) used to deposit Mo during ALD processes can contribute to blocking layer damage (e.g., Al2O3 blocking layer damage). Blocking layer damage can negatively impact memory device performance. For example, blocking layer damage can affect threshold voltage shift during program / erase cycling, resulting in shorter memory device endurance, negatively impacting erase performance due to electron tunneling, etc.

[0017] Some approaches to address blocking layer damage may include the use of different nucleation or liner layers. However, nucleation or liner layers are typically formed from materials that have a higher resistance or resistivity than the word line material. Therefore, approaches that use nucleation or liner layers may increase the resistance or resistivity of the word lines.

[0018] To address these and other drawbacks, embodiments described herein relate to forming wordlines comprising Mo with reduced blocking layer damage. More specifically, the embodiments described herein can provide an ALD process for depositing low-resistivity Mo in forming wordlines and can utilize a blocking layer formed from a high-k dielectric material that resists damage caused by the ALD chemistry used to form the Mo. The high-k dielectric material used to form the blocking layers described herein can have a dielectric constant greater than that of Al2O3. More specifically, the high-k dielectric material used to form the blocking layers described herein can have a dielectric constant greater than about 7.8. For example, the high-k dielectric material used to form the blocking layers described herein can have a dielectric constant of about 10 or greater. Thus, the embodiments described herein can be used to form 3D memory device wordlines with low resistance and reduced blocking layer damage that can maintain or improve threshold voltage shift during program / erase cycling. In addition, forming the word lines from Mo and the blocking layer from a high-k dielectric material can reduce electron tunneling from the word lines to the charge trapping layer, thereby improving erase performance.

[0019] 1 illustrates an exemplary portion of a 3D NAND memory device ("device") 100, according to some embodiments. Device 100 includes word lines 110, blocking layers 120, channel layers 130, tunnel layers 140, charge trapping layers 150, and / or charge blocking layers 160. In this illustrated example, there is no barrier layer (i.e., it is barrier-less). In some embodiments, word lines 110 are replacement word lines.

[0020] In some embodiments, the wordlines 110 can include Mo. In some embodiments, an ALD process can be used to deposit Mo to form the wordlines 110 in a manner that reduces damage to the blocking layer 120. The ALD process can use any suitable ALD chemistry. For example, the ALD chemistry can include any suitable ALD Mo precursor and reactants. Examples of suitable ALD chemistries include a molybdenum dioxide dichloride (MoOCl) precursor or a molybdenum pentachloride (MoCl) precursor, and a hydrogen gas (H) reactant.

[0021] In this example, device 100 further includes a nucleation layer 170, which may also be referred to as a seed layer. Nucleation layer 170 may be used to form Mo during an ALD process. Nucleation layer 170 may include any suitable material to promote the formation of Mo during an ALD process. Examples of materials that may be used to form nucleation layer 170 include molybdenum silicide (MoSi x ), molybdenum oxide silicide (e.g., MoSiO), molybdenum nitride (δ-MoN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), and the like. Nucleation layer 170 can be formed using any suitable deposition process. In some embodiments, nucleation layer 170 is formed using an ALD process. Nucleation layer 170 can be formed to have any suitable thickness. In some embodiments, the thickness of nucleation layer 170 is in the range of about 0.25 nm to about 5 nm. In some embodiments, the thickness of nucleation layer 170 is in the range of about 0.5 nm to about 3 nm.

[0022] Blocking layer 120 can include a high-k dielectric material having a dielectric constant greater than Al2O3. More specifically, blocking layer 120 can include a high-k dielectric material having a dielectric constant greater than about 7.8. For example, blocking layer 120 can include a high-k dielectric material having a dielectric constant of about 10 or greater. In some embodiments, blocking layer 120 includes a zirconium oxide material. Examples of zirconium oxide materials include zirconium dioxide (ZrO2), aluminum zirconium dioxide (AlZrO2), doped ZrO2, and the like. In some embodiments, blocking layer 120 includes a lanthanum oxide material. An example of a lanthanum oxide material is lanthanum aluminate (LaAlO3). In some embodiments, blocking layer 120 includes a hafnium oxide material. Examples of hafnium oxide materials include hafnium oxide (hafnia) (HfO2), doped HfO2, and the like. In some embodiments, blocking layer 120 comprises yttrium oxide (yttria) (YO). In some embodiments, blocking layer 120 comprises a doped AlO material (i.e., AlO doped with a high-k material sufficient to increase the dielectric constant of the doped AlO material to greater than about 7.8). Blocking layer 120 can be formed using any suitable deposition process. In some embodiments, blocking layer 120 is formed using an ALD process. Blocking layer 120 can be formed to have any suitable thickness. In some embodiments, the thickness of blocking layer 120 is in the range of about 1 nm to about 5 nm. In some embodiments, the thickness of blocking layer 120 is in the range of about 2 nm to about 3 nm.

[0023] In some embodiments, channel layer 130 comprises silicon (Si). In some embodiments, tunnel layer 140 comprises an oxide material. For example, tunnel layer 140 may comprise SiO2. In some embodiments, charge trapping layer 150 comprises a nitride material. For example, charge trapping layer 150 may comprise a silicon nitride material. In some embodiments, charge blocking layer 160 comprises an oxide material. For example, charge blocking layer 160 may comprise SiO2. Further details regarding the formation of device 100 will now be described in more detail with respect to Figures 2-3G.

[0024] 2 is a diagram 200 of an exemplary deposition process that can be used to form at least a portion of a 3D memory device, according to some embodiments. In some implementations, the deposition process comprises an ALD process. Various types of ALD processes exist, and a particular type may be selected based on several factors, such as the surface to be coated, the coating material, and the chemical interaction between the surface and the coating material. The general principle of these various ALD processes involves growing a thin film layer by repeatedly exposing the surface to be coated to sequential, alternating pulses of gaseous chemical precursors and reactants that chemically react with the surface, one at a time, in a self-limiting manner.

[0025] FIG. 2 illustrates an article 210 having a surface 205. The article 210 may represent a partially formed memory cell of a 3D NAND device. In embodiments, the article 210 and the surface 205 may include a blocking layer (not shown) already formed thereon. Each individual chemical reaction between a precursor or reactant and the surface is known as a "half-reaction." During each half-reaction, the precursor or reactant is pulsed to the surface for a sufficient time to allow the precursor to fully react with the surface. The reaction is self-limiting because the precursor reacts only with a finite number of available reactive sites on the surface, thereby forming a uniform, continuous adsorbed layer on the surface. Sites already reacted with a precursor become unavailable for further reaction with the same precursor unless and / or until the reacted sites undergo a treatment that forms new reactive sites on the uniform, continuous coating. Exemplary treatments can be plasma treatments, treatments by exposing the uniform, continuous adsorbed layer to radicals, or the introduction of a different precursor that can react with the latest uniform, continuous film layer adsorbed on the surface.

[0026] In FIG. 2 , an article 210 having a surface 205 may be exposed to a first precursor 260 for a first duration until a first half-reaction between the first precursor 260 and the surface 205 forms an adsorbed layer 214, thereby partially forming layer 215. The article 210 may then be exposed to a second precursor 265 (also referred to as a reactant) until a second half-reaction reacts with the adsorbed layer 214 to fully form layer 215. The first precursor 260 may be, for example, a molybdenum precursor. The second precursor 265 may be, for example, a hydrogen precursor or reactant. To achieve a target thickness of layer 215, the article 210 may be alternately exposed to the first precursor 260 and the second precursor 265 up to x times, where x may be an integer between 1 and 100, for example.

[0027] ALD processes may be performed at a variety of temperatures depending on the type of ALD process. The optimal temperature range for a particular ALD process is called the "ALD temperature window." Temperatures below the ALD temperature window may result in poor growth rates and non-ALD type deposition. Temperatures above the ALD temperature window may result in thermal decomposition of the article or rapid desorption of the precursors. The ALD temperature window may range from about 20°C to about 600°C. In some embodiments, the ALD temperature window is between about 150°C and 350°C.

[0028] The ALD process enables conformal film layers with uniform thickness on articles and surfaces with complex geometries, large aspect ratio holes, and three-dimensional structures. Sufficient exposure time of the precursor to the surface allows the precursor to distribute and fully react with the entire surface, including all of the surface's complex three-dimensional features. The exposure time utilized to achieve conformal ALD on high aspect ratio structures is proportional to the square of the aspect ratio and can be predicted using modeling techniques. Additionally, ALD techniques offer advantages over other commonly used coating technologies because they enable in situ, on-demand material synthesis of specific compositions or formulations without the time-consuming and difficult fabrication of source materials (e.g., powder feedstocks and sintered targets).

[0029] 3A-3G are diagrams of an exemplary process flow for forming at least a portion of a 3D memory device, according to some embodiments. FIG. 3A shows a diagram 300A of an initial structure 305. The initial structure 305 includes a stack of alternating dielectric layers, including dielectric layers 310-1-310-3 formed from a first material and dielectric layers 320-1-320-2 formed from a second material different from the first material. Although three dielectric layers 310-1-310-3 and two dielectric layers 320-1-320-2 are shown, the initial structure 305 can include any suitable number of dielectric layers. In some embodiments, the first material includes an oxide material and the second material includes a nitride material. For example, the first material includes silicon oxide (e.g., SiO) and the second material includes silicon nitride (e.g., SiN).

[0030] The initial structure 305 further includes a channel stack 330 disposed within the stack of dielectric layers. For example, the channel stack 330 may include a channel layer 332, a tunnel layer 334, a charge trapping layer 336, a channel layer 338, and a dielectric layer (e.g., silicon oxide) layer 339. The channel layer 332 may be similar to the channel layer 130 of FIG. 1 , the tunnel layer 334 may be similar to the tunnel layer 140 of FIG. 1 , the charge trapping layer 336 may be similar to the charge trapping layer 150 of FIG. 1 , and the charge blocking layer 338 may be similar to the charge blocking layer 160 of FIG. 1 .

[0031] FIG. 3B shows diagram 300B illustrating an etching process performed to form opening 340 in initial structure 305 to form intermediate structure 345. Opening 340 is formed to expose dielectric layers 320-1 and 320-2, which are subsequently removed as described below with respect to FIG. 3C. In some embodiments, opening 340 is a slit, and the etching process is a slit etching process. Any suitable etching process can be used to form opening 340 according to embodiments described herein. In some embodiments, the etching process is a dry etching process. For example, the etching process can be a reactive ion etching (RIE) process.

[0032] 3C shows diagram 300C illustrating the removal of dielectric layers 320-1 and 320-2 to form intermediate structure 350, also referred to as a base structure. Dielectric layers 320-1 and 320-2 can be removed using any suitable process. In some embodiments, dielectric layers 320-1 and 320-2 are removed using an etching process (e.g., a selective etching process) that can selectively etch a second material relative to a first material. For example, the etching process can be a wet etching process using a suitable wet etchant.

[0033] FIG. 3D shows diagram 300D illustrating the formation of a conformal blocking layer 360 on the exposed surface of base structure 350 to form intermediate structure 365. Blocking layer 360 can be similar to blocking layer 120 of FIG. 1. Blocking layer 360 can be formed using any suitable deposition process. In some embodiments, blocking layer 360 is formed using an ALD process. Blocking layer 360 can be formed to have any suitable thickness. In some embodiments, the thickness of blocking layer 360 is in the range of about 1 nm to about 5 nm. In some embodiments, the thickness of blocking layer 360 is in the range of about 2 nm to about 3 nm.

[0034] FIG. 3E shows diagram 300E illustrating the formation of a conformal nucleation layer 370 on blocking layer 360 of intermediate structure 365 to form intermediate structure 375. Nucleation layer 370 can be similar to nucleation layer 170 of FIG. 1. Nucleation layer 370 can be formed using any suitable deposition process. In some embodiments, nucleation layer 370 is formed using an ALD process. Nucleation layer 370 can be formed to have any suitable thickness. In some embodiments, the thickness of nucleation layer 370 is in the range of about 0.25 nm to about 5 nm. In some embodiments, the thickness of nucleation layer 370 is in the range of about 0.5 nm to about 3 nm.

[0035] FIG. 3F illustrates diagram 300F showing the formation of wordline material 380 in the gaps (e.g., lateral gaps) of intermediate structure 375 to form intermediate structure 385. In some embodiments, wordline material 380 includes Mo. Wordline material 380 can be formed using any suitable deposition process. In some embodiments, wordline material 380 is formed using an ALD process. Wordline material 380 can be formed to have any suitable thickness. In some embodiments, wordline material 380 has a thickness in the range of about 5 nm to about 30 nm. The thickness of wordline material 380 need not exceed the thickness of opening 340 of FIG. 3B. In some embodiments, wordline material 380 does not completely fill the lateral gaps, leaving seams or voids in the lateral gaps. In some embodiments, wordline material 380 completely fills the lateral gaps, and no seams or voids are formed. In some embodiments, the process flow steps illustrated in Figures 3E-3F (eg, forming nucleation layer 370 and forming wordline material 380) can be performed without breaking vacuum.

[0036] FIG. 3G shows diagram 300G illustrating forming word lines 390 to form structure 395. More specifically, word lines 390 may be formed by recessing or etching back word line material 380. Word lines 390 may be formed using any suitable process. In some embodiments, word lines 390 are formed by using an isotropic etching process. For example, the isotropic etching process may be a dry etching process or a wet etching process. Further details regarding the process flow illustrated in FIGS. 3A-3G are described above with respect to FIGS. 1-2 and in further detail with respect to FIGS. 7-8.

[0037] 4 is a graph 400 illustrating the difference in threshold voltage (Vth) shift in volts (V) after 1000 program / erase (P / E) cycles for various combinations of word line and blocking layer materials. As shown, word lines formed from Mo and blocking layers including high-k dielectric materials (e.g., ZrO2, AlZrO2, and LaAlO3) exhibit improved Vt shift after 1000 P / E cycles compared to word lines formed from Mo and blocking layers including Al2O3.

[0038] 5 is a graph 500 illustrating leakage current in amperes (A) as a function of equivalent oxide thickness (EOT) in nanometers (nm) for various combinations of word line and blocking layer materials, according to some embodiments. EOT may refer to the thickness of a silicon oxide (SiO) layer that would provide electrical performance similar to that of a high-k dielectric material used to form a blocking layer (e.g., blocking layer 120 of FIG. 1).

[0039] FIG. 6 is a diagram 600 illustrating an example portion of a 3D memory device, according to some embodiments. The 3D memory device can include several components, including word lines (WL) 610, blocking layers (BL) 620, charge blocking layers (CBL) 630, charge trapping layers (CTL) 640, tunneling layers (TL) 650, and channel layers (CH) 650. More specifically, the word lines 610 can include Mo, and the blocking layers 620 can include the high-k dielectric material described above. The diagram illustrates electron energy (eV) and distance in nanometers (nm) for the components of the 3D memory device. The arrows with "X"s thereon indicate that the combination of the word lines 610 including Mo and the blocking layers 620 including the high-k dielectric material can reduce electron tunneling from the word lines 610 to the charge trapping layers 640, which can improve erase performance.

[0040] FIG. 7A is a flow diagram of a method 700 for fabricating three-dimensional (3D) word lines with reduced blocking layer damage, according to some embodiments. At block 710, a base structure of a 3D memory device is obtained. The base structure can include multiple components. In some embodiments, the base structure includes a channel layer, a tunnel layer, a charge trapping layer, and a charge blocking layer. In some embodiments, obtaining the base structure includes forming at least one component of the base structure. For example, obtaining the base structure can include forming at least one of the channel layer, the tunnel layer, the charge trapping layer, or the charge blocking layer. Further details regarding obtaining the base structure are described above with respect to FIGS. 1 and 3A-3C and will be described in more detail later with respect to FIG. 7B.

[0041] At block 720, a blocking layer is formed on the base structure. In some embodiments, the blocking layer is formed directly on the base structure. For example, the blocking layer can be a conformal layer. The blocking layer can be formed of a high-k dielectric material that is resistant to damage from the chemistry (e.g., ALD chemistry) used to form the at least one word line. In some embodiments, the blocking layer is formed of a high-k dielectric material that is resistant to damage from the chemistry used to form Mo. Further details regarding forming the blocking layer are described above with respect to FIGS. 1 and 3D and in further detail with respect to FIG. 7C.

[0042] At block 730, at least one word line for the 3D memory device is formed on the blocking layer. In some embodiments, the at least one word line comprises a replacement word line. In some embodiments, the at least one word line is formed from Mo. Further details regarding forming the at least one word line on the blocking layer are described above with respect to FIGS. 1 and 3D and in further detail with respect to FIG. 7D.

[0043] FIG. 7B is a flow diagram of a method 710 for obtaining a base structure of a 3D memory device according to some embodiments. At block 712, an initial structure of a 3D memory device is obtained, including a stack of alternating dielectric layers and a channel layer stack. More specifically, the stack of alternating dielectric layers can include at least one first dielectric layer formed from a first material and at least one second dielectric layer formed from a second material different from the first material. In some embodiments, the first material includes an oxide material and the second material includes a nitride material. For example, the first material includes silicon oxide (e.g., SiO) and the second material includes silicon nitride (e.g., SiN). The channel stack can include a channel layer, a tunnel layer, a charge trapping layer, and a channel layer.

[0044] At block 714, an opening is formed in the stack of alternating dielectric layers to obtain an intermediate structure. Forming the opening may include performing an etching process. The opening is formed to expose at least one second dielectric layer of the stack of alternating dielectric layers. In some embodiments, the opening is a slit, and the etching process is a slit etching process. Any suitable etching process may be used to form the opening according to embodiments described herein. In some embodiments, the etching process is a dry etching process. For example, the etching process may be an RIE process.

[0045] At block 716, a base structure of the 3D memory device is formed from the intermediate structure. Forming the base structure may include removing the at least one second dielectric layer. The at least one second dielectric layer may be removed using any suitable process. In some embodiments, the at least one second dielectric layer is removed using an etching process (e.g., a selective etching process) that can selectively etch the second material relative to the first material. For example, the etching process may be a wet etching process using a suitable wet etchant. Further details regarding blocks 712-716 are described above with respect to FIGS. 1, 3A-3C, and 7A.

[0046] 7C is a flow diagram of a method 720 for forming a blocking layer on a base structure of a 3D memory device, according to some embodiments. At block 722, a base structure of a 3D memory device is obtained. For example, the base structure can be the base structure obtained at block 710 of FIG. 7A (e.g., blocks 710-716 of FIG. 7B).

[0047] At block 724, a conformal blocking layer is formed on the exposed surfaces of the base structure of the 3D memory device. The blocking layer can be formed using any suitable deposition process. In some embodiments, the blocking layer is formed using an ALD process. The blocking layer can be formed to have any suitable thickness. In some embodiments, the thickness of the blocking layer is in a range from about 1 nm to about 5 nm. In some embodiments, the thickness of the blocking layer is in a range from about 2 nm to about 3 nm.

[0048] The blocking layer can be formed of a high-k dielectric material that is resistant to damage from the ALD chemistry used to form the wordline material used to form the wordlines of the 3D memory device. In some embodiments, the wordline material includes Mo. The blocking layer can include a high-k dielectric material having a dielectric constant greater than Al2O3. More specifically, the blocking layer can include a high-k dielectric material having a dielectric constant greater than about 7.8. For example, the blocking layer can include a high-k dielectric material having a dielectric constant of about 10 or greater. In some embodiments, the blocking layer includes zirconium oxide. Examples of zirconium oxide materials include ZrO2, AlZrO2, doped ZrO2, etc. In some embodiments, the blocking layer includes lanthanum oxide. An example of a lanthanum oxide is LaAlO3. In some embodiments, the blocking layer includes hafnium oxide. Examples of hafnium oxide include HfO2, doped HfO2, etc. In some embodiments, the blocking layer includes YO3. In some embodiments, the blocking layer comprises doped Al2O3 (i.e., Al2O3 doped with a high-k material sufficient to increase the dielectric constant of the doped Al2O3 material to greater than about 7.8). Further details regarding blocks 722-724 are described above with respect to Figures 1, 3A-3D, and 7A.

[0049] 7D is a flow diagram of a method 730 of forming at least one word line on a blocking layer according to some embodiments. For example, the blocking layer can be the blocking layer formed in block 720 of FIG. 7A (e.g., blocks 722-724 of FIG. 7C).

[0050] At block 732, a nucleation layer is formed on the blocking layer. More specifically, a conformal nucleation layer can be formed on the blocking layer. The nucleation layer can be used to facilitate the formation of the word line material at block 734. The nucleation layer can be formed using any suitable deposition process. In some embodiments, the nucleation layer is formed using an ALD process. The nucleation layer can be formed to have any suitable thickness. In some embodiments, the thickness of the nucleation layer is in a range from about 0.25 nm to about 5 nm. In some embodiments, the thickness of the nucleation layer 370 is in a range from about 0.5 nm to about 3 nm.

[0051] At block 734, wordline material is formed using a nucleation layer. More specifically, the wordline material can be formed in the gaps (e.g., lateral gaps). In some embodiments, the wordline material includes Mo. The wordline material can be formed using any suitable deposition process. In some embodiments, the wordline material is formed using an ALD process. More specifically, forming the wordline material can include depositing Mo using an ALD process using a suitable ALD chemistry (e.g., MoO2Cl2 or MoCl5 precursor and H2 reactant). The wordline material can be formed to have any suitable thickness. In some embodiments, the thickness of the wordline material is in a range from about 5 nm to about 30 nm. In some embodiments, an opening (e.g., a seam or void) is formed in the wordline material to form at least one wordline. In some embodiments, the wordline material completely fills the gaps, and no openings are formed. In some embodiments, the formation of the nucleation layer at block 732 and the formation of the wordline material at block 734 can be performed without breaking vacuum.

[0052] At block 736, at least one word line is formed from the word line material. More specifically, the at least one word line may be formed by recessing or etching back the word line material. The at least one word line may be formed using any suitable process. In some embodiments, the at least one word line is formed by using an isotropic etching process. For example, the isotropic etching process may be a dry etching process or a wet etching process. Further details regarding blocks 732-736 are described above with respect to FIGS. 1, 3E-3G, and 7A.

[0053] The foregoing description sets forth numerous specific details, such as examples of particular systems, components, methods, and the like, to provide a thorough understanding of some embodiments of the present disclosure. However, it will be apparent to one skilled in the art that at least some embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known components or methods have not been described in detail or have been shown in simple block diagram form to avoid unnecessarily obscuring the present disclosure. Thus, the specific details described are merely examples. It is contemplated that particular implementations may vary from these illustrative details and still be within the scope of the present disclosure.

[0054] Throughout this specification, a reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." When the term "about" or "approximately" is used herein, this term is intended to mean that the stated nominal value is accurate to within + / - 10%.

[0055] Although the operations of the methods herein are illustrated and described in a particular order, the order of the operations in each method may be changed so that certain operations are performed in the reverse order, or so that certain operations are performed, at least in part, concurrently with other operations. In alternative embodiments, instructions or sub-operations of different operations may be performed intermittently and / or alternately.

[0056] It should be understood that the foregoing description is intended to be illustrative, and not limiting. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the foregoing description. Accordingly, the scope of the present disclosure should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. Obtaining a base structure for a three-dimensional (3D) memory device; forming a blocking layer over the base structure, the blocking layer comprising a high-k dielectric material; forming word lines for the 3D memory device comprising molybdenum on the blocking layer using an atomic layer deposition (ALD) process; A method comprising:

2. The method of claim 1 , wherein the blocking layer comprises a high-k dielectric material having a dielectric constant greater than about 7.

8.

3. The method of claim 2 , wherein the blocking layer comprises a high-k dielectric material having a dielectric constant of about 10 or greater.

4. The method of claim 1 , wherein the blocking layer comprises at least one of zirconium oxide, lanthanum oxide, hafnium oxide, yttrium oxide, or doped aluminum oxide.

5. The method of claim 4 , wherein the blocking layer comprises at least one of zirconium dioxide, zirconium aluminum dioxide, or doped zirconium dioxide.

6. The method of claim 4 , wherein the blocking layer comprises lanthanum aluminate.

7. The method of claim 4 , wherein the blocking layer comprises doped hafnium oxide.

8. 10. The method of claim 1, wherein forming the word lines comprises performing the ALD process using a hydrogen gas reactant and a molybdenum precursor selected from the group consisting of molybdenum dioxide dichloride and molybdenum pentachloride.

9. 10. The method of claim 1, wherein forming the word lines comprises forming a nucleation or seed layer on the blocking layer by exposing the blocking layer to a precursor.

10. 10. The method of claim 9, wherein the nucleation layer or the seed layer comprises at least one of molybdenum silicide, molybdenum oxide silicide, molybdenum nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or tantalum silicon nitride.

11. 10. The method of claim 1, wherein the high-k dielectric layer is resistant to damage from the ALD chemistry used to form the molybdenum of the word lines.

12. a blocking layer; and a word line comprising molybdenum disposed on the blocking layer; wherein the blocking layer comprises a high-k dielectric material that is resistant to damage from atomic layer deposition (ALD) chemistry used to form the molybdenum of the word lines.

13. 13. The 3D memory device of claim 12, wherein the blocking layer comprises a high-k dielectric material having a dielectric constant greater than about 7.

8.

14. 13. The 3D memory device of claim 12, wherein the blocking layer comprises a high-k dielectric material having a dielectric constant of about 10 or greater.

15. 13. The 3D memory device of claim 12, wherein the blocking layer comprises at least one of zirconium oxide, lanthanum oxide, hafnium oxide, yttrium oxide, or doped aluminum oxide.

16. 16. The 3D memory device of claim 15, wherein the blocking layer comprises at least one of zirconium dioxide, zirconium aluminum dioxide, or doped zirconium dioxide.

17. 16. The 3D memory device of claim 15, wherein the blocking layer comprises lanthanum aluminate.

18. 16. The 3D memory device of claim 15, wherein the blocking layer comprises doped hafnium oxide.

19. 13. The 3D memory device of claim 12, comprising a nucleation or seed layer disposed between the blocking layer and the word lines.

20. 20. The 3D memory device of claim 19, wherein the nucleation layer or the seed layer comprises at least one of molybdenum silicide, molybdenum oxide silicide, molybdenum nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or tantalum silicon nitride.

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