Stacked field effect transistor structure with independent gate control between top and bottom gates - Patents.com

Abstract

The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric insulating layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent from control of the second gate through the second conductive contact.

Description

[Technical Field]

[0001] The present disclosure relates generally to electrical devices, and more particularly to stacked FET structures that allow independent gate control of the top and bottom gates. [Background technology]

[0002] In stacked nanosheet transistor structures, the gate controls of individual transistors can generally be shared by the same gate element. FIG. 1A shows a conventional stacked transistor device. As can be seen in this figure, the top and bottom transistors share the same gate. In some devices, the top and bottom transistors may be different types of devices (e.g., PFET and NFET). In I / O circuit designs, not all of the gates of an NFET / PFET structure are connected. By sharing the same gate, the NFET may induce noise in the circuitry connected to the PFET.

[0003] Although noise is undesirable, current fabrication processes are typically limited by the standard practice of forming dummy gate areas for all channels in a stacked nanosheet structure. The nanosheets of the semiconducting channels are formed with sacrificial layers that ultimately define the insulators between each channel layer. Dummy gate material is deposited around the nanosheet stack until the signal channels are defined. When the dummy gate material is removed, dummy gate cavities are adjacent to all signal channels. The gate material indiscriminately fills the cavities adjacent to these channels, so that each transistor contacts the same gate metal. Therefore, when a signal is conducted by the gate for one transistor, the other transistor sharing contact with the same gate material may induce parasitics, such as noise. Summary of the Invention

[0004] Generally, embodiments provide semiconductor devices and fabrication methods that enable independent gate control between top and bottom gates in stacked transistor devices. Stacked transistors no longer need to share the same gate element. By separating the gate control, the device eliminates parasitics, such as noise, from transistors that are not part of a circuit that generates a signal but share their gates with transistors used in a different circuit that generates a signal.

[0005] According to one embodiment of the present disclosure, a semiconductor chip device is provided. The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A dielectric insulating layer is over at least a portion of the first transistor. A second transistor is over at least a portion of the dielectric insulating layer. A second gate is electrically coupled to the second transistor. The dielectric insulating layer is disposed to insulate the first gate from the second gate. A first conductive contact is electrically coupled to the first gate. The first conductive contact is within a first lateral boundary of the first transistor and outside a second lateral boundary of the second transistor.

[0006] In one embodiment, a second conductive contact is electrically coupled to the second gate. The second conductive contact is within the first lateral boundary and within the second lateral boundary. As can be seen, this structure defines individual access to each gate by offsetting the boundaries of each gate. In a stacked structure, the gates typically share the same contact because the bottom gate is blocked from accessing the top side by the top gate. However, offsetting the gate boundaries allows a path to access the bottom gate independently from the top gate.

[0007] According to one embodiment of the present disclosure, a semiconductor chip device is provided. The semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric insulating layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. Control of the first gate through the first conductive contact is independent from control of the second gate through the second conductive contact.

[0008] In one embodiment that may be combined with the preceding embodiments, the semiconductor device includes a third conductive contact electrically coupled to the first source / drain of the first transistor. The third conductive contact is connected to the front side of the first transistor. A fourth conductive contact is electrically coupled to the second source / drain of the first transistor. The fourth conductive contact is connected to the front side of the first transistor. A fifth conductive contact is electrically coupled to the first source / drain of the second transistor. The fifth conductive contact is connected to the front side of the second transistor. A sixth conductive contact is electrically coupled to the second source / drain of the second transistor. The sixth conductive contact is connected to the front side of the second transistor. When combined with independent gate access, access to the bottom transistor element can be achieved simultaneously with access to the top transistor element from the front side of the device. Thus, the manufacturing process may be easier by forming access to stacked transistors entirely on the front side of the device.

[0009] According to one embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device. The method includes forming a first stack of nanosheets on a substrate. A second stack of nanosheets is formed on top of the first stack of nanosheets. A first dummy gate is formed adjacent to the first stack of nanosheets and below a bottom nanosheet of the second stack of nanosheets. A dielectric insulating layer is formed on top of the first dummy gate and intermediate the first stack of nanosheets and the second stack of nanosheets. A second dummy gate is formed on top of the dielectric insulating layer and adjacent to the second stack of nanosheets. The first dummy gate is replaced with a bottom gate electrically coupled to the first stack of nanosheets. The first stack of nanosheets cooperates with a gate material of the bottom gate to form a first transistor. The second dummy gate is replaced with a top gate electrically coupled to the second stack of nanosheets. The second stack of nanosheets cooperates with a gate material of the top gate to form a second transistor. A first conductive contact is formed electrically coupled to the bottom gate, and a second conductive contact is formed electrically coupled to the top gate, where control of the bottom gate through the first conductive contact is independent from control of the top gate through the second conductive contact.

[0010] In one embodiment that may be combined with the previous embodiments, the method includes forming a third conductive contact electrically coupled to the first source / drain of the first transistor. The third conductive contact is connected to the backside of the first transistor. A fourth conductive contact is formed electrically coupled to the second source / drain of the first transistor. The fourth conductive contact is connected to the backside of the first transistor. A fifth conductive contact is formed electrically coupled to the first source / drain of the second transistor. The fifth conductive contact is connected to the front side of the second transistor. A sixth conductive contact is formed electrically coupled to the second source / drain of the second transistor. The sixth conductive contact is connected to the front side of the second transistor. This embodiment provides backside access to bottom transistor elements, which may be useful in applications involving backside layers. For example, some applications include back-end layers on the backside of a device and / or a wafer carrier. By having connections to the bottom transistor available from the backside, topside area is conserved for more circuit elements.

[0011] The techniques described herein can be implemented in multiple ways. Exemplary implementations are provided below with reference to the following figures: [Brief explanation of the drawings]

[0012] The drawings are of exemplary embodiments. They do not depict all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more efficient illustration. Some embodiments may be practiced with additional components or steps and / or without all of the components or steps shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0013] [Figure 1]FIG. 1A is a cross-sectional view of a conventional field effect transistor with shared gate control, and FIG. 1B is a cross-sectional view of a field effect transistor with independent control of the top and bottom gates consistent with embodiments of the present disclosure.

[0014] [Figure 2] 18A, 18B, and 18C are legends illustrating the axes of view perspective in FIGS. 3A, 3B, and 3C through 18A, 18B, and 18C, consistent with an embodiment of the present disclosure.

[0015] [Figure 3] FIG. 3A shows a diagram of an initial starting formation of a process for fabricating a semiconductor with independent gate control according to an embodiment, FIG. 3B shows a diagram of an initial starting formation of a process for fabricating a semiconductor with independent gate control according to an embodiment, and FIG. 3C shows a diagram of an initial starting formation of a process for fabricating a semiconductor with independent gate control according to an embodiment.

[0016] [Figure 4] FIG. 4A shows a diagram of depositing a hard mask and an organic planar layer according to one embodiment, FIG. 4B shows a diagram of depositing a hard mask and an organic planar layer according to one embodiment, and FIG. 4C shows a diagram of depositing a hard mask and an organic planar layer according to one embodiment.

[0017] [Figure 5] FIG. 5A illustrates etching down a portion of the hard mask and dummy gate material according to one embodiment, FIG. 5B illustrates etching down a portion of the hard mask and dummy gate material according to one embodiment, and FIG. 5C illustrates etching down a portion of the hard mask and dummy gate material according to one embodiment.

[0018] [Figure 6] FIG. 6A shows a diagram of removing the organic planar layer according to one embodiment, FIG. 6B shows a diagram of removing the organic planar layer according to one embodiment, and FIG. 6C shows a diagram of removing the organic planar layer according to one embodiment.

[0019] [Figure 7] FIG. 7A shows a diagram of depositing a dielectric insulating layer according to one embodiment, FIG. 7B shows a diagram of depositing a dielectric insulating layer according to one embodiment, and FIG. 7C shows a diagram of depositing a dielectric insulating layer according to one embodiment.

[0020] [Figure 8] Figure 8A shows a diagram of removing a portion of the dielectric insulating layer from the top stack of nanosheets according to one embodiment, Figure 8B shows a diagram of removing a portion of the dielectric insulating layer from the top stack of nanosheets according to one embodiment, and Figure 8C shows a diagram of removing a portion of the dielectric insulating layer from the top stack of nanosheets according to one embodiment.

[0021] [Figure 9] Figure 9A shows a diagram of depositing an upper section of dummy gate material around an upper stack of nanosheets according to one embodiment, Figure 9B shows a diagram of depositing an upper section of dummy gate material around an upper stack of nanosheets according to one embodiment, and Figure 9C shows a diagram of depositing an upper section of dummy gate material around an upper stack of nanosheets according to one embodiment.

[0022] [Figure 10] FIG. 10A shows a diagram of patterning an upper section of dummy gate material according to one embodiment, FIG. 10B shows a diagram of patterning an upper section of dummy gate material according to one embodiment, and FIG. 10C shows a diagram of patterning an upper section of dummy gate material according to one embodiment.

[0023] [Figure 11] FIG. 11A shows a diagram of penetrating downward through the top stack of nanosheets to form a recess, according to one embodiment; FIG. 11B shows a diagram of penetrating downward through the top stack of nanosheets to form a recess, according to one embodiment; and FIG. 11C shows a diagram of penetrating downward through the top stack of nanosheets to form a recess, according to one embodiment.

[0024] [Figure 12] Figure 12A shows a diagram of selectively removing sacrificial layer material from a top stack of nanosheets and from a portion of a bottom stack of nanosheets according to one embodiment, Figure 12B shows a diagram of selectively removing sacrificial layer material from a top stack of nanosheets and from a portion of a bottom stack of nanosheets according to one embodiment, and Figure 12C shows a diagram of selectively removing sacrificial layer material from a top stack of nanosheets and from a portion of a bottom stack of nanosheets according to one embodiment.

[0025] [Figure 13] Figure 13A shows a diagram of depositing a space material into a cavity formed by selective removal of a sacrificial layer material according to one embodiment, Figure 13B shows a diagram of depositing a space material into a cavity formed by selective removal of a sacrificial layer material according to one embodiment, and Figure 13C shows a diagram of depositing a space material into a cavity formed by selective removal of a sacrificial layer material according to one embodiment.

[0026] [Figure 14] FIG. 14A shows a diagram of removing a portion of the bottom gate material according to one embodiment, FIG. 14B shows a diagram of removing a portion of the bottom gate material according to one embodiment, and FIG. 14C shows a diagram of removing a portion of the bottom gate material according to one embodiment.

[0027] [Figure 15] FIG. 15A shows a diagram of removing a portion of the top gate material according to one embodiment, FIG. 15B shows a diagram of removing a portion of the top gate material according to one embodiment, and FIG. 15C shows a diagram of removing a portion of the top gate material according to one embodiment.

[0028] [Figure 16]FIG. 16A illustrates a diagram of replacing an upper dummy gate material with a metal gate material according to one embodiment, FIG. 16B illustrates a diagram of replacing an upper dummy gate material with a metal gate material according to one embodiment, and FIG. 16C illustrates a diagram of replacing an upper dummy gate material with a metal gate material according to one embodiment.

[0029] [Figure 17] FIG. 17A illustrates the removal of interlayer dielectric material above the bottom dummy gate material from the top side in accordance with one embodiment, FIG. 17B illustrates the removal of interlayer dielectric material above the bottom dummy gate material from the top side in accordance with one embodiment, and FIG. 17C illustrates the removal of interlayer dielectric material above the bottom dummy gate material from the top side in accordance with one embodiment.

[0030] [Figure 18] FIG. 18A illustrates a diagram of replacing a bottom dummy gate material with a metal gate material according to one embodiment, FIG. 18B illustrates a diagram of replacing a bottom dummy gate material with a metal gate material according to one embodiment, and FIG. 18C illustrates a diagram of replacing a bottom dummy gate material with a metal gate material according to one embodiment.

[0031] [Figure 19] FIG. 19A is a legend similar to FIG. 2 but including a fourth axis M consistent with the embodiment, FIG. 19B shows a diagram of forming metal contacts according to one embodiment, FIG. 19C shows a diagram of forming metal contacts according to one embodiment, FIG. 19D shows a diagram of forming metal contacts according to one embodiment, and FIG. 19E shows a diagram of forming metal contacts according to one embodiment.

[0032] [Figure 20]Figure 20A shows a diagram of bonding a back-end layer and carrier wafer to the bottom side of a substrate according to one embodiment, Figure 20B shows a diagram of bonding a back-end layer and carrier wafer to the bottom side of a substrate according to one embodiment, Figure 20C shows a diagram of bonding a back-end layer and carrier wafer to the bottom side of a substrate according to one embodiment, and Figure 20D shows a diagram of bonding a back-end layer and carrier wafer to the bottom side of a substrate according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0033] [overview] In conventional stacked transistor devices, transistor structures generally share the same gate element and must share metal contacts. Shared gate control leads to various signal issues, including undesired noise from nearby transistors that are not part of the circuit. Generally, embodiments in the present disclosure provide semiconductor devices that enable independent gate control between top and bottom gate-all-around structures within a transistor. In one example, the device is a field effect transistor (FET) with a stacked nanosheet structure.

[0034] In the following detailed description, by way of example, numerous specific details are set forth in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described in relatively broad terms, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0035] In one aspect, spatially related terms, such as "front," "back," "top," "bottom," "beneath," "below," "lower," "above," "upper," "side," "left," and "right," are used with reference to the orientation of the figures being described. Because components of the embodiments of the present disclosure may be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It will therefore be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is rotated, elements described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, for example, the term "below" can encompass both an orientation of above and below. The device may be oriented differently (rotated 90 degrees or viewed or referenced in other directions) and the spatially relative descriptors used herein should be interpreted accordingly.

[0036] As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a chip or substrate. In this disclosure, the "first surface" may be the top layer of a semiconductor device where individual circuit devices are patterned into the semiconductor material.

[0037] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to the first surface of the chip, chip carrier, chip substrate, or semiconductor body.

[0038] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together; intervening elements may be provided between "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low-resistance electrical connection between elements that are electrically connected together. The phrase "electrically connected" does not necessarily imply that elements must be in direct physical contact together; intervening elements may be provided between "connected" or "electrically connected" elements.

[0039] Although terms such as "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the exemplary embodiments. Describing an element as "first" or "second," etc., does not necessarily imply an order or priority to any of the elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Exemplary embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Accordingly, regions illustrated in the figures are schematic in nature, and their shapes do not necessarily represent the actual shape of a region of a device and are not limiting in scope. It should be understood that the figures and / or drawings accompanying this disclosure are illustrative, non-limiting, and are not necessarily drawn to scale.

[0041] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments. [Example Device Structure]

[0042] Referring now to FIG. 1B, a cross-sectional view of a semiconductor device 100 (generally referred to as “device 100”) consistent with embodiments of the present disclosure is shown. Device 100 includes a first transistor structure 110 and a second transistor structure 120. The areas of each of transistor structures 110 and 120 are delimited by dashed lines. Both transistor structures 110 and 120 may include multiple stacked nanosheet semiconductor channels (115 and 125, respectively). Transistor structures 110 and 120 may be either PFET, NFET, or one PFET or one NFET type transistor. In the illustrated embodiment, transistor structure 110 is stacked on top of transistor structure 120. Accordingly, in some cases, transistor structure 110 is referred to as the “top transistor 110” and transistor structure 120 is referred to as the “bottom transistor 120.” Embodiments may also include a gate element 340 dedicated to the top transistor 110 and a gate element 350 dedicated to the bottom transistor 120 that is separate from the gate element 340. The gate element 340 may sometimes be referred to as a “top gate 340,” consistent with embodiments that refer to the top transistor 100. The gate element 350 may sometimes be referred to as a “bottom gate 350,” consistent with embodiments that refer to the “bottom transistor 120.” The device 100 includes a dielectric insulating layer 235 that separates or partitions the gate element 340 from the gate element 350. The transistor structures 110 and 120, the gate element 340, and the gate element 350 may be supported by a substrate 150. Embodiments generally also include a metal contact 135 electrically connected to the first transistor structure 110. Embodiments may include separate metal contacts for the top and bottom gates 340 and 350. Metal contact 135 may be electrically connected to gate element 340 from the top side of device 100. Metal contact 145 may be electrically connected to gate element 350 and may be dedicated to gate element 350. Although not shown in this figure, embodiments may include a separate metal contact electrically connected to transistor 120. [Exemplary Manufacturing Method]

[0043] Below, the process describes a general method for forming a semiconductor device with independent gate control for multiple transistors within the same device. Figure 2 shows a legend providing various views of the semiconductor device during the fabrication process. The "X" axis is from an end-on perspective of the stack of nanosheets, showing the bottom and top gates. The "Y" axis is from a side-on perspective along the top of the nanosheet stack. The "M" axis is from a perspective down the center of the bottom stack of nanosheets.

[0044] Referring now first to Figures 3A through 3C, a method of fabricating a semiconductor device 100 having independent gate control of top and bottom transistors will be described, by way of example. Figures 3A through 20D illustrate a fabrication process that includes additive and subtractive processes for forming several circuit elements within the end device. The additive and subtractive processes involved (e.g., masking, deposition, etching, lithography, etc.) may be known to those skilled in the art but are not necessarily identified in each act shown. Fabrication of the devices described herein may include, for example, a multi-step sequence of photolithographic and / or chemical processing steps that facilitate the progressive creation of electronic-based systems, devices, components, and / or circuits within semiconductors and / or semiconductor devices (e.g., integrated circuits). For example, devices may be fabricated on one or more substrates (e.g., silicon (Si) substrates and / or other substrates) using techniques including, but not limited to, photolithography, microlithography, nanolithography, nanoprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, and / or other photoresist techniques), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or other etching techniques), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or other thermal treatments), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), backgrinding techniques, and / or other techniques for fabricating integrated circuits. In some figures, some reference numbers of elements not affected by a step may not be repeated.

[0045] 3A-3C, the process is shown from an initial starting point including a first stack of nanosheets formed below a second stack of nanosheets on a substrate 150. One skilled in the art would understand that the process arrives at this initial structure without any discussion of the formation of nanosheets on the substrate 150. References to a "first" structure may generally refer to the bottom gate and bottom transistor element. References to a "second" structure may generally refer to the top gate and top transistor element.

[0046] The first stack of nanosheets includes alternating layers of sacrificial material 240 (e.g., including silicon-germanium with a germanium concentration of 30% (SiGe30)) and a semiconductor layer (e.g., silicon) 125. The second stack of nanosheets is similar to the first stack, except that the semiconductor layer is labeled 115. Additionally, as shown from the perspective shown in FIG. 3A, the first stack of nanosheets can be formed laterally longer than the width of the second stack. Some embodiments include a sacrificial layer 250 (e.g., SiGe60) formed between the first stack of nanosheets and the second stack of nanosheets. As a prelude to the final result, the second stack of nanosheets is used to define the second (or top) transistor structure 110, while the first stack of nanosheets is used to define the first (or bottom) transistor structure 120 (both shown in FIG. 1B).

[0047] An oxide layer 230 may be formed on top of both the top and bottom stacks of nanosheets. A first dummy gate material 220 is formed on top of the oxide layer 230. The first dummy gate material 220, at this stage, surrounds both the top stack of nanosheets and the bottom stack of nanosheets. A hard mask 210 may be added to the top of the structure to define an area for the recess.

[0048] 4A-4C show the placement of an organic planarization layer (OPL) 260 into the recess resulting from FIGS. 3B and 3C.

[0049] In FIGS. 5A-5C, the hard mask 210 is stripped. The dummy gate material 220 is etched down around the second stack of nanosheets (e.g., using reactive ion etching (RIE)). In the vertical plane, the top step of the dummy gate material 220 can be removed until the top step is below the bottom semiconductor layer 115. In the illustrated embodiment, the removal is performed down to the same level as the sacrificial layer 250, but portions of the dummy gate material 220 remain on top of the oxide layer 230 above and on either side of the first stack of nanosheets. In FIGS. 6A-6C, the OPL 260 can be removed to expose the oxide layer 230 all around the second stack of nanosheets. By way of preamble, the remaining dummy gate material 220 defines the gate area of ​​the bottom transistor 120.

[0050] 7A-7C, a layer of dielectric 235 (e.g., silicon nitride or any non-EG oxide) is deposited on top of oxide layer 230 and dummy gate material 220, for example, using an atomic layer deposition (ALD) process. FIGS. 8A-8C show the placement of OPL 245 above dielectric 235 positioned above dummy gate material 220. A portion of OPL 245 may cover a vertical portion of dielectric 235 that extends to the side of the base of the top stack of nanosheets. Dielectric 235 above OPL 245 and surrounding the top stack of nanosheets may be removed to expose oxide layer 230.

[0051] 9A-9C, a second dummy gate material 280 can be deposited on top of the dielectric 235 and the exposed section of oxide 230 surrounding the top stack of nanosheets. The second dummy gate material 280 can be the same as or different from the dummy gate material 220. A portion of the second dummy gate material 280 is deposited in the area planned for the formation of the top gate element. As can be seen, the location of the dielectric 235 isolates the top gate area from the bottom gate area (outside the area where the top transistor transitions to the bottom transistor), which ultimately leads to the formation of a connection that provides independent control of the top gate element from the bottom gate element. FIGS. 10A-10C show the patterning of a recess in the dummy gate material 280 using a gate hard mask 290.

[0052] 11A-11C show the execution of a recess into the top stack of nanosheets. The height of the recess can extend beyond the sacrificial layer 250 to the top sacrificial layer 240 of the bottom stack of nanosheets. Some embodiments can include depositing a spacer layer 225 on both sides of the recessed walls. Some embodiments include depositing a dielectric layer 265, for example, using a spin-on-glass (SOG) process, on the section of the oxide layer 230 covering the bottom stack of nanosheets.

[0053] 12A-12C, material in the sacrificial layer 240 in the top stack of nanosheets can be selectively removed to form a cavity recessed inward from either side of the semiconducting channel 115 (see FIG. 12B). Material removal can be performed down to the top sacrificial layer 240 of the bottom stack of nanosheets. In addition, the same process for removing sacrificial layer 240 can also remove sacrificial layer 250 from between the top and bottom nanosheet stacks, leaving space 250. e 13A-13C, the depressions and spaces 250 remaining from the removal of the sacrificial layer material are shown. eThe cavity defining the top and bottom transistor structures 110, 120 may be filled with insulating spacer material 270. The insulating spacer material 270 provides a conductive barrier between the top and bottom transistor structures 110, 120. At this stage, the insulating spacer material 270 cooperates with the dielectric layer 235 to form an insulating barrier between the top and bottom gate areas.

[0054] 14A-14C illustrate the process of removing portions of the dummy gate materials 220 and 280 using a hard mask 290 (exposing the oxide 275 during this process). The left and right edges of the dummy gate material 220 define the lateral boundaries of the bottom gate area. In FIG. 14B, the source-drain material 310 (oriented horizontally) of the top transistor is shown. In FIGS. 14B and 14C, the source-drain material 320 (oriented horizontally) of the bottom transistor is shown. An insulator 330 is positioned intermediate the top transistor source-drain 310 and the bottom transistor source-drain 320.

[0055] 15A-15C, a cutting process for removing dummy gate material 220 of the top gate element is shown. As shown in FIG. 15A, a portion of dummy gate material 280 is removed. In one embodiment, the left lateral boundary edge of dummy gate material 280 shares a lateral boundary edge with the left side of dummy gate material 220. The right side of dummy gate material 280 may be removed laterally inward beyond the outer right lateral boundary edge of dummy material 220. By shifting the gate area, space becomes available for adding a separate metal contact for the bottom gate, which is accessed by the top side (as can be seen in FIG. 19B).

[0056] 16A-16C, the process removes the sacrificial layer 240 in favor of the top stack of nanosheets and top dummy gate material 280. The top dummy gate material 280 is replaced with a metal gate 340. Those skilled in the art will understand available techniques for replacing the dummy gate material 280 with the metal gate 340. The removal of the sacrificial layer 240 may also form a cavity in the middle of the semiconductor channel 115. The placement of the metal gate 340 may fill the channel cavity and form a mandrel around the channel. In some embodiments, the top transistor 110 may be a gate-all-around structure.

[0057] 17A-17C, an area of ​​oxide 275 above dummy gate material 220 can be opened. In the embodiment shown, the opened area is above a section of the bottom nanosheet stack that extends laterally to the right of upper transistor 110. This opening allows both oxide 275 and a section of dielectric 235 to be removed, exposing dummy gate material 220 to the top side of device 100. FIGS. 18A-18C show the results of removing dummy gate material 220 and replacing it with metal gate 350. Metal gate 350 can be the same metal as gate 340 or a different metal than gate 340. Similar to upper transistor 110, metal gate 350 can wrap around channel 125 to form transistor 120.

[0058] Figures 19A-19E show an example of the resulting structure for device 100 after metal contacts 130, 135, and 145 have been added to connect top gate 340 and bottom gate 350 to the top side of device 100. Figure 19A has a legend similar to that in Figure 2, except that a fourth axis H has been added to show a cross-sectional perspective view along the bottom gate contact. Process steps showing recessing material to form openings for metal contacts 130, 135, and 145 have been omitted.

[0059] In Figure 19B, metal contact 130 electrically couples the source-drain of top transistor 110 to the upper surface through the top side of transistor 110. Metal contact 140 electrically couples the source-drain of bottom transistor 120 to the upper surface through the top side of transistor 120. Metal contact 135 electrically couples gate 340 of top transistor 110 to the upper surface. Metal contact 145 electrically couples bottom gate 350 of bottom transistor 120 to the upper surface. An additional perspective shown along axis H is added, which is from a cross-sectional perspective along a device structure including multiple metal contacts 145 (as shown in Figure 19D).

[0060] 20A-20D show one embodiment of device 100, which is similar to the embodiment shown in FIGS. 19B-19E, except that device 100 is configured for backside access of bottom transistor 120. Metal contacts 165 may be formed on the backside of substrate 150 (FIG. 20C). Metal contacts 165 may be electrically coupled to source-drain areas 320 of bottom transistor 120. In some embodiments, back-end layers 370 may be formed below substrate 150. Some embodiments may include a carrier wafer 380 formed below back-end layers 370. [Conclusion]

[0061] The description of various embodiments of the present teachings is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0062] While the above describes what is believed to be the best mode and / or alternative examples, it is understood that various modifications may be made therein, that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied to many applications, only some of which are described herein. It is intended that the following claims claim any and all applications, modifications, and variations that are within the true scope of the present teachings.

[0063] The components, steps, features, objects, benefits, and advantages described herein are merely exemplary. Neither they nor the descriptions associated therewith are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, dimensions, sizes, and other specifications described herein, including the following claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they relate and that which is customary in the technical field to which they pertain.

[0064] Many other embodiments are contemplated, including embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, including embodiments in which the components and / or steps are arranged and / or ordered differently.

[0065] While the above has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" means only an example, not best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, or should be construed to, provide the public with any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0066] Unless a specific meaning is otherwise stated herein, it is understood that the terms and expressions used herein have the ordinary meanings ascribed to such terms and expressions with respect to the corresponding respective fields of inquiry and study. For example, relative terms such as first and second may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between the entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may include other elements not inherent in or expressly described in such process, method, article, or apparatus. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the element.

[0067] An Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. a first transistor; a first gate electrically coupled to the first transistor; a dielectric insulating layer over at least a portion of the first transistor; a second transistor over at least a portion of the dielectric insulating layer; a second gate electrically coupled to the second transistor, the dielectric insulating layer being disposed to insulate the first gate from the second gate; and a first conductive contact electrically coupled to the first gate, the first conductive contact being within a first lateral boundary of the first transistor and outside a second lateral boundary of the second transistor; A semiconductor device comprising:

2. 2. The semiconductor device of claim 1, further comprising a second conductive contact electrically coupled to the second gate, the second conductive contact being within the first lateral boundary and within the second lateral boundary.

3. a second conductive contact electrically coupled to the first source or drain of the first transistor, the second conductive contact being connected to a front side of the first transistor; and a third conductive contact electrically coupled to a second source or drain of the first transistor, the third conductive contact being connected to the front side of the first transistor; The semiconductor device of claim 1 further comprising:

4. a fourth conductive contact electrically coupled to the first source or drain of the second transistor, the fourth conductive contact being connected to a front side of the second transistor; and a fifth conductive contact electrically coupled to a second source or drain of the second transistor, the fifth conductive contact being connected to the front side of the second transistor; The semiconductor device of claim 3 further comprising:

5. a second conductive contact electrically coupled to the first source or drain of the first transistor, the second conductive contact being connected to a backside of the first transistor; a third conductive contact electrically coupled to a second source or drain of the first transistor, the third conductive contact being connected to the backside of the first transistor; a fourth conductive contact electrically coupled to the first source or drain of the second transistor, the fourth conductive contact being connected to a front side of the second transistor; and a fifth conductive contact electrically coupled to a second source or drain of the second transistor, the fifth conductive contact being connected to the front side of the second transistor; The semiconductor device of claim 1 further comprising:

6. The semiconductor device of claim 1 , further comprising a stack of nanosheets in the first transistor and in the second transistor.

7. a first transistor; a first gate electrically coupled to the first transistor; a second transistor positioned above the first transistor; a second gate electrically coupled to the second transistor; a dielectric insulating layer positioned between the first gate and the second gate; a first conductive contact electrically coupled to the first gate; and a second conductive contact electrically coupled to the second gate, wherein control of the first gate through the first conductive contact is independent from control of the second gate through the second conductive contact; A semiconductor device comprising:

8. The semiconductor device of claim 7 , wherein the second gate is positioned above at least a portion of the first gate.

9. The semiconductor device of claim 7 , further comprising a stack of nanosheets in the first transistor and in the second transistor.

10. 10. The semiconductor device of claim 9, further comprising a gate material for the first and second gates, the gate material being wrapped around the stack of nanosheets.

11. a third conductive contact electrically coupled to the first source or drain of the first transistor, the third conductive contact being connected to a front side of the first transistor; a fourth conductive contact electrically coupled to a second source or drain of the first transistor, the fourth conductive contact being connected to the front side of the first transistor; a fifth conductive contact electrically coupled to the first source or drain of the second transistor, the fifth conductive contact being connected to a front side of the second transistor; and a sixth conductive contact electrically coupled to a second source or drain of the second transistor, the sixth conductive contact being connected to the front side of the second transistor; The semiconductor device of claim 7 further comprising:

12. a third conductive contact electrically coupled to the first source or drain of the first transistor, the third conductive contact being connected to a backside of the first transistor; a fourth conductive contact electrically coupled to a second source or drain of the first transistor, the fourth conductive contact being connected to the backside of the first transistor; a fifth conductive contact electrically coupled to the first source or drain of the second transistor, the fifth conductive contact being connected to a front side of the second transistor; and a sixth conductive contact electrically coupled to a second source or drain of the second transistor, the sixth conductive contact being connected to the front side of the second transistor; The semiconductor device of claim 7 further comprising:

13. 8. The semiconductor device of claim 7, wherein the first transistor is an NFET and the second transistor is a PFET.

14. 8. The semiconductor device of claim 7, wherein the first transistor is a PFET and the second transistor is an NFET.

15. 1. A method for manufacturing a semiconductor device, comprising: forming a first stack of nanosheets on a substrate; forming a second stack of nanosheets on top of the first stack of nanosheets; forming a first dummy gate adjacent to the first stack of nanosheets and below a bottom nanosheet of the second stack of nanosheets; forming a dielectric insulating layer on top of the first dummy gate and between the first stack of nanosheets and the second stack of nanosheets; forming a second dummy gate on top of the dielectric insulating layer and adjacent to the second stack of nanosheets; replacing the first dummy gate with a bottom gate electrically coupled to the first stack of nanosheets, the first stack of nanosheets cooperating with a gate material of the bottom gate to form a first transistor; replacing the second dummy gate with a top gate electrically coupled to the second stack of nanosheets, the second stack of nanosheets cooperating with a gate material of the top gate to form a second transistor; forming a first conductive contact electrically coupled to the bottom gate; and forming a second conductive contact electrically coupled to the top gate, wherein control of the bottom gate through the first conductive contact is independent from control of the top gate through the second conductive contact. A method comprising:

16. 16. The method of claim 15, further comprising forming the first stack of nanosheets to include a width greater than a width of the second stack of nanosheets.

17. forming a recess inward to a lateral boundary of the second dummy gate, the lateral boundary of the second dummy gate being within a lateral boundary of the first dummy gate; and positioning the first conductive contact outside a lateral boundary of the top gate and within a lateral boundary of the bottom gate; 17. The method of claim 16, further comprising:

18. forming a third conductive contact electrically coupled to a first source or drain of the first transistor, the third conductive contact connected to a front side of the first transistor; forming a fourth conductive contact electrically coupled to a second source or drain of the first transistor, the fourth conductive contact connected to the front side of the first transistor; forming a fifth conductive contact electrically coupled to a first source or drain of the second transistor, the fifth conductive contact being connected to a front side of the second transistor; and forming a sixth conductive contact electrically coupled to a second source or drain of the second transistor, the sixth conductive contact connected to the front side of the second transistor. The method of claim 15 further comprising:

19. forming a third conductive contact electrically coupled to a first source or drain of the first transistor, the third conductive contact connected to a backside of the first transistor; forming a fourth conductive contact electrically coupled to a second source or drain of the first transistor, the fourth conductive contact connected to the backside of the first transistor; forming a fifth conductive contact electrically coupled to a first source or drain of the second transistor, the fifth conductive contact being connected to a front side of the second transistor; and forming a sixth conductive contact electrically coupled to a second source or drain of the second transistor, the sixth conductive contact connected to the front side of the second transistor. The method of claim 15 further comprising:

20. forming a back-end layer on the back side of the substrate; and forming a wafer carrier behind the back end layer; 20. The method of claim 19 further comprising:

Images