Super-junction power semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a super-junction power semiconductor device (20) comprising a substrate (1), a plurality of core structures (4), and a plurality of annular shell structures (5). Each core structure (4) has a cylindrical shape extending in a direction perpendicular to a major surface of the substrate (1) and including a first semiconductor material of a first conductivity type. Each shell structure (5) surrounds one of the core structures (4) on its exterior and includes a second semiconductor material of a second conductivity type. The present disclosure further relates to a method (30) for manufacturing the super-junction power semiconductor device (20).

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor devices and methods for their manufacture, and more particularly to novel approaches involving selectively grown superjunction nanostructures for power semiconductor devices. [Background technology]

[0002] Wide bandgap (WBG) semiconductor materials such as silicon carbide (SiC) have advantageous properties, including high critical electric fields and electron mobility or high-frequency switching. Therefore, they offer a much larger Baliga figure of merit (BFOM) compared to commonly used semiconductor materials such as silicon, making them a good choice for power semiconductor devices such as power MISFETs. These advantages enable several applications for energy efficiency and electrical transport. Summary of the Invention [Problem to be solved by the invention]

[0003] Today, most commercially available power SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are based on a cell design with a planar channel aligned with the silicon (Si) face, i.e., the SiC(0001) wafer surface. However, increasing the current density in such switches is hindered by the increasing junction-FET (JFET) resistance due to injector downscaling, as well as low inversion channel mobility.

[0004] As an alternative approach, trench MOSFETs, which incorporate dry-etched U-shaped channels, enable low on-resistance due to the lack of a JFET region and high cell density. For SiC channel devices in particular, trench MOSFET architectures allow for carrier mobility optimization by engineering the channel relative to different crystal planes and enhancing gate dielectric control. Despite utilizing different crystal planes for carrier transport, the trench pitch and cell width of known trench MOSFET devices are still quite large when using conventional fabrication techniques. This, in turn, prevents higher cell density and therefore improved current density in the completed semiconductor power device. Furthermore, single-crystal SiC wafers are relatively expensive, further delaying the widespread adoption of this approach on a large scale.

[0005] Therefore, novel processing methods and device architectures that enable higher currents in smaller areas, i.e., improved current densities, are desirable. Furthermore, it would be desirable to integrate such architectures onto a wide range of widely available and competitively priced substrates, such as Si, gallium nitride (GaN), 4H-SiC, or polycrystalline SiC substrates. [Means for solving the problem]

[0006] SUMMARY Embodiments of the present disclosure relate to a super-junction power semiconductor device comprising a substrate, a plurality of core structures, and a plurality of annular shell structures, as well as a method for fabricating the super-junction power semiconductor device.

[0007] According to a first aspect of the present disclosure, there is provided a super-junction power semiconductor device, the device comprising: A substrate; a plurality of core structures, each having a cylindrical shape extending in a direction perpendicular to a major surface of the substrate, and including a first semiconductor material of a first conductivity type; a plurality of annular shell structures, each shell structure externally surrounding one of the core structures and including a second semiconductor material of a second conductivity type; Equipped with.

[0008] The proposed device concept is based on vertically oriented, preferably very narrow, superjunction structures that can be selectively grown from suitable semiconductor materials, including WBG semiconductor materials. Due to their small size and vertical orientation, these structures are also called nanowires or nanopillars. Such superjunction structures go far beyond conventional trench designs, and the proposed selective growth technique allows for improved pitch scaling, i.e., higher currents in smaller areas, and integration on a variety of widely available substrates.

[0009] According to at least one embodiment, the device further comprises a dielectric layer disposed on the primary surface of the substrate. The shell structures surrounding the core structures are embedded in the dielectric layer. Embedding the superjunction structures in the dielectric layer has many advantages over conventional superjunction structures formed directly in bulk semiconductor material. First, it reduces the amount of semiconductor material required to implement the device. Second, the individual superjunction structures are electrically isolated from each other. Third, at least a portion of the dielectric layer can function as a growth template for creating the core structures and / or the annular shell structures and / or as a support structure for carrying terminal contacts.

[0010] According to at least one embodiment, the dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is disposed between the substrate and the second sublayer and includes a plurality of vias therebetween. The second sublayer includes at least a lower portion of each of a plurality of shell structures. The device further includes a plurality of plug structures, each including a third semiconductor material of the second conductivity type and positioned in the region of one of the vias so as to contact the major surface of the substrate and a respective one of the shell structures. The structure allows electrical contact between the shell structures and the substrate of the device. At the same time, the vias may be used to implement a defect filter.

[0011] According to at least one embodiment, the device further comprises a plurality of channel regions formed in each of the shell structures, each channel region comprising a fourth semiconductor material of the first conductivity type and disposed in a control layer of the device. The device further comprises at least one gate structure disposed in the control layer, the at least one gate structure being insulated from and surrounding at least a portion of each of the shell structures. The device comprises a so-called gate-all-around structure that provides very high electric field control of the channel regions. The channel regions can be used to implement various known power semiconductor switching cells, such as MOSFETs.

[0012] According to different embodiments, the substrate may be one of a Si, SiC or GaN semiconductor substrate. The first semiconductor material may be a p-type semiconductor material, in particular Si, or a p-type WBG semiconductor material, in particular SiC, GaN or gallium oxide (Ga x O y The second semiconductor material may comprise an n-type semiconductor material, particularly Si, an n-type WBG semiconductor material, particularly SiC, GaN, Ga x O y , in particular Ga2O3, or n-type diamond.

[0013] The above substrate materials are widely available. At least some of them are significantly less expensive than single-crystal SiC wafers. Furthermore, the specific semiconductor materials used in the core-end cell construction are also widely available and can be processed using conventional semiconductor processing equipment.

[0014] According to various embodiments, the core structure and / or shell structure may extend over a length of 1 to 100 μm, particularly 3 to 15 μm, in a direction perpendicular to the main surface of the substrate. The core structure may have a diameter of 25 μm to 5 μm, particularly 0.1 to 5 μm. The annular cell structure may have a thickness of 0.1 to 5 μm. Multiple core structures may be arranged in a regular pattern, particularly an array structure, with a pitch distance of less than 1 μm and / or at a spacing in the range of 1.1 to 2.5 times the total diameter of one of the core structures surrounded by one of the shell structures.

[0015] The above dimensions and configurations are suitable for fabricating high-density, high-voltage, and / or high-current semiconductor power switching devices. For example, lengths of 1 to 100 μm are suitable for implementing semiconductor switching devices with switching voltages of 1.2 to 3.3 kV at the device level. Core structures with diameters of around 25 nm are particularly suitable for heteroepitaxy, while larger diameters are suitable for higher currents and / or homoepitaxy. Current density is also affected by the dopant concentration of the semiconductor material used. Preferably, the wall thickness of the shell structure may be similar to the diameter of the core structure and / or any plug structures, e.g., with an aspect ratio of 1:1.

[0016] In at least one embodiment, multiple core and / or shell structures are electrically connected in parallel to form a multi-cell field-effect transistor (FET), particularly a metal-insulator-semiconductor field-effect transistor (MISFET), MOSFET, insulated gate bipolar transistor (IGBT), and / or JFET.

[0017] According to a second aspect of the present disclosure, there is provided a method for manufacturing a super-junction power semiconductor device, the method comprising: providing a growth substrate; providing a plurality of vertical growth masks on a growth substrate; Selectively growing a first semiconductor material within a plurality of vertical growth masks to form a corresponding plurality of core structures in a direction perpendicular to the major surface of the growth substrate; at least partially removing the plurality of vertical growth masks, thereby exposing vertical surfaces of the plurality of core structures; selectively growing a second semiconductor material on vertical surfaces of the plurality of core structures to form a corresponding plurality of shell structures surrounding each core structure; Includes.

[0018] In particular, the above method steps enable the fabrication of core-shell superjunction structures as detailed above with respect to the first aspect, for example for implementing nanowire-based superjunction power MOSFETs.

[0019] Instead of processing devices in a conventional top-down manner, such as is used in the fabrication of conventional trench-gate MOSFETs, the fabrication method of the present disclosure is based on a bottom-up approach based on selective epitaxy, which allows for advantageous use of materials in the formation of high density power devices, as described above with respect to the first aspect.

[0020] The vertical growth masks may be formed in a two-stage process. In at least one embodiment, a growth seed mask layer is first formed having a plurality of first openings corresponding to the pitch distance between the core structures. A core structure mask layer is then formed having a plurality of second openings, each of which is located in a region corresponding to a respective first opening and is wider than the respective first opening. This two-layer structure allows for the implementation of defect filtering for a subsequent selective growth stage. Furthermore, the top portion of the vertical growth mask can be partially removed, for example, by using different materials for the sublayers and selectively etching.

[0021] Similarly, the multiple core structures may be formed in a two-stage process. In at least one embodiment, in a first stage, the multiple plug structures are formed by selectively growing a third semiconductor material containing impurities of a first conductivity type, particularly n-type SiC, directly on the growth substrate within the multiple vertical growth masks. The main portions of the multiple core structures are then formed by selectively growing a first semiconductor material containing impurities of a second conductivity type, particularly p-type SiC, within the multiple vertical growth masks, either as a separate step or within a continuous vertical growth process with a modified dopant profile.

[0022] In at least one embodiment, forming the plurality of shell structures includes covering the upper surfaces of the plurality of core structures with a growth inhibitor material, particularly one of silicon dioxide (SiO), silicon nitride (SiN), or aluminum trioxide (AlO), removing upper portions of the plurality of vertical growth masks, particularly the core structure mask, so that the remaining lower portions of the plurality of vertical growth masks, particularly the growth seed mask, cover the growth substrate, and then forming the plurality of shell structures by selectively growing a second semiconductor material in a radial direction, the second semiconductor material including impurities of a first conductivity type, particularly n-type SiC. The above steps allow for controlled radial growth of the shell structures.

[0023] The present disclosure includes several aspects of novel architectures for high density semiconductor devices, particularly super-junction power semiconductor devices. All features described with respect to one of the aspects are also disclosed herein with respect to the other aspects, even if the respective feature is not explicitly mentioned in the context of the particular aspect.

[0024] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals even if they are part of different embodiments and / or have different configurations. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a schematic cross-sectional view of a single cell of a power semiconductor switching device. [Figure 2] FIG. 1 is a perspective view of a power semiconductor device comprising a plurality of nanopillars. [Figure 3A] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3B] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3C] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3D] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3E] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3F] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3G] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3H] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3I] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3J] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3K] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3L] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3M] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 3N] 1 illustrates various stages in the manufacture of a power semiconductor device; [Figure 4] 1 illustrates, in flow chart form, the steps of a method for fabricating a super-junction power semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0026] FIG. 1 shows a cross-sectional view of a cell 10 of a power semiconductor device or similar semiconductor device. A complete semiconductor device may typically include a relatively large number of similar cells electrically connected in parallel to achieve a desired function, including a desired current rating. However, for simplicity of presentation, only a single cell 10 is shown in FIG. 1 and described below.

[0027] The cell 10 comprises a substrate 1, which acts as a carrier substrate and also provides an electrical bottom contact as will be described below.

[0028] A dielectric layer 2 is disposed on the upper major surface of the substrate 1. The dielectric layer 2 may be made of SiO2 or any other suitable insulating material. In the embodiment described herein, the dielectric layer 2 comprises several sublayers 2a to 2c, as described below.

[0029] Embedded in the dielectric layer 2 is a superjunction structure 3. The superjunction structure 3 comprises a core structure 4 and a shell structure 5, the latter surrounding the former on its outside. In the described embodiment, the core structure 4 has a cylindrical shape surrounded by an annular shell structure. However, in other embodiments, an elongated, fin-shaped, or stripe-shaped core structure 4 may be surrounded by a corresponding shell structure. When the superjunction structure 3 is essentially cylindrical, it is also referred to as a nanowire or nanopillar.

[0030] The core structure 4 is made of a first semiconductor material, in particular a WBG semiconductor material of a first conductivity type, such as p-type SiC. The shell structure 5 is made of a second semiconductor material of a different second conductivity type, such as n-type SiC. Preferably, the majority charge carriers in the superjunction structure 3 balance each other.

[0031] The superjunction structure 3 further comprises a plug structure 6 at the bottom end of the core structure 4. The plug structure 6 is made of a third semiconductor material of a second conductivity type. For example, the second and third semiconductor materials may be the same. The plug structure 6 electrically connects the material of the shell structure 5 with the material of the substrate 1. For this purpose, a relatively narrow passage or opening 13 is formed in the bottom sublayer 2a of the dielectric layer 2. The opening 13 may also function as a defect filter for the semiconductor material of the superjunction structure 3 during the growth stage, as will be described below.

[0032] The superjunction structure 3 further includes a channel region 7. The channel region 7 forms part of the shell structure 5. In the embodiment shown in FIG. 1, the channel region 7 is disposed on top of the annular shell structure 5. Because the channel region 7 can be used to control the flow of current through the superjunction structure 3, the plane containing the channel region 7 is also referred to as a control layer. The thickness of the channel region 7 can be between 100 nm and 1000 nm. This can be formed, for example, by implanting a suitable dopant species, such as Al or B, into the top of the shell structure 5 to form a p-type region within the n-type semiconductor material of the shell structure 5. This can be achieved, for example, by ion implantation.

[0033] The conductivity of the channel region 7 is controlled by the surrounding gate structure 8. The gate structure 8 should overlap the channel region 7 on both sides. Its thickness can be between 200 nm and 1500 nm. In the illustrated embodiment, the gate structure 8 is buried in the dielectric layer 2. In particular, it is disposed between its two upper sublayers 2b and 2c. The gate structure 8 is electrically insulated from the shell structure 5 containing the channel region 7 by a relatively thin gate insulator 9. For example, the gate insulator 9 may be formed by a film formed by selective oxidation or deposition of an insulating material.

[0034] A drain electrode 11 is formed on the second major surface below the substrate 1 to contact the upper and lower ends of the superjunction structure 3. A source electrode 12 is also formed on the upper surface of the cell 10, including the upper surface of the top sublayer 2c of the dielectric layer 2 and the upper end of the superjunction structure 3 itself.

[0035] FIG. 2 shows a perspective view of a power semiconductor device 20 including a plurality of switching cells, such as the cell 10 described above with respect to FIG. 1. The switching cells are arranged in a regular pattern, particularly a grid or array structure having a pitch distance d. In the described embodiment, the pitch distance may be about 1 μm or less. Each cell includes a superjunction structure 3 as detailed above. As previously mentioned, these may take the form of nanowires or nanopillars. To achieve high current densities, the pitch distance d may be selected to be slightly larger than the total diameter of each superjunction structure 3, e.g., having an aspect ratio of 1.1:1 to 2.5:1.

[0036] As seen in the front of FIG. 2 , a single cylindrical gate structure 8 surrounds the channel region of each of the superjunction structures 3. These so-called gate-all-around structures 8 are interconnected by a metal layer 15. As detailed above, the gate-all-around structures 8 are embedded between sublayers 2b and 2c, which are formed from dielectric material. In the illustrated embodiment, the metal layer 15 is thinner than the vertical thickness of the gate-all-around structures 8. However, it may also have the same thickness, essentially resulting in a uniform metal layer 15 that acts as a gate structure 8 common to all of the superjunction structures 3.

[0037] In the embodiment shown in Figure 2, the upper edges of the superjunction structures 3 extend slightly over the top surface of the top sublayer 2c of dielectric material. These edges are embedded directly in the metal material of the source electrodes 12 formed thereon. Outside the array of superjunction structures 3, the dielectric material is thicker, forming termination regions 16. On top of termination regions 16, metal layer 15 and gate runners 17 are formed, which serve as external contacts for gate structures 8.

[0038] FIG. 2 further illustrates that the substrate 1 can include multiple sublayers. In the illustrated embodiment, the lower sublayer 1a may be formed by a wafer material, such as a silicon wafer. On its upper surface, an epitaxially grown layer forms a second upper sublayer 1b. For example, polycrystalline SiC may be grown on the lower sublayer 1a as a seed material for growing the superjunction structure 3. In this case, the upper sublayer 1b removes growth defects. In other embodiments, the upper sublayer 1b itself may form part of the completed semiconductor device 20. For example, the upper sublayer 1b may act as part of the drift layer. In still other embodiments, the upper sublayer 1b may be omitted entirely.

[0039] 3A-3N illustrate various stages in the fabrication of a super-junction semiconductor device, such as super-junction power semiconductor device 20 shown in FIG.

[0040] In a first step, shown in Figure 3A, a substrate 1 is provided. As detailed above, the substrate 1 itself comprises two sublayers 1a and 1b. In the described embodiment, the first sublayer 1a is a silicon wafer. The sublayer 1b is an epitaxially grown silicon carbide layer. The substrate 1 is covered with a first dielectric layer 21. As shown in Figure 1, the first dielectric layer 21 covers the top surface of the sublayer 1b of the substrate 1. The first dielectric layer 21 is made of silicon oxide, SiO x , in particular may consist essentially of SiO2, silicon nitride, SiN, or Al2O3.

[0041] As shown in FIG. 3B, portions of the first dielectric layer 21 may be removed to form multiple openings 13. The openings 13 may be formed at regular intervals to form an array or other regular structure on the upper surface of the substrate 1. Such openings 13 may be formed, for example, using conventional lithography. Alternatively, dielectric material may be deposited only in the areas between the intended openings 13, for example, using a suitable selective deposition method. The underlying material of the substrate 1 or its top sublayer 1b serves as a growth seed. In the described embodiment, the openings 13 may have a cross-section of 25 nm. A passage of this diameter effectively functions as a defect filter for selectively growing a core structure on a substrate containing a different semiconductor material and / or crystallographic composition, for example, for growing a SiC superjunction structure on a Si wafer using heteroepitaxy. Therefore, the first dielectric layer 21 is also referred to as a growth seed mask layer. If homoepitaxy is used to grow a SiC superjunction structure on a SiC wafer or epilayer, for example, the openings 13 may be wider, for example, to correspond to the diameter of the subsequently formed core structure 4.

[0042] Figure 3C shows a further stage in the fabrication process, where the top surface of the device under fabrication is covered with a dielectric material to form a second dielectric layer 22. The second dielectric layer 22 is also referred to as the core structure mask layer, as it serves to form a growth mask for the actual core structure. The second dielectric layer 22 is made of SiO x , particularly SiO2, SiN, or Al2O3. The materials of the first and second dielectric layers 21 and 22 may be different if subsequent selective etching is employed. The second dielectric layer 22 may be planarized using commonly known semiconductor processing methods.

[0043] FIG. 3D shows the situation after the material of the second dielectric layer 22 has been structured. This can be achieved, for example, using conventional lithography and selective etching. As can be seen in FIG. 3D, several hollow vertical growth templates or masks 23 are formed. The vertical growth masks 23 include openings 13 in the first dielectric layer 21 and wider openings 24 in the second dielectric layer 22. The vertical growth masks 23 are used to selectively grow an appropriate semiconductor material, such as a WBG semiconductor material, which will later form the core structure 4.

[0044] 3E, the plug structure 6 is formed by selective area epitaxy. This can be achieved, inter alia, by selectively growing, i.e., depositing, semiconductor material only inside the vertical growth mask 23, while growth is inhibited in other areas covered by the material of the growth template, i.e., the first and second dielectric layers 21 and 22.

[0045] As shown, the plug structure 6 is grown within the opening 13 in the first dielectric layer 21 and within the bottom of the opening 24 in the second dielectric layer 22. In the described embodiment, the plug structure 6 is formed by depositing n-type SiC material.

[0046] The remainder of the core structure 4 is then grown on top of the plug structure 6. Growth of the main portion 4a of the core structure 4 may be performed as a separate selective growth step, or may be performed in successive selective growth steps with altered dopant profiles. In the described embodiment, p-type semiconductor material is selectively grown to form the main portion 4a of the core structure 4. This completed core structure 4 is shown in FIG. 3F.

[0047] 3G, the top end of the core structure 4 is capped with a capping element 25. In the described embodiment, this is achieved by filling the remaining portion of the opening 24 in the second dielectric layer 22 with a dielectric material. The capping element 25 may be formed by depositing a growth inhibitor material such as SiO, SiN, or AlO.

[0048] 3H shows the device in fabrication after the remaining material of second dielectric layer 22 has been removed, which can be accomplished, for example, by a selective etching process, exposing the vertical faces 26 of each of the pre-formed core structures 4.

[0049] In a subsequent step shown in FIG. 3I, shell structures 5 are grown radially outward starting from each of the vertical surfaces 26. This step can again be performed using a suitable selective growth method, either homoepitaxy, e.g., forming a SiC shell on a SiC core, or heteroepitaxy, e.g., forming a GaN shell on a SiC core, a diamond shell on a SiC core, or a SiC shell on a Si core. Because both the capping element 25 and the first dielectric layer include growth-inhibiting materials, the shell structures 5 grow only on the vertical surfaces 26, but not on the first dielectric layer 21 overlying the substrate 1, or on or beside the capping element 25. In the described embodiment, the shell structures 5 are grown using n-type SiC material, thereby completing the multiple superjunction structures 3 comprising p-type core structures 4 and n-type shell structures 5.

[0050] In the situation shown in FIG. 3J, the capping element 25 has been removed, for example by selective etching.

[0051] FIG. 3K shows the situation after implanting the channel region 7 in the shell structure 5. For this purpose, ions of a suitable species of the first conductivity type are implanted through the top surface of the superjunction structure 3. This is indicated by the dotted arrow in FIG. 3K. Suitable species for p-type implantation include, for example, Al and B. Note that the additional charge carriers introduced by ion implantation do not significantly affect the electrical properties of the core structure 4. However, they overcompensate the charge concentration in the shell structure 5, changing it from an n-type semiconductor material to a p-type semiconductor material.

[0052] In a subsequent processing stage, shown in Figure 3L, a third dielectric layer 27 may be formed and planarized. In the illustrated embodiment, a suitable dielectric layer is deposited in the areas between the individual superjunction structures 3. The third dielectric layer 27 may be SiO x , in particular may consist essentially of SiO2, SiN or Al2O3, and may be the same material as the second dielectric layer 22. The third dielectric layer 27 serves as the base for a subsequently formed gate electrode and corresponds to the second sublayer 2b in the embodiment shown in FIG.

[0053] The gate insulating structure 9 may be formed, for example, by selective oxidation or controlled deposition of a dielectric material on the exposed portions of the vertical surfaces 26 of the shell structure 5 .

[0054] 3M, a metal material is deposited on top of the third dielectric layer 27 and optionally planarized to form a gate structure 8. In the described embodiment, the gate structure 8 covers essentially the entire surface of the third dielectric layer 27, thereby forming the gate-all-around structure 14 as shown in FIG.

[0055] In the situation shown in Figure 3N, the upper surface of the gate structure 8 is covered by a fourth dielectric layer 28, which corresponds to the third sublayer 2c in Figure 1. This, together with the third dielectric layer 27 and the gate insulator 9, completes the insulation of the gate structure 8.

[0056] Thereafter, a source electrode 12 may be formed on the planarized top surface of the device under fabrication, as also shown in Figure 3N. Similarly, a drain electrode 11 may be formed on the opposite major surface of the substrate 1, i.e., on the back surface of the lower sublayer 1b (not shown in Figure 3N).

[0057] FIG. 4 shows a method 30 for manufacturing a super-junction power semiconductor device, including steps S31 to S35.

[0058] In step S31, a growth substrate, such as substrate 1, comprising sublayers 1a and 1b is provided.

[0059] In step S32, a plurality of vertical growth masks 23 are formed on the growth substrate 1. This may be achieved by the method steps detailed above with respect to Figures 3A-3d, or may be performed using additive manufacturing techniques.

[0060] In step S33, a first semiconductor material is selectively grown within the vertical growth masks to form corresponding core structures perpendicular to the major surface of the growth substrate. This may be performed in one or more selective growth stages, as described above with respect to Figures 3E and 3F. For example, the n-type plug structure 6 may be formed first, followed by the p-type main portion 4a of the core structure.

[0061] In step S34, the vertical growth masks are at least partially removed, thereby exposing the vertical surfaces of the core structures. This may be accomplished, for example, by a selective etching method such as described above with respect to Figures 3G and 3H, or by other suitable methods, such as controlling the length of the etching step to achieve the desired depth of material removal.

[0062] In step S35, a second semiconductor material, such as an n-type semiconductor material, is selectively grown on the previously exposed vertical surfaces of the core structures to form multiple shell structures surrounding each core structure, effectively forming multiple superjunction structures. As discussed above with respect to FIG. 3I, the selective growth can be limited to desired surfaces by covering other surfaces with a dielectric material. Alternatively, the second semiconductor material can be grown on all surfaces of the device being fabricated, with the unwanted portions of the deposited second semiconductor material subsequently removed.

[0063] For example, as described above with respect to Figures 3J-3N, further process steps may follow to create additional functional areas within the created super-junction structure and / or metal contact areas.

[0064] The novel device architecture and fabrication method are described with respect to super-junction power semiconductor devices. However, the use of the described architecture and fabrication method is not limited to power semiconductor devices, but may also be employed in other conventional cell-based very high density semiconductor devices. Such devices may include sensor arrangements such as photovoltaic cells and image sensors, as well as other optical devices such as matrix displays.

[0065] It should be noted that the embodiments illustrated in Figures 1-4 above represent exemplary embodiments of the improved device structures and methods for their implementation only. They do not constitute an exhaustive list of all embodiments of the improved devices and methods. Actual devices and fabrication methods may differ from the described embodiments, for example, with respect to materials used, processing steps and parameters, dimensions, and circuit configurations. [Explanation of symbols]

[0066] Reference sign 1 board 1a, 1b (substrate) sublayers 2. Dielectric Layer 2a-2c (Dielectric Layer) Sublayers 3 Super-junction structure 4 Core Structure 4a Main part (of the core structure) 5. Shell structure 6 Plug structure 7 Channel Region 8-gate structure 9 Gate insulator 10 cells 11 Drain electrode 12 Source electrode 13 (1st) Opening 15 metal layer 16 Termination area 17 Gate Runner 20 Power Semiconductor Devices 21 First dielectric layer (growth seed mask layer) 22 Second dielectric layer (core structure mask layer) 23 Vertical Growth Mask 24 (Second) Opening 25 Capping Elements 26 Vertical plane 27 Third dielectric layer 28 Fourth dielectric layer 30 Manufacturing method d pitch distance

Claims

1. A super-junction power semiconductor device (20), comprising: A substrate (1), a plurality of core structures (4), each having a cylindrical shape extending in a direction perpendicular to a major surface of the substrate (1) and including a first semiconductor material of a first conductivity type; a plurality of annular shell structures (5), each of which surrounds one of the core structures (4) on its outside and contains a second semiconductor material of a second conductivity type; A super-junction power semiconductor device (20) comprising:

2. 2. The device (20) of claim 1, further comprising a dielectric layer (2) disposed on the main surface of the substrate (1), wherein the plurality of shell structures (5) surrounding the plurality of core structures (4) are embedded within the dielectric layer (2).

3. the dielectric layer (2) comprises at least a first sublayer (2a) and a second sublayer (2b); the first sublayer (2a) is disposed between the substrate (1) and the second sublayer (2b) and has a plurality of passages therebetween; the second sublayer (2b) comprises at least a lower portion of each of the plurality of shell structures (5); the device (20) further comprises a plurality of plug structures (6), each plug structure (6) comprising a third semiconductor material of the second conductivity type and positioned in the region of one of the passages so as to contact the main surface of the substrate (1) and a respective one of the shell structures (5); The device (20) of claim 2.

4. a plurality of channel regions (7) formed in each of the shell structures (5), each channel region (7) comprising a fourth semiconductor material of the first conductivity type, the channel regions (7) being disposed within a control layer of the device (20); at least one gate structure (8) disposed within the control layer, the at least one gate structure (8) being insulated from and surrounding at least a portion of each of the shell structures (5); The device (20) of any one of claims 1 to 3, further comprising:

5. 5. The device (20) according to claim 4, wherein the at least one gate structure (8) is buried in a dielectric layer (2), in particular between the second sublayer (2b) of claim 3 and a third sublayer (2c) of the dielectric layer (2).

6. The substrate (1) is one of silicon, Si, monocrystalline or polycrystalline silicon carbide, SiC, or gallium nitride, GaN, semiconductor substrates; The first semiconductor material is a p-type semiconductor material, particularly Si, or a p-type wide bandgap (WBG) semiconductor material, particularly SiC, GaN, or gallium oxide, Ga x O y , especially gallium trioxide (III), Ga ２ O ３ and / or The second semiconductor material is an n-type semiconductor material, particularly Si, an n-type WBG semiconductor material, particularly SiC, GaN, Ga x O y , especially Ga ２ O ３ , or n-type diamond, A device (20) according to any one of claims 1 to 5.

7. The core structure (4) and / or the shell structure (5) extend over a length of 1 to 100 μm, particularly 3 to 15 μm, in a direction perpendicular to the main surface of the substrate (1). The core structure (4) has a diameter of 25 nm to 5 μm, in particular 0.1 to 5 μm. the shell structure (5) has a thickness of 0.1 to 5 μm, and / or the plurality of core structures (4) are arranged in a regular pattern, in particular in an array structure, with a pitch distance (d) of less than 1 μm and / or in the range of 1.1 to 2.5 times the total diameter of one of the core structures (4) surrounded by one of the shell structures (5); A device (20) according to any one of claims 1 to 6.

8. a drain electrode (11) formed on the second main surface of the substrate (1); a source electrode (12) formed on the dielectric layer (1), in particular on the third sublayer (2c) of the dielectric layer (2) according to claim 5, interconnecting the upper ends of each of the core structures (5); and / or At least one gate structure (8), in particular a gate electrode electrically connected to said at least one gate structure (8) according to claim 4 or 5. The device (20) of any one of claims 1 to 7, further comprising at least one of:

9. 9. The device (20) according to any one of claims 1 to 8, wherein the plurality of core structures (4) and / or shell structures (5) are electrically connected in parallel to form a multi-cell field effect transistor, FET (field effect transistor), in particular a metal-insulator-semiconductor field effect transistor, MISFET (metal-insulator-semiconductor field-effect transistor), metal-oxide-semiconductor field effect transistor, MOSFET (metal-oxide-semiconductor field-effect transistor), insulated gate bipolar transistor, IGBT (insulated gate bipolar transistor), and / or a junction-gate field effect transistor, JFET (junction-gate field-effect transistor).

10. A method (30) for manufacturing a super-junction power semiconductor device (20), in particular a device (20) according to any one of claims 1 to 9, comprising: Providing a growth substrate (1) (S31); forming (S32) a plurality of vertical growth masks (23) on the growth substrate (1); Selectively growing (S33) a first semiconductor material within the plurality of vertical growth masks (23) to form a corresponding plurality of core structures (4) in a direction perpendicular to the major surface of the growth substrate (1); At least partially removing (S34) the plurality of vertical growth masks (23), thereby exposing the vertical surfaces (26) of the plurality of core structures (4); Selectively growing (S35) a second semiconductor material on the vertical surfaces (26) of the core structures (4) to form corresponding shell structures (5) surrounding each of the core structures (4); A method (30).

11. forming (S32) the plurality of vertical growth masks (23); forming a growth seed mask layer (21) having a plurality of first openings (13) corresponding to a pitch distance (d) between the plurality of core structures (4); forming a core structure mask layer (22) having a plurality of second openings (24), each of the second openings (24) being disposed in a region corresponding to a respective one of the first openings (13) and being wider than the respective one of the first openings (13); The method (30) of claim 10, comprising:

12. forming the plurality of core structures (4), selectively growing a third semiconductor material containing impurities of a first conductivity type, in particular n-type silicon carbide, SiC, directly on the growth substrate (1) within the vertical growth masks (23) to form a plurality of plug structures (6); Then, forming main portions (4a) of the plurality of core structures (4) by selectively growing the first semiconductor material containing impurities of a second conductivity type, in particular p-type SiC, within the plurality of vertical growth masks (23).

12. The method of claim 10 or 11, comprising:

13. forming said plurality of shell structures (5), Growth inhibitor materials, especially SiO ２ , SiN, or Al ２ O ３ covering the top surfaces of the plurality of core structures (4) with one of the following: removing upper portions of the plurality of vertical growth masks (23), in particular the core structure mask layer (22) according to claim 11, so that the remaining lower portions of the plurality of vertical growth masks (23), in particular the growth seed mask layer (21) according to claim 11, cover the growth substrate (1); Thereafter, forming said plurality of shell structures (5) by selectively growing in a radial direction said second semiconductor material containing impurities of said first conductivity type, in particular n-type SiC; The method (30) of any one of claims 10 to 12, comprising:

14. implanting a dopant species into a control layer of the device (20), in particular one of aluminum, Al, or boron, B, ions, to form a channel region (7) in each of the plurality of shell structures (5); electrically insulating the outer surface of each of said shell structures (5) at least in the area corresponding to said channel region (7); forming at least one gate structure (8) in the control layer, the gate structure (8) surrounding the insulating channel regions (7) of the plurality of shell structures (5); The method (30) of any one of claims 10 to 13, further comprising:

15. depositing a first conductive layer on the second major surface of the growth substrate (1) to form a common drain electrode (11) for the devices (20); depositing a second conductive layer on the planarized first dielectric layer (27) surrounding the lower portions of the plurality of shell structures (5) to provide a common gate structure (8) for the devices; and / or depositing a third conductive layer on top of the second dielectric layer (28), in particular on the dielectric layer (28) arranged on said top surface of the common gate structure (8), to form a common source electrode (12) for said devices (20); The method (30) of any one of claims 10 to 14, further comprising at least one of:

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