Phase change memory device with conductive cladding - Patent application

Abstract

A device structure for a phase change memory device is disclosed. The device structure includes a top electrode, a phase change material recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts sidewalls of the top electrode, sidewalls of the phase change material, and portions of the top and bottom surfaces of each of the two layers of resistive liner material. The device structure includes a bottom electrode and a heater contacting the lower layer of resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is below the top electrode.

Description

[Background technology]

[0001] The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to phase change devices having a conductive cladding connecting a phase change material to a top electrode.

[0002] Phase change materials include various chalcogenide glass materials and can be used in semiconductor device applications such as phase-change random access memory (PCRAM or PCM) and radio frequency (RF) switches. Phase change materials typically have at least two solid phases: a crystalline state and an amorphous state. A transition between these two phases can typically be achieved by changing the temperature of the phase change material above its transition temperature using electrical heating or light pulses.

[0003] In many phase-change materials, the amorphous state exhibits higher resistance than the crystalline state. In typical semiconductor switch applications, such as highly integrated radio frequency (RF) switches, when the phase-change material is in the low-resistivity crystalline state, the switch is in the "on" state and transmits a signal, such as an RF signal. Similarly, in typical semiconductor switch applications, when the phase-change material is in the high-resistivity amorphous state, the switch is in the "off" state and does not transmit a signal. In typical semiconductor applications, phase-change materials can be switched between multiple electrically detectable states of different resistance within nanosecond timescales with the input of a few picojoules of energy. Optical and electronic properties can differ significantly between the amorphous and crystalline phases of a phase-change material.

[0004] In typical memory applications, switching from a high-resistance or "reset" state, in which the phase-change material is partially or completely amorphous, occurs when a current pulse is applied that heats the amorphous material above its crystallization temperature long enough for the material to crystallize. Switching occurs when, at a given threshold voltage, a threshold switching effect causes the amorphous phase to rapidly and suddenly (within nanoseconds) decrease in resistance when a specific threshold electric field is exceeded. Switching from a low-resistance or "set" state, in which the phase-change material is crystalline, is achieved by a high current pulse with a very short falling edge. In typical PCM semiconductor applications, the current pulse heats the material by Joule heating, melting it and allowing very rapid cooling (melt quenching), resulting in the phase-change material solidifying in the amorphous state. Because the phase-change material in typical PCRAM devices is capable of reversible phase transitions, the status of a memory bit can be distinguished by determining the state of the phase-change material in the memory bit. Summary of the Invention

[0005] An embodiment of the present invention provides a device structure for a phase change memory device, including a top electrode, a phase change material recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewalls of the top electrode, the sidewalls of the phase change material, and portions of the top and bottom surfaces of each of the two layers of resistive liner material, and the sidewalls of the phase change material are undamaged by directional etching of the phase change material. The undamaged sidewalls of the phase change material provide lower electrical contact resistance with the conductive material carrying electrical signals to the top electrode than PCM devices formed using conventional methods that use directional etching of the phase change material. Furthermore, contact with undamaged material reduces contact resistance variation across multiple devices. Two layers of resistive material cover the top and bottom surfaces of the phase change material to reduce the effects of resistance drift that occurs in the amorphous state of the phase change material and protect the phase change material during device formation. An embodiment of the device structure includes a heater contacting the bottom electrode and the lower layer of resistive liner material. An embodiment of the present invention includes a heater element for a PCM device that is in a first bi-layer dielectric. An embodiment of the present invention includes a second bi-layer dielectric that underlies the top electrode.

[0006] Embodiments of the present invention provide a device structure for a phase change memory device that includes a heater overlying a portion of a bottom electrode. Embodiments of the present invention include a device structure having a first dielectric material around a bottom portion of the heater and a recessed second dielectric material around a top portion of the heater. Embodiments of the present invention provide a device structure including a first resistive liner overlying the second dielectric material and a recessed phase change material over a portion of the first resistive liner. The sidewalls of the phase change material are undamaged by the directional etching process used to form the features of the phase change memory device because a second etching process after the directional etching process recesses the sidewalls of the phase change material and removes outer portions of the sidewalls of the phase change material that were damaged during the directional etching process. Removal of the damaged sidewalls of the phase change material improves the electrical performance of the completed phase change memory device.

[0007] The second resistive liner is above the recessed phase change material. The first and second resistive liners protect the phase change material from semiconductor fabrication processes used to complete the phase change memory device. The first and second resistive liners extend beyond the sidewalls of the recessed phase change material. Additionally, the first and second resistive liners can mitigate the effects of resistance drift that occurs in the amorphous state of the phase change material in the completed phase change memory device.

[0008]

[0009] Embodiments of the present invention disclose a third dielectric material on the second resistive liner, the third dielectric material being recessed on the second resistive liner. The third dielectric material is composed of a material having the same etch selectivity as the second dielectric material.

[0010] Embodiments of the present invention provide a fourth dielectric material below the top electrode and above the third dielectric material. The device structure includes a conductive material contacting at least the sidewalls of the top electrode, the intact sidewalls of the phase change material, portions of the first, second, third, and fourth dielectric materials, and portions of the top and bottom surfaces of the first resistive liner and the second resistive liner.

[0011] Embodiments of the present invention provide a device structure for a phase change memory device having a thin layer of phase change material that provides lower electrical contact resistance between the sidewalls of the phase change material and the conductive material connecting to the top electrode than conventional phase change memory devices formed with a thin layer of phase change material.

[0009] An embodiment of the present invention provides a method for forming a device structure, the method including directional etching to form pillars comprised of an upper electrode overlying an upper bilayer dielectric, a phase change material between an upper resistive liner and a bottom resistive liner, and an upper dielectric layer of a bottom dielectric bilayer underlying the bottom resistive liner, wherein forming the pillars by directional etching damages sidewalls of the phase change material. The method includes etching the exposed, damaged sidewalls of the phase change material and conformally depositing a conductive material on the pillars, in recesses adjacent the sidewalls of the phase change material, and on a top surface of the bottom dielectric material in the bottom bilayer dielectric. The method includes removing the exposed horizontal portions of the conductive material. Etching the phase change material to remove the damaged sidewalls of the phase change material followed by conformal deposition of the conductive material provides lower contact resistance for improving performance of the completed PCM device. The etching process removes the exposed horizontal portions of the conductive material while leaving portions of the deposited conductive material adjacent the sidewalls of the recessed phase change material. The method includes recessing a lower layer of the top bi-layer dielectric on the top resistive liner and an upper layer of the bottom bi-layer dielectric below the bottom resistive liner, followed by conformally depositing another layer of conductive material over the device structure. The method includes removing a portion of the exposed horizontal surfaces of the conductive material deposited over the device structure. The remaining portion of the conductive material connects at least a portion of the top electrode to the conductive material between the two layers of resistive liner, creating a connection between the top electrode and the phase change material. [Brief explanation of the drawings]

[0010] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0011] [Figure 1] 2 illustrates a cross-sectional view of a semiconductor structure after forming a bottom electrode in a first dielectric material over a semiconductor substrate, according to one embodiment of the present invention.

[0012] [Figure 2] 2 illustrates a cross-sectional view of a semiconductor structure after successive deposition of layers of two different dielectric materials on the exposed surface of the bottom electrode and the first dielectric material, according to one embodiment of the present invention.

[0013] [Figure 3] 1 illustrates a cross-sectional view of a semiconductor structure after forming a heater on a bottom electrode in two layers of different dielectric materials, according to one embodiment of the present invention.

[0014] [Figure 4] 2 shows a cross-sectional view of a semiconductor structure after depositing a phase change material, two more layers of dielectric material, and a layer of top electrode material, according to one embodiment of the present invention.

[0015] [Figure 5] 1 illustrates a cross-sectional view of a semiconductor structure after patterning the top electrode material and etching a layer of the top electrode material, two layers of dielectric material over the phase change material, the phase change material, and a portion of the top dielectric material of the first layer of the first two dielectric materials, in accordance with one embodiment of the present invention.

[0016] [Figure 6] 3A illustrates a cross-sectional view of a semiconductor structure after recessing layers of dielectric material directly above and below the layer of phase change material, in accordance with one embodiment of the present invention.

[0017] [Figure 7] 2 illustrates a cross-sectional view of a semiconductor structure after conformal deposition of a layer of conductive material, according to one embodiment of the present invention.

[0018] [Figure 8] 2 illustrates a cross-sectional view of a semiconductor structure after performing an anisotropic etching process to remove exposed horizontal portions of conductive material, according to one embodiment of the present invention.

[0019] [Figure 9]7 illustrates a cross-sectional view of the semiconductor structure of FIG. 6 after conformally depositing a layer of liner material over the semiconductor structure and depositing a layer of conductive material over the liner material, in accordance with one embodiment of the present invention.

[0020] [Figure 10] 1 illustrates a cross-sectional view of a semiconductor structure after removing the liner material and exposed horizontal portions of the conductive material, according to one embodiment of the present invention.

[0021] [Figure 11] 1 illustrates a cross-sectional view of a semiconductor structure after forming a heater on the bottom electrode, according to one embodiment of the present invention.

[0022] [Figure 12] 4 shows a cross-sectional view of the semiconductor structure of FIG. 3 after depositing a layer of phase change material on the lower layer of resistive liner, depositing an upper layer of resistive liner on the phase change material, depositing two different layers of dielectric material forming an upper bilayer dielectric on the upper resistive liner, and depositing a layer of upper electrode material on the upper layer of the upper bilayer dielectric, in accordance with one embodiment of the present invention.

[0023] [Figure 13] FIG. 1 illustrates a cross-sectional view of a semiconductor structure after patterning a layer of top electrode material and removing exposed portions of the top dielectric material in the top electrode material, the top bi-layer dielectric material, the upper layer of resistive liner, the phase change material, the lower layer of resistive liner underlying the phase change material, and the bottom bi-layer dielectric underlying the resistive material, in accordance with one embodiment of the present invention.

[0024] [Figure 14] 3 illustrates a cross-sectional view of a semiconductor structure after recessing a layer of phase change material, according to one embodiment of the present invention.

[0025] [Figure 15] 1 illustrates a cross-sectional view of a semiconductor structure after conformally depositing a layer of conductive material over and around the semiconductor structure and performing an anisotropic etch to remove exposed horizontal portions of the conductive material, in accordance with one embodiment of the present invention.

[0026] [Figure 16] FIG. 1 illustrates a cross-sectional view of a semiconductor structure after recessing a layer of dielectric material over a top resistive liner and below a bottom resistive liner on a heater element, a portion of the first dielectric material, and a conductive liner, in accordance with one embodiment of the present invention.

[0027] [Figure 17] 2 illustrates a cross-sectional view of a semiconductor structure after conformal deposition of a layer of conductive material, according to one embodiment of the present invention.

[0028] [Figure 18] 1 illustrates a cross-sectional view of a semiconductor structure after etching exposed horizontal portions of conductive material, according to one embodiment of the present invention.

[0029] [Figure 19] 1 illustrates a cross-sectional view of a semiconductor structure after forming a pillar comprised of a portion of a top electrode material, two layers of two different dielectric materials, a second resistive liner, a phase change material, a first resistive liner, and a portion of the upper layer of dielectric material surrounding a heater, in accordance with one embodiment of the present invention.

[0030] [Figure 20] 1 illustrates a cross-sectional view of a semiconductor structure after recessing two resistive liners surrounding a phase change material, recessing the dielectric material directly above and below the two resistive liners, conformally depositing a layer of conductive material, and removing the exposed horizontal portions of the conductive material, in accordance with one embodiment of the present invention.

[0031] [Figure 21] 4 illustrates a cross-sectional view of the semiconductor structure of FIG. 3 after depositing a first layer of phase change material on the semiconductor structure, depositing a layer of resistive liner material on the first layer of phase change material, depositing a second layer of phase change material on the layer of resistive liner, depositing two layers of different dielectric materials forming an upper bilayer dielectric, and depositing an upper electrode material on the upper bilayer dielectric, in accordance with one embodiment of the present invention.

[0032] [Figure 22] 1 illustrates a cross-sectional view of a semiconductor structure after recessing a layer of dielectric material above a second layer of phase change material and below a first layer of phase change material, conformally depositing a layer of conductive material, and removing exposed horizontal portions of the conductive material, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] Embodiments of the present invention recognize that phase-change materials are increasingly being used in integrated circuits (ICs). Embodiments of the present invention recognize that directional etching processes, such as reactive ion etch (RIE), used to pattern phase-change memory (PCM) devices can damage the sidewalls of the phase-change material. Damaged sidewalls of the phase-change material increase the electrical contact resistance between the phase-change material and any conductive material that contacts the damaged sidewalls of the phase-change material. Increased contact resistance between the phase-change material and conductive materials, such as conductive metal cladding or resistive liners that carry read / write currents from the phase-change material to the top electrode of the PCM device, degrades PCM device performance. Embodiments of the present invention recognize that providing a damage-free surface of the sidewalls of the phase-change material that contacts a metal conductor will improve the electrical performance of the PCM device.

[0034] Embodiments of the present invention recognize that improving the speed of the phase transition in a phase change material will improve the functionality of semiconductor devices. Embodiments of the present invention recognize that there is an emerging trend to form PCM devices using thin layers of phase change material having thicknesses in the sub-10 nanometer range. Embodiments of the present invention recognize that PCM devices formed using thin layers of phase change material may have reduced reset currents.

[0035] Embodiments of the present invention recognize that in conventionally formed PCM devices using a thin layer of phase change material, only a small contact area of ​​the sidewalls of the thin layer of phase change material is exposed for contact with a metal contact or conductor that carries current from the phase change material to the top electrode. In PCM devices made using conventionally formed thin layers of phase change material, the contact area of ​​the sidewalls of the thin layer of phase change material with the metal conductor is particularly small. The small contact area between the phase change material and the conductor results in a significant amount of undesirable electrical contact resistance, especially when the sidewalls of the phase change material are formed using a directional etching process and the outer edges of the sidewalls of the phase change material are damaged. Embodiments of the present invention recognize that a PCM device providing undamaged sidewalls of the phase change material and a larger contact area for contacting the phase change material to the metal conductor would reduce electrical contact resistance and improve PCM device performance.

[0036] Embodiments of the present invention provide various structures for PCM devices and methods of forming PCM device structures, where the device structures use thinner layers of phase change material to reduce the capacitance of the phase change material, providing both a lower electrical resistance path for read / write currents and more efficient and easier phase transition conversion of the phase change material. Embodiments provide undamaged sidewalls of the phase change material and a larger direct contact area between the conductive material and a portion of each surface of the resistive liner above and below the phase change material. Embodiments of the present invention provide device structures having a conductive material contacting a portion of the top surface, bottom surface, and sidewalls of the phase change material, where the conductive material extends around and over a portion of the device structure to contact a portion of the sidewall of the top electrode. The larger contact area between the phase change material and the conductive material improves the electrical performance of the PCM device. Embodiments of the present invention eliminate damaged sidewalls of the phase change material and provide device structures with increased contact area of ​​the conductive material that carries current from the phase change material to a portion of the top electrode or from the resistive liner to the top electrode when the phase change material is in an amorphous state. The contact between the undamaged sidewalls of the PCM device and the conductive material, and the increased contact area between the phase change material and the conductive material, improves the electrical performance of the resulting PCM device.

[0037] Embodiments of the present invention provide lower contact resistance between the phase change material and the conductive metal overlying or surrounding the phase change material by creating a damage-free sidewall surface of the phase change material that provides a lower electrical contact resistance of the conductive material in contact with the phase change material than the sidewalls of conventionally formed PCM devices.

[0038] Embodiments of the present invention provide semiconductor structures in which resistive liners above and below the phase change material protect the phase change material during processing steps, such as etching processes, used to form the completed PCM device. Embodiments of the present invention also provide semiconductor structures that use one or two resistive liners to mitigate the effects of resistance drift that occurs in the amorphous phase of the phase change material. Embodiments of the present invention expose the top and bottom surfaces of the resistive liners that extend beyond the phase change material.

[0039] An embodiment of the present invention provides a layer of recessed dielectric material above the top resistive liner and a layer of recessed dielectric material below the bottom resistive liner, exposing portions of the top surface of the top resistive liner and the bottom surface of the bottom resistive liner to increase the contact area with the conductive material covering the upper portion of the PCM device. When the phase change material is in a high resistance state (i.e., amorphous state), current passes through the resistive liner, which has a lower electrical resistivity than the amorphous phase change material. An embodiment of the present invention includes a conductive material surrounding a layer of phase change material (e.g., resistive liners above and below a layer of phase change material) and covering the exposed portions of the top surface of the top resistive liner and the bottom surface of the bottom resistive liner. In this way, the top surface of the top resistive liner and the bottom surface of the bottom resistive liner are in direct contact with the metallic conductive material surrounding the resistive liner, the sidewalls of the phase change material, and portions of the sidewalls of the upper electrode.

[0040] Additionally, embodiments of the present invention provide a thin layer of phase change material in a PCM device. The use of a thin layer of phase change material allows a smaller volume of phase change material to be heated or cooled by a heater element to the transition temperature of the phase change material. A thinner layer of phase change material can be heated or cooled more quickly than a thicker layer to initiate a phase change of the phase change material from an amorphous state to a crystalline state (or vice versa).

[0041] Embodiments of the present invention provide a method for forming a device structure in which a phase change material is between two layers of resistive liner material. After directional etching of the phase change material to form pillars of material for a PCM device, the directional etching process damages the surface of the sidewalls of the phase change material, and a suitable wet or dry etching process is used to etch back the phase change material to remove the damaged surface of the sidewalls. A conductive material fills the recesses between the two layers of resistive liner and contacts the undamaged sidewalls of the phase change material, thereby improving the electrical contact resistance of the phase change material with the conductive material.

[0042] Embodiments of the present invention disclose recessing the dielectric material directly above and below the phase change material and / or the resistive liner on the top and bottom surfaces of the phase change material. By recessing the dielectric material directly above the phase change material or above the resistive liner, a larger surface area of ​​the phase change material and / or the resistive liner above the phase change material is exposed for contact with the conductive metal that connects to the top electrode. The metallic conductive material covering the sidewalls of the phase change material and the top electrode delivers read / write current to the top electrode of the PCM device.

[0043] The following description, which refers to the accompanying drawings, is provided to aid in a comprehensive understanding of exemplary embodiments of the present invention, as defined by the claims and their equivalents. While various specific details are included to facilitate understanding, these are considered to be merely exemplary. Accordingly, those skilled in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope of the present invention. Some of the process steps shown can be combined into an integrated process step. Additionally, for clarity and conciseness, descriptions of well-known functions and structures may be omitted.

[0044] The terms and phrases used in the following description and claims are not limited to their bibliographical meanings, but are merely used to enable a clear and consistent understanding of the present invention. Therefore, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only, and is not intended to limit the present invention as defined by the appended claims and their equivalents.

[0045] The singular forms "a," "an," and "the" should be understood to include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a "component surface" includes a reference to the presence of one or more of such surfaces unless the context clearly dictates otherwise.

[0046] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," and "bottom," and their derivatives, refer to the disclosed structures and methods as oriented in the drawing figures. Terms such as "above," "overlying," "above," "on top of," "located on," or "located on top of" mean that a first element, such as a first structure, is present in a second element, such as a second structure, where an intervening element, such as an interfacial structure, may be present between the first and second elements. The term "direct contact" or "contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0047] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations that are known in the art may be combined for presentation and illustration purposes, and in some cases may not be described in detail. In other cases, some process steps or operations that are known in the art may not be described at all. It should be understood that the following description will focus largely on the distinctive features or elements of various embodiments of the present invention.

[0048] As used herein, deposition processes include, but may not be limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVOD), atomic layer deposition (ALD), ionized plasma vapor deposition (iPVD), plasma vapor deposition (PVD), gas cluster ion beam (GCIB) deposition, and electroplating, but may not be limited to these known semiconductor deposition processes.

[0049] As used herein, removal or etching may or may not include patterning using one of lithography, photolithography, extreme ultraviolet (EUV) lithography processes, or other known semiconductor patterning processes followed by one or more etching processes. Various materials are referred to herein as being removed or "etched," where etching generally refers to one or more processes implementing the removal of one or more materials. In some cases, removal of material in certain areas occurs while sparing other protected areas of material that were masked during the lithography process. Some examples of etching processes include, but are not limited to, dry etching processes using the following processes, such as reactive ion etching (RIE) or ion beam etching (IBE), wet chemical etching processes, or combinations of these etching processes. Dry etching may be performed using a plasma. The plasma system may be operated in several ways by adjusting the parameters of the plasma. Ion milling, sputter etching, or reactive ion etching (RIE) bombard the wafer with fast ions of a noble gas that approach the wafer from more or less one direction, and are therefore anisotropic or directional etching processes. Chemical mechanical planarization (CMP) is another known process of removing material using a combination of abrasives (polishing with an abrasive substance) and chemical processes to remove material from the top surface of a substrate.

[0050] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing integrated circuits on semiconductor chips. The embodiments can be practiced in conjunction with integrated circuit fabrication techniques for semiconductor chips and devices currently used in the art, and only some of the commonly practiced process steps are included as necessary for understanding the described embodiments. The figures represent cross-sectional portions of semiconductor chips or substrates, such as semiconductor wafers, during fabrication, and are not drawn to scale; instead, they are drawn to illustrate features of the described embodiments. The embodiments may use the terms device structure and semiconductor structure interchangeably. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to variously use the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0051] References herein to "one embodiment," "another embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is understood that it is within the knowledge of one skilled in the art to provide such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0052] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.

[0053] 1 illustrates a cross-sectional view of a device structure 100 after forming a bottom electrode 4 on a substrate 2, in accordance with one embodiment of the present invention. As shown, FIG. 1 includes a substrate 2, a dielectric layer 3, and a bottom electrode 4.

[0054] Substrate 2 can be composed of any semiconductor substrate material. In various embodiments, substrate 2 is silicon. In other examples, substrate 2 can be composed of Group IV semiconductor material, Group III-V semiconductor material, Group II-VI semiconductor material, silicon on insulator (SOI), or other known semiconductor materials used in semiconductor chips. In various embodiments, substrate 2 includes one or more semiconductor devices. For example, substrate 2 can include various front-end-of-line devices such as field-effect transistors, isolation structures, contacts, or any other semiconductor device elements formed on a semiconductor wafer or semiconductor substrate. In some cases, substrate 2 need not necessarily be a semiconductor substrate, as its primary function is to provide mechanical support and / or a thermal path for cooling. For example, substrate 2 can be made of materials such as glass, flexible materials used for flexible electronics, etc.

[0055] Dielectric layer 3 resides on substrate 2. Dielectric layer 3 can be a layer of dielectric material deposited by known deposition processes. In various embodiments, dielectric layer 3 is comprised of silicon nitride (SiN). In other examples, dielectric layer 3 can be comprised of one or more dielectric materials, including, but not limited to, silicon dioxide (SiO), silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), carbon-doped silicon oxide (SiO:C), fluorine-doped silicon oxide (SiO:F), silicon carbonitride (SiCN), boron nitride (BN), silicon oxygen carbonitride (SiOCN), or any other suitable dielectric material used in semiconductor device formation.

[0056] The bottom electrode 4 may be formed of any conductive material used for semiconductor chip electrodes. In one embodiment, one or more semiconductor devices may be present below or adjacent to the bottom electrode 4. The bottom electrode 4 may be formed, for example, using known patterning, etching, deposition, and CMP techniques to create the bottom electrode 4. The bottom electrode 4 may have a circular shape, a rectangular shape, or any other shape. The bottom electrode 4 in the dielectric layer 3 may be composed of any electrode material, such as, but not limited to, copper (Cu), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tungsten carbide (WC), aluminum (Al), or multilayer stacks thereof.

[0057] Figure 2 shows a cross-sectional view of device structure 200 after depositing a layer of dielectric material 22 on the exposed surfaces of bottom electrode 4 and dielectric layer 3, and a layer of dielectric material 23 on dielectric material 22, in accordance with one embodiment of the present invention. As shown, Figure 2 includes the elements of Figure 1 and dielectric material 22 and dielectric material 23. Dielectric material 22 and dielectric material 23 are deposited by one or more of known dielectric material deposition processes (e.g., CVD, PVD, ALD, etc.).

[0058] Dielectric material 22 is deposited on the top surface of bottom electrode 4, and dielectric layer 3 can be any dielectric material. In various embodiments, dielectric material 22 is comprised of a low-k dielectric material. For example, dielectric material 22 can be SiOCN, SiBCN, or another low-k dielectric material, but is not limited to these low-k dielectric materials, and can be a dielectric material having a dielectric constant greater than 3.9. Dielectric material 22 and dielectric material 23 are materials that are compatible with processes for forming heaters in phase change materials (PCMs).

[0059] Dielectric material 23 resides on dielectric material 22 and is comprised of a different dielectric material. For example, dielectric material 23 may be comprised of a nitride-based dielectric material such as SiN, or an oxide-based dielectric material such as SiO2, but is not limited to these dielectric materials. In various embodiments, the combination of dielectric material 22 and dielectric material 23 forms a dual-layer dielectric or dual-layer dielectric structure above bottom electrode 4 and dielectric layer 3. In one embodiment, only one layer of dielectric material is deposited over dielectric layer 3 and bottom electrode 4. For example, only dielectric material 22 is deposited.

[0060] In various embodiments, dielectric material 23 and dielectric material 22 are selected based on their etchant selectivity and etch rate. For example, an etchant for dielectric material 23 may not etch dielectric material 22. In other words, dielectric material 22 and dielectric material 23 are selected such that dielectric material 23 can be etched without removing dielectric material 22. Another consideration for selecting dielectric material 23 is that it acts as a good stop layer when polishing the heater material, as described further below.

[0061] 3 illustrates a cross-sectional view of device structure 300 after forming heater 34 on bottom electrode 4 in portions of dielectric material 22 and dielectric material 23, in accordance with one embodiment of the present invention. As shown, FIG. 3 includes the elements of FIG. 2 and heater 34. Using known processes for forming heaters for PCM devices (e.g., lithography, heater hole etch, heater material deposition, and CMP), heater 34 is formed on a portion of bottom electrode 4 in a portion of the dual-layer dielectric formed of dielectric material 23 and dielectric material 22, as shown in FIG.

[0062] A conductive material is deposited into the vias to form the heater 34 using known deposition processes, such as CVD, PVD, ALD, MOCVOD, PECVD, etc. Conductive materials for the heater 34 include, but are not limited to, titanium nitride (TiN), tungsten (W), tantalum nitride (TaN), TiAl, or other similar resistive metallic materials. The heater 34 may include multiple different conductive materials disposed in multiple layers of material (e.g., TaN / TiN / TaN). After filling the vias with the conductive material, CMP may be used to planarize the top of the device structure 300 and remove excess heater 34 material from the top surface of the dielectric material 23. CMP may be used to planarize the surface of the device structure 300 and remove excess heater 34 material on the top surface of the dielectric material 23. Alternatively, the heater 34 may be formed by depositing a blanket layer of heater 34 material on the surfaces of the dielectric layer 3 and bottom electrode 4 before depositing layers 22 and 23. Lithography and RIE are used to pattern and etch the layer of material for heater 34 to form pillars of heater material. Next, the process includes depositing a layer of dielectric material 22 over the exposed surfaces. The top surface is planarized by CMP, and then dielectric material 22 may be recessed or etched back to expose the top of heater 34. In this example, dielectric material 23 may not be deposited over dielectric material 22.

[0063] FIG. 4 illustrates a cross-sectional view of a device structure 400 after depositing a phase change material 44, a dielectric material 43, a dielectric material 45, and a top electrode 46 according to one embodiment of the present invention. As shown, FIG. 4 includes the elements of FIG. 3 plus a phase change material 44, a dielectric material 43, a dielectric material 45, and a top electrode 46. In various embodiments, the dielectric materials 43 and 45 are composed of the same dielectric material as the dielectric materials 23 and 22, respectively. However, the dielectric materials 43 and 45 are not limited to the same dielectric material as the dielectric materials 23 and 22, and may be composed of other dielectric materials. The combination of the dielectric materials 43 and 45 may also be known as a dual-layer dielectric or dual-layer dielectric structure. In some examples, the dielectric materials 22 and 45 may be composed of different dielectric materials. In these cases, the thicknesses of the dielectric materials 22 and 45 may be different to obtain similar amounts of recess (e.g., so that the horizontal lengths of the dielectric materials 22 and 45 removed after etching are the same). Similar to dielectric material 23 and dielectric material 22, in various embodiments, dielectric material 43 and dielectric material 45 are selected based on their etch selectivity and etch rate. For example, an etchant for dielectric material 43 may not etch dielectric material 45. In one embodiment, only one layer of dielectric material is deposited on phase change material 44. For example, only dielectric material 43 is deposited.

[0064] In various embodiments, a layer of phase change material 44 is deposited on the exposed top surface of dielectric material 43 and heater 34. For example, phase change material 44 may be comprised of germanium-antimony-tellurium (GeSbTe, also known as GST) or a germanium-telluride material (GeTe). Alternatively, other suitable materials for phase change material 44 may include a Si—Sb—Te (silicon-antimony-tellurium) alloy, a Ga—Sb—Te (gallium-antimony-tellurium) alloy, a Ge—Bi—Te (germanium-bismuth-tellurium) alloy, an In—Te (indium tellurium) alloy, an As—Sb—Te (arsenic-antimony-tellurium) alloy, an Ag—In—Sb—Te (silver-indium-antimony-tellurium) alloy, a Ge—In—Sb—Te alloy, a Ge—Sb alloy, an Sb—Te alloy, a Si—Sb alloy, a Ge—Te alloy, combinations thereof, or another phase change material suitable for use in a PCM device. Phase change material 44 may be undoped or doped (e.g., doped with one or more of O, N, Si, C, SiC, or Ti). A typical thickness of the phase change material 44 in the device structure 400 may be, but is not limited to, 5-30 nm. Prior to depositing the phase change material 44 on the heater 34, cleaning of the top surface of the heater 34 may be performed (typically in-situ) by sputtering the surface with ions (e.g., using Ar sputtering).

[0065] 4, a layer of electrode material for the top electrode 46 is deposited on the dielectric material 45. The top electrode 46 can be any electrode material (e.g., Cu, TiN, W, WN, WC, Au, etc. for single layer or multilayer electrodes) deposited using known electrode deposition processes (e.g., CVD, PVD, etc.). In various embodiments, the top electrode 46 is composed of the same material as the bottom electrode 4, although in other embodiments, the top electrode 46 and the bottom electrode 4 can be different electrode materials.

[0066] FIG. 5 illustrates a cross-sectional view of device structure 500 after patterning top electrode 46 and etching exposed portions of top electrode 46, dielectric material 45, dielectric material 43, phase change material 44, and dielectric material 23, in accordance with one embodiment of the present invention. As shown, FIG. 5 includes the elements of FIG. 4 but does not include portions of the layer of material between and including top electrode 46 and dielectric material 23. After patterning the top surface of top electrode 46, an anisotropic etching process using, for example, RIE, removes the exposed portions of the layer of material below top electrode 46, stopping on the top surface of dielectric material 22, to form pillars above dielectric material 22. As shown in FIG. 5, the pillars formed by the directional etching process include top electrode 46, dielectric material 45, dielectric material 43, remaining portions of phase change material 44, and the tops of heaters 34 that reside in remaining portions of dielectric material 23.

[0067] As previously discussed, using a directional etching process such as RIE damages the sidewalls of the phase change material 44. The wavy vertical lines along the vertical edges of the phase change material 44 indicate damage to the sidewalls of the phase change material 44 caused by etching. The damaged surface of the sidewalls of the phase change material 44 can result in greater or higher electrical contact resistance between the metal spacers or metal cladding subsequently deposited to conduct current from the sidewalls of the phase change material 44 to the top electrode 46, negatively impacting the operation of the completed PCM device. While damage to the sidewalls of the phase change material 44 can be an increase in surface roughness (as indicated by the wavy vertical lines), it is important to note that in many cases the damage consists of a change in the composition of the phase change material. For example, depending on the RIE chemistry, a Ge2Sb2Te5 material may have a Ge:Sb:Te elemental ratio different from 2:2:5 at the surface of the sidewalls of the phase change material after etching with RIE.

[0068] Figure 6 shows a cross-sectional view of device structure 600 after recessing layers of dielectric material 23 and dielectric material 43, in accordance with one embodiment of the present invention. As shown, Figure 6 includes elements of Figure 5, except for outer portions of dielectric material 23 and dielectric material 43. In Figure 6, the removed portions of dielectric material 23 and dielectric material 43 are directly below and above phase change material 44, respectively.

[0069] For example, to create small recesses (e.g., in the range of 5-20 nm) in the outer edges of each of dielectric material 23 and dielectric material 43, a dry etching process such as RIE at zero bias can be a quasi-isotropic etch or a lateral etch to remove a small portion of dielectric material 23 below phase change material 44 and a small portion of dielectric material 43 above phase change material 44. If dielectric material 23 and dielectric material 43 are composed of the same material and have essentially the same thickness, the removed portions of dielectric material 23 and dielectric material 43 will be the same or very similar (i.e., by removing the outer edges of dielectric materials 23 and 43, the recesses will be essentially the same, and the etchback of each material will extend approximately the same or the same lateral distance). Recessing dielectric material 23 and dielectric material 43 can use various mixtures of one or more of various etch chemistries, such as CF4, CHF3, and NF3, with Ar, O2, or N2, for example. However, as previously discussed above using GST as an example of phase change material 44, compositional variations on the surface of phase change material 44 can occur, resulting in slightly different properties, such as material transition temperatures or melting points, in the surface portions of phase change material 44 adjacent to the removed portions of dielectric material 23 and dielectric material 43. In another example, a wet or dry etching process can be used to recess portions of dielectric material 23 and dielectric material 43, if they are composed of the same dielectric material. For example, a wet etching process using ultra-diluted hydrofluoric acid (HF) as an etchant can be used to remove outer portions or sidewalls of the exposed sides of dielectric material 23 and dielectric material 43 using H3PO4 as an etchant, or heated phosphoric acid as an etchant. In some cases, a small portion of the exposed surface of phase change material 44 may be affected by the wet etching process, and the surface of the remaining portion of phase change material 44 that extends beyond the sidewalls or vertical edges of dielectric material 23 and dielectric material 43 may be somewhat rounded, have a rougher surface (not shown in FIG. 6), or have a slightly different composition.

[0070] If the surface of phase change material 44 is slightly or somewhat damaged by the etching process used to recess dielectric material 23 and dielectric material 43, higher electrical contact resistance may occur at the affected surface of phase change material 44; however, the increased electrical contact resistance may be offset by a larger contact area for phase change material 44, as shown in FIG. 6 . In some cases, little or no damage to phase change material 44 may occur after etching dielectric material 23 and dielectric material 43. In other cases, minimal or no damage to phase change material 44 may occur during the sidewall etching or recessing of dielectric material 23 and dielectric material 43. As shown in FIG. 6 , after etching dielectric material 23 and dielectric material 43, a larger surface area of ​​phase change material 44 is exposed for later contact with a conductive material that may connect to top electrode 46. As shown in FIG. 6, after the selective etching of dielectric material 23 and dielectric material 43 exposes a portion of the top surface and a portion of the bottom surface of phase change material 44, the selective etching further exposes the sidewalls of phase change material 44.

[0071] Overall, providing a larger exposed surface of phase change material 44 may improve the electrical performance of the completed PCM device, even if the exposed surface is slightly damaged or has a slightly altered surface composition (e.g., any small surface variations in phase change material 44 may be offset by the larger contact area of ​​phase change material 44 with a metal spacer or conductive metal cladding that connects phase change material 44 to a top electrode, formed in a later process step). The larger contact area with phase change material 44 in Figure 6 is particularly advantageous in conventional PCM device structures having a thin layer of PCM material, where the contact area with the top electrode 46 and the conductor that carries current through the phase change material occurs only on the sidewalls of the thin layer of phase change material (e.g., portions of the top and bottom surfaces of the phase change material are not exposed in conventional PCM devices).

[0072] 7 illustrates a cross-sectional view of device structure 700 after conformally depositing a layer of conductive material 77, according to one embodiment of the present invention. As shown, FIG. 7 includes the elements of FIG. 6 and conductive material 77. Conductive material 77 is conformally deposited over the top of the device structure, filling recesses adjacent to the sides of dielectric material 23 and dielectric material 43. As shown in device structure 700, the exposed portions of phase change material 44 in contact with conductive material 77 include the sidewalls, a portion of the top surface of phase change material 44, and a portion of the bottom surface of phase change material 44.

[0073] Conductive material 77 may be deposited over the exposed top surfaces of top electrode 46 and dielectric material 43 and along the vertical sidewalls of dielectric material 23, phase change material 44, dielectric material 43, and dielectric material 45 using a conformal deposition process, such as ALD or CVD. Conductive material 77 may be composed of TiN or any other conductive material or alloy used in PCM devices. Conductive material 77 may form a conductive cladding strap that electrically connects phase change material 44 to top electrode 46 in the completed PCM device. Conformal deposition of conductive material 77 into the recess or notch formed by the selective isotropic etching process in FIG. 6 fills the recess with conductive material 77 and pinches off the recess.

[0074] After deposition of conductive material 77, the exposed portions of phase change material 44 in contact with conductive material 77 include the vertical sides or sidewalls of phase change material 44, a portion of the top surface of phase change material 44, and a portion of the bottom surface of phase change material 44, as shown in device structure 700.

[0075] The conductive material 77 surrounding a portion of the top and bottom surfaces of the exposed portion of phase change material 44 provides a larger contact area between phase change material 44 and conductive material 77 for electrical current or signals to flow than in conventional PCM devices. The larger contact area of ​​phase change material 44 with the metal cladding formed by conductive material 77 can be particularly advantageous in PCM devices formed with a thin layer of phase change material 77. As previously discussed, conventional PCM devices formed with a thin horizontal layer of phase change material only provide electrical contact with the conductive material connecting to the top electrode at the sidewalls of the thin layer of phase change material (e.g., only a small contact area is provided by the sidewalls of the thin layer of phase change material in conventional PCM devices, and the sidewalls are also damaged by the directional etching process). Device structure 700 increases the contact area between phase change material 44 and conductive material 77 connecting to the top electrode 46 compared to conventional PCM devices formed with a thin horizontal layer of phase change material 44.

[0076] 8 illustrates a cross-sectional view of device structure 800 after performing an anisotropic etching process to remove exposed horizontal portions of conductive material 77, in accordance with one embodiment of the present invention. As shown, FIG. 8 includes conductive material 77, top electrode 46 below conductive material 77, dielectric material 45, dielectric material 43 above phase change material 44, dielectric material 23, heater 34 in contact with phase change material 44 and bottom electrode 4, dielectric material 22, dielectric layer 3, and substrate 2, which may include various semiconductor devices. The horizontal portions of conductive material 77 may be removed during the etching process. For example, RIE may remove the horizontal portions of conductive material 77, exposing the top surfaces of top electrode 46 and dielectric material 22.

[0077] As shown, remaining portions of conductive material 77 after etching remain abutting vertical edges of dielectric material 23, phase change material 44, dielectric material 43, dielectric material 45, and portions of top electrode 46. Conductive material 77 extends into the notch or recess formed in FIG.

[0078] 8 , conductive material 77 surrounds the exposed surfaces (i.e., top, bottom, and vertical edges) of the thin layer of phase change material 44. Device structure 800 provides a larger contact area between phase change material 44 and conductive material 77 than conventional PCM devices, particularly conventional PCM devices formed with a thin layer of phase change material where contact to the thin layer of phase change material occurs only at the vertical edges of the thin layer of phase change material. In device structure 800, the larger contact area between top electrode 46, current-carrying conductive material 77, and the thin layer of phase change material 44 provides improved electrical performance of the completed PCM device, even if some of the surface of phase change material 44 is slightly damaged during the etching of dielectric material 23 and dielectric material 43.

[0079] Device structure 800, having undercuts or recesses in dielectric material 23 and dielectric material 43 directly below and above the exposed portions of phase change material 44 that extend beyond the sidewalls of the remaining portions of dielectric material 23 and dielectric material 43, respectively, increases the contact area between conductive material 77 and phase change material 44. While the increased contact area of ​​phase change material 44 may be particularly advantageous in PCM devices formed with thin layers of phase change material 44, the increased contact area may also be beneficial in other PCM devices having thicker layers of phase change material 44. Increasing the contact area between phase change material 44 and conductive material 77 still reduces the contact resistance between phase change material 44 and conductive material 77, even if the surface of phase change material 44 is slightly damaged by the etching process that recesses dielectric material 23 and dielectric material 43. For example, the size or amount of contact area of ​​conductive material 77 with phase change material 44 may be increased as needed in some cases to compensate for any surface changes that occur in phase change material 44 as a result of recessing dielectric material 23 and dielectric material 43. Device structure 800 providing a larger contact area between phase change material 44 and conductive material 77 may improve the electrical performance of the completed PCM device.

[0080] Figure 9 shows a cross-sectional view of device structure 900 after conformally depositing a layer of liner 91 over device structure 600 shown in Figure 6 and depositing liner 91 and conductive material 92 over liner 91, in accordance with one embodiment of the present invention. As shown, Figure 9 includes elements of Figure 7, but with conductive material 92 replacing conductive material 77 and liner 91 added below conductive material 92.

[0081] Liner 91 may be composed of any known liner material used in PCM devices. For example, liner 91 may be composed of TiN or TaN, but is not limited to these materials. Liner 91 is a relatively thin layer of liner material deposited over the exposed portions of device structure 600 shown in FIG. 6. Liner 91 and conductive material 92 may be conformally deposited, for example, by ALD or CVD.

[0082] Conductive material 92 may be comprised of one or more of the same conductive materials as conductive material 77. In various embodiments, conductive material 92 is comprised of, but is not limited to, tungsten. As shown in FIG. 9 , conductive material 92, like conductive material 77, fills the depressions or recesses between liner 91 on phase change material 44 and liner 91 on dielectric material 43 and dielectric material 23.

[0083] FIG. 10 illustrates a cross-sectional view of device structure 1000 after removing liner 91 and exposed horizontal portions of conductive material 92, according to one embodiment of the present invention. As shown, FIG. 10 includes elements of FIG. 8 , but includes liner 91, and conductive material 77 has been replaced with conductive material 92. In some examples, conductive material 92 is one of the materials used for conductive material 77. As discussed in detail above with respect to FIG. 8 , conductive material 92, similar to conductive material 77, surrounds exposed portions of phase change material 44. Conductive material 92 covers the sidewalls and exposed portions of the top and bottom surfaces of phase change material 44, increasing the contact area between phase change material 44 and conductive material 92.

[0084] Figure 11 shows a cross-sectional view of device structure 1100 after forming heater 34 on bottom electrode 4, according to one embodiment of the present invention. As shown, Figure 11 includes elements of Figure 3. Device structure 1100 and device structure 300 are essentially the same and may be formed from essentially the same materials and processes as described with respect to device structure 300.

[0085] 12 shows a cross-sectional view of device structure 1200 after depositing a lower layer of resistive liner 122 (bottom resistive liner), a layer of phase change material 104 on the lower layer of resistive liner 122, depositing a second layer of resistive liner 122 (top resistive liner) on phase change material 104, depositing dielectric material 103 on the second layer of resistive liner 122, depositing dielectric material 105 on dielectric material 103, and depositing a layer of top electrode 106 on top of dielectric material 105, on device structure 300 shown in FIG. 3 , in accordance with one embodiment of the present invention. As shown, FIG. 12 includes the elements of FIG. 11 as well as two layers of resistive liner 122 surrounding phase change material 104, a second bilayer dielectric composed of dielectric material 103 and dielectric material 105, and top electrode 106. The materials of phase change material 104, dielectric material 103, dielectric material 105, and top electrode 106 are essentially the same as phase change material 44, dielectric material 43, dielectric material 45, and top electrode 46, respectively, may be deposited by the same or similar known deposition processes (e.g., CVD, PVD, ALD, etc.), and may have the same or similar thicknesses and material types. Similar to the criteria for selecting dielectric material 23 and dielectric material 22, dielectric material 103 and dielectric material 105 may be selected based on their etch selectivities. For example, an etchant for dielectric material 23 may not etch dielectric material 105.

[0086] The resistive liner 122 may be deposited using a conformal deposition process, such as, but not limited to, ALD or CVD. For example, the resistive liner 122 may be TaN or a hydrogenated carbon-based material, but is not limited to these resistive liner materials. A typical thickness of the resistive liner 122 may be 2-6 nm, but is not limited to these thicknesses. The resistive liner 122 may be composed of any conductive material that does not react with the deposited phase change material in later process steps or during device operation. More specifically, the material for the resistive liner 122 does not react with the phase change material 104 at the melting temperature of the phase change material 104 (e.g., above 650 degrees Celsius for GST).

[0087] Following a RESET pulse, an amorphous region of phase change material 104 may form above heater 34. During read, current from heater 34 flows through resistive liner 122, bypassing the amorphous region of phase change material 104. This is because the material of resistive liner 122 is selected to have a lower electrical resistance than the amorphous phase of phase change material 104. Current can return to crystalline phase change material 104, which remains unchanged by RESET, at the edge of the amorphous region. This return occurs because the material of resistive liner 122 is selected to have a higher resistance (at least ten times higher) than the crystalline phase of phase change material 104.

[0088] The electrical resistivity of the phase change material 104 in the crystalline state (e.g., following a SET pulse) is significantly lower than the electrical resistivity of the resistive liner 122; therefore, in this case, current will flow from the heater 34 through the phase change material 104 in its crystalline phase to the top electrode 106 after the conductive cladding (i.e., conductive material 177 and contact 150) is deposited in a later process step as shown in FIG. 17 . The electrical resistance of the resistive liner 122 can also be tuned by varying the composition of the resistive liner material. For example, if the resistive liner 122 is composed of tantalum and nitrogen (TaN), the electrical resistivity of the resistive liner material can be increased by increasing the amount of nitrogen in the resistive liner material.

[0089] 13 illustrates a cross-sectional view of device structure 1300 after patterning top electrode 106 and removing top electrode 106, dielectric material 105, dielectric material 103, portions of both layers of resistive liner 122, phase change material 104, and exposed portions of dielectric material 23, in accordance with one embodiment of the present invention. As shown, FIG. 13 includes elements of FIG. 12, with the exception of top electrode 106, dielectric material 105, dielectric material 103, resistive liner 122, phase change material 104, and portions of dielectric material 23.

[0090] After performing a directional etch using, for example, RIE, the remaining portions of the stack materials in FIG. 13 form pillars above dielectric material 22. The pillars may be comprised of top electrode 106, dielectric materials 105 and 103, two layers of resistive liner 122 surrounding the layer of phase change material 104, and the remaining portion of dielectric material 23. In various embodiments, the pillars have a circular or elliptical shape. In other embodiments, the pillars are rectangular-shaped pillars or columns. However, in other examples, the pillars may be any shape or combination of shapes (e.g., irregular shapes, or triangles combined with circles, etc.). The lower layer of the pillars is comprised of dielectric material 23, which includes the top of heater 34. As previously discussed, after etching phase change material 104 (e.g., by RIE), the sidewalls or outer exposed vertical edges of phase change material 104 may be damaged by the RIE process. 5, the wavy vertical lines indicate damage that can occur to the sidewalls of the phase change material 104 during the directional etching process. In various embodiments, the phase change material 104 in the pillars has a disk or circular shape after RIE.

[0091] FIG. 14 illustrates a cross-sectional view of a device structure 1400 after recessing the phase change material 104, according to one embodiment of the present invention. As shown, FIG. 14 includes elements of FIG. 13, with the exposed, damaged sidewalls of the phase change material 104 removed. Undercutting the phase change material 104 removes the damaged sidewall portions of the phase change material 104 and recesses the remaining portions of the phase change material 104 between the two layers of resistive liner 122. For example, using one or more of a dry etching process, a wet etching process, or a digital etching process, the digital etching process uses a self-limiting oxidizer followed by an etchant that removes only the oxidized layer. Typically, the oxidizer is HO and the etchant is diluted HF. This process is repeated multiple times until the desired amount of phase change material 104 is removed and the undamaged sidewall surfaces of the phase change material 104 are exposed. Recessing phase change material 104 also exposes a portion of the bottom surface of top resistive liner 122 and a portion of the top surface of bottom resistive liner 122 .

[0092] In another example, phase change material 104 can be recessed using Cl-based chemistries in a dry etching process, minimizing etching of surrounding dielectric material 23 and dielectric material 103. The process can be highly selective for etching phase change material 104 relative to dielectric material 23 and dielectric material 103.

[0093] The damaged sidewall and the portion of phase change material 104 immediately adjacent to the sidewall may also be removed using a selective dry or wet etching process, such as, for example, zero-bias RIE (which provides an anisotropic etch). The undercut or lateral length of the removed phase change material 104 may vary and may range from 5 nm to 50 nm, but is not limited to these distances.

[0094] 15 illustrates a cross-sectional view of a device structure 1500 after conformally depositing a conductive material over and around the device structure to form side contacts 150 and removing exposed horizontal portions of the conductive material to form side contacts 150, in accordance with one embodiment of the present invention. As shown, FIG. 15 includes elements of FIG. 14, with side contacts 150 formed between two layers of resistive liner 122. Side contacts 150 directly abut undamaged sidewalls of phase change material 104.

[0095] A layer of conductive material for side contact 150 is conformally deposited, for example, by ALD or another suitable conformal deposition process capable of pinching off or filling the recessed region between two layers of resistive liner 122. Side contact 150 may be composed of, for example, TiN, but is not limited to this conductive material. After conformal deposition, exposed horizontal portions of side contact 150 that are not between the two layers of resistive liner 122 are removed (e.g., by RIE). After deposition and etching of side contact 150, a portion of the conductive material for side contact 150 directly abuts and surrounds the undamaged sidewall of phase change material 104. In this way, after RIE to form the pillars discussed with respect to FIG. 13 , the electrical contact resistance between side contact 150 and the undamaged sidewall of phase change material 104 is lower than the electrical contact resistance of the same conductive material with the same contact area and damaged sidewall of phase change material 104.

[0096] FIG. 16 illustrates a cross-sectional view of a device structure 1600 after recessing a portion of the dielectric material 103 overlying the upper layer of the resistive liner 122 over the phase change material 104 and recessing the dielectric material 23 underlying the lower layer of the resistive liner 122, in accordance with one embodiment of the present invention. As shown, FIG. 16 includes elements of FIG. 15 , with the outer exposed sidewall portions of the dielectric material 23 and the dielectric material 103 removed. The etchback of the dielectric material 23 and the dielectric material 103 exposes a portion of the top surface of the upper layer of the resistive liner 122 and a portion of the bottom surface of the lower layer of the resistive liner 122. In various embodiments, the etchback of the dielectric material 23 and the dielectric material 103 occurs in the same process step. In one embodiment, more than one etching process is used to recess the dielectric material 23 and the dielectric material 103. By etching back or recessing the dielectric material 23 and the dielectric material 103, essentially the same or similar amounts of each of the dielectric material 23 and the dielectric material 103 may be removed. In various embodiments, dielectric material 23 and dielectric material 103 are composed of the same material, however, in some embodiments, dielectric material 43 and dielectric material 103 are different dielectric materials. In some examples, dielectric material 23 and dielectric material 103 are composed of nitride or oxide materials such as SiN or SiO2, but are not limited to these dielectric materials.

[0097] The etch back of dielectric material 23 and dielectric material 103 can be performed using one of the etchants and processes (e.g., hot phosphoric acid) previously discussed in detail with respect to FIG. 6, or another etching process / etchant that is selective to dielectric material 23 and dielectric material 103 but not to dielectric material 22 or dielectric material 105. After recessing dielectric material 23 and dielectric material 103, the sidewalls of dielectric material 23 and the remaining portions of dielectric material 103 underlie a portion of phase change material 104 (e.g., the horizontal length of dielectric material 23 and the remaining portions of dielectric material 103 is less than the horizontal length of phase change material 104. As shown in FIG. 16, each of the two layers of resistive liner 122 has a horizontal length that is greater than the horizontal length of phase change material 104, and dielectric material 23 and dielectric material 104 have horizontal lengths that are less than the horizontal length of phase change material 104. As shown in FIG. 16, the sidewalls of side contact 150 are flush with the outer edges or sidewalls of the two layers of resistive liner 122 (e.g., the edges of the two resistive liners 122 and side contact 150 form essentially vertical surfaces with their sidewalls).

[0098] 16, side contact 150 resides between the outer portions of two layers of resistive liner 122 that extend beyond phase change material 104. Side contact 150 abuts phase change material 104, while the remaining portions of dielectric material 23 and dielectric material 103 are centered directly below and above bottom resistive liner 122 and top resistive liner 122, respectively, and are centered in phase change material 104 between the two resistive liners 122. For example, dielectric material 23 and dielectric material 103 may be recessed by approximately 5-100 nm or less than the horizontal extent of phase change material 104, but are not limited to these different lengths.

[0099] 17 illustrates a cross-sectional view of device structure 1700 after conformal deposition of conductive material 177, in accordance with one embodiment of the present invention. As shown, FIG. 17 includes elements of FIG. 16 with the addition of conductive material 177 over device structure 1700. Conductive material 177 is conformally deposited (e.g., by ALD or CVD) to fill the recesses created by the etchback of dielectric material 23 and dielectric material 103. As shown in FIG. 17, conductive material 177 is over and / or around dielectric material 22, the exposed surface of dielectric material 23, portions of the exposed bottom and top surfaces of both layers of resistive liner 122, side contact 150, dielectric material 103, dielectric material 105, and top electrode 106.

[0100] Conductive material 177 may be comprised of any suitable conductive material, such as a metal or metal alloy. For example, conductive material 177 may be, but is not limited to, TiN. In various embodiments, conductive material 177 and side contacts 150 are comprised of the same conductive material. In some embodiments, conductive material 177 is comprised of a different conductive material than side contacts 150.

[0101] FIG. 18 illustrates a cross-sectional view of device structure 1800 after etching exposed horizontal portions of conductive material 177, according to one embodiment of the present invention. As shown, FIG. 18 includes remaining portions of conductive material 177 along substrate 2, bottom electrode 4, dielectric layer 3, sidewalls or vertical edges of dielectric material 23, lateral contact 150, recessed dielectric material 103, portions of the sides and bottom surface of dielectric material 105, portions of the sidewalls of top electrode 106, portions of the outer edge and bottom surface of the lower layer of resistive liner 122, and portions of the edge and outer edge of the top surface of upper resistive liner 122. After the directional etching process (e.g., RIE), conductive material 177 remains along at least the bottom of top electrode 106 and, in some cases, may contact most of the sidewalls of top electrode 106. A portion of conductive material 177 resides directly on a portion of dielectric material 22 in the bottom bilayer dielectric composed of dielectric material 22 and recessed dielectric material 23. The conductive material 177 may transmit a current or signal from the side contact 150 to the top electrode 106. The side contact 150 may receive a current or signal from the heater 34 from one or both of the phase change material 104 or the resistive liner 122 (e.g., depending on the material phase or state of the phase change material 104, as previously discussed).

[0102] 18 , device structure 1800 provides direct contact between conductive material 177 and a portion of each layer of resistive liner 122 (i.e., direct contact to a portion of the top and bottom surfaces of each of the upper and lower layers of resistive liner 122, respectively, and to the edges or sidewalls of each layer of resistive liner 122). Device structure 1800 also provides direct contact of phase change material 104 with side contacts 150, the sidewalls of which directly abut or contact conductive material 177 and the phase change material 104 that resides between the two layers of resistive liner 122.

[0103] In various embodiments, device structure 1800 provides an electrical path from bottom electrode 4 through heater 34 to bottom resistive liner 122, through either one or both of phase change material 104 and resistive liner 122 (e.g., depending on the phase of phase change material 104). For example, when phase change material 104 is in a crystalline phase, which is a phase or atomic structure of phase change material 104 that has a lower electrical resistance than resistive liner 122, device structure 1800 may provide an electrical path from heater 34 through the lower layer of resistive liner 122, through phase change material 104, and then through an intact sidewall of phase change material 104 to side contact 150 in abutting contact with material 177 that connects to top electrode 106. As previously discussed, side contact 150 may be composed of the same conductive material as conductive material 177. A portion of the current may flow from phase change material 104 through resistive liner 122 to conductive material 177. The current distribution will depend at least in part on the degree to which the dielectric materials 23 and 103 are recessed or concave.

[0104] In many cases, when a portion of the phase change material 104 is in the amorphous state, a portion of the current flows through the resistive liner 122 adjacent to the amorphous portion of the phase change material 104, and a portion of the current may pass through portions of the phase change material 104 that are not in the amorphous state (e.g., portions of the phase change material 104 that are in a crystalline or low-resistivity state). More specifically, following a RESET pulse, amorphous regions of the phase change material 104 may form on the heater 34. The material of the resistive liner 122 is selected so that it has a lower electrical resistance than the amorphous phase of the phase change material 104, so that during readout, current from the heater 34 flows through the resistive liner 122, bypassing the amorphous regions of the phase change material 104. Current may flow back to the crystalline phase change material 104, which remains unchanged by RESET, at the edges of the amorphous regions. This current flow occurs because the material for resistive liner 122 is selected to have a higher resistivity (at least 10 times higher) than the crystalline phase of phase change material 104 .

[0105] As shown in device structure 1800, the phase change memory device includes a top electrode 106, a top bi-layer dielectric composed of dielectric material 105 and recessed dielectric material 103, side contact 150, phase change material 104 abutting side contact 150 and located between the upper and lower layers of resistive liner 122, a bottom bi-layer dielectric composed of recessed dielectric material 23 and dielectric material 22, and a heater 34 in the bottom bi-layer dielectric contacting bottom resistive liner 122 and residing above substrate 2 on bottom electrode 4. In various embodiments, the top bi-layer dielectric and the bottom bi-layer dielectric are composed of the same dielectric material deposited in reverse order. For example, dielectric material 22 and dielectric material 105 can be low-k dielectric materials, and dielectric material 23 and dielectric material 105 can be oxide-based or nitride-based dielectric materials. As previously discussed, in some cases, one or both materials in the top bi-layer dielectric and the bottom dielectric can be different dielectric materials.

[0106] As shown in device structure 1800, some of the layers of material have different lengths or widths within device structure 1800. For example, the layer lengths or layer widths of dielectric material 23 and dielectric material 103 in device structure 1800 are smaller than the layer length or width of phase change material 104. Similarly, the width of each of resistive liners 122 around phase change material 104 is greater than the width or length of phase change material 104. Recessing phase change material 104, for example, using a digital etching process, dry or wet etching process as previously described, provides undamaged surfaces for the sidewalls of phase change material 104 that contact the conductive material of side contact 150. Furthermore, recessing dielectric material 23 and dielectric material 103 exposes portions of the top and bottom surfaces of each of the two layers of resistive liner 122 for contact with side contact 150 and conductive material 177, which form the conductive cladding that contacts top electrode 106. Conductive material 177 contacts portions of the two layers of resistive liner 122. As shown, conductive material 177 contacts portions of the two resistive liners over the outer portions of phase change material 104 and contacts portions of the two layers of resistive liner 122 that extend beyond the sidewalls of phase change material 104.

[0107] As will be known to those skilled in the art, the thicknesses and lengths of the various layers of material shown in Figure 18 represent only one example embodiment of the present invention, and in other examples, the thicknesses and / or lengths of the material layers may vary. For example, as shown in Figure 18, phase change material 104 is a thin layer of phase change material 104, but in other examples, phase change material 104 may have any thickness (i.e., phase change material 104 may be a thick layer of phase change material 104).

[0108] FIG. 19 illustrates a cross-sectional view of device structure 1900 after forming pillars comprised of top electrode 106, dielectric material 105, dielectric material 103, two layers of resistive liner 122 surrounding phase change material 104, dielectric material 23, and the top of heater 34 in dielectric material 23, in accordance with one embodiment of the present invention. As shown, FIG. 19 includes elements of FIG. 13 . Device structure 1900 may be formed using essentially the same or similar processes and materials as those used to form device structure 1300. After forming the pillars shown in FIG. 19 , for example, using RIE, damage may occur to the sidewalls of phase change material 104. For example, after etching, the sidewalls of phase change material 104 may have a different composition or a roughened surface. The roughened surface or slightly different composition of the etched sidewalls of phase change material 104 may increase the electrical contact resistance between phase change material 104 and any conductive material deposited in later process steps. The electrical contact resistance of as-deposited or undamaged phase change material 104 is lower than the contact resistance of damaged sidewalls of phase change material 104 after directional etching (eg, by RIE).

[0109] 20 illustrates a cross-sectional view of device structure 2000 after recessing dielectric material 103 and dielectric material 23 directly above and below two resistive liners 122, respectively, recessing portions of the two layers of resistive liners 122, conformally depositing conductive material 277, and removing exposed horizontal portions of conductive material 277, in accordance with one embodiment of the present invention. As shown, FIG. 20 includes remaining portions of conductive material 277 along substrate 2, bottom electrode 4, dielectric layer 3, vertical sides of recessed dielectric material 23, recessed dielectric material 103, dielectric material 105, portions of the sidewalls of top electrode 106, sidewalls or edges of each of two resistive liners 122, sidewalls of phase change material 104, and portions of the top and bottom surfaces of phase change material 104. Additionally, a portion of conductive material 277 resides directly above a portion of dielectric material 22. Semiconductor structure 2000 is similar to semiconductor structure 800 and may be formed using some of the same processes, but semiconductor structure 2000 has two layers of resistive liner 122 surrounding phase change material 104. As shown, after recessing resistive liner 122, the two layers of resistive liner 122 around phase change material 104 may have the same length as dielectric materials 23 and 103. As shown, a portion of conductive material 277 directly contacts the vertical sides or sidewalls of phase change material 104, a portion of the top surface of phase change material 104, and a portion of the bottom surface of phase change material 104. Conductive material 277 may directly contact a portion of phase change material 104 that extends beyond the layers of resistive liner 122 surrounding phase change material 104.

[0110] Recessing or etching back dielectric material 23 and dielectric material 103 may be performed using one of the previously discussed dielectric material etching processes (e.g., hydrofluoric acid etchant, H3PO4 etchant, hot phosphoric acid, etc.), as discussed with respect to FIG. 8. As previously discussed with respect to FIG. 8, some erosion or slight compositional changes may occur to the exposed surface of phase change material 104 during the etching of dielectric material 23 and dielectric material 103. After recessing the two dielectric materials, exposed portions of each of the two layers of resistive liner 122 surrounding the outer portion of phase change material 104 may be removed. For example, if resistive liner 122 is composed of TaN, resistive liner 122 may be etched back using a mixture of H2O2 and ethylenediaminetetraacetic acid (EDTA). Etching back the two layers of resistive liners 122 exposes outer portions of phase change material 104 (eg, portions of phase change material 104 not covered by either of resistive liners 122).

[0111] After etching back dielectric material 23, dielectric material 103, and resistive liner 122, a portion of phase change material 104 extends beyond the remaining portions of resistive liner 122 and dielectric material 23 and recessed dielectric material 105. In some cases, as previously discussed, after etching back resistive liner 122, the surface of the extended portion of phase change material 104 may be rough, rounded, or have a slightly different composition. In other cases, the surface of phase change material 104 is essentially the same or essentially unaffected by the etch-back process. As shown, the vertical sides of dielectric material 23 and dielectric material 103 are essentially above and below each other and generally above and below the remaining portions of resistive liner 122.

[0112] Following the etchback of dielectric material 23 and dielectric material 103, and after the etchback of the two layers of resistive liner 122, conductive material 277 is conformally deposited on the exposed surfaces of dielectric material 22, phase change material 104, upper electrode 106, and around the exposed sides of each of the recessed dielectric material 23, resistive liner 122, and the upper dual-layer dielectric composed of dielectric material 103 and dielectric material 105.

[0113] A directional etching process (e.g., RIE) may be used to remove horizontal portions of conductive material 277. The remaining portion of conductive material 277 on top of a portion of dielectric material 22 covers the top, bottom, and portions of the sidewalls of phase change material 104, as well as the sidewalls of the material in the pillar (i.e., comprised of dielectric material 23, both resistive liners 122, phase change material 104, dielectric material 103, dielectric material 105, and top electrode 106) formed after the directional etching process. As shown, conductive material 277 connects phase change material 104 to top electrode 106.

[0114] As previously discussed, the two layers of resistive liner 122 surround phase change material 104 in the central or switching region of phase change material 104 to mitigate the effects of resistance drift that can occur in the amorphous state of phase change material 104. Additionally, device structure 2000 increases the contact area between phase change material 104 and conductive material 277, thereby reducing the electrical resistance of the interface between phase change material 104 and conductive material 277 compared to conventional PCM device structures, particularly compared to PCM device structures formed using a thin layer of phase change material 104. Device structure 2000 provides direct contact with conductive material 277 on portions of the sidewalls, top surface, and bottom surface of phase change material 104. The extension of phase change material 104 beyond dielectric material 23 and dielectric material 103 provides a larger surface area for contacting conductive material 277, improving the electrical performance of the PCM device, as previously discussed. The length of extension and the amount of contact area between conductive material 277 and phase change material 104 can be customized depending on the length, type of etch-back process, and device performance requirements. Compared to conventional PCM devices with a thin layer of phase change material, semiconductor structure 2000 can significantly increase the contact area between conductive material 277 and phase change material 104.

[0115] 21 illustrates a cross-sectional view of device structure 2100 after depositing a lower layer of phase change material 204 on the semiconductor structure of FIG. 3 , depositing a layer of resistive liner 222 on the lower layer of phase change material 204, depositing an upper layer of phase change material 204 on resistive liner 222, and depositing dielectric material 103, dielectric material 105, and top electrode 106, in accordance with one embodiment of the present invention. As shown, FIG. 21 includes elements of FIG. 12 , but the two layers of phase change material 104 and resistive liner 122 have been replaced with a single layer of resistive liner 222 between the two layers of phase change material 204. The materials of resistive liner 222 and phase change material 204 can be any of the materials previously discussed for phase change material 104 and resistive liner 122.

[0116] A resistive liner 222 present between the layers of phase change material 204 can reduce the effects of resistance drift in the upper layer of phase change material 204. In some cases, the two layers of phase change material 204 have the same thickness, while in other cases, the thicknesses of the two layers can be different (e.g., the upper layer of phase change material 204 is slightly thinner than the lower layer of phase change material 204).

[0117] Figure 22 shows a cross-sectional view of device structure 2200 after recessing dielectric material 23 and dielectric material 103, conformally depositing conductive material 377, and removing horizontal portions of conductive material 377. As shown, Figure 21 includes the elements of Figure 20, but the conductive material 277, phase change material 104, and two layers of resistive liner have been replaced with two layers of phase change material 204 surrounding conductive material 377 and a layer of resistive liner 222.

[0118] Device structure 2200 provides similar electrical advantages as semiconductor structure 2000 due to the increased contact area between conductive material 377 and the two layers of phase change material 204, but as previously discussed, the effects of resistance drift that can occur in the amorphous state of phase change material 204 are slightly different or reduced.

[0119] While the present invention has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will recognize that various changes in form and details can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0120] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technology, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. Upper electrode; a phase change material, wherein the phase change material is recessed between two layers of resistive liner material; and a conductive material contacting the sidewalls of the top electrode, the phase change material, and a portion of the top and bottom surfaces of each of the two layers of resistive liner material; 1. A device structure for a phase change memory device comprising:

2. a heater in contact with a bottom electrode and a lower one of the two layers of resistive liner material, the heater being in a first bi-layer dielectric; and a second bilayer dielectric below the top electrode; The device structure of claim 1 further comprising:

3. 3. The device structure of claim 2, wherein the top dielectric layer of the first dual-layer dielectric is recessed below the lower layer of the two layers of resistive liner material.

4. 4. The device structure of claim 3, wherein the bottom dielectric layer of the second dual-layer dielectric is recessed above the upper one of the two layers of resistive liner material.

5. The device structure of claim 1 , wherein the two layers of the resistive liner material extend beyond the sidewalls of the phase change material.

6. 2. The device structure of claim 1, wherein the two layers of resistive liner material include outer portions of the portions of the top and bottom surfaces of each of the two layers of resistive liner material surrounded by the conductive material.

7. 5. The device structure of claim 4, wherein the upper layer of the first bilayer dielectric and the lower layer of the second bilayer dielectric are composed of the same dielectric material.

8. 8. The device structure of claim 7, wherein the upper layer of the first bi-layer dielectric and the lower layer of the second bi-layer dielectric have the same length.

9. 5. The device structure of claim 4, wherein the lower layer of the first bi-layer dielectric and the upper layer of the second bi-layer dielectric are comprised of a low-k dielectric material.

10. The device structure of claim 1 , wherein the phase change material has a damage-free sidewall surface.

11. The device structure of claim 1 , wherein the phase change material has a disk shape.

12. a heater overlying a portion of the bottom electrode; a first dielectric material around a lower portion of the heater; a second dielectric material around a top portion of the heater, wherein the second dielectric material is recessed; a first resistive liner overlying the second dielectric material; a phase change material recessed over a portion of the first resistive liner; a second resistive liner over the phase change material; a third dielectric material overlying the second resistive liner, wherein the third dielectric material is recessed over the second resistive liner; a fourth dielectric material underlying the top electrode; and a conductive material contacting at least a sidewall of the top electrode, the phase change material, and a portion of the top and bottom surfaces of the first resistive liner and the second resistive liner; 1. A device structure for a phase change memory device comprising:

13. 13. The device structure of claim 12, wherein the second and third dielectric materials are recessed with a horizontal length that is less than a horizontal length of the phase change material.

14. 13. The device structure of claim 12, wherein the second dielectric material and the third dielectric material are composed of the same dielectric material.

15. The device structure of claim 13 , wherein the first resistive liner and the second resistive liner extend beyond the sidewalls of the phase change material.

16. 15. The device structure of claim 14, wherein the first resistive liner and the second resistive liner have the same length as the second dielectric material and the third dielectric material, and the phase change material has a disk shape.

17. 1. A method of forming a device structure, the method comprising: forming a pillar using a directional etching process, wherein the pillar is comprised of a top electrode on a top bilayer dielectric, a phase change material between a top resistive liner and a bottom resistive liner, and a top dielectric layer of a bottom bilayer dielectric below the bottom resistive liner, wherein the directional etching that forms the pillar damages sidewalls of the phase change material; etching exposed sidewalls of the phase change material; conformally depositing a conductive material; removing the exposed horizontal portions of said conductive material; recessing a lower layer of the top dual-layer dielectric on the top resistive liner and the top dielectric layer of the bottom dual-layer dielectric below the bottom resistive liner; conformally depositing the conductive material onto the device structure; and removing a portion of the exposed horizontal surface of the conductive material. A method comprising:

18. 18. The method of claim 17, wherein removing the portion of the exposed horizontal surface of the conductive material further comprises the conductive material contacting sidewalls of the top electrode, the top bi-layer dielectric, the phase change material, and contacting the top dielectric layer of the bottom bi-layer dielectric, the top resistive liner, and a portion of the bottom resistive liner.

19. 18. The method of claim 17, wherein the lower layer of the top dual-layer dielectric on the top resistive liner and the upper layer of the bottom dual-layer dielectric below the bottom resistive liner are composed of the same dielectric material.

20. forming the pillars using the directional etching process; depositing the top dielectric layer of the bottom dual-layer dielectric above a bottom electrode; depositing a top dielectric layer of the bottom dual layer dielectric on the top dielectric layer of the bottom dual layer dielectric; forming a heater in a portion of the top dielectric layer and the bottom dielectric layer of the bottom dual-layer dielectric; depositing the bottom resistive liner; depositing the phase change material on the bottom resistive liner; depositing the top resistive liner over the phase change material; depositing the bottom dielectric layer of the upper dual-layer dielectric; depositing an upper dielectric layer of the upper dual-layer dielectric; depositing the upper electrode onto the upper electrical layer of the upper dual-layer dielectric; and performing the directional etching to pattern the top electrode material to form the pillars; 20. The method of claim 17, further comprising:

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