Transistor, 3D memory and its manufacturing method, electronic device

Abstract

A transistor, a 3D memory and its manufacturing method, and an electronic device, relating to the semiconductor technology field. The 3D memory comprises memory units and word lines (110) stacked in multiple layers in a direction perpendicular to a substrate (1). The memory units comprise transistors, each of which comprises a source electrode (51), a drain electrode (52), a gate electrode (11) extending in a direction perpendicular to the substrate (1), and a semiconductor layer (9) surrounding the sidewalls of the gate electrode (11). The semiconductor layer (9) comprises source and drain contact regions spaced apart, and a channel between the source and drain contact regions is a horizontal channel. The word lines (110) extend in a direction perpendicular to the substrate (1) and penetrate the memory units in different layers.

Description

[Technical Field]

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, but are not limited thereto, and in particular to transistors, 3D memories and their manufacturing methods, and electronic devices. This application claims priority to a Chinese patent application filed with the China Patent Office on October 18, 2022, bearing application number 202211270027.3 and entitled "Transistor, 3D memory and its manufacturing method, and electronic device," the contents of which are hereby incorporated by reference. [Background technology]

[0002] In recent years, 3D memory structures have attracted increasing attention and offer certain advantages in increasing memory density. For example, semiconductor memory devices using metal oxides, such as indium gallium zinc oxide (IGZO), as channels, have attracted attention in the industry due to their ability to be deposited on the surface of any material and their high switching ratio. In the memory field, these metal oxide semiconductor transistors can be used in 3D stacked structures of memory units to increase the density of memory units.

[0003] Currently, there is increasing attention being paid to the advantages of 3D device design structures in industrial manufacturing convenience and storage density. Summary of the Invention

[0004] The following is a general overview of the subject matter discussed in detail in the text, which is not intended to limit the scope of protection of the claims.

[0005] An embodiment of the present disclosure provides a 3D memory, comprising: memory units and word lines stacked in multiple layers in a direction perpendicular to a substrate, the word lines extending in a direction perpendicular to the substrate and passing through the memory units in different layers; The memory unit comprises a transistor, the transistor comprising a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer located on a sidewall of the gate electrode and insulated from the gate electrode, the semiconductor layer comprising a source contact region and a drain contact region spaced apart, and a channel between the source contact region and the drain contact region being a horizontal channel.

[0006] In one exemplary embodiment, the semiconductor layer surrounds the sidewalls of the gate electrode.

[0007] In one exemplary embodiment, the source electrodes of transistors in different layers are spaced apart and the drain electrodes of transistors in different layers are spaced apart.

[0008] In one exemplary embodiment, the gate electrodes of transistors in different layers are part of the word lines, and semiconductor layers corresponding to transistors in different layers are located on the sidewalls of the word lines.

[0009] In one exemplary embodiment, the source electrode of the same transistor is a source electrode film layer, and the drain electrode of the same transistor is a drain electrode film layer, and the drain electrode film layer and the source electrode film layer are located in the same layer and spaced apart.

[0010] In one exemplary embodiment, the source electrode film layer or the drain electrode film layer of different transistors are located on different film layers.

[0011] In one exemplary embodiment, in a plane parallel to the substrate, the orthogonal projections of the source electrode and the drain electrode of the same transistor do not overlap.

[0012] In a plane parallel to the substrate, the orthogonal projections of the source and drain electrodes of different transistors do not overlap.

[0013] In one exemplary embodiment, the source electrode is located on a first side of the gate electrode, and the drain electrode is located on a second side of the gate electrode, and the source electrode and the drain electrode are disposed opposite each other.

[0014] In one exemplary embodiment, the semiconductor layers of the transistors of the storage units of different layers are spaced apart in a direction perpendicular to the substrate.

[0015] In one exemplary embodiment, an insulating layer is exposed between the spaced apart semiconductor layers, and the insulating layer is a gate insulating layer located between the gate electrode and the semiconductor layer.

[0016] In one exemplary embodiment, every two adjacent semiconductor layers in the storage units of different layers are connected in an integral structure.

[0017] An embodiment of the present disclosure provides a vertical transistor for use in a 3D memory, comprising: a substrate; a source electrode, a drain electrode disposed on the substrate; a gate electrode extending in a direction perpendicular to the substrate; and a semiconductor layer that wholly or partially surrounds the gate electrode and is insulated from the gate electrode, wherein the semiconductor layer comprises a source contact region and a drain contact region that are spaced apart from each other, and a channel between the source contact region and the drain contact region is a horizontal channel.

[0018] In one exemplary embodiment, the source electrode film layer and the drain electrode film layer are different regions of the same conductive film layer and are spaced apart, and the same conductive film layer is substantially parallel to the substrate.

[0019] In one exemplary embodiment, the material of the semiconductor layer comprises a metal oxide semiconductor material.

[0020] In one exemplary embodiment, in a plane parallel to the substrate, the orthogonal projection of the source electrode and the orthogonal projection of the drain electrode do not overlap.

[0021] In one exemplary embodiment, the source contact region is located on a first side of the semiconductor layer, the drain contact region is located on a second side of the semiconductor layer, the source electrode contacts the source contact region, the drain electrode contacts the drain contact region, and the source electrode and the drain electrode are positioned opposite each other.

[0022] In one exemplary embodiment, the semiconductor layer is an annular, all-surrounding semiconductor layer.

[0023] An embodiment of the present disclosure provides a method for manufacturing a 3D memory, the 3D memory comprising: a plurality of memory units stacked in multiple layers in a direction perpendicular to a substrate; and one word line; The storage unit includes a transistor, the transistor including a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode, and the manufacturing method of the 3D memory includes: providing a substrate; sequentially and alternately depositing and patterning a plurality of insulating thin films and a plurality of conductive thin films on the substrate to form a plurality of stacked structures spaced apart in a direction parallel to the substrate, each stacked structure including a stack of insulating layers and conductive layers alternately arranged in a direction perpendicular to the substrate, each conductive layer corresponding to one transistor in one of the memory units, each conductive layer including a first sub-portion and a second sub-portion connected to each other; etching the stacked structure to form through-holes that penetrate the stacked structure in a direction perpendicular to the substrate, sidewalls of the through-holes exposing the first sub-portions, second sub-portions of each of the conductive layers, and the insulating layer; etching the first sub-portions in the through-holes to form a plurality of first vias corresponding to a plurality of transistors; etching the second sub-portions in the through-holes to form a plurality of second vias corresponding to a plurality of transistors, each of the first vias and each of the second vias being spaced apart and penetrating the through-hole; depositing a metal thin film in each of the first passages, each of the second passages, and each of the through-holes, and etching the metal thin film to remove the metal thin film in the through-holes, leaving a metal film layer in each of the first passages and each of the second passages, thereby forming a plurality of source electrodes located in each of the first passages and a plurality of drain electrodes located in each of the second passages; a semiconductor thin film is filled on a side wall of the through hole to form a semiconductor layer of each of the transistors, the semiconductor layer contacts each of the source electrodes and each of the drain electrodes, and a channel between the source electrode and the drain electrode of the same transistor is a horizontal channel; sequentially depositing a gate insulating layer and a metal thin film in the through hole, the metal thin film filling the through hole in the gate insulating layer to form the word line, and the gate electrode of the transistor in a different layer being part of the word line.

[0024] An embodiment of the present disclosure provides an electronic device, comprising the 3D memory according to any of the above embodiments, or comprising the vertical transistor for use in the 3D memory according to any of the above embodiments.

[0025] Other features and advantages of the present disclosure will be set forth in the specification which follows, and in part will be obvious from the specification, or may be learned by the practice of the present disclosure. The objects and advantages of the present disclosure will be realized and attained by the structure particularly pointed out in the specification and drawings.

[0026] Other aspects may be understood after reading and understanding the accompanying drawings and detailed description. [Brief explanation of the drawings]

[0027] The drawings are intended to provide a better understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions together with the embodiments of the present disclosure, but are not intended to limit the technical solutions.

[0028] [Figure 1]FIG. 1 is a schematic diagram of a transistor according to one exemplary embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the transistor shown in FIG. 1 taken along the line AA. [Figure 3] FIG. 3 is a schematic diagram after the second insulating thin film is formed, according to one exemplary embodiment. [Figure 4] FIG. 4 is a schematic diagram after the slots have been formed, according to one example embodiment. [Figure 5] FIG. 5 is a schematic diagram of the slot after filling, according to one exemplary embodiment. [Figure 6] FIG. 6 is a schematic diagram after through-holes have been formed, according to one exemplary embodiment. [Figure 7A] FIG. 7A is a schematic diagram after the passages have been formed, according to one example embodiment. [Figure 7B] FIG. 7B is a schematic diagram of a first metal layer according to one example embodiment. [Figure 8A] FIG. 8A is a schematic diagram after the active layer and the first gate insulating layer have been formed, according to one exemplary embodiment. [Figure 8B] FIG. 8B is a partial schematic diagram of FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view taken along the line BB in FIG. 8B. [Figure 9A] FIG. 9A is a schematic diagram after the second metal layer has been formed, according to one example embodiment. [Figure 9B] FIG. 9B is a partial schematic diagram of FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view taken along the line BB in FIG. 9B. [Figure 10A] FIG. 10A is a schematic diagram of the through-hole after the second metal layer has been removed, according to one illustrative embodiment. [Figure 10B] FIG. 10B is a partial schematic diagram of FIG. 10A. [Figure 10C] FIG. 10C is a schematic cross-sectional view taken along the line BB in FIG. 10B. [Figure 11A] FIG. 11A is a schematic diagram after a gate electrode has been formed, according to one example embodiment. [Figure 11B] FIG. 11B is a partial schematic diagram of FIG. 11A. [Figure 11C] FIG. 11C is a schematic cross-sectional view taken along the line BB in FIG. 11B. [Figure 11D] FIG. 11D is a cross-sectional schematic diagram of a source electrode, a drain electrode, and a gate electrode according to one illustrative embodiment. [Figure 12] FIG. 12 is a schematic diagram after the second insulating thin film is formed, according to one exemplary embodiment. [Figure 13] FIG. 13 is a schematic diagram after the slots have been formed, according to one example embodiment. [Figure 14] FIG. 14 is a schematic diagram of the slot after filling, according to one exemplary embodiment. [Figure 15] FIG. 15 is a schematic diagram after through-holes have been formed, according to one exemplary embodiment. [Figure 16] FIG. 16 is a schematic diagram after the gate electrode has been formed, according to one exemplary embodiment. [Figure 17A] FIG. 17A is a schematic diagram of a semiconductor device according to one example embodiment. [Figure 17B] FIG. 17B is a partial schematic diagram of FIG. 17A. [Figure 18] FIG. 18 is a flow chart of a method for manufacturing a semiconductor device according to one exemplary embodiment. [Figure 19] FIG. 19 is a flowchart of a method for manufacturing a semiconductor device according to another exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following describes in detail the embodiments of the present disclosure with reference to the drawings. The embodiments of the present disclosure and the features in the embodiments can be arbitrarily combined unless they conflict.

[0030] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs.

[0031] The embodiments of the present disclosure are not limited to the sizes, and the shapes and sizes of the components in the drawings do not reflect actual scale. Although the drawings show ideal examples in a schematic manner, the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0032] In this disclosure, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of elements and do not indicate any order, quantity, or importance.

[0033] In this disclosure, for convenience, terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used to describe the positional relationships of components with reference to the drawings. However, these terms are merely for the purpose of explaining and simplifying the present specification, and do not explicitly or implicitly indicate that the indicated devices or elements necessarily have a specific orientation or are constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present disclosure. The positional relationships of components are appropriately changed depending on the direction in which each component is described. Therefore, without being limited to the terms described in the disclosure, they can be appropriately substituted depending on the situation.

[0034] In the present disclosure, unless otherwise clearly specified or limited, the terms "attach" and "connect" should be understood in a broad sense. For example, they may mean fixedly connected, detachably connected, or integrally connected, may be mechanically connected or electrically connected, may be directly connected, may be indirectly connected via an intermediate part, or may be in communication within two elements. Those skilled in the art can understand the specific meanings in the present disclosure described above depending on the specific circumstances.

[0035] In the present disclosure, the functions of the "source electrode" and the "drain electrode" may be interchanged when using transistors of opposite polarity, when the current direction changes during circuit operation, etc. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" are interchangeable.

[0036] In this disclosure, "electrical connection" includes cases where components are connected via an element having some electrical function. The "element having some electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0037] In the present disclosure, "parallel" refers to being approximately parallel or nearly parallel, for example, the angle between two lines is -10° or more and 10° or less, and therefore also includes the angle being -5° or more and 5° or less. "Perpendicular" refers to being approximately perpendicular, for example, the angle between two lines is 80° or more and 100° or less, and therefore also includes the angle being 85° or more and 95° or less.

[0038] Below, the present application will be described in the order of transistors and 3D memory.

[0039] Fig. 1 is a schematic cross-sectional view of a transistor in a memory unit array according to an exemplary embodiment. Fig. 2 is a cross-sectional view of the transistor shown in Fig. 1 in the AA direction. As shown in Figs. 1 and 2, this embodiment provides a transistor, which may include a substrate 1, a source electrode 51, a drain electrode 52, and a gate electrode 11 disposed on the substrate 1 and extending in a first direction Z, and a semiconductor layer 9 surrounding the gate electrode 11 and insulated from the gate electrode 11 (for example, a gate insulating layer 10 surrounding the gate electrode 11 and a semiconductor layer 9 surrounding the gate insulating layer 10 may be included).

[0040] The substrate is a base substrate that plays a supporting role, and its material and internal structure are not the focus of this application, so they will not be described in detail in this application.

[0041] The source electrode 51, the drain electrode 52, and the gate electrode 11 extending in the first direction Z on the substrate 1 can be understood as the source electrode 51, the drain electrode 52, and the gate electrode 11 extending in the first direction Z disposed above the substrate.

[0042] The gate electrode 11 extending in the first direction Z is a gate electrode extending in a direction perpendicular to the substrate, and may be understood to extend only in the direction of the substrate as a whole, but the shape of the side surface of the gate electrode is not specifically limited. For example, the cross-sectional shape and dimensions of the gate electrode may be similar, or the cross-sectional shape and dimensions may be different in different regions.

[0043] Here, in some embodiments, the functions of the source electrode 51 and the drain electrode 52 are interchangeable; for example, the source electrode 51 in FIG. 1 is a drain electrode in some other embodiments, and the drain electrode 52 in FIG. 1 is a source electrode in some other embodiments.

[0044] The gate electrode extends in a direction perpendicular to the substrate, has side surfaces and upper and lower end faces, and the side surfaces are perpendicular to the substrate as a whole, or in other words, for a portion of the sidewall region that corresponds to the semiconductor layer and performs the gate electrode control function, the film layer in that region is perpendicular to the substrate.

[0045] Here, the semiconductor layer 9 surrounding the gate electrode 11 and insulated from the gate electrode 11 may be understood as a single film layer having two opposing main surfaces and two end faces. The two opposing main surfaces have a larger surface area than the end faces. For example, the semiconductor layer 9 extends along the sidewalls of the gate electrode, the thickness direction of the film layer is parallel to the substrate, the length of the film layer extending above and below the sidewalls of the gate electrode is the height of the film layer, and the length surrounding the gate electrode is the width of the film layer.

[0046] Here, surrounding may be understood to mean partially or completely surrounding the gate electrode. In some embodiments, the surrounding may be completely surrounding, and the cross section of the semiconductor layer after surrounding is annular. The cutting direction of the cross section is along a direction parallel to the substrate. In some embodiments, the surrounding may be partially surrounding, and the cross section after surrounding is not closed but has an annular shape, for example, an annular shape with an opening.

[0047] 2, the semiconductor layer 9 may include a source contact region 91 and a drain contact region 92 that are spaced apart, the source electrode 51 and the source contact region 91 being in contact, and the drain electrode 52 and the drain contact region 92 being insulated from the gate electrode 11 by the gate insulating layer 10. The channel between the source contact region 91 and the drain contact region 92 is a horizontal channel, i.e., the carrier transport direction in the channel is parallel to the upper surface of the substrate 1 (i.e., the surface facing the gate electrode 11). Alternatively, the length direction of the channel may be understood to be parallel to the substrate 1. The channel has a carrier transport direction, which is the length direction of the channel, and the direction perpendicular to the length direction is the width direction of the channel. The first direction Z may be perpendicular to the substrate 1.

[0048] The source contact region 91 and the drain contact region 92 being spaced apart means that they are not directly connected. In some embodiments, they may be spaced apart in a direction parallel to the substrate 1, and the central positions of the source contact region 91 and the drain contact region 92 in a direction perpendicular to the substrate 1 may be on the same plane or may be offset by a certain distance from each other, provided that the overall channel direction is inclined horizontally rather than perpendicular to the substrate.

[0049] In one exemplary embodiment, the semiconductor layer 9 is located only on the sidewalls of the gate electrode 11. Alternatively, it may be understood that a hole extending toward the substrate is formed in an insulating layer, the semiconductor layer is located on the wall of the hole, and extends in a direction perpendicular to the substrate to form a hole-like structure, the gate electrode is formed in the hole according to the shape of the hole, and is insulated from the gate electrode by a gate insulating layer. The gate electrode may be a solid structure or a hollow structure.

[0050] In one exemplary embodiment, the semiconductor layer 9 may extend on the sidewalls of the gate electrode 11 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate 1. In one exemplary embodiment, the semiconductor layer 9 surrounds the gate electrode 11 but is not in contact with the gate electrode 11, and the outer wall of the gate electrode 11 is surrounded by the gate insulating layer 10, and the semiconductor layer 9 surrounds the gate insulating layer 10. The semiconductor layer 9 may be of a fully surrounding type or a partially surrounding type, for example, the semiconductor layer 9 may have a gap in the direction perpendicular to the substrate 1.

[0051] The source contact region 91 and the drain contact region 92 on the semiconductor layer 9 are determined based on the source electrode and the drain electrode. The regions where the source electrode 51 and the drain electrode 52 are located and in contact with the semiconductor layer are the source contact region 91 and the drain contact region 92, respectively. Due to the locations of the source contact region 91 and the drain contact region 92, the carrier transport direction in the channel is horizontal rather than vertical. For example, the channel direction between the source electrode 51 and the drain electrode 52 generally extends parallel to the substrate 1. Furthermore, when fabricating a 3D stacked memory unit, the gate electrodes 11 of the transistors in each stack can be connected to each other to form word lines connected to each transistor in the 3D stack. The vertically extending word lines save space and allow the gate electrodes and word lines of each transistor to be formed in a single process, reducing the number of masks, effectively simplifying the fabrication process, and reducing costs.

[0052] Each source electrode 51 is provided with a separate source contact region, and each drain electrode 52 is provided with a separate drain contact region.

[0053] The word line may extend vertically in a straight line or a curved line. In some embodiments, the vertically extending gate electrode 11 of each transistor may be straight, and the orthogonal projections on the substrate 1 may be at the same position, so that the gate electrodes of each transistor form a straight word line after being connected. The curve may not be entirely straight, but the gate electrodes of the corresponding semiconductor regions or active semiconductor regions are straight lines extending in a direction perpendicular to the substrate, and the word line portion between two adjacent layers may not be straight.

[0054] The cross section of the straight word line along the direction parallel to the substrate 1 may be the same everywhere, or may not be completely the same. The present embodiment does not limit the characteristics of the cross section of the straight line.

[0055] In some embodiments, the vertically extending gate electrodes 11 of each transistor may be straight, and their orthogonal projections on the substrate 1 may not be at exactly the same position, so that after being connected, the gate electrodes 11 of each transistor are formed so that they extend in a direction perpendicular to the substrate 1 as a whole, but are partially curved.

[0056] In a horizontal channel, the carrier transport direction in the channel is in a plane parallel to the substrate, but the carrier transport direction is not necessarily limited to one direction. In practical applications, the carrier transport direction generally extends in one direction, but locally depends on the shape of the semiconductor layer. In other words, a horizontal channel does not necessarily extend in a straight line in a horizontal plane but may extend in a different direction. For example, if the semiconductor layer 9 is annular, the source contact region 91 and the drain contact region 92 in the annular semiconductor layer are part of the annulus. In this case, the carriers generally extend in one direction from the source contact region 91 to the drain contact region 92, but locally may not be unidirectional. Of course, the carrier transport direction in a plane parallel to the substrate 1 is a macroscopic concept and is not necessarily absolutely parallel to the substrate. This application also claims a channel between the source electrode 51 and the drain electrode 52 that is not perpendicular to the substrate 1.

[0057] In the transistors according to some embodiments of the present disclosure, the gate electrode of each transistor is a vertical gate electrode and the channel is a horizontal channel, which is beneficial for realizing a 3D stacked memory with a simple structure and relatively easy manufacturing. In one exemplary embodiment, in a plane parallel to the substrate 1, the orthogonal projection of the source electrode 51 and the orthogonal projection of the drain electrode 52 may not overlap, thereby ensuring that the channel is a horizontal channel.

[0058] In one exemplary embodiment, the orthogonal projections of the source contact region 91 and the drain contact region 92 in a plane perpendicular to the substrate 1 may overlap, the plane being located between the source contact region 91 and the drain contact region 92.

[0059] In one exemplary embodiment, the semiconductor layer 9 may be of a fully surrounding type that completely surrounds the sidewall of the gate electrode 11, i.e., the cross section of the semiconductor layer 9 is a closed loop in the region corresponding to the gate electrode 11. Exemplarily, the semiconductor layer 9 is annular, and the cross section of the semiconductor layer 9 at each position of the gate electrode 11 is annular, and the annular shape matches the outer contour shape of the cross section of the gate electrode 11. Exemplarily, the outer contour of the cross section of the gate electrode 11 may have a circular, elliptical, square, or other structure.

[0060] In one exemplary embodiment, a first distance between the surface of the source electrode 51 closer to the substrate 1 and the substrate 1 along a direction perpendicular to the substrate 1 may be the same as a second distance between the surface of the drain electrode 52 closer to the substrate 1 and the substrate 1. That is, the source electrode 51 and the drain electrode 52 are the same distance from the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the first distance and the second distance may be different. The source electrode 51 and the drain electrode 52 may be understood to be located in different regions of the same metal film layer, spaced apart, and formed by patterning a single metal film layer, with the metal film layer and the upper surface of the substrate 1 being approximately parallel. The source electrode 51 and the drain electrode 52 each have two main surfaces, upper and lower, and side surfaces. The side surfaces contact the semiconductor layer 9, and the shape of the side surfaces matches the shape of the sidewalls of the semiconductor layer 9.

[0061] In one exemplary embodiment, the first thickness of the source electrode 51 may be the same as the second thickness of the drain electrode 52 along a direction perpendicular to the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the first thickness and the second thickness may be different.

[0062] In one exemplary embodiment, the source electrode 51 and the drain electrode 52 may be located in the same conductive film layer along a direction perpendicular to the substrate 1. This may be understood to mean that the source electrode 51 and the drain electrode 52 are located in the same metal film layer and are formed by patterning one metal film layer, and the metal film layer and the upper surface of the substrate 1 are approximately parallel to each other.

[0063] In one exemplary embodiment, in a plane parallel to the substrate 1, the orthogonal projection of the gate electrode 11 may be located outside the orthogonal projection of the source electrode 51, and the orthogonal projection of the gate electrode 11 may be located outside the orthogonal projection of the drain electrode 52. According to the solution provided by this embodiment, it is possible to realize the fabrication of multiple transistors with a simple structure and relatively easy operation, and the gate electrodes 11 of each transistor are connected to form a word line.

[0064] In one exemplary embodiment, the semiconductor layer 9 may be a metal oxide semiconductor layer or a silicon-containing semiconductor layer.

[0065] In one exemplary embodiment, the metal in the metal oxide semiconductor layer may include at least one of indium, tin, zinc, aluminum, and gallium, but is not limited to the examples of such materials.

[0066] In one exemplary embodiment, the metal oxide semiconductor layer may include at least one of indium oxide, tin oxide, indium zinc (In-Zn)-based oxide, tin zinc (Sn-Zn)-based oxide, aluminum zinc (Al-Zn)-based oxide, indium gallium (In-Ga)-based oxide, indium gallium zinc (In-Ga-Zn)-based oxide, indium aluminum zinc (In-Al-Zn)-based oxide, indium tin zinc (In-Sn-Zn)-based oxide, tin gallium zinc (Sn-Ga-Zn)-based oxide, aluminum gallium zinc (Al-Ga-Zn)-based oxide, and tin aluminum zinc (Sn-Al-Zn)-based oxide.

[0067] In one exemplary embodiment, as shown in FIG. 2 , the cross section of the gate electrode 11 may be rectangular, and the side surface may have four sides, with each two sides facing each other (e.g., a first side facing a second side). The source electrode 51 may be located on the first side of the gate electrode 11, and the drain electrode 52 may be located on the second side of the gate electrode 11, with the source electrode 51 and the drain electrode 52 being disposed opposite each other. That is, the first side and the second side are opposite sides. However, embodiments of the present disclosure are not limited thereto, and the source electrode 51 and the drain electrode 52 may be located in other positions.

[0068] In one exemplary embodiment, when the transistors are arranged in an array, the source electrode 51 may extend in a second direction X, and the drain electrode 52 may extend in a third direction Y, where the second direction X may be parallel to the substrate 1, and the third direction Y may be parallel to the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the source electrode 51 and the drain electrode 52 may have other shapes. It may be understood that the source electrode 51 and a lead wire are integrally formed, and the drain electrode 52 and a lead wire are integrally formed. In this case, although it is difficult to determine the boundaries of the source electrode 51 and the drain electrode 52 with the respective lead wires, it may be understood that the lead wire integral with the source electrode 51 extends in the row direction in a horizontal plane, and the lead wire integral with the drain electrode 52 extends in the column direction.

[0069] In one exemplary embodiment, the second direction X and the third direction Y may intersect.

[0070] In one exemplary embodiment, the second direction X and the third direction Y may be perpendicular to each other, but embodiments of the present disclosure are not limited thereto, and the second direction X and the third direction Y may be at other angles.

[0071] In one exemplary embodiment, in a direction perpendicular to the substrate 1, the cross section of the source electrode 51 may be square, circular, elliptical, etc., and the cross section of the drain electrode 52 may be square, circular, elliptical, etc., but the embodiments of the present disclosure are not limited thereto, and the cross sections of the source electrode 51 and the drain electrode 52 may be other shapes, for example, circular, hexagonal, etc.

[0072] In one exemplary embodiment, the source electrode 51 and the drain electrode 52 may be connected to other positions different from those shown in FIG. 1, for example, the source electrode 51 is connected to a first side of the annular pillar made of the semiconductor layer 9, the drain electrode 52 is connected to a second side of the annular pillar made of the semiconductor layer 9, and the first and second sides are adjacent to each other, etc.

[0073] In one exemplary embodiment, the source electrode 51 and the drain electrode 52 may be disposed in the same layer. That is, the source electrode 51 and the drain electrode 52 may be simultaneously formed by the same patterning process. However, the embodiment of the present disclosure is not limited thereto, and the source electrode 51 and the drain electrode 52 may be manufactured by different patterning processes.

[0074] The source electrode 51 and the drain electrode 52 described in the examples of the present application refer only to the first electrode and the second electrode of one transistor, excluding the gate electrode, where one of the first electrode and the second electrode is the source electrode and the other is the drain electrode. The identification of the source electrode or the drain electrode in a product is determined based on the flow of current. For example, the source electrode described in the examples of the present application may be interpreted as the drain electrode depending on the flow of current.

[0075] 2, in the solution of this embodiment, the size of the channel between the source electrode 51 and the drain electrode 52 can be controlled by the overlap length between the orthogonal projection of the source electrode 51 and the orthogonal projection of the drain electrode 52 in a plane perpendicular to the substrate 1. In FIG. 2, the overlap length between the orthogonal projection of the source electrode 51 and the orthogonal projection of the drain electrode 52 is d, and the channel size can be controlled by controlling the thickness of the source electrode 51 and the drain electrode 52 in the direction perpendicular to the substrate 1. In the case of a transistor in which the source electrode surrounds the gate electrode and the drain electrode surrounds the gate electrode, the channel size can be controlled more easily with less process change and less impact on the transistor size than controlling the channel size by changing the size of the through hole in which the gate electrode is located (which requires a process change) or by increasing the distance between the source electrode and the drain electrode (which increases the volume of the transistor).

[0076] 1 and 2 are simplified schematic diagrams. An actually manufactured transistor may further include other film layers, such as an insulating layer located between the substrate 1 and the source electrode 51 and the drain electrode 52, and an insulating layer covering the source electrode 51 and the drain electrode 52.

[0077] Next, the technical solution of this embodiment will be described through the fabrication process of the transistor of this embodiment. The "patterning process" described in this embodiment includes processes such as film layer deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature fabrication process in the relevant technology. The "photolithography process" described in this embodiment includes film layer coating, mask exposure, and development, and is a mature fabrication process in the relevant technology. The deposition can be performed using known techniques such as sputtering, evaporation, chemical vapor deposition, and atomic layer deposition. The coating can be performed using known coating processes, and the etching can be performed using known methods, and is not limited thereto. In this description, a "thin film" refers to a layer of a thin film made of a certain material and fabricated on a base substrate by a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process in the entire fabrication process, the "thin film" may also be referred to as a "layer." If the "thin film" requires a patterning or photolithography process in the overall fabrication process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. After the patterning or photolithography process, the "layer" contains at least one "pattern."

[0078] There are various methods for fabricating the above-mentioned transistor 3D stacking. In this application, one implementation method is introduced as an example from the perspective of understanding the proposed structure. This implementation method is used to understand the above-mentioned structure, but is not used to limit the above-mentioned structure.

[0079] In one exemplary embodiment, the manufacturing process of the transistor may include the following steps 1) to 8).

[0080] 1) As shown in FIG. 3, a first insulating thin film, a first metal thin film, and a second insulating thin film are sequentially deposited on a substrate 1 to form a first insulating layer 2, a first metal layer 3, and a second insulating layer 4, respectively.

[0081] In one exemplary embodiment, the substrate 1 may be manufactured using glass, silicon, a flexible material, etc. The flexible material may be a material such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film. In an exemplary embodiment, the substrate 1 may have a single-layer structure or a multi-layer laminate structure, and the laminate structure substrate may include a flexible material / inorganic material / flexible material, and the inorganic material may be, for example, one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc.

[0082] In one exemplary embodiment, the first insulating thin film and the second insulating thin film may be low-K dielectric layers, i.e., dielectric layers with a dielectric constant K<3.9. For example, they may be one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). The first insulating thin film and the second insulating thin film may be made of the same material or different materials.

[0083] In one exemplary embodiment, the first metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum (Ta), and the like.

[0084] 4 , the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are patterned by a patterning process to form a first slot P1 and a second slot P2. The first slot P1 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and the second slot P2 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4. The first metal layer 3 may include a first sub-portion 31 extending in the second direction X and a second sub-portion 32 extending in the third direction Y.

[0085] In one exemplary embodiment, the cross sections of the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 may be H-shaped in a plane parallel to the substrate 1. In this case, the first metal layer 3 may include a second sub-portion 32 and a third sub-portion 33 facing each other, and a first sub-portion 31 connecting the second sub-portion 32 and the third sub-portion 33.

[0086] In one exemplary embodiment, the first slot P1 and the second slot P2 may have the same size and shape, but embodiments of the present disclosure are not limited thereto, and the first slot P1 and the second slot P2 may have different sizes and shapes.

[0087] In one exemplary embodiment, the third sub-portion 33 may extend in the third direction Y. However, embodiments of the present disclosure are not limited thereto, and the third sub-portion 33 may have other shapes. In one exemplary embodiment, the third sub-portion 33 may be eliminated.

[0088] In this embodiment, the pattern of the first metal layer 3 is merely an example, and the first metal layer 3 may have a pattern of other shapes, for example, the current second sub-section 32 may be divided into two parts along the extension direction of the first sub-section 31, and only one of the parts may be left as the second sub-section 32.

[0089] 3) As shown in FIG. 5, on the substrate 1 on which the pattern is formed, a third insulating thin film is deposited to form a third insulating layer 5, and the third insulating layer 5 fills the first slot P1 and the second slot P2.

[0090] In one exemplary embodiment, the third insulating thin film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K<3.9, such as one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). The third insulating thin film, the first insulating thin film, and the second insulating thin film may be made of the same material or different materials.

[0091] 6, in the substrate 1 on which the pattern is formed, a through hole 41 is formed penetrating the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and in a plane parallel to the substrate 1, an orthogonal projection of the through hole 41 overlaps with an orthogonal projection of the first sub-portion 31 and overlaps with an orthogonal projection of the second sub-portion 32. Although the cross section of the through hole 41 in the plane parallel to the substrate 1 shown in FIG. 6 is rectangular, the embodiment of the present disclosure is not limited thereto, and the cross section of the through hole 41 in the plane parallel to the substrate 1 may be other shapes, such as a circle, a pentagon, a hexagon, etc.

[0092] 5) As shown in FIGS. 7A and 7B, in the substrate 1 on which the pattern is formed, the first metal layer 3 is selectively etched at the first sub-portion 31, the second sub-portion 32, and the connection portion between the third sub-portion 33 and the first sub-portion 31, so that only the third sub-portion 33 remains in the first metal layer 3, and a third slot P3 is formed in the third sub-portion 33 toward the first sub-portion 31 (the first sub-portion 31 has already been etched). At this time, a first passage 42 is formed in the region where the selectively etched first sub-portion 31 is located, a second passage 43 is formed in the region where the second sub-portion 32 is located, and the through hole 41 is formed, and the first passage 42 penetrates the through hole 41, and the second passage 43 penetrates the through hole 41.

[0093] 6) As shown in Figures 8A, 8B, and 8C, a first semiconductor thin film and a first gate electrode oxide thin film are sequentially deposited on the sidewalls of the vias (i.e., through-hole 41, first via 42, and second via 43) formed in step 5 to form an active layer 6 and a first gate insulating layer 7, respectively. Here, Figure 8C is a cross-sectional view taken along the B-B direction of Figure 8B, showing only the active layer 6 and the first gate insulating layer 7. At this time, the active layer 6 and the first gate insulating layer 7 become the via walls, and the active layer 6 surrounds the first gate insulating layer 7.

[0094] In one exemplary embodiment, the first gate electrode oxide thin film may be a high-K dielectric material, which may include, but is not limited to, at least one of silicon oxide, aluminum oxide, and hafnium oxide.

[0095] In one exemplary embodiment, the first semiconductor thin film may be a silicon-containing film layer or a metal oxide semiconductor as a channel layer, and the metal oxide semiconductor may be formed of at least one of, but not limited to, IGZO, indium tin oxide (ITO), and indium zinc oxide (IZO). When IGZO is used as the semiconductor layer, it has the advantages of low leakage current and a short refresh time. The subsequent second semiconductor thin film is similar and will not be described again.

[0096] In one exemplary embodiment, the first semiconductor thin film and the first gate electrode oxide thin film may be deposited by atomic layer deposition (ALD).

[0097] 6) As shown in Figures 9A, 9B, and 9C, a second metal thin film is deposited in the vias (i.e., through-hole 41, first via 42, and second via 43) to form a second metal layer 8, completely filling the vias. Figure 9C is a cross-sectional view along the B-line of Figure 9B, showing only the active layer 6, first gate insulating layer 7, and second metal layer 8. At this time, the first gate insulating layer 7 surrounds the second metal layer 8.

[0098] In one exemplary embodiment, the second metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta), and the second metal thin film may be the same as or different from the first metal thin film.

[0099] 10A, 10B, and 10C, the second metal layer 8 and the first gate insulating layer 7 are selectively lithographed and etched at the positions where the through holes 41 are located, leaving the second metal layer 8 at other positions in the passages (the second metal layer 8 in the first passages 42 and second passages 43 parallel to the substrate 1). FIG. 10C is a cross-sectional view along the B-B direction of FIG. 10B, showing only the active layer 6, the first gate insulating layer 7, and the second metal layer 8. The second metal layer 8 located in the first passage 42 becomes the source electrode 51 of the transistor, and the second metal layer 8 located in the second passage 43 becomes the drain electrode 52 of the transistor, and the source electrode 51 and the drain electrode 52 are disconnected from each other.

[0100] 11A, 11B, and 11C, a second semiconductor thin film, a second gate electrode oxide thin film, and a third metal thin film are sequentially deposited on the sidewalls of the through-holes formed by the etching to form a semiconductor layer 9, a gate insulating layer 10, and a gate electrode 11, respectively, where the gate insulating layer 10 surrounds the gate electrode 11, the semiconductor layer 9 surrounds the gate insulating layer 10, and the gate electrode 11 completely fills the area surrounded by the gate insulating layer 10. FIG. 11C is a cross-sectional view taken along the B-B direction in FIG. 11B, and shows only the active layer 6, the first gate insulating layer 7, the semiconductor layer 9, the gate insulating layer 10, the second metal layer 8 (source electrode 51, drain electrode 52), and the gate electrode 11.

[0101] In one exemplary embodiment, the second gate electrode oxide thin film may be a high-K dielectric material, which may include, but is not limited to, at least one of silicon oxide, aluminum oxide, and hafnium oxide.

[0102] In one exemplary embodiment, the third metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta). The third metal thin film may be the same as or different from the first and second metal thin films.

[0103] The transistor manufactured by the above manufacturing method may further include a first gate insulating layer 7 surrounding the source electrode 51 and the drain electrode 52, and an active layer 6 surrounding the first gate insulating layer 7 (as shown in FIG. 11D , the sides of the source electrode 51 and the drain electrode 52 away from the gate electrode 11 are sequentially covered with the first gate insulating layer 7 and the active layer 6). In another exemplary embodiment, the active layer 6 and the first gate insulating layer 7 may be removed by etching, although the embodiments of the present disclosure are not limited thereto.

[0104] The above manufacturing process is merely an example, and the embodiments of the present disclosure are not limited thereto. Other manufacturing methods are also possible. For example, after depositing a first metal thin film, a patterning process can be used to form an H-shaped first metal layer 3. Then, a second insulating thin film can be deposited to form a second insulating layer 4. There is no need to slot the first slot P1 and the second slot P2, and there is no need to deposit a third insulating thin film.

[0105] An embodiment of the present disclosure further provides an electronic device, comprising the transistor according to any one of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet PC, an artificial intelligence device, a wearable device, a mobile power source, etc. The storage device may include, but is not limited to, a memory in a computer.

[0106] In another exemplary embodiment, the manufacturing process of the transistor may include the following steps 1) to 5).

[0107] 1) As shown in FIG. 12, a first insulating thin film, a first metal thin film, and a second insulating thin film are sequentially deposited on a substrate 1 to form a first insulating layer 2, a first metal layer 3, and a second insulating layer 4, respectively.

[0108] 13 , the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are patterned by a patterning process to form a third slot P3 and a fourth slot P4. The third slot P3 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and the fourth slot P4 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4. The first metal layer 3 may include a first sub-portion 31 extending in the second direction X and a second sub-portion 32 extending in the third direction Y.

[0109] In one exemplary embodiment, the third slot P3 and the fourth slot P4 may have the same size and shape, but embodiments of the present disclosure are not limited thereto, and the third slot P3 and the fourth slot P4 may have different sizes and shapes.

[0110] In this embodiment, the pattern of the first metal layer 3 is merely an example, and the first metal layer 3 may have a pattern of other shapes, for example, the current second sub-section 32 may be divided into two parts along the extension direction of the first sub-section 31, and only one of the parts may be left as the second sub-section 32.

[0111] 3) As shown in FIG. 14, on the substrate 1 on which the pattern has been formed, a third insulating thin film is deposited to form a third insulating layer 5, and the third insulating layer 5 fills the third slot P3 and the fourth slot P4.

[0112] In one exemplary embodiment, the third insulating thin film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K<3.9, such as one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). The third insulating thin film, the first insulating thin film, and the second insulating thin film may be made of the same material or different materials.

[0113] 15 , the substrate 1 on which the pattern is formed is etched to form a through-hole 41 penetrating the first insulating layer 2, the first metal layer 3, and the second insulating layer 4. In a plane parallel to the substrate 1, the orthogonal projection of the through-hole 41 may overlap the orthogonal projection of the first sub-portion 31, and the orthogonal projection of the through-hole 41 may overlap the orthogonal projection of the second sub-portion 32. After the first sub-portion 31 and the second sub-portion 32 are etched, one of them forms a drain electrode, and the other forms a source electrode. Although the cross section of the through-hole 41 in the plane parallel to the substrate 1 shown in FIG. 15 is rectangular, the embodiment of the present disclosure is not limited thereto, and the cross section of the through-hole 41 in the plane parallel to the substrate 1 may have other shapes, such as a circle, a pentagon, a hexagon, etc.

[0114] 16, a second semiconductor thin film, a second gate electrode oxide thin film, and a third metal thin film are sequentially deposited on the sidewall of the through hole 41 to form a semiconductor layer 9, a gate insulating layer 10, and a gate electrode 11, respectively, and the gate insulating layer 10 surrounds the gate electrode 11, the semiconductor layer 9 surrounds the gate insulating layer 10, and the gate electrode 11 completely fills the area surrounded by the gate insulating layer 10. Here, the semiconductor layer 9 is the semiconductor layer of the transistor, the gate insulating layer 10 is the gate insulating layer of the transistor, and the gate electrode 11 is the gate electrode of the transistor.

[0115] In one exemplary embodiment, the second gate electrode oxide thin film may be a high-K dielectric material, which may include, but is not limited to, at least one of silicon oxide, aluminum oxide, and hafnium oxide.

[0116] In one exemplary embodiment, the third metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta), and the third metal thin film may be the same as or different from the first metal thin film.

[0117] When manufacturing the above transistor, insulating thin films and metal thin films are alternately stacked, whereby a plurality of transistors sharing the semiconductor layer 9, gate insulating layer 10 and gate electrode 11 can be manufactured.

[0118] The transistors can be used in 3D memory. When fabricating a 3D stacked memory unit, if at least one transistor in a memory unit of a different layer requires stacking, the transistors according to the embodiments of the present application can be used to form a vertically stacked structure. The stacked structure can be a stack of transistors in a 1T1C memory unit, or a stack of one transistor in a 2T0C or 2T1C structure.

[0119] Taking a 1T1C memory unit as an example, only the stacking scheme between different transistors in a vertical row is introduced as follows: An embodiment of the present disclosure provides a 3D memory, which may include memory units and word lines stacked in multiple layers in a direction perpendicular to a substrate, and the word lines extend in a direction perpendicular to the substrate and pass through the memory units in different layers; The memory unit may include a transistor, which may include a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, and the semiconductor layer may include a source contact region and a drain contact region spaced apart, and a channel between the source contact region and the drain contact region is a horizontal channel.

[0120] In one exemplary embodiment, the source electrodes of transistors in different layers may be spaced apart, and the drain electrodes of transistors in different layers may be spaced apart.

[0121] In one exemplary embodiment, the gate electrodes of transistors in different layers are part of the word lines.

[0122] As shown in FIG. 2, FIG. 17A and FIG. 17B, transistor stacking in two stacked storage units is shown, and an embodiment of the present disclosure provides a 3D memory; The memory device may include a memory unit (only a transistor is shown in the drawing, and a capacitor is not shown) and a word line 110 (the word line 110 includes a gate electrode 11) stacked in multiple layers in a direction perpendicular to the substrate 1, The memory unit may include one transistor, and the transistor may include a source electrode 51 (since Figures 17A and 17B are not cross-sectional views but three-dimensional structures and the source electrode 51 cannot be displayed therein, the source electrode 51 is not shown in the drawings. Please refer to Figures 2 and 11A to 11D for an example of a transistor), a drain electrode 52, a gate electrode 11 extending in a direction perpendicular to the substrate 1, and a semiconductor layer 9 located on a sidewall of the gate electrode 11 and insulated from the gate electrode 11, and the semiconductor layer 9 may include a source contact region and a drain contact region that are spaced apart, the source electrode 51 and the source contact region are in contact, and the drain electrode 52 and the drain contact region are in contact, and a channel between the source contact region and the drain contact region is a horizontal channel, The word lines 110 extend in a direction perpendicular to the substrate 1 and pass through the memory units in different layers.

[0123] In one exemplary embodiment, the semiconductor layer 9 may surround the sidewalls of the gate electrode 11. In some embodiments, the sidewalls of the gate electrode extend only in a direction perpendicular to the substrate, and the semiconductor layer extends entirely only in a direction perpendicular to the substrate; however, curved regions that may partially exist when actually manufacturing a product are also included in the above situation of the present application.

[0124] In one exemplary embodiment, the source electrodes 51 of transistors in different layers may be spaced apart, and the drain electrodes 52 of transistors in different layers may be spaced apart, where spaced apart may be understood to mean that they are not in direct contact with each other and are spaced apart from each other by an insulating layer, but it does not mean that the source electrodes or drain electrodes of different layers are coupled in other regions.

[0125] In one exemplary embodiment, the gate electrodes 11 of the transistors in different layers may be part of the word lines 110, and the semiconductor layers 9 corresponding to the transistors in different layers are located on the sidewalls of the word lines 110. This design allows the word lines and gate electrodes of the storage units in different layers to be formed in one process, which can significantly reduce costs.

[0126] In one exemplary embodiment, the gate electrodes 11 of transistors in different layers are connected to form the word lines 110. The word lines may be understood to extend only vertically and have no branch structures extending to the sidewalls.

[0127] In one exemplary embodiment, the word line 110 extending in a direction perpendicular to the substrate 1 may be a straight line.

[0128] In one exemplary embodiment, the material components of different regions of the word line extending in a direction perpendicular to the substrate 1 are the same, which may be understood as being formed in the same film layer fabrication process, and the material components being the same may be understood as the main elements detected from the material being the same, for example, both being made of metal or a transparent conductive material such as ITO, but the atomic ratio in the different regions is not limited.

[0129] In one exemplary embodiment, the cross-sectional shapes of the word lines 110 extending in a direction perpendicular to the substrate 1 are substantially the same, and may be understood as holes formed using a single process, which are vertical holes, and the word lines are filled into the holes where the channel and gate insulating layer are formed, and generally the cross-sectional shapes of the holes are substantially the same and the sizes are also substantially similar. For example, the word lines correspond to regions of different layers, and the cross-sectional shapes are all circular, specifically all square, all elliptical, or other shapes, and the present application is not limited thereto.

[0130] In one exemplary embodiment, the semiconductor layers 9 corresponding to the transistors of different layers are located on the sidewalls of the word line 110 and in different regions extending in a direction perpendicular to the substrate 1 .

[0131] In one exemplary embodiment, the source electrode 51 and the drain electrode 52 of the same transistor may be located in the same conductive film layer, and the source electrode 51 or the drain electrode 52 of different transistors may be located in different conductive film layers.

[0132] In one exemplary embodiment, the source electrode of the same transistor is a source electrode film layer, the drain electrode of the same transistor is a drain electrode film layer, and the drain electrode film layer and the source electrode film layer are located in the same layer and spaced apart. In an actual process, the source electrode and the drain electrode of one transistor are formed by patterning one conductive film layer, so it may be understood that the drain electrode film layer and the source electrode film layer are located in the same layer, and in an actual product, the cross section is on one horizontal plane and the material is the same.

[0133] In one exemplary embodiment, the source electrode film layer or the drain electrode film layer of different transistors is located on a different film layer, resulting in a 3D stacked structure of different transistors, where the projections of the source electrodes of different transistors in the 3D stacked structure in a direction perpendicular to the substrate overlap, and the projections of the drain electrodes of different transistors in the direction perpendicular to the substrate overlap, and during the process, the conductive layer and the insulating layer can be stacked relative to each other, and multiple stacked source electrodes and drain electrodes can be formed using one mask, thereby simplifying the process.

[0134] In one exemplary embodiment, the conductive film layer may be parallel to the substrate 1 .

[0135] In one exemplary embodiment, the orthogonal projections of the source contact region and the drain contact region in a plane perpendicular to the substrate 1 overlap.

[0136] In one exemplary embodiment, in a plane parallel to the substrate 1, the orthogonal projections of the source electrode 51 and the drain electrode 52 of the same transistor do not overlap.

[0137] In one exemplary embodiment, in a plane parallel to the substrate 1, the orthogonal projections of the source electrodes 51 and the drain electrodes 52 of different transistors do not overlap.

[0138] In one exemplary embodiment, the source electrode 51 may be located on a first side of the gate electrode 11, and the drain electrode 52 may be located on a second side of the gate electrode 11, and the source electrode 51 and the drain electrode 52 may be disposed opposite each other.

[0139] In one exemplary embodiment, the semiconductor layers 9 of the transistors of the memory units in different layers may be spaced apart in a direction perpendicular to the substrate 1. This solution can avoid current leakage between the transistors in different layers due to the semiconductor layers 9, thereby reducing power consumption.

[0140] In one exemplary embodiment, there is an isolation layer between the spaced apart semiconductor layers 9, which may be an insulating layer obtained by doping the semiconductor layers 9.

[0141] In one exemplary embodiment, a gate insulating layer 10 is provided on the sidewall of the word line 110, surrounding the word line 110, and the semiconductor layers 9 of the transistors of different layers may be continuously distributed on the sidewall of the word line 110.

[0142] In one exemplary embodiment, an insulating layer may be exposed between the spaced apart semiconductor layers 9, and the insulating layer may be a gate insulating layer 10 located between the gate electrode 11 and the semiconductor layer 9.

[0143] In one exemplary embodiment, the connection between every two adjacent semiconductor layers 9 in the storage units of different layers may be integral.

[0144] In one exemplary embodiment, stacked transistors in different layers may share one word line 110 extending in a direction perpendicular to the substrate 1 .

[0145] In one exemplary embodiment, transistors in different layers may share one annular gate insulating layer 10 extending in a direction perpendicular to the substrate 1. In this embodiment, the gate insulating layers 10 of transistors in multiple layers can be formed in a single manufacturing process, thereby simplifying the process and reducing costs.

[0146] In one exemplary embodiment, transistors in different layers may share one annular semiconductor layer 9 extending in a direction perpendicular to the substrate 1. In this embodiment, the semiconductor layers 9 of multiple transistor layers can be formed in a single manufacturing process, thereby simplifying the process and reducing costs.

[0147] In one exemplary embodiment, the semiconductor layer 9 may be a metal oxide semiconductor layer, or the semiconductor layer 9 may be a silicon-containing semiconductor layer.

[0148] In one exemplary embodiment, projections of the source electrodes 51 of different layers on the substrate 1 may be located in the same region, projections of the drain electrodes 52 of different layers on the substrate 1 may be located in the same region, and projections of the gate electrodes 11 of different layers on the substrate may be located in the same region. In the proposal according to this embodiment, the orthogonal projections of the source electrodes 51, the drain electrodes 52, and the gate electrodes 11 of different layers are located in the same region, which can make the structure of the 3D memory compact and eliminate the need to pattern the source electrodes 51 and the drain electrodes 52 of each layer respectively, thereby simplifying the manufacturing process.

[0149] For the structure of a single transistor in the above 3D memory, reference can be made to the structures of the transistors in the above-mentioned embodiments, and the description will not be repeated here.

[0150] In the 3D memory according to this embodiment, the gate electrodes of the transistors are vertical gate electrodes and the channels are horizontal channels, which is advantageous for realizing a 3D stacked memory with a simple structure and relatively easy fabrication, and the degree of 3D integration is high. Furthermore, the gate electrodes of the transistors in each stack can be shared as word lines, and the vertically extending word lines can save space. Furthermore, in the 3D memory according to this embodiment, the channel size in the semiconductor device can be changed by adjusting the thickness of the source electrode or drain electrode, which simplifies the process and has little impact on the device size.

[0151] Although FIG. 17A shows only three insulating layers and two metal layers stacked alternately, the embodiments of the present disclosure are not limited thereto, and more layers may be stacked as needed, for example, hundreds of insulating layers and hundreds of metal layers, and the embodiments of the present disclosure are not limited thereto.

[0152] An embodiment of the present disclosure further provides an electronic device, comprising the 3D memory according to any one of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet PC, an artificial intelligence device, a wearable device, a mobile power source, etc. The storage device may include, but is not limited to, a memory in a computer.

[0153] As shown in FIG. 18 , an embodiment of the present disclosure provides a method for manufacturing a 3D memory, the 3D memory comprising: a plurality of memory units stacked in multiple layers in a direction perpendicular to a substrate; and one word line; the memory units comprising transistors; the transistors comprising a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate; and a semiconductor layer surrounding the gate electrode; and the method for manufacturing the 3D memory includes the following steps 1801 to 1805: Step 1801: prepare a substrate; sequentially and alternately deposit a plurality of insulating thin films and a plurality of metal thin films on the substrate; and pattern the deposited layers to form a plurality of stacked structures, each of which includes a stack of alternating insulating layers and metal layers, each of which corresponds to one transistor in one of the memory units, and each of which includes a first sub-part and a second sub-part connected to each other; In step 1802, the stacked structure is etched to form through-holes that penetrate the stacked structure in a direction perpendicular to the substrate, sidewalls of the through-holes exposing the first sub-portions, second sub-portions of each of the metal layers, and the insulating layer, each first sub-portion in the through-holes is etched to form a first passage, each second sub-portion in the through-holes is etched to form a second passage, and the first passage and the second passage penetrate the through-hole; In step 1803, a metal thin film is deposited in the first passage, the second passage, and the through-hole, and the metal thin film in the through-hole is etched to form a source electrode located in the first passage and a drain electrode located in the second passage; In step 1804, a semiconductor thin film is filled on the sidewall of the through-hole to form a semiconductor layer of each of the transistors, the semiconductor layer contacting each of the source electrodes and each of the drain electrodes, and a channel between the source electrode and the drain electrode of the same transistor is a horizontal channel; In step 1805, a gate insulating layer and a metal thin film are sequentially deposited in the through hole, the metal thin film filling the through hole in the gate insulating layer to form the word line, and the gate electrode of the transistor in a different layer is part of the word line.

[0154] After alternately depositing the insulating thin films and the metal thin films as described above, a plurality of insulating thin films and metal thin films are formed, with the insulating thin film being the thin film farthest from the substrate.

[0155] In one exemplary embodiment, before depositing a metal thin film in the passages consisting of the first passage, the second passage, and the through-hole, further sequentially depositing a semiconductor thin film and a gate insulating thin film on sidewalls of the first via, the second via, and the via formed of the through hole; Etching the metal thin film in the through hole includes etching the gate insulating thin film and the metal thin film in the through hole.

[0156] The above manufacturing process can refer to the manufacturing process of the transistor in the above embodiment, and the processing of the multiple metal thin films may be the same as the processing of the metal thin films in the manufacturing process of the above transistor, and will not be repeated here.

[0157] In the 3D memory fabrication method according to this embodiment, by providing source and drain contact regions in the semiconductor layers of the fabricated 3D memory, the channel direction between the source and drain electrodes generally extends parallel to the substrate, which is advantageous for realizing a 3D stacked memory with a simple structure and relatively easy fabrication. Furthermore, the gate electrodes of the transistors in each stack can be shared as word lines, which saves space for vertically extending word lines. Furthermore, the 3D memory according to this embodiment allows the channel size to be changed by adjusting the thickness of the source or drain electrodes, which simplifies the process and has little impact on the device size.

[0158] As shown in FIG. 19 , an embodiment of the present disclosure provides a method for manufacturing a 3D memory, the 3D memory including a memory unit and a word line stacked in multiple layers in a direction perpendicular to a substrate, the memory unit may include one transistor, and the transistor may include a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding a sidewall of the gate electrode, and the manufacturing method may include the following steps 1901 to 1904: Step 1901: prepare a substrate; sequentially and alternately deposit a plurality of insulating thin films and a plurality of metal thin films on the substrate; and pattern the deposited layers to form a plurality of stacked structures, each of which includes a stack of alternating insulating layers and metal layers, each of which corresponds to one transistor in one of the memory units, and each of which includes a first sub-part and a second sub-part connected to each other; Step 1902 includes etching the stacked structure to form a through-hole that penetrates the stacked structure in a direction perpendicular to the substrate, forming a source electrode by etching a first sub-portion, and forming a drain electrode by etching a second sub-portion; Step 1903: sequentially depositing semiconductor thin films on the sidewalls of the through-holes to form semiconductor layers, the semiconductor layers contacting each of the source electrodes and each of the drain electrodes, and the length direction of a channel between the source electrode and the drain electrode in the same transistor is parallel to the substrate; In step 1904, a gate insulating layer and a metal thin film are sequentially deposited in the through hole, the metal thin film filling the through hole in the gate insulating layer to form the word line, and the gate electrode of the transistor in a different layer is part of the word line.

[0159] The manufacturing method of the 3D memory according to the embodiment of the present disclosure is advantageous for realizing a 3D stacked memory with a simple structure and relatively easy fabrication, and the 3D memory according to the embodiment can change the channel size by adjusting the thickness of the source electrode or the drain electrode, which is a simple process and has a small impact on the transistor size. The manufacturing method of the embodiment of the present disclosure can be realized using existing mature manufacturing equipment, requires only small changes to the existing process, has good compatibility with the existing manufacturing process, is simple to realize and easy to implement, has high production efficiency, low production cost, and high yield rate.

[0160] An embodiment of the present disclosure provides a method for manufacturing a 3D memory, the 3D memory comprising: a plurality of memory units stacked in multiple layers in a direction perpendicular to a substrate; and one word line; The storage unit includes a transistor, the transistor including a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode, and the manufacturing method of the 3D memory includes: providing a substrate; sequentially and alternately depositing and patterning a plurality of insulating thin films and a plurality of conductive thin films on the substrate to form a plurality of stacked structures spaced apart in a direction parallel to the substrate, each stacked structure including a stack of insulating layers and conductive layers alternately arranged in a direction perpendicular to the substrate, each conductive layer corresponding to one transistor in one of the memory units, each conductive layer including a first sub-portion and a second sub-portion connected to each other; etching the stacked structure to form through-holes penetrating the stacked structure in a direction perpendicular to the substrate, sidewalls of the through-holes exposing the first sub-portions, second sub-portions of each of the conductive layers and the insulating layer; etching each of the first sub-portions in the through-holes to form a plurality of first vias corresponding to a plurality of transistors; etching each of the second sub-portions in the through-holes to form a plurality of second vias corresponding to a plurality of transistors, each of the first vias and each of the second vias being spaced apart and penetrating the through-hole; depositing a metal thin film in each of the first passages, each of the second passages, and each of the through-holes, and etching the metal thin film to remove the metal thin film in the through-holes, leaving a metal film layer in each of the first passages and each of the second passages, thereby forming a plurality of source electrodes located in each of the first passages and a plurality of drain electrodes located in each of the second passages; a semiconductor thin film is filled on a side wall of the through hole to form a semiconductor layer of each of the transistors, the semiconductor layer contacts each of the source electrodes and each of the drain electrodes, and a channel between the source electrode and the drain electrode of the same transistor is a horizontal channel; The method may further include sequentially depositing a gate insulating layer and a metal thin film in the through hole, the metal thin film filling the through hole in the gate insulating layer to form the word line, and the gate electrode of the transistor in a different layer being part of the word line.

[0161] Although the embodiments disclosed in the present disclosure are as above, the contents of the description are merely embodiments adopted for understanding the present disclosure and are not intended to limit the present disclosure. Those skilled in the art may make modifications and changes in the implementation form and details without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present disclosure should be in accordance with the scope described in the claims.

Claims

1. A 3D memory comprising: a substrate; memory units stacked in a plurality of layers in a direction perpendicular to the substrate; and word lines, the word lines extending in a direction perpendicular to the substrate and penetrating the memory units in different layers; the storage unit comprises a transistor, the transistor comprising a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, the semiconductor layer extending on sidewalls of the gate electrode and extending in a direction perpendicular to the substrate, the semiconductor layer comprising a source contact region and a drain contact region spaced apart, and a channel between the source contact region and the drain contact region being a horizontal channel.

2. 2. The 3D memory of claim 1, wherein the source electrodes of transistors in different layers are spaced apart, the drain electrodes of transistors in different layers are spaced apart, and the semiconductor layer is a closed ring shape surrounding the gate electrode.

3. 2. The 3D memory of claim 1, wherein the gate electrodes of transistors in different layers are part of the word lines.

4. A 3D memory as described in claim 1, characterized in that the source electrode and the drain electrode of the same transistor are located in the same conductive film layer, and the source electrode or the drain electrode of a different transistor are located in a different conductive film layer.

5. In a plane parallel to the substrate, the orthogonal projections of the source electrode and the drain electrode of the same transistor do not overlap; 2. The 3D memory of claim 1, wherein in a plane parallel to the substrate, orthogonal projections of source and drain electrodes of different transistors in the same layer do not overlap.

6. 2. The 3D memory of claim 1, wherein the source electrode is located on a first side of the gate electrode, the drain electrode is located on a second side of the gate electrode, and the source electrode and the drain electrode are disposed opposite each other.

7. 7. The 3D memory of claim 1, wherein the semiconductor layers of the transistors of the storage units of different layers are spaced apart in a direction perpendicular to the substrate.

8. 8. The 3D memory of claim 7, further comprising an insulating layer between the semiconductor layers spaced apart, the insulating layer being a gate insulating layer located between the gate electrode and the semiconductor layer.

9. The 3D memory according to any one of claims 1 to 6, wherein two adjacent semiconductor layers in the storage units of different layers are connected in an integral structure.

10. A transistor, the transistor being disposed on a substrate of a memory, comprising: a source electrode disposed on the substrate; a drain electrode; a gate electrode extending in a direction perpendicular to the substrate; and a semiconductor layer surrounding the gate electrode and insulated from the gate electrode, the semiconductor layer extending on sidewalls of the gate electrode and extending in a direction perpendicular to the substrate, the semiconductor layer comprising a source contact region and a drain contact region disposed at a distance from each other, and a channel between the source contact region and the drain contact region being a horizontal channel.

11. 11. The transistor of claim 10, wherein the source electrode and the drain electrode are located in the same conductive film layer, and the conductive film layer is parallel to the substrate.

12. 11. The transistor of claim 10, wherein the material of the semiconductor layer comprises a metal oxide semiconductor material.

13. 11. The transistor of claim 10, wherein in a plane parallel to the substrate, the orthogonal projection of the source electrode and the orthogonal projection of the drain electrode do not overlap.

14. 11. The transistor of claim 10, wherein the source contact region is located on a first side of the semiconductor layer, the drain contact region is located on a second side of the semiconductor layer, the source electrode contacts the source contact region, the drain electrode contacts the drain contact region, and the source electrode and the drain electrode are disposed opposite each other.

15. 11. The transistor of claim 10, wherein the semiconductor layer is a total surrounding type semiconductor layer.

16. A method for manufacturing a 3D memory, the 3D memory comprising a plurality of memory units stacked in a direction perpendicular to a substrate and one word line; The storage unit includes a transistor, the transistor including a source electrode, a drain electrode, a gate electrode extending in a direction perpendicular to the substrate, and a semiconductor layer surrounding the gate electrode, and the manufacturing method of the 3D memory includes: providing a substrate; sequentially and alternately depositing and patterning a plurality of insulating thin films and a plurality of metal thin films on the substrate to form a plurality of stacked structures, each of the stacked structures including a stack of alternating insulating layers and metal layers, each of the metal layers including a first sub-portion and a second sub-portion connected to each other; etching the stacked structure to form through-holes that penetrate the stacked structure in a direction perpendicular to the substrate, with sidewalls of the through-holes exposing the first sub-portions, the second sub-portions of each of the metal layers, and the insulating layer, to form source and drain electrodes; a semiconductor thin film is filled on a side wall of the through hole to form a semiconductor layer of each of the transistors, the semiconductor layer contacts each of the source electrodes and each of the drain electrodes, and a channel between the source electrode and the drain electrode of the same transistor is a horizontal channel; sequentially depositing a gate insulating layer and a metal thin film in the through hole, the metal thin film filling the through hole in the gate insulating layer to form the word line, and the gate electrode of the transistor in a different layer being part of the word line.

17. The method of forming the source electrode and the drain electrode, comprising: etching each first sub-portion within the through-hole to form a first passageway, and etching each second sub-portion within the through-hole to form a second passageway, the first passageway and the second passageway penetrating the through-hole; 17. The method for manufacturing a 3D memory according to claim 16, further comprising: depositing a metal thin film in a passage consisting of the first passage, the second passage, and the through hole; and etching the metal thin film in the through hole.

18. The method of forming the source electrode and the drain electrode, comprising:

17. The method of claim 16, further comprising: overlapping an orthogonal projection of the through-hole with an orthogonal projection of the first sub-portion, overlapping an orthogonal projection of the through-hole with an orthogonal projection of the second sub-portion, and etching the first sub-portion and the second sub-portion, one of which forms a drain electrode and the other of which forms a source electrode.

19. An electronic device, comprising a transistor according to any one of claims 10 to 15.

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