Configurable flash memory physical interface in a host device

Abstract

The flash memory physical interface in the host device can be configured based on a select signal indicating whether the flash memory system is of a first type or a second type. Based on the select signal, either a first differential memory data signal input of the driver circuit or a second differential memory data signal input of the driver circuit can be coupled to a differential data input of the flash memory system. Based on the select signal, a differential data output of the flash memory system can be coupled to either a first differential memory data signal output of the receiver circuit or a second differential memory data signal output of the receiver circuit.

Description

[Technical Field]

[0001] 2. Description of Related Art

[0001] Mobile computing devices such as smartphones typically include one of two types of flash memory systems as their main memory: Universal Flash Storage ("UFS") and Non-Volatile Memory Express ("NVMe"). Accordingly, host processing systems in some mobile computing devices may be configured to interface with UFS, while host processing systems in other mobile computing devices may be configured to interface with NVMe.

[0002]

[0002] A UFS physical layer interface or link between a UFS host and a UFS storage device may conform to a protocol known as M-PHY. The M-PHY interface may include six signal paths (e.g., wires or other conductors). Two of the conductors form a first differential pair configured to carry data from the UFS host to the UFS storage device, and two of the conductors form a second differential pair configured to carry data from the UFS storage device to the UFS host. The remaining two conductors may be configured to carry a clock signal and a reset signal.

[0003]

[0003] The NVMe physical interface or link between a host and an NVMe storage device may conform to a protocol known as Peripheral Component Interconnect Express ("PCIe"). The PCIe interface may include four signal paths (e.g., wires). Two of the conductors form a first differential pair configured to carry data from the host to the NVMe storage device, and two of the conductors form a second differential pair configured to carry data from the NVMe storage device to the host.

[0004] A host device such as a system-on-a-chip ("SoC") may include only one of the above-mentioned types of physical interfaces, depending on the computing device the SoC is included in. For example, a first smartphone may include an SoC that includes UFS as its flash memory and therefore has an M-PHY flash memory physical interface, while a second smartphone may include an SoC that includes NVMe as its flash memory and therefore has a PCIe flash memory physical interface. Summary of the Invention

[0005]

[0005] Systems, methods, computer-readable media, and other examples are disclosed for configuring a flash memory physical interface in a host device.

[0006] An exemplary system for selectively configuring a flash memory physical interface may include a driver circuit and a receiver (buffer) circuit. The driver circuit may have a first differential memory data signal input and a second differential memory data signal input. The driver circuit may also have a driver selector input configured to receive a select signal indicating one of the first and second flash memory types. The driver circuit may be configured to couple the selected one of the first and second differential memory data signal inputs to a differential data input of a flash memory system based on the select signal. The receiver circuit may be coupled to a differential data output of the flash memory system. The receiver circuit may have a receiver selector input configured to receive the select signal. The receiver circuit may also have a first differential memory data signal output and a second differential memory data signal output. The receiver circuit may be configured to couple the differential data output of the flash memory system to the selected one of the first and second differential memory data signal outputs based on the select signal.

[0007] An exemplary method for selectably configuring a flash memory physical interface may include providing a select signal indicating a selected one of a first flash memory type and a second flash memory type. The method may further include coupling, by a driver circuit, one of the first differential memory data signal inputs and the second differential memory data signal inputs to differential data inputs of the flash memory system based on the select signal. The method may further include coupling, by a receiver circuit, a differential data output of the flash memory system to the selected one of the first differential memory data signal output and the second differential memory data signal output based on the select signal.

[0008] Another exemplary system for selectively configuring a flash memory physical interface may include means for providing a select signal indicating a selected one of a first flash memory type and a second flash memory type. The exemplary system may further include means for coupling one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the select signal. The exemplary system may further include means for coupling a differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the select signal.

[0009] An exemplary system-on-chip or "SoC" may include a processing system configured to direct memory transactions to a flash memory system, memory type selection logic, and flash memory physical interface configuration logic. The memory type selection logic may be configured to provide a select signal indicating whether the flash memory system is a first flash memory type or a second flash memory type. The flash memory physical interface configuration logic may include a driver circuit and a receiver (buffer) circuit. The driver circuit may have a first differential memory data signal input and a second differential memory data signal input. The driver circuit may have a driver selector input configured to receive the select signal. The driver circuit may be configured to couple a selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the select signal. The receiver circuit may be coupled to a differential data output of the flash memory system. The receiver circuit may have a receiver selector input configured to receive the select signal. The receiver circuit may have a first differential memory data signal output and a second differential memory data signal output. The receiver circuit may be configured to couple a selected one of the first differential memory data signal output and the second differential memory data signal output to a differential data output of the flash memory system based on a selection signal. [Brief explanation of the drawings]

[0010]

[0010] In the figures, like reference numbers refer to like parts throughout the various figures unless otherwise indicated. In the case of a reference number accompanied by a letter designation such as "101A" or "101B," the letter designation may distinguish between two like parts or elements present in the same figure. When the reference number is intended to encompass all parts having the same reference number in all figures, the letter designation for the reference number may be omitted. [Figure 1]

[0011] FIG. 1 is a block diagram of a system for selectively configuring a flash memory physical interface, according to an example embodiment. [Figure 2]

[0012] FIG. 2 is a block diagram of a flash memory physical interface configuration logic and a configurable impedance matching network, according to an example embodiment. [Figure 3]

[0013] FIG. 10 is a block diagram of a transmit or TX portion of the flash memory physical interface configuration logic, in accordance with an example embodiment. [Figure 4]

[0014] FIG. 2 is a block diagram of an example of a driver circuit, according to an illustrative embodiment. [Figure 5]

[0015] FIG. 10 is a block diagram of another example of a driver circuit, in accordance with an illustrative embodiment. [Figure 6]

[0016] FIG. 10 is a block diagram of the receive or RX portion of the flash memory physical interface configuration logic, according to an example embodiment. [Figure 7]

[0017] FIG. 2 is a block diagram of an example of a receiver circuit or buffer circuit, according to an exemplary embodiment. [Figure 8]

[0018] FIG. 10 is a block diagram of another example of a receiver circuit or buffer circuit, in accordance with an exemplary embodiment. [Figure 9]

[0019] FIG. 2 is a block diagram of a configurable TX impedance network and an RX impedance network in accordance with an example embodiment. [Figure 10]

[0020] FIG. 1 is a block diagram of a configurable clock circuit in accordance with an illustrative embodiment. [Figure 11]

[0021] FIG. 1 is a flow diagram illustrating a method for selectively configuring a flash memory physical interface, according to an example embodiment. [Figure 12]

[0022] FIG. 1 is a block diagram of a portable computing device in accordance with an illustrative embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0023] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "illustrative" may be used herein as a synonym for "exemplary." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012]

[0024] As shown in FIG. 1 , in an exemplary or typical embodiment, system 100 may include host device 102 and flash memory device or system 104. Host device 102 may be, for example, a system-on-chip ("SoC"). Flash memory system 104 may be coupled to the SoC. Although not shown in FIG. 1 for purposes of clarity, host device 102 and flash memory system 104 may be included in a computing device, such as a mobile computing device. In an exemplary embodiment, flash memory system 104 may include one of two types of flash memory: Universal Flash Storage ("UFS") and Non-Volatile Memory Express ("NVMe").

[0013]

[0025] The term "UFS" is used herein to refer to a family of storage access and transport protocols promulgated by the industry consortium JEDEC. One example of such a protocol is UFS Version 4.0 (published as JESD220F UFS 4.0). As will be understood by those of ordinary skill in the art, UFS may use a UFS physical layer interface known as M-PHY. The UFS Version 4.0 protocol may incorporate or reference protocols promulgated by the Mobile Industry Processor Interface ("MIPI") Alliance. UFS Version 4.0 references, for example, the MIPI M-PHY v5.0 physical layer specification and the MIPI UNIPRO v2.0 transport layer specification.

[0014]

[0026] The term "NVMe" is used herein to refer to a family of storage access and transport protocols for flash memory and solid-state storage drives promulgated by the NVMe Workgroup, an industry consortium. As will be understood by those of ordinary skill in the art, the NVMe protocol accesses flash storage over a Peripheral Component Interconnect Express ("PCIe") bus. The host device 102 may include UFS, M-PHY, NVMe, PCIe, etc., functionality for communication between the host device 102 and the flash memory system 104. Such functionality is well understood by those of ordinary skill in the art and will not be described herein.

[0015]

[0027] Regardless of whether flash memory system 104 is UFS or NVMe, the signal paths of the physical interface coupling flash memory system 104 to host device 102 may include differential data output signal paths 106 configured to carry true and complement output data signals Dout_t and Dout_c, respectively, and differential data input signal paths 108 configured to carry true and complement input data signals Din_t and Din_c, respectively. Host device 102 may send data to differential data inputs of flash memory system 104 on differential data output signal paths 106 and receive data from differential data signal outputs of flash memory system 104 on differential data input signal paths 108.

[0016]

[0028] The host device 102 may include flash memory interface configuration logic 110. The flash memory interface configuration logic 110 may have a first data input configured to receive a PCIe data output signal 112 ("PCIe Data Out") and a second data input configured to receive an M-PHY data output signal 114 ("M-PHY Data Out"). The configuration logic 110 may also have a first data output configured to provide a PCIe data input signal 116 (also referred to as "PCIe Data In") and a second data output configured to provide an M-PHY data input signal 118 ("M-PHY Data In"). The PCIe Data Out signal and the M-PHY Data Out signal are configured to provide data that the host device 102 is sending to (i.e., from) the flash memory 104. The PCIe Data In signal path and the M-PHY Data In signal path are configured to receive data from (i.e., into) the flash memory 104. Although the term "data" is used herein for convenience, it should be understood that the "data" communicated between the host device 102 and the flash memory system 104 may include any type of information.

[0017]

[0029] The host device 102 may also include memory type selection logic 120. The memory type selection logic 120 may be configured to provide a selection signal 122 (“Select”) to the flash memory interface configuration logic 110. The selection signal 122 may indicate whether the flash memory 104 is UFS or NVMe. The memory type selection logic 120 may have any of a variety of structures (not shown for clarity). In one example, the memory type selection logic 120 may include an SoC pin hardwired to a voltage, where a first voltage level (e.g., ground) may indicate UFS and a second voltage level (e.g., a positive voltage) may indicate NVMe. In another example, the memory type selection logic 120 may include an impedance, where a first impedance level may indicate UFS and a second impedance level may indicate NVMe. In yet another example, the memory type selection logic 120 may include a fusible link (fuse or eFuse), where a fuse state (i.e., either intact or blown) may indicate either UFS or NVMe. In yet another example, memory type selection logic 120 may include a register into which a bit value indicating either UFS or NVMe may be loaded by a processor. Memory type selection logic 120 may include detector circuitry to detect voltage, impedance, fuse state, bit value, etc., and generate selection signal 122 based on the detection results.

[0018]

[0030] The signal paths of the physical interface coupling the flash memory system 104 to the host device 102 may also include a reference clock signal path 124 and a reset signal path 126. The flash memory 104 may utilize a reference clock signal received on the reference clock signal path 124. The flash memory 104 may utilize a reset signal received on the reset signal path 126. The host device 102 may include a configurable clock circuit 128. The configurable clock circuit 128 may be configurable based on the select signal 122.

[0019]

[0031] 2, system 200 may include flash memory interface configuration logic 202. Flash memory interface configuration logic 202 may be an example of flash memory interface configuration logic 102 (FIG. 1) described above. Flash memory interface configuration logic 202 may include transmit (“TX”) interface configuration logic 204 and receive (“RX”) interface configuration logic 206.

[0020]

[0032] The TX interface configuration logic 204 may have a first data input configured to receive a PCIe data output signal 212 (“PCIe Data Out”) and a second data input configured to receive an M-PHY data output signal 214 (“M-PHY Data Out”). The RX interface configuration logic 206 may have a first data output configured to provide a PCIe data input signal 216 (“PCIe Data In”) and a second data output configured to provide an M-PHY data input signal 218 (“M-PHY Data In”). The TX interface configuration logic 204 and the RX interface configuration logic 206 may each receive a select signal 222.

[0021]

[0033] A data output of TX interface configuration logic 204 may be coupled to a TX impedance matching network 208. The impedance coupled by TX impedance matching network 208 may be controlled or selected based on a select signal 222. Similarly, a data input of RX interface configuration logic 206 may be coupled to an RX impedance matching network 210. The impedance coupled by RX impedance matching network 210 may be controlled or selected based on a select signal 222. Thus, TX impedance matching network 208 may couple a configurable or selectable impedance to a differential data output signal path 224 between flash memory interface configuration logic 202 and a flash memory (not shown in FIG. 2 ). Similarly, RX impedance matching network 210 may couple a configurable or selectable impedance to a differential data input signal path 226 between flash memory interface configuration logic 202 and a flash memory (not shown in FIG. 2 ).

[0022]

[0034] 3 illustrates TX interface configuration logic 300. TX interface configuration logic 300 may be one example of TX interface configuration logic 204 (FIG. 2) described above. TX interface configuration logic 300 may include encoding logic 302, a serializer 304, a multi-level signaling formatter 306, and a driver circuit 308, each of which may have a selector input configured to receive a select signal 310.

[0023]

[0035] The encoding logic 302 may be configured to receive the PCIe data output signal 312 and the M-PHY data output signal 314. For example, the PCIe data output signal 312 and the M-PHY data output signal 314 may be received from a processing unit (not shown). Such a processing unit may comprise a processor, such as a central processing unit ("CPU"), an application processor ("AP"), a graphics processing unit ("GPU"), or other processor that may initiate or control memory transactions. Such a processor may be configured to provide PCIe data (i.e., the PCIe data output signal 312) to the encoding logic 302 via a PCIe bus and M-PHY data (i.e., the M-PHY data output signal 314) via a bus. Alternatively, such a processing unit may be an intermediate component (not shown), such as a peripheral interface block, that receives data from the processor via a bus or other data interconnect. Such a peripheral block may include a processor, a finite state machine, specific hardware, or the like. The peripheral block can format data received from the processor into PCIe or M-PHY format. The peripheral block may be configured to provide PCIe data to the encoding logic 302 over a PCIe bus and also provide M-PHY data over the bus.

[0024]

[0036] The encoding logic 302 may include PCIe-specific encoding logic 316, M-PHY-specific encoding logic 318, and common (to both PCIe and M-PHY) encoding logic 320. The encoding logic 302 encodes PCIe output data and M-PHY output data according to the PCIe and M-PHY protocols, respectively. Because such encoding logic 316-320 is well understood by those of ordinary skill in the art, these elements will not be described in further detail herein.

[0025]

[0037] The encoding logic 302 can provide encoded output data to a serializer 304, which can convert the encoded output data from a parallel format to a serial format. The serializer 304 can provide the resulting serial format data to a multi-level signaling formatter 306. The multi-level signaling formatter 306 can convert its input signal from a serial format to pulse-width modulation (PWM), pulse-amplitude modulation (PAM), such as PAM-3, PAM-4, or any combination thereof. The multi-level signaling formatter 306 can provide PCIe differential data output signals (including a true signal PCIe Dout_t and a complementary signal PCIe Dout_c) and M-PHY differential data output signals (including a true signal M-PHY Dout_t and a complementary signal M-PHY Dout_c) to the driver circuit 308. As described below, the driver circuit 308 may provide a differential data output signal 322 selected from either a PCIe differential memory data signal or an M-PHY differential memory data signal based on the select signal 310.

[0026]

[0038] FIG. 4 illustrates a driver circuit 400. The driver circuit 400 may be an example of the driver circuit 308 (FIG. 3) described above. The driver circuit 400 may include a first tri-state differential driver 402 and a second tri-state differential driver 404. The first tri-state differential driver 402 may receive a PCIe differential data output signal 406, and the second tri-state differential driver 404 may receive an M-PHY differential data output signal 408. The outputs of the first tri-state differential driver 402 and the second tri-state differential driver 404 are coupled to each other to provide a differential data output including a Dout_t signal and a Dout_c signal. The first tri-state differential driver 402 and the second tri-state differential driver 404 may operate in a complementary manner with respect to each other in response to a select signal 410. That is, when the select signal 410 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), the second tri-state differential driver 404 drives its output to high impedance while the first tri-state differential driver 402 drives its output to provide a PCIe differential data output signal. Conversely, when the select signal 410 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), the first tri-state differential driver 402 drives its output to high impedance while the second tri-state differential driver 404 drives its output to provide an M-PHY differential data output signal.

[0027]

[0039] Drivers 402 and 404 can drive their respective signals using respective voltage levels. A first voltage level (“V1”) may be provided to the first driver 402, and a second voltage level (“V2”) may be provided to the second driver 404. Thus, when the physical interface protocol is PCIe, driver 402 drives the differential data outputs (including the Dout_t and Dout_c signals) at the first voltage level, and when the physical interface protocol is M-PHY, driver 404 drives the differential data outputs at the second voltage level.

[0028]

[0040] 5 illustrates a driver circuit 500. The driver circuit 500 may be another example of the driver circuit 308 (FIG. 3) described above. The driver circuit 500 and the driver circuit 400 (FIG. 4) described above may be alternatives to each other. The driver circuit 500 may include a differential mode signal multiplexer (“MUX”) 502 configured to select either a PCIe differential data output signal 504 or an M-PHY differential data output signal 506 in response to a select signal 508. A pair of drivers 510 and 512 may receive the output of the differential mode signal MUX 502 and provide differential data outputs including Dout_t and Dout_c signals.

[0029]

[0041] Drivers 510 and 512 may drive their respective signals using voltage levels provided by power rail selector 514. Power rail selector 514 may provide either a first voltage level (“V1”) or a second voltage level (“V2”) in response to select signal 508. For example, when select signal 508 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), power rail selector 514 may provide the first voltage level, and when select signal 508 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), power rail selector 514 may provide the second voltage level.

[0030]

[0042] 6 illustrates RX interface configuration logic 600. RX interface configuration logic 600 may be an example of the RX interface configuration logic 206 (FIG. 2) described above. RX interface configuration logic 600 may include a buffer circuit (also called a receiver circuit) 608, a multi-level signaling deformatter 606, a parallelizer or deserializer 604, and decoding logic 602, each of which may have a selector input configured to receive a selection signal 610.

[0031]

[0043] The receiver or buffer circuit 608 may receive a differential data output signal 622, which may be either a PCIe differential data output signal or an M-PHY differential data output signal. The buffer circuit 608 provides the PCIe differential data output signal or the M-PHY differential data output signal to the multi-level signaling deformatter 606.

[0032]

[0044] The multi-level signaling deformatter 606 may convert its input signal from PWM, PAM, etc. to a serial format. The output of the multi-level signaling deformatter 606 may be provided to a deserializer 604, which may convert the data from serial format to parallel format. The deserializer 604 may provide the resulting parallel format data to the decoding logic 602. In some examples, the output of the multi-level signaling deformatter 606 may also be provided to clock-data recovery (“CDR”) logic 612. The CDR logic 612 may recover a clock signal from the data signal. The host device can use the recovered clock signal to further process the data.

[0033]

[0045] The decoding logic 602 may be configured to decode data, which may be either PCIe data or M-PHY data. The decoding logic 602 may include PCIe-specific decoding logic 616, M-PHY-specific decoding logic 618, and common (for both PCIe and M-PHY) decoding logic 620. The decoding logic 602 decodes PCIe data and M-PHY data according to the PCIe and M-PHY protocols, respectively. Because such decoding logic 616-620 is well understood by those of ordinary skill in the art, these elements will not be described in further detail herein. Outputs of the decoding logic 602 may include a PCIe data input signal 624 (“PCIe Data In”) and an M-PHY data input signal 626 (“M-PHY Data In”).

[0034]

[0046] The decode logic 602 may provide a PCIe data input signal 624 and an M-PHY data input signal 626 to a processing unit (not shown) of the type described above with respect to FIG. 3. The processing unit to which the decode logic 602 provides the PCIe data input signal 624 may be the same processing unit to which the encoding logic 302 (FIG. 3) receives the PCIe data output signal 312, or may be a different processing unit. The processing unit to which the decode logic 602 provides the M-PHY data input signal 626 may be the same processing unit to which the encoding logic 302 receives the M-PHY data output signal 314, or may be a different processing unit. The PCIe data may be provided to the processing unit via a PCIe bus, and the M-PHY data may similarly be provided via a bus.

[0035]

[0047] FIG. 7 illustrates a receiver or buffer circuit 700. The buffer circuit 700 may be an example of the buffer circuit 608 (FIG. 6) described above. The buffer circuit 700 may include a first differential mode buffer 702 and a second differential mode buffer 704. The buffers 702 and 704 may be tri-state buffers. The first buffer 702 and the second buffer 704 may each receive a differential data input including a Din_t signal and a Din_c signal. The buffers 702 and 704 may drive their respective signals using respective voltage levels. A first voltage level (“V1”) may be provided to the first buffer 702, and a second voltage level (“V2”) may be provided to the second buffer 704. Thus, when the physical interface protocol is PCIe, the first buffer 702 may drive the PCIe differential data input signal 706 at a first voltage level, and when the physical interface protocol is M-PHY, the second buffer 704 may drive the M-PHY differential data input signal 708 at a second voltage level.

[0036]

[0048] In examples where buffers 702 and 704 are tri-state buffers, buffers 702 and 704 may operate in a complementary manner relative to one another in response to select signal 710. That is, when select signal 710 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), the second buffer 704 sets its output to high impedance, while the first buffer 702 drives its output to provide the PCIe differential data input signal. Conversely, when select signal 710 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), the first buffer 702 sets its output to high impedance, while the second buffer 704 drives its output to provide the M-PHY differential data input signal.

[0037]

[0049] 8 illustrates a receiver or buffer circuit 800. The buffer circuit 800 may be another example of the buffer circuit 608 (FIG. 6) described above. The buffer circuit 800 and the driver circuit 700 (FIG. 7) described above may be alternatives to each other. The buffer circuit 800 may include a differential mode signal de-multiplexer ("DEMUX") 802 configured to provide a PCIe differential data output signal 804 or an M-PHY differential data output signal 806 in response to a select signal 808.

[0038]

[0050] A pair of buffers 810 and 812 can receive differential data inputs including a Din_t signal and a Din_c signal. The buffers 810 and 812 can receive their respective signals using reference voltage levels provided by a power rail selector 814 (e.g., by setting a signal detection threshold level). The power rail selector 814 can provide either a first reference voltage level (“V1”) or a second reference voltage level (“V2”) in response to a select signal 808. For example, when the select signal 808 indicates that the memory is NVMe (i.e., the physical interface protocol is PCIe), the power rail selector 814 can provide the first reference voltage level, and when the select signal 808 indicates that the memory is UFS (i.e., the physical interface protocol is M-PHY), the power rail selector 814 can provide the second reference voltage level. When receiving data, the buffers 810 and 812 can compare the differential data inputs including the Din_t and Din_c signals with the selected reference voltage levels.

[0039]

[0051] 9 shows a TX impedance network 902 and an RX impedance network 904. The TX impedance network 902 and the RX impedance network 904 may be examples of the TX impedance matching network 208 and the RX impedance matching network 210 (FIG. 2) described above.

[0040]

[0052] The TX impedance network 902 may include a first impedance 906, a second impedance 908, a third impedance 910, and a fourth impedance 912. The RX impedance network 904 may include a fifth impedance 914, a sixth impedance 916, a seventh impedance 918, an eighth impedance 920, and a ninth impedance 922.

[0041]

[0053] The first impedance 906 may be in the Dout_t signal path between the input and output sides of the TX impedance network 902. The second impedance 908 may be in the Dout_c signal path between the input and output sides of the TX impedance network 902. The third impedance 910 may be in the Dout_c signal path between the input side of the TX impedance network 902 and ground. The fourth impedance 912 may be in the Dout_t signal path between the input side of the TX impedance network 902 and ground. The first impedance 906 and the second impedance 908 may have the same impedance value Z1. The third impedance 910 and the fourth impedance 912 may have the same impedance value Z2. Each of the first impedance 906, the second impedance 908, the third impedance 910, and the fourth impedance 912 may have a control input configured to receive a select signal 913. Each of the first impedance 906, the second impedance 908, the third impedance 910, and the fourth impedance 912 can change the values ​​of Z1 and Z2 in response to a select signal 913. For example, the combination of the first impedance 906, the second impedance 908, the third impedance 910, and the fourth impedance 912 can assume a first impedance configuration in response to a select signal 913 indicating a PCIe physical interface type and can assume a second impedance configuration in response to a select signal 913 indicating an M-PHY physical interface type.

[0042]

[0054] A fifth impedance 914 may be in the Din_t signal path between the input and output sides of the RX impedance network 904. A sixth impedance 916 may be in the Din_c signal path between the input and output sides of the RX impedance network 904. A seventh impedance 918 may be in the Din_c signal path between the input side of the RX impedance network 904 and ground. An eighth impedance 920 may be in the Din_t signal path between the input side of the RX impedance network 904 and ground. A ninth impedance 922 may span the Din_t and Din_c signal paths on the input side of the input impedance network 902. The fifth impedance 914 and the sixth impedance 916 may have an impedance value Z1. The seventh impedance 918 and the eighth impedance 922 may have an impedance value Z2. The ninth impedance 922 may have yet another impedance value Z3. Each of the fifth impedance 914, the sixth impedance 916, the seventh impedance 918, the eighth impedance 920, and the ninth impedance 922 may have a control input configured to receive the select signal 913. Each of the fifth impedance 914, the sixth impedance 916, the seventh impedance 918, the eighth impedance 920, and the ninth impedance 922 may change the values ​​of Z1, Z2, and Z3 in response to the select signal 913. For example, the combination of the fifth impedance 914, the sixth impedance 916, the seventh impedance 918, the eighth impedance 920, and the ninth impedance 922 may assume a third impedance configuration in response to the select signal 913 indicating a PCIe physical interface type and may assume a fourth impedance configuration in response to the select signal 913 indicating an M-PHY physical interface type.

[0043]

[0055] FIG. 10 illustrates a configurable clock circuit 1000. The configurable clock circuit 1000 may be an example of the configurable clock circuit 128 (FIG. 1) described above. The configurable clock circuit 1000 may include a differential driver 1002, a first level shifter 1004, a first clock buffer 1006, a single-ended driver 1008, a second level shifter 1010, a second clock buffer 1012, a clock MUX 1014, and a phase-locked loop (PLL) 1016. The differential mode driver 1002 may receive differential mode clock signals (“Clock” and its complement “Clock_N”). The single-ended driver 1008 may receive a Clock signal. An output of the differential driver 1002 may be provided to an input of the first level shifter 1004. An output of the first level shifter 1004 may be provided to an input of the first clock buffer 1006. The output of the first clock buffer 1006 may be provided to a first input of a clock MUX 1014. The output of the single-ended driver 1008 may be provided to an input of a second level shifter 1010. The output of the second level shifter 1010 may be provided to an input of a second clock buffer 1012. The output of the second clock buffer 1012 may be provided to a second input of the clock MUX 1014. The clock MUX 1014 may have a selector input configured to receive a select signal 1018. In response to the select signal 1018, the clock MUX 1014 may select as its output either a differential clock signal (processed by the differential driver 1002, the first level shifter 1004, and the first clock buffer 1006) or a single-ended clock signal (processed by the single-ended driver 1008, the second level shifter 1010, and the second clock buffer 1012). The output of clock MUX 1014 (i.e., the selected clock signal) may be provided to PLL 1016. The output of PLL 1016 may serve as reference clock signal 1020, as described above with respect to reference clock signal 124 (FIG. 1).

[0044]

[0056] 11 illustrates, in block diagram form, a method 1100 for selectably configuring a flash memory physical interface. As indicated by block 1102, method 1100 may include providing a select signal indicating a selected one of a first flash memory type and a second flash memory type. As indicated by block 1104, method 1100 may also include coupling, by the driver circuit, one of the first differential memory data signal input of the driver circuit and the second differential memory data signal input of the driver circuit to differential data inputs of the flash memory system based on the select signal. As indicated by block 1106, method 1100 may further include coupling, by the receiver circuit, a differential data output of the flash memory system to a selected one of the first differential memory data signal output of the receiver circuit and the second differential memory data signal output of the receiver circuit based on the select signal.

[0045]

[0057] 12 illustrates an example portable computing device ("PCD") 1200 in which illustrative embodiments of systems, methods, computer-readable media, and other examples for selectably configuring a flash memory physical interface may be provided. The PCD 1200 may be, for example, a laptop or palmtop computer, a mobile phone or smartphone, a personal digital assistant, a navigation device, a smartbook, a portable game console, a satellite phone, etc. For clarity, some data buses, interconnects, signals, etc. are not shown in FIG. 12. For example, a PCIe bus is not shown, but may be included and configured to interconnect various processing systems, memories, etc., as will be understood by those of ordinary skill in the art.

[0046]

[0058] PCD 1200 may include SoC 1202. SoC 1202 may include CPU 1204, GPU 1206, digital signal processor ("DSP") 1207, analog signal processor 1208, modem / modem subsystem 1254, or other processor. CPU 1204 may include one or more CPU cores, such as a first CPU core 1204A, a second CPU core 1204B, etc., up to an Nth CPU core 1204N.

[0047]

[0059] The display controller 1210 and the touchscreen controller 1212 may be coupled to the CPU 1204. A touchscreen display 1214 external to the SoC 1202 may be coupled to the display controller 1210 and the touchscreen controller 1212. The PCD 1200 may further include a video decoder 1216 coupled to the CPU 1204. A video amplifier 1218 may be coupled to the video decoder 1216 and the touchscreen display 1214. A video port 1220 may be coupled to the video amplifier 1218. A universal serial bus ("USB") controller 1222 may also be coupled to the CPU 1204, and a USB port 1224 may be coupled to the USB controller 1222. A subscriber identity module ("SIM") card 1226 may also be coupled to the CPU 1204.

[0048]

[0060] The CPU 1204 may be coupled to one or more memories with which the CPU 1204 may initiate memory transactions. The one or more memories may include both volatile and non-volatile memory or NVM. Examples of volatile memory include static random access memory ("SRAM") 1228 and dynamic random access memory ("DRAM") 1230. Such memory may be internal to the SoC 1202, as in the illustrated embodiment, or may be external to the SoC 1202. A DRAM controller 1229 coupled to the CPU 1204 may control the writing of data to and reading of data from the DRAM 1230.

[0049]

[0061] The one or more memories may also include flash memory 1231. Flash memory 1231 may be NVMe or UFS. Flash memory controller 1229, coupled to CPU 1204, may control aspects of writing data to and reading data from flash memory 1231. In examples where flash memory 1231 is NVMe, some or all of the NVMe controller functionality may be included within flash memory 1231, which may be coupled to CPU 1204 via a PCIe bus (not shown).

[0050]

[0062] Flash memory interface configuration logic 1233 may be coupled to a path between flash memory controller 1229 and flash memory 1231. Flash memory interface configuration logic 1233 may be an example of flash memory interface configuration logic 110 (FIG. 1) or 202 (FIG. 2) described above. Although not shown in FIG. 12 for clarity, flash memory interface configuration logic 1233 may be coupled to a source of the select signal described above that indicates whether flash memory 1231 is NMVe or UFS.

[0051]

[0063] A stereo audio codec 1234 may be coupled to the analog signal processor 1208. Further, an audio amplifier 1236 may be coupled to the stereo audio codec 1234. A first stereo speaker 1238 and a second stereo speaker 1240 may each be coupled to the audio amplifier 1236. Additionally, a microphone amplifier 1242 may be coupled to the stereo audio codec 1234, and a microphone 1244 may be coupled to the microphone amplifier 1242. A frequency modulation ("FM") radio tuner 1246 may be coupled to the stereo audio codec 1234. An FM antenna 1248 may be coupled to the FM radio tuner 1246. Further, stereo headphones 1250 may be coupled to the stereo audio codec 1234. Other devices that may be coupled to the CPU 1204 include one or more digital (e.g., CCD or CMOS) cameras 1252.

[0052]

[0064] A modem or RF transceiver 1254 may be coupled to the analog signal processor 1208 and the CPU 1204. An RF switch 1256 may be coupled to the RF transceiver 1254 and the RF antenna 1258. Additionally, a keypad 1260, a mono headset with microphone 1262, and a vibration device 1264 may be coupled to the analog signal processor 1208.

[0053]

[0065] The SoC 1202 may have one or more internal or on-chip thermal sensors 1270A and may be coupled to one or more external or off-chip thermal sensors 1270B. An analog-to-digital converter controller 1272 can convert the voltage drops generated by the thermal sensors 1270A and 1270B into digital signals. A power supply 1274 and a power management integrated circuit (“PMIC”) 1276 can provide power to the SoC 1202.

[0054]

[0066] The firmware or software may be stored in any of the memories described above, such as DRAM 1230, flash memory 1231, SRAM 1228, or may be stored in local memory directly accessible by the processor hardware on which the software or firmware executes. Execution of such firmware or software may control aspects of any of the methods described above or may constitute aspects of any of the systems described above. Any such memory or other temporary storage medium having firmware or software stored therein in computer-readable form for execution by the processor hardware may be an example of a "computer-readable medium" as that term is understood in patent vocabulary.

[0055]

[0067] Example implementations are described in the following numbered clauses.

[0068] Clause 1. A system for selectively configuring a flash memory physical interface, comprising:

[0069] a driver circuit having a first differential memory data signal input and a second differential memory data signal input, the driver circuit having a driver selector input configured to receive a select signal indicative of a selected one of the first flash memory type and the second flash memory type, the driver circuit configured to couple the selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the select signal;

[0070] a receiver circuit having a receiver selector input coupled to a differential data output of a flash memory system and configured to receive a selection signal, the receiver circuit having a first differential memory data signal output and a second differential memory data signal output, the receiver circuit being configured to couple the differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the selection signal; A system comprising:

[0071] Clause 2. The driver circuit

[0072] a first tri-state differential driver coupled to the first differential memory data signal input;

[0073] a second tri-state differential driver coupled to the second differential memory data signal input, the output of the first tri-state differential driver and the output of the second tri-state differential driver being coupled together; 2. The system of claim 1, comprising:

[0074] Clause 3. The system of clause 1, wherein the driver circuit comprises a differential signal multiplexer.

[0075] Clause 4. The system of any of clauses 1 to 3, wherein the first flash memory type is Universal Flash Storage (“UFS”) and the second flash memory type is Non-Volatile Memory Express (“NVMe”).

[0076] Article 5.

[0077] encoding logic configured to encode output data for transmission to the flash memory system via the driver circuit, the encoding logic including M-PHY encoding logic and Peripheral Component Interconnect Express ("PCIe") encoding logic, the M-PHY encoding logic configured to encode the output data using an M-PHY protocol, and the PCIe encoding logic configured to encode the output data using the PCIe protocol;

[0078] decode logic configured to decode input data received from the flash memory system via the receiver circuit, the decode logic comprising M-PHY decode logic and PCIe decode logic, the M-PHY decode logic configured to decode the input data using the M-PHY protocol, and the PCIe decode logic configured to decode the input data using the PCIe protocol; 5. The system of any of clauses 1 to 4, further comprising:

[0079] Article 6.

[0080] serializer logic configured to receive the parallel output data from the encoding logic and convert the parallel output data into serial output data;

[0081] deserializer logic configured to receive serial input data from the receiver circuit and convert the serial input data into parallel input data; 6. The system of clause 5, further comprising:

[0082] Article 7.

[0083] a configurable transmit impedance network coupled to the differential data outputs of the driver circuit and the differential data inputs of the flash memory system, the configurable transmit impedance network configured to provide a selected one of a first impedance configuration and a second impedance configuration based on a selection signal;

[0084] a configurable receiver impedance network coupled to the differential data inputs of the receiver circuit and the differential data outputs of the flash memory system, the configurable receiver impedance network configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on a selection signal; 7. The system of any of clauses 1 to 6, further comprising:

[0085] Clause 8. The system described in any of clauses 1 to 7, further comprising a clock signal circuit configured to select one of the first clock signal and the second clock signal based on the selection signal and provide the selected clock signal to the flash memory system.

[0086] Clause 9. The system of any of clauses 1 to 8, wherein the system is included in a system-on-chip ("SoC"), the SoC including at least one processing system configured to initiate memory transactions with the flash memory system.

[0087] Clause 10. A method for selectively configuring a flash memory physical interface, comprising:

[0088] providing a selection signal indicating a selected one of the first flash memory type and the second flash memory type;

[0089] coupling, by the driver circuit, one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on a select signal;

[0090] coupling, by the receiver circuit, a differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on a selection signal; A method comprising:

[0091] Clause 11. The method of clause 10, wherein the first flash memory type is Universal Flash Storage (“UFS”) and the second flash memory type is Non-Volatile Memory Express (“NVMe”).

[0092] Article 12.

[0093] encoding output data for transmission to the flash memory system via a driver circuit, the encoding including encoding the output data using an M-PHY protocol and encoding the output data using a Peripheral Component Interconnect Express ("PCIe") protocol;

[0094] decoding input data received from the flash memory system via the receiver circuit, the decoding including decoding the input data using an M-PHY protocol and decoding the input data using a PCIe protocol; 12. The method of clause 10 or 11, further comprising:

[0095] Article 13.

[0096] converting the encoded parallel output data into serial output data;

[0097] converting serial input data from a receiver circuit to parallel input data; 13. The method of clause 12, further comprising:

[0098] Article 14.

[0099] coupling, by a configurable output impedance network, one of a first impedance configuration and a second impedance configuration to differential data outputs of the driver circuit and differential data inputs of the flash memory system based on a select signal;

[0100] coupling, by a configurable output impedance network, one of the third impedance configuration and the fourth impedance configuration to the differential data inputs of the receiver circuit and the differential data outputs of the flash memory system based on a selection signal; 14. The method of any of clauses 10 to 13, further comprising:

[0101] Article 15.

[0102] selecting one of the first clock signal and the second clock signal based on a selection signal;

[0103] providing a selected clock signal to a flash memory system; 15. The method of any of clauses 10 to 14, further comprising:

[0104] Clause 16. A system for selectively configuring a flash memory physical interface, comprising:

[0105] means for providing a selection signal indicative of a selected one of the first flash memory type and the second flash memory type;

[0106] first means for coupling one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on a select signal;

[0107] second means for coupling a differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on a select signal; A system comprising:

[0108] Clause 17. The system of clause 16, wherein the first flash memory type is Universal Flash Storage (“UFS”) and the second flash memory type is Non-Volatile Memory Express (“NVMe”).

[0109] Article 18.

[0110] means for encoding output data for transmission to a flash memory system via differential data outputs, the means including means for encoding the output data using an M-PHY protocol and means for encoding the output data using a Peripheral Component Interconnect Express ("PCIe") protocol;

[0111] means for decoding input data received from a flash memory system via a differential data input, the means including means for decoding the input data using an M-PHY protocol and means for decoding the input data using a PCIe protocol; 18. The system of clause 16 or 17, further comprising:

[0112] Article 19.

[0113] means for converting the encoded parallel output data into serial output data;

[0114] means for converting the serial input data from the first means for combining into parallel input data; 19. The system of clause 18, further comprising:

[0115] Article 20.

[0116] means for coupling one of the first impedance configuration and the second impedance configuration to the differential data outputs of the driver circuit and the differential data inputs of the flash memory system based on a select signal;

[0117] means for coupling one of the third impedance configuration and the fourth impedance configuration to the differential data inputs of the second means for coupling and to the differential data outputs of the flash memory system based on a selection signal; 20. The system of any of clauses 16 to 19, further comprising:

[0118] Clause 21. A system according to any of clauses 16 to 20, further comprising means for selecting one of the first clock signal and the second clock signal based on a selection signal.

[0119] Clause 22. A system on a chip ("SoC"),

[0120] a processing system configured to direct memory transactions to a flash memory system;

[0121] memory type selection logic configured to provide a selection signal indicating whether the flash memory system is a first flash memory type or a second flash memory type;

[0122] a flash memory physical interface configuration logic,

[0123] a driver circuit having a first differential memory data signal input and a second differential memory data signal input, the driver circuit having a driver selector input configured to receive a select signal, the driver circuit configured to couple a selected one of the first differential memory data signal input and the second differential memory data signal input to a differential data input of the flash memory system based on the select signal;

[0124] a receiver circuit having a receiver selector input coupled to a differential data output of a flash memory system and configured to receive a selection signal, the receiver circuit having a first differential memory data signal output and a second differential memory data signal output, the receiver circuit being configured to couple the differential data output of the flash memory system to a selected one of the first differential memory data signal output and the second differential memory data signal output based on the selection signal; a flash memory physical interface configuration logic comprising: SoC equipped with.

[0125] Clause 23. The selection logic may be a processor-configurable register, a fuse, a voltage detector responsive to a predetermined voltage level indicative of a flash memory type, or an impedance detector responsive to a predetermined impedance level indicative of a flash memory type; 23. The SoC of claim 22, comprising at least one of:

[0126] Clause 24. The driver circuit

[0127] a first tri-state differential driver coupled to the first differential memory data signal input;

[0128] a second tri-state differential driver coupled to the second differential memory data signal input, the output of the first tri-state differential driver and the output of the second tri-state differential driver being coupled together; 24. The SoC of clause 22 or 23, comprising:

[0129] Clause 25. The SoC of clause 22 or 23, wherein the driver circuit comprises a differential signal multiplexer.

[0130] Clause 26. The SoC of any of clauses 22 to 25, wherein the first flash memory type is Universal Flash Storage (“UFS”) and the second flash memory type is Non-Volatile Memory Express (“NVMe”).

[0131] Article 27.

[0132] encoding logic comprising M-PHY encoding logic and Peripheral Component Interconnect Express ("PCIe") encoding logic, wherein the M-PHY encoding logic is configured to encode output data using an M-PHY protocol and the PCIe encoding logic is configured to encode output data using the PCIe protocol;

[0133] decoding logic comprising M-PHY decoding logic and PCIe decoding logic, wherein the M-PHY decoding logic is configured to decode input data using an M-PHY protocol and the PCIe decoding logic is configured to decode input data using a PCIe protocol; 27. The SoC of any of clauses 22 to 26, further comprising:

[0134] Article 28.

[0135] serializer logic configured to receive the parallel output data from the encoding logic and convert the parallel output data into serial output data;

[0136] deserializer logic configured to receive serial input data from the receiver circuit and convert the serial input data into parallel input data; 28. The SoC of clause 27, further comprising:

[0137] Article 29.

[0138] a configurable transmit impedance network coupled to the differential data outputs of the driver circuit and the differential data inputs of the flash memory system, the configurable transmit impedance network configured to provide a selected one of a first impedance configuration and a second impedance configuration based on a selection signal;

[0139] a configurable receiver impedance network coupled to the differential data inputs of the receiver circuit and the differential data outputs of the flash memory system, the configurable receiver impedance network configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on a selection signal; 29. The SoC of any of clauses 22 to 28, further comprising:

[0140] Clause 30. The SoC described in any of clauses 22 to 29, further comprising a clock signal circuit configured to select one of the first clock signal and the second clock signal based on the selection signal and provide the selected clock signal to the flash memory system.

[0056]

[0141] Alternative embodiments will be apparent to those skilled in the art to which the invention pertains. Thus, while selected aspects have been shown and described in detail, it will be understood that various substitutions and modifications may be made thereto.

Claims

1. A system for selectively configuring the physical interface of flash memory, A memory type selection logic configured to provide a selection signal indicating whether the flash memory system is a first flash memory type or a second flash memory type, wherein the first flash memory type comprises M-PHY flash memory and the second flash memory type comprises Peripheral Component Interconnect Express (PCIe) flash memory, Flash memory physical interface configuration logic, A driver circuit having a first differential memory data signal input and a second differential memory data signal input, wherein the driver circuit has a driver selector input configured to receive a selection signal from the memory type selection logic indicating the selected one of the first flash memory type and the second flash memory type, and the driver circuit is configured to couple the selected one of the first differential memory data signal input and the second differential memory data signal input to the differential data input of a flash memory system based on the selection signal, A receiver circuit having a receiver selector input coupled to the differential data output of the flash memory system and configured to receive the selection signal from the memory type selection logic, wherein the receiver circuit has a first differential memory data signal output and a second differential memory data signal output, and the receiver circuit is configured to couple the differential data output of the flash memory system to one of the first differential memory data signal output and the second differential memory data signal output, based on the selection signal received from the memory type selection logic, A flash memory physical interface configuration logic comprising, A system that includes these features.

2. The aforementioned driver circuit A first tristate differential driver coupled to the first differential memory data signal input, A second tristate differential driver coupled to the second differential memory data signal input, wherein the output of the first tristate differential driver and the output of the second tristate differential driver are coupled to each other. Equipped with, The system according to claim 1.

3. The system according to claim 1, wherein the driver circuit comprises a differential signal multiplexer.

4. The system according to claim 1, wherein the first flash memory type is universal flash storage (UFS) and the second flash memory type is non-volatile memory express (NVMe).

5. Encoding logic configured to encode output data for transmission to the flash memory system via the driver circuit, wherein the encoding logic includes M-PHY encoding logic and PCIe encoding logic, wherein the M-PHY encoding logic is configured to encode the output data using the M-PHY protocol, and the PCIe encoding logic is configured to encode the output data using the PCIe protocol, A decoding logic configured to decode input data received from the flash memory system via the receiver circuit, wherein the decoding logic comprises an M-PHY decoding logic and a PCIe decoding logic, the M-PHY decoding logic is configured to decode the input data using the M-PHY protocol, and the PCIe decoding logic is configured to decode the input data using the PCIe protocol. The system according to claim 4, further comprising the above.

6. A serializer logic configured to receive parallel output data from the encoding logic and convert the parallel output data into serial output data, A deserializer logic configured to receive serial input data from the receiver circuit and convert the serial input data into parallel input data, The system according to claim 5, further comprising the above.

7. A configurable transmitting-side impedance network coupled to the differential data output of the driver circuit and the differential data input of the flash memory system, wherein the configurable transmitting-side impedance network is configured to provide a selected one of a first impedance configuration and a second impedance configuration based on the selection signal, A configurable receiver-side impedance network coupled to the differential data input of the receiver circuit and the differential data output of the flash memory system, wherein the configurable receiver-side impedance network is configured to provide a selected one of a third impedance configuration and a fourth impedance configuration based on the selection signal, The system according to claim 1, further comprising the following:

8. The system according to claim 1, further comprising a clock signal circuit configured to select one of a first clock signal and a second clock signal based on the selection signal and to provide the selected clock signal to the flash memory system.

9. The system according to claim 1, wherein the system is included in a system-on-a-chip (SoC), and the SoC includes at least one processing system configured to initiate memory transactions with the flash memory system.

10. A method for selectively configuring the flash memory physical interface, The present invention provides a memory type selection logic for a selection signal indicating one of a first flash memory type and a second flash memory type, wherein the first flash memory type comprises an M-PHY flash memory and the second flash memory type comprises a Peripheral Component Interconnect Express (PCIe) flash memory. The driver circuit couples one of the first differential memory data signal input and the second differential memory data signal input to the differential data input of the flash memory system based on the selection signal received from the memory type selection logic. The receiver circuit, based on the selection signal received from the memory type selection logic, combines the differential data output of the flash memory system with one of the first differential memory data signal output and the second differential memory data signal output. Methods that include...

11. The method according to claim 10, wherein the first flash memory type is universal flash storage (UFS) and the second flash memory type is non-volatile memory express (NVMe).

12. Encoding output data for transmission to the flash memory system via the driver circuit, comprising encoding the output data using the M-PHY protocol and encoding the output data using the Peripheral Component Interconnect Express (PCIe) protocol, Decoding input data received from the flash memory system via the receiver circuit, comprising decoding the input data using the M-PHY protocol and decoding the input data using the PCIe protocol, Converting encoded parallel output data to serial output data, Converting serial input data from the receiver circuit into parallel input data, The method according to claim 11, further comprising:

13. A configurable output impedance network is used to couple one of the first and second impedance configurations to the differential data output of the driver circuit and the differential data input of the flash memory system based on the selection signal. A configurable output impedance network is used to couple one of the third and fourth impedance configurations to the differential data input of the receiver circuit and the differential data output of the flash memory system based on the selection signal. The method according to claim 10, further comprising:

14. Based on the aforementioned selection signal, one of the first clock signal and the second clock signal is selected. To provide the selected clock signal to the flash memory system, The method according to claim 10, further comprising:

15. The selection logic includes a voltage detector that responds to a predetermined voltage level indicating a register, fuse, or flash memory type configurable by the processor, or an impedance detector that responds to a predetermined impedance level indicating a flash memory type. The system according to claim 1, comprising at least one of the following.

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