High Dynamic Range Pixel Architecture

Abstract

A given pixel of the pixel array includes various operating modes, each with a different conversion gain for charge received from the pixel's photodetector. When the modes are used in conjunction with one another, the dynamic range of the pixel can be increased. A readout circuit connected to the photodetector in a given pixel includes a transfer gate between the photodetector and a gain mode selection block, which includes capacitors of different sizes and one or more switches that control which capacitor receives charge from the photodetector. Depending on the state of the one or more switches, different operating modes with different conversion gains can be selected to increase the dynamic range of the pixel. The adaptability of the readout circuit can enable a high dynamic range even in extreme temperature environments by reducing dark current.

Description

[Background technology]

[0001] Image sensors are widely used in many different applications across a large portion of the electromagnetic spectrum. Many image sensor designs use an array of sensors that capture light over a given region. Each sensor may be considered a pixel in a sensor array, with the pixels arranged in any number of rows and columns. Each pixel contains some form of photodetector and circuitry that collects charge from the photodetector in response to light input. Designing circuitry that provides both a high dynamic range and a high conversion gain presents a number of significant challenges. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an image sensor using a pixel array according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram illustrating various components of one pixel of the pixel array of FIG. 1 in accordance with an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram illustrating one pixel of FIG. 2 according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a timing diagram for various signals controlling certain elements of the pixel circuit of FIG. 3 in a first mode of operation, according to an embodiment of the present disclosure. [Figure 5] FIG. 4 is a timing diagram for various signals controlling certain elements of the pixel circuit of FIG. 3 in a second mode of operation, according to an embodiment of the present disclosure. [Figure 6] FIG. 4 is a timing diagram for various signals controlling certain elements of the pixel circuit of FIG. 3 in a third mode of operation, according to an embodiment of the present disclosure. [Figure 7] 2 illustrates an example computing platform that may include the image sensor of FIG. 1 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0003] These and other features of the present embodiments will be better understood from the following detailed description taken in conjunction with the drawings described herein.

[0004] A structure for a given pixel of a pixel array is disclosed that allows various operating modes for the given pixel. Each operating mode can have a different conversion gain for charge received from the photodetector. When the modes are used in conjunction with one another, the overall dynamic range of the pixel can be increased. In some embodiments, a readout circuit connected to the photodetector in a given pixel includes a transfer gate between the photodetector and a gain mode selection block. The gain mode selection block includes capacitors of various sizes and one or more switches that control which capacitor receives charge from the photodetector. Depending on the state of the one or more switches, different operating modes with different conversion gains can be selected to increase the dynamic range of the pixel. In an exemplary first operating mode, a first capacitor is selected to store charge from the photodetector. In an exemplary second operating mode, a first capacitor and a second capacitor in parallel are selected to store charge from the photodetector. In an exemplary third operating mode, a first capacitor, a second capacitor, and a third capacitor in parallel with one another are selected to store charge from the photodetector. During either mode of operation, the photodetector signal can be amplified, for example, via a source follower component, and ultimately read out to a column amplifier. The adaptability of the readout circuitry can enable high dynamic range, even in extreme temperature environments, by reducing dark current throughout the circuit.

[0005] overview As noted above, designing readout circuits for photodetectors presents significant challenges. For example, achieving a high dynamic range while still maintaining a high conversion gain from the charge received from the photodetector can be challenging. The dynamic range of a photodetector generally refers to the maximum light intensity that can be received while remaining within the linear operating range of the readout circuit. This allows photodetector architectures with higher dynamic range to receive higher light intensities that can be accurately represented as an electrical signal. Conversion gain generally indicates how much voltage can be generated per electron of charge from the photodetector. In many situations, a trade-off between conversion gain and dynamic range can exist, as high conversion gain is less susceptible to noise but can limit the dynamic range.

[0006] Therefore, and in accordance with embodiments of the present disclosure, techniques are disclosed for designing a readout circuit that can read out charge from a photodetector while taking advantage of both high conversion gain and high dynamic range. The readout circuit and photodetector can be part of a pixel, which is one pixel of an array of similarly designed pixels. The pixel sensor array can be, for example, any type of charge-coupled device (CCD) designed to receive light for the purpose of generating an image from the light received across the sensor array. Other pixel-based imaging arrays can also be useful.

[0007] In some embodiments, a pixel circuit (or, more simply, a pixel) of a pixel array (e.g., in a matrix format) includes a readout circuit connected to a photodetector. A sense node in the readout circuit is configured to connect to one or more different capacitors based on the state of two or more switches in the readout circuit. Changing which capacitor is used to store charge from the sense node represents a change in the operational mode of the readout circuit. Each operational mode, in some embodiments, may have a different conversion gain for charge read from the photodetector based on the total capacitance connected to the sense node. For example, the state of a first switch may be used to select between a first operational mode that connects the first capacitor to the sense node and a second operational mode that connects the first capacitor and the second capacitor to the sense node. Furthermore, the states of both the first switch and the second switch may be used to select a third operational mode that connects the first capacitor, the second capacitor, and a third capacitor to the sense node. Different conversion gains may be achieved for each operational mode by varying the level of capacitance for storing detector charge. Note that any one of the capacitors may consist substantially of or include a parasitic capacitance associated with the sense node and / or an actual capacitor connected to the sense node. In some embodiments, a given conversion gain associated with the first mode of operation is reduced by a factor of 10 compared to the second mode of operation and by a factor of 100 compared to the third mode of operation. For each mode of operation, the charge received from the photodetector may be used to generate a current signal that is ultimately supplied to a column amplifier or other amplifier element before being converted to a digital signal via an analog-to-digital converter (ADC).

[0008] According to an exemplary embodiment, the CCD includes a plurality of pixels, at least one of which has a photodetector, a transfer gate connected to the output of the photodetector, and a gain mode selection block connected to the output of the transfer gate. The gain mode selection block includes a first switch connected between a first node and a second node and a second switch connected between the second node and a third node. The first node is connected to a first capacitor, the second node is connected to a second capacitor, and the third node is connected to a third capacitor. According to some embodiments, the first capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the third capacitor, or vice versa, or the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor. Again, any one of the three capacitors may be implemented with only parasitic capacitance, a combination of parasitic capacitance and actual capacitance, or only actual capacitance. According to some such example embodiments, a resistive element, such as a field effect transistor (FET), biased to provide a consistent potential barrier, is connected between the output of the photodetector and a third node.

[0009] According to another exemplary embodiment, an image sensor includes a pixel array having at least one column of addressable pixels, column amplifiers connected to the at least one column of addressable pixels, an analog-to-digital converter (ADC) connected to the column amplifiers, and a processor connected to the ADC. The at least one column of addressable pixels includes at least one pixel circuit, the at least one pixel circuit including a photodetector, a transfer gate connected to an output of the photodetector, and a gain mode selection block connected to an output of the transfer gate. The gain mode selection block includes a first switch connected between a first node and a second node, and a second switch connected between the second node and a third node. The first node is connected to a first capacitor, the second node is connected to a second capacitor, and the third node is connected to a third capacitor. Note that the terms pixel and pixel circuit may be used interchangeably herein for ease and clarity of description.

[0010] According to another exemplary embodiment, a pixel of a pixel array in a CCD device includes a photodetector, a transfer gate having a first terminal connected to an output of the photodetector, a first capacitor connected to a second terminal of the transfer gate, a first switch having a first terminal connected to the second terminal of the transfer gate, a second capacitor connected to the second terminal of the first switch, a second switch having a first terminal connected to the second terminal of the first switch, and a third capacitor connected to the second terminal of the second switch.

[0011] The description uses the phrases "in one embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, when used with respect to embodiments of the present disclosure, are synonymous.

[0012] Various operations may be described as multiple independent acts or operations and in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that the operations are necessarily order dependent. In particular, the operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0013] System Architecture FIG. 1 is a block diagram of an exemplary image sensor 100 according to some embodiments. Image sensor 100 may be, or may be an integral part of, a charge-coupled device (CCD) camera or other type of imaging device. In some embodiments, image sensor 100 may be configured to capture different portions of the electromagnetic spectrum, such as visible light, ultraviolet light, infrared light, or X-rays, to name a few. Image sensor 100 may include a pixel array 102, column amplifiers 106, an ADC 108, and a processor 110. Each of the illustrated components may be included together on the same printed circuit board (PCB) or in a single chip package (e.g., a system-in-package or system-on-chip). In some other embodiments, any one or more of the elements may be provided in separate chip packages and / or on separate PCBs.

[0014] In some embodiments, the pixel array 102 includes a plurality of pixels arranged in a matrix. Each pixel in the pixel array 102 may have a similar architecture, including a photodetector and readout circuitry. The photodetection area of ​​each pixel that may be impinged by incident radiation may vary from embodiment to embodiment, but in some exemplary cases has a physical size of about 1 μm×1 μm to about 5 μm×5 μm. Similarly, the shape of the photodetection area (e.g., photodiode) and lens configuration (if present) may also vary from exemplary embodiment, depending on factors such as the desired fill factor of the array. In some embodiments, each row of pixels may be connected together to a common row select line (e.g., word line) to provide an individually addressable row of pixels.

[0015] In some embodiments, outputs from N different columns of pixels are received by column amplifiers 106. In some embodiments, column amplifiers 106 represent N separate column amplifiers, with a given column amplifier configured to receive outputs from pixels in a corresponding column of pixel array 102. In this manner, pixels in a given row of pixel array 102 may be selected via a row select line and simultaneously read out via the N column amplifiers 106. In some embodiments, column amplifiers 106 may include any type of amplifier configuration, such as any number of source follower FETs or operational amplifiers. In some embodiments, a single column amplifier 106 may be used in conjunction with a multiplexer to receive each of the N column outputs from pixel array 102.

[0016] In some embodiments, the outputs from the column amplifiers 106 are received by the ADCs 108. As noted above, the ADCs 108 may be N different ADCs, with a given ADC configured to receive the output from a corresponding column amplifier 106. The ADCs 108 may be any known type of ADC, without limitation.

[0017] The processor 110 may be configured to receive the digitized signals from the ADC 108 (or N digitized signals across the N ADCs) and perform any number of operations on the signals. For example, the processor 110 may receive signal data from pixels in a given row of the pixel array 102 and use the signal data to generate an image or portion of an image captured by the pixel array 102. As used herein, the term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processor 110 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, custom semiconductors, or any other suitable processing devices.

[0018] Pixel Design 2 shows a block diagram of a pixel 200 of the pixel array 102 including a photodetector 202 and readout circuitry 203, according to some embodiments. The photodetector 202 may include any type of light-sensitive design, such as a PN diode. Note that the term "pixel" may refer to the photodetection area of ​​a given pixel as well as the functional pixel circuitry.

[0019] In some embodiments, readout circuitry 203 includes a transfer gate 204 connected to the output of photodetector 202. As mentioned above, the active area of ​​photodetector 202 (e.g., the area that is sensitive to incident light and generates a corresponding signal based on the intensity of that light) and any lens configuration may vary depending on a given application. Transfer gate 204 acts like a gatekeeper for the charge generated by photodetector 202 in response to the light input. In some embodiments, transfer gate 204 may include a single field effect transistor (FET), such as a p-doped or n-doped metal oxide semiconductor device (PMOS or NMOS), or any number of FETs performing a similar function.

[0020] In some embodiments, the transfer gate 204 is configured to allow charge from the photodetector 202 to be transferred to the gain mode selection block 206, where the charge is stored in one or more selected capacitors. The gain mode selection block 206 may include, for example, two or more switches and any number of capacitors, where the state of the switches can be used to select the conversion gain mode in which to operate. For example, two switches and three capacitors may be arranged to allow three different conversion gain modes. However, other layouts may include more switches and / or more capacitors to create any number of additional conversion gain modes. Also, from the above, it should be noted that any one of the capacitors may be implemented with parasitic capacitance or a combination of parasitic capacitance and an actual capacitor device. The charge passing through the transfer gate 204 may be stored at a given conversion gain based on which capacitor is connected to the sense node in the gain mode selection block 206.

[0021] In some embodiments, resistive element 208 is also connected between the output of photodetector 202 and a portion of gain mode select block 206. Resistive element 208 may be, for example, an NMOS or PMOS device that is biased to create a controllable potential barrier based on how much bias is applied to the gate of the NMOS or PMOS device. In some other examples, resistive element 208 may be a resistor or a PN junction that is biased to provide a given potential barrier.

[0022] In some embodiments, the sense node of the gain mode select block 206, which is connected to the selected capacitor or capacitors, is further connected to an amplifier 210 that generates an output signal. The amplifier 210 may be implemented, for example, as a single source follower NMOS or PMOS device or as an operational amplifier.

[0023] In some embodiments, the row select switch 212 is included within the readout circuitry 203. The row select switch 212 may have a gate or select input connected to a common row line (e.g., word line) along with other pixels in the same row, such that when the current row is activated and read out, the row select switch 212 is activated and turned on to read out an output signal to the column amplifiers 106. When the current row is not selected, the row select switch 212 is not activated and no signal is read out to the column amplifiers 106. The row select switch 212 may be implemented as an NMOS or PMOS device, with the row line connected to the gate of the NMOS or PMOS device.

[0024] 3 shows an example circuit diagram of any given pixel of pixel array 102, according to some embodiments. Each of the FETs shown can be either an NMOS or PMOS device, depending on the layout. Additionally, in some embodiments, any of the FETs may be replaced with other transistor technologies, such as a bipolar junction transistor (BJT). According to some embodiments, the pixel readout circuitry includes a current source I that provides a bias current for operating a source follower amplifier SF. b Includes:

[0025] When light is incident on the photodetector PD, it is converted into an electric charge that can flow as a photocurrent. At a given moment, at least a portion of the converted electric charge is released to the sense node SN through the transfer gate TX1 by turning on the transfer gate TX1 for a predetermined number of clock cycles. Once the electric charge is released to the sense node SN, it can be stored in various combinations of capacitors depending on the states of the first switch DCG1 and the second switch DCG2. In a first exemplary mode of operation, DCG1 is turned off (e.g., not biased) so that the electric charge at the sense node SN is stored only in the first capacitor Cfd. In some examples, the capacitor Cfd may have a relatively small capacitance of about 1 femtofarad (fF) or about 0.2 fF to about 3 fF. The conversion gain may be relatively high, such as about 170 μV / electron to about 200 μV / electron, in the first mode of operation. In a second exemplary mode of operation, DCG1 is turned on (e.g., biased) and DCG2 is turned off (e.g., unbiased) so that the charges at both the sense node SN and the second node N2 are stored in the parallel first capacitor Cfd and second capacitor Cg1. In some examples, capacitor Cg1 may have a high capacitance compared to capacitor Cfd. For example, capacitor Cg1 may have a capacitance of about 10 fF or about 5 fF to about 15 fF. The conversion gain in the second mode of operation may be relatively lower than the conversion gain in the first mode of operation. For example, the conversion gain in the second mode of operation may be about 17 μV / electron to about 20 μV / electron. In a third exemplary mode of operation, DCG1 is turned on (e.g., biased) and DCG2 is turned on (e.g., biased) so that the charges at the sense node SN, the second node N2, and the third node N3 are stored in the parallel first capacitor Cfd, the second capacitor Cg1, and the third capacitor Cg2. In some examples, capacitor Cg2 may have a high capacitance compared to capacitor Cg1. For example, capacitor Cg2 may have a capacitance of about 100 fF or about 75 fF to about 125 fF. The conversion gain in the third mode of operation may be relatively lower than the conversion gain in the second mode of operation.For example, the conversion gain in the third mode of operation can be between about 1.7 μV / electron and about 2.0 μV / electron.

[0026] In some embodiments, DCG1 and DCG2 have the same transistor characteristics. For example, DCG1 and DCG2 may each have a substantially identical W / L ratio and approximately identical switching speed, such that their respective W / L ratios and switching speeds are each within a given tolerance (e.g., ±10%, ±5%, or ±2%) of a target value.

[0027] In any of the above modes of operation, a stored potential (at a given conversion gain based on the mode of operation) activates the source follower amplifier SF to generate an output signal to send to the column amplifier 106. The source follower amplifier SF can be a single FET device or any other amplifier structure, such as an operational amplifier. The source follower amplifier SF can be powered by a power rail VAA_PIX, for example, between about 2 V and about 2.5 V, or some other suitable rail voltage. The output signal generated by the source follower amplifier SF can only be sent to the column amplifier 106 if the row select switch RS is biased. According to some such examples, all pixels in a given row of the pixel array 102 will share the same row select line (e.g., word line) that connects to the gate of the row select switch RS. If the row select switch RS is not biased, the current pixel is part of a row that is not currently being read out, and no signal is sent from the current pixel to the column amplifier 106.

[0028] In some embodiments, the potential of any of the sense node SN, the second node N2, or the third node N3 can be reset to a baseline or reference value by the reset switch RST. When the reset switch RST is biased, the rail voltage VAA_RST is applied to all of the nodes connected to the end of the reset switch RST. For example, when the reset switch RST is biased to apply the voltage VAA_RST to both the sense node SN and the second node N2, DCG1 can also be biased to overwrite all of the charge from the photodetector PD. In another example, when the reset switch RST is biased to apply the voltage VAA_RST to the output node of the photodetector PD, both DCG1 and TX1 may be biased. The rail voltage VAA_RST may be approximately 2 V to approximately 2.5 V. Although the reset switch RST is connected to the second node N2, the reset switch RST may be connected to any node in the readout circuit, such as the sense node SN, the second node N2, or the third node N3.

[0029] In some embodiments, a resistive element TX2 is disposed between the output of the photodetector PD and the third node N3. In the illustrated example, TX2 is a biasable FET to provide an adjustable potential barrier (variable resistor) based on the amount of voltage applied to its gate. In other examples, the resistive element TX2 can be implemented by a resistor with a consistent resistance or any doped junction that provides the potential barrier. The presence of the resistive element TX2 allows some charge from the photodetector to always leak across the resistive element TX2 to the third node N3.

[0030] Timing diagrams for various operating modes 4-6 provide exemplary timing diagrams for the various operation modes of the pixel circuit. FIG. 4 provides an exemplary timing diagram for various control signals in a first operation mode (e.g., using only capacitor Cfd). FIG. 5 provides an exemplary timing diagram for various control signals in a second operation mode (e.g., using only capacitor Cfd and capacitor Cg1 in parallel). FIG. 6 provides an exemplary timing diagram for various control signals in a third operation mode (e.g., using capacitor Cfd, capacitor Cg1, and capacitor Cg2 in parallel).

[0031] For both modes of operation, the same initialization period t0 can be used to reset the potentials of various nodes around the circuit before light capture occurs. During the initialization period t0, RST is biased, while DCG1, DCG2, and TX1 are each biased for at least one clock cycle. During this time, all nodes connected to DCG1, DCG2, and TX1 are reset with the reset rail voltage VAA_RST. In some embodiments, the various switches are then turned off in the following order: first TX1, then DCG2, and then DCG1 are debiased. During this process, the row select RS can be biased to read out baseline values ​​from the various nodes of the readout circuit.

[0032] Referring to FIG. 4, in the first mode of operation, after light is captured by the photodetector PD, the row select RS is biased to begin reading data from the readout circuit in a first period t1. During this time, RST is also biased along with DCG1 to reset at least the sense node SN and the second node N2. In a second period t2, a baseline reading is captured at the potentials of both the sense node SN and the second node N2. In a third period t3, DCG1 is unbiased, so another baseline reading is captured only of the sense node SN. In a fourth period t4, the photodetector charge is dumped to the sense node SN by biasing TX1. In a fifth period t5, TX1 is no longer biased, and a reading is captured from the sense node SN with the charge stored on the capacitor Cfd because DCG1 is unbiased. Because only the capacitor Cfd is used, this reading has a relatively high conversion gain. During the sixth period t6, DCG1 is also biased along with TX1, so that the photodetector charge is dumped onto both the sense node SN and the second node N2. During the seventh period t7, TX1 is unbiased, and because DCG1 is still biased, a reading is captured from the sense node SN and the second node N2 with the charge stored on the parallel capacitors Cfd and Cg1. Due to the use of parallel capacitors Cfd and Cg1, this reading has a lower conversion gain compared to the reading obtained during the fifth period t5. During the eighth period t8, all switches, including RST, are biased to again reset all nodes with the rail voltage VAA_RST. Since no reading is required during this period, the row select RS is unbiased.

[0033] In some embodiments, the baseline readings are compared to the signal readings to capture differences related to the amount of light incident on the photodetector PD. For example, during the first mode of operation, the baseline reading captured at time period t2 is compared to the signal reading captured at time period t7, and the baseline reading captured at time period t3 is compared to the signal reading captured at time period t5. Note that during the first mode of operation, DCG2 is not used in any of the readout operations.

[0034] Referring to FIG. 5, in the second mode of operation, after light is captured by the photodetector PD, the row select RS is biased to begin reading data from the readout circuit in the first period t1. During this time, RST is also biased together with DCG1 to reset at least the sense node SN and the second node N2. In the second period t2, a baseline reading is captured at the potential of the sense node SN. In the third period t3, the photodetector charge is dumped to the sense node SN by biasing TX1. In the fourth period t4, TX1 is no longer biased, and because DCG1 is unbiased, a reading is captured from the sense node SN with the charge stored in Cfd. Because only capacitor Cfd is used, this reading has a relatively high conversion gain. In the fifth period t5, both DCG1 and DCG2 are biased together with TX1, so the photodetector charge is dumped to the sense node SN, the second node N2, and the third node N3. During the sixth period t6, TX1 is unbiased, but both DCG1 and DCG2 are still biased, so a reading is captured from the sense node SN, the second node N2, and the third node N3 at the charges stored in parallel on capacitors Cfd, Cg1, and Cg2. Because parallel capacitors Cfd, Cg1, and Cg2 are used, this reading has a lower conversion gain compared to the reading taken during the fourth period t4. During the seventh period t7, RST is biased along with both DCG1 and DCG2 to reset the potentials of the sense node SN, the second node N2, and the third node N3. During the eighth period t8, both DCG1 and DCG2 are biased, so a baseline reading is captured at the potentials of the sense node SN, the second node N2, and the third node N3. During the ninth period t9, all switches, including RST, are biased to again reset all nodes with the rail voltage VAA_RST. Since no read is required during this period, the row select RS is not biased.

[0035] In some embodiments, the baseline readings are compared to signal readings to capture differences related to the amount of light incident on the photodetector PD. For example, during the second mode of operation, a baseline reading captured at time period t2 is compared to a signal reading captured at time period t4, and a baseline reading captured at time period t8 is compared to a signal reading captured at time period t6. In some embodiments, during the second mode of operation, DCG2 simply remains biased following capture of light at the photodetector PD.

[0036] Referring to FIG. 6, in the third mode of operation, after light is captured by the photodetector PD, the row select RS is biased to begin reading data from the readout circuit during the first period t1. During this time, RST is also biased along with DCG1 to reset at least the sense node SN and the second node N2. During the second period t2, a baseline reading is captured at the potential of the sense node SN and the second node N2 because DCG1 is still biased. During the third period t3, a baseline reading is captured at the potential of the sense node SN, but not the potential of the second node N2 because DCG1 is not biased. During the fourth period t4, the photodetector charge is released to the sense node SN by biasing TX1. During the fifth period t5, TX1 is no longer biased, and a reading is captured from the sense node SN with the charge stored in Cfd because DCG1 is not biased. This reading has a relatively high conversion gain because only capacitor Cfd is used. During the sixth period t6, the photodetector charge is released to the sense node SN and the second node N2, but not to the third node N3 because DCG1 is biased together with TX1 and DCG2 is not biased. During the seventh period t7, TX1 is no longer biased, DCG1 is biased, and DCG2 is not biased, so a reading is captured from the sense node SN and the second node N2 with the charge stored on the parallel capacitors Cfd and Cg1. Because parallel capacitors Cfd and Cg1 are used, this reading has a lower conversion gain compared to the reading obtained during the fifth period t5. During the eighth period t8, both DCG1 and DCG2 are biased together with TX1, so the photodetector charge is released to the sense node SN, the second node N2, and the third node N3. During the ninth period t9, TX1 is no longer biased and both DCG1 and DCG2 are biased so that readings are captured from the sense node SN, the second node N2 and the third node N3 with the charges stored in capacitors Cfd, Cg1 and Cg2 in parallel.Due to the use of capacitors Cfd, Cg1 and Cg2 in parallel, this reading has a lower conversion gain compared to the reading taken in the seventh period t7. Tenth period t. 10 In the eleventh period t, RST is biased together with both DCG1 and DCG2 to reset the potentials of the sense node SN, the second node N2, and the third node N3. 11 During the twelfth period t, both DCG1 and DCG2 are biased so that a baseline reading is captured at the potentials of the sense node SN, the second node N2, and the third node N3. 12 Now all switches including RST are biased to again reset all nodes with the rail voltage VAA_RST. Since no reads are required during this period, the row select RS is not biased.

[0037] In some embodiments, the baseline readings are compared to signal readings to capture differences related to the amount of light incident on the photodetector PD. For example, during a third mode of operation, a baseline reading captured during time period t2 is compared to a signal reading captured during time period t7, a baseline reading captured during time period t3 is compared to a signal reading captured during time period t5, and so on. 11 The baseline reading captured at time period t is compared to the signal reading captured at time period t. According to some embodiments, DCG2 may be used in conjunction with DCG1 to generate three different signal readings with different conversion gains.

[0038] Exemplary Computing Platform 7 illustrates an exemplary computing platform 700 interfacing with an image sensor 100 configured in accordance with certain embodiments of the present disclosure. In some embodiments, the computing platform 700 may host or be incorporated into a personal computer, a workstation, a server system, a laptop computer, an ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a mobile phone, a combination mobile phone and PDA, a smart device (e.g., a smartphone or smart tablet), a mobile internet device (MID), a messaging device, a data communication device, an imaging device, a wearable device, an embedded system, or the like. Any combination of various devices may be used in certain embodiments. The computing platform 700 may host a controller area network (CAN) used in a vehicle. In some embodiments, the computing platform 700 represents one system in a network of systems interconnected via a CAN bus.

[0039] In some embodiments, computing platform 700 may include any combination of processor 702, memory 704, image sensor 100, network interface 706, input / output (I / O) system 708, user interface 710, and storage system 712. In some embodiments, one or more components of image sensor 100 are implemented as part of processor 702. As will be further appreciated, buses and / or interconnects are also provided to enable communication between the various components listed above and / or other components not shown. Computing platform 700 may be connected to a network 716 via network interface 706 to enable communication with other computing devices, platforms, or resources. Other components and functionality not reflected in the block diagram of FIG. 7 will be apparent in light of this disclosure, and it should be understood that other embodiments are not limited to any particular hardware configuration.

[0040] Processor 702 may be any suitable processor and may include one or more coprocessors or controllers that assist in control and processing operations associated with computing platform 700. In some embodiments, processor 702 may be implemented as any number of processor cores. A processor (or processor core) may be any type of processor, such as, for example, a microprocessor, an embedded processor, a digital signal processor (DSP), a graphics processor (GPU), a network processor, a field programmable gate array, or other device configured to execute code. A processor may be a multithreaded core that may include two or more hardware thread contexts (i.e., "logical processors") per core.

[0041] Memory 704 may be implemented using any suitable type of digital storage, such as, for example, flash memory and / or random access memory (RAM). In some embodiments, memory 704 may include various layers of memory hierarchy and / or memory caches known to those skilled in the art. Memory 704 may be implemented as a volatile memory device, such as, but not limited to, a RAM, a dynamic RAM (DRAM), or a static RAM (SRAM) device. Storage system 712 may be implemented as a non-volatile storage device, such as, but not limited to, one or more of a hard disk drive (HDD), a solid-state drive (SSD), a universal serial bus (USB) drive, an optical disk drive, a tape drive, an internal storage device, an external storage device, flash memory, a battery-backed synchronous DRAM (SDRAM), and / or a network-accessible storage device. In some embodiments, storage system 712 may include technology to enhance storage performance and protection for valuable digital media when multiple hard drives are included.

[0042] Processor 702 may be configured to execute operating system (OS) 714, which may comprise any suitable operating system, such as Google Android® (Google, Inc., Mountain View, Calif.), Microsoft Windows® (Microsoft Corporation, Redmond, Wash.), Apple OS X (Apple Inc., Cupertino, Calif.), Linux®, or a real-time operating system (RTOS). As will be appreciated in light of this disclosure, the techniques provided herein may be implemented regardless of the particular operating system provided in conjunction with computing platform 700, and thus may be implemented using any suitable existing or later-developed platform.

[0043] The network interface 706 may be any suitable network chip or chipset that enables wired and / or wireless connections between the computing platform 700 and / or other components of the network 716, thereby enabling the computing platform 700 to communicate with other local and / or remote computing systems, servers, cloud-based servers, and / or other resources. The wired communication may conform to existing (or yet to be developed) standards such as, for example, Ethernet. The wireless communication may conform to existing (or yet to be developed) standards such as, for example, Long Term Evolution (LTE), Wireless Fidelity (Wi-Fi), Bluetooth, and / or Near Field Communication (NFC). Exemplary wireless networks include, but are not limited to, wireless local area networks, wireless personal area networks, wireless metropolitan area networks, cellular networks, and satellite networks.

[0044] The I / O system 708 may be configured to interface between various I / O devices and other components of the computing platform 700. The I / O devices may include, but are not limited to, a user interface 710. The user interface 710 may include devices (not shown) such as a display element, a touchpad, a keyboard, a mouse, and speakers. The I / O system 708 may include a graphics subsystem configured to process images for rendering on a display element. The graphics subsystem may be, for example, a graphics processing unit or a visual processing unit (VPU). An analog or digital interface may be used to communicatively connect the graphics subsystem to the display element. For example, the interface may be any of High-Definition Multimedia Interface (HDMI), DisplayPort, Wireless HDMI, and / or any other suitable interface using wireless high-definition enabled technology. In some embodiments, the graphics subsystem may be integrated into the processor 702 or any chipset of the computing platform 700.

[0045] It should be appreciated that in some embodiments, the various components of computing platform 700 may be combined or integrated into a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0046] In various embodiments, computing platform 700 may be implemented as a wireless system, a wired system, or a combination of both. If implemented as a wireless system, computing platform 700 may include components and interfaces suitable for communication over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, etc. Examples of wireless shared media may include portions of a wireless spectrum, such as the radio frequency spectrum. If implemented as a wired system, computing platform 700 may include components and interfaces suitable for communication over a wired communication medium, such as input / output adapters, physical connectors connecting the input / output adapters to corresponding wired communication media, network interface cards (NICs), disk controllers, video controllers, audio controllers, etc. Examples of wired communication media may include wires, cable metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cable, fiber optics, etc.

[0047] Unless otherwise specified, terms such as "processing," "computing," "calculating," "determining," and the like may be understood to refer to the operations and / or processing of a computer or computer system or similar electronic computing device that manipulates and / or transforms data represented as physical quantities (e.g., electronic quantities) in the registers and / or memory units of the computer system into other data similarly represented as physical quantities in the registers, memory units, or other such information storage and transmission or display of the computer system. Embodiments are not limited in this context.

[0048] The term "circuit" or "circuitry" as used herein in any embodiment may include, for example, alone or in any combination, hardwired circuitry, programmable circuitry such as a computer processor with one or more individual instruction processing cores, state machine circuitry, and / or firmware that stores instructions executed by the programmable circuitry. The circuitry may include a processor and / or controller configured to execute one or more instructions to perform one or more operations described herein. The instructions may be embodied, for example, as an application, software, firmware, etc. configured to cause the circuitry to perform any of the operations described above. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a computer-readable storage device. Software may be implemented or performed to include any number of processes, and processes may be implemented or performed to include any number of threads, etc., in a hierarchical manner. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, instruction sets, and / or data in a memory device. The circuits may be implemented as circuits that collectively or individually comprise part of a larger system, such as an integrated circuit (IC), an application specific integrated circuit (ASIC), a system on a chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smartphone, etc. Other embodiments may be implemented as software executed by a programmable control device. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include a processor, a microprocessor, a circuit, a circuit element (e.g., a transistor, a resistor, a capacitor, an inductor, etc.), an integrated circuit, an application specific integrated circuit (ASIC), a programmable logic device (PLD), a digital signal processor (DSP), a field programmable gate array (FPGA), a logic gate, a register, a semiconductor device, a chip, a microchip, a chipset, etc.

[0049] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, GPUs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an embodiment is implemented using hardware and / or software elements may depend on any number of factors, such as desired computational speed, power levels, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speeds, and other design or performance constraints.

[0050] Further exemplary embodiments The following examples relate to further embodiments, from which numerous variations and configurations should become apparent.

[0051] Example 1 is a charge-coupled device (CCD) including a plurality of pixels. At least one pixel of the plurality of pixels includes a photodetector, a transfer gate connected to an output of the photodetector, and a gain mode selection block connected to an output of the transfer gate. The gain mode selection block includes a first switch connected between a first node and a second node, and a second switch connected between the second node and a third node. The first node is connected to a first capacitor, and the second node is connected to a second capacitor. The third node is connected to a third capacitor.

[0052] A second embodiment includes the CCD according to the first embodiment, and the transfer gate is connected to the first node of the gain mode selection block.

[0053] A third embodiment includes the CCD according to the first or second embodiment, and each of the first switch and the second switch is a field effect transistor (FET).

[0054] Example 4 includes the CCD according to Example 3, wherein the first switch has substantially the same width / length (W / L) ratio as the second switch.

[0055] A fifth embodiment includes the CCD according to any one of the first to fourth embodiments, and further includes a resistive element connected between the output of the photodetector and the third node.

[0056] A sixth embodiment includes a CCD according to the fifth embodiment, in which the resistive elements are FETs.

[0057] Example 7 includes the CCD according to any one of Examples 1 to 6, wherein the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor.

[0058] An eighth embodiment includes the CCD according to any one of the first to seventh embodiments, and further includes a reset switch connected to any one of the nodes of the gain mode selection block.

[0059] Example 9 is an image sensor including a pixel array having at least one column of addressable pixels, column amplifiers connected to the at least one column of addressable pixels, an analog-to-digital converter (ADC) connected to the column amplifiers, and a processor connected to the ADC. The at least one column of addressable pixels includes at least one pixel including a photodetector, a transfer gate connected to an output of the photodetector, and a gain mode selection block connected to an output of the transfer gate. The gain mode selection block includes a first switch connected between a first node and a second node, and a second switch connected between the second node and a third node. The first node is connected to a first capacitor, and the second node is connected to a second capacitor. The third node is connected to a third capacitor.

[0060] A tenth embodiment includes the image sensor according to the ninth embodiment, in which the transfer gate is connected to the first node of the gain mode selection block.

[0061] An eleventh embodiment includes the image sensor according to the ninth or tenth embodiment, wherein each of the first switch and the second switch is a field effect transistor (FET).

[0062] Example 12 includes the image sensor according to Example 11, wherein the first switch has substantially the same width / length (W / L) ratio as the second switch.

[0063] Example 13 includes the image sensor according to any one of Examples 9 to 12, wherein at least one pixel further comprises a resistive element connected between the output of the photodetector and the third node.

[0064] A fourteenth embodiment includes the image sensor according to the thirteenth embodiment, in which the resistive element is a FET.

[0065] Example 15 includes the image sensor according to any one of Examples 9 to 14, wherein the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor.

[0066] A sixteenth embodiment includes the image sensor according to any one of the ninth to fifteenth embodiments, wherein at least one pixel further includes a reset switch connected to any node of the gain mode selection block.

[0067] Example 17 is a pixel of a pixel array in a CCD device, the pixel including a photodetector, a transfer gate having a first terminal connected to an output of the photodetector, a first capacitor connected to a second terminal of the transfer gate, a first switch having a first terminal connected to the second terminal of the transfer gate, a second capacitor connected to the second terminal of the first switch, a second switch having a first terminal connected to the second terminal of the first switch, and a third capacitor connected to the second terminal of the second switch.

[0068] Example 18 includes the pixel according to Example 17, further comprising a resistive element connected between the output of the photodetector and the second terminal of the second switch.

[0069] Example 19 includes the pixel according to Example 18, in which the resistive element is a FET.

[0070] Example 20 includes the pixel according to any one of Examples 17 to 19, wherein the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor.

[0071] Example 21 includes the pixel according to any one of Examples 17 to 20, wherein the second terminal of the transfer gate is further connected to the gate of the amplifier FET.

[0072] Example 22 includes the pixel according to any one of Examples 17 to 21, and each of the first switch and the second switch is a field effect transistor (FET).

[0073] Example 23 includes the pixel according to Example 22, wherein the first switch has substantially the same width / length (W / L) ratio as the second switch.

[0074] Example 24 includes the pixel according to any one of Examples 17 to 23, and further includes a reset switch connected to the second terminal of the first switch.

[0075] Numerous specific details have been described herein to provide a thorough understanding of the embodiments. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known operations, components, and circuits have not been described in detail so as not to obscure the embodiments. It will be understood that specific structural and functional details disclosed herein are representative and do not necessarily limit the scope of the embodiments. Furthermore, although subject matter has been described in language specific to structural features and / or methodological acts, it will be understood that the subject matter defined in the following claims is not necessarily limited to the specific features or acts described herein. Rather, the specific features and acts described herein are disclosed as example forms of implementing the claims.

Claims

1. a charge coupled device (CCD), a plurality of pixels, at least one of the plurality of pixels comprising: a photodetector; a transfer gate connected to the output of the photodetector; a gain mode selection block connected to the output of the transfer gate, the gain mode selection block comprising: a first switch connected between a first node and a second node, the first node being connected to a first capacitor and the second node being connected to a second capacitor; a second switch connected between the second node and a third node, the third node being connected to a third capacitor; Equipped with a CCD.

2. 2. The CCD of claim 1, wherein the transfer gate is connected to the first node of the gain mode selection block.

3. 2. The CCD of claim 1, wherein each of the first switch and the second switch is a field effect transistor (FET).

4. 4. The CCD of claim 3, wherein the first switch has substantially the same width / length (W / L) ratio as the second switch.

5. 2. The CCD of claim 1, further comprising a resistive element connected between the output of the photodetector and the third node.

6. 6. The CCD of claim 5, wherein the resistive element is a FET.

7. 2. The CCD of claim 1, wherein the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor.

8. 2. The CCD according to claim 1, further comprising a reset switch connected to any one of the nodes of the gain mode selection block.

9. An image sensor, a pixel array having at least one column of addressable pixels; a column amplifier connected to the at least one column of addressable pixels; an analog-to-digital converter (ADC) connected to the column amplifiers; a processor connected to the ADC; Equipped with The at least one column of addressable pixels comprises: a photodetector; a transfer gate connected to the output of the photodetector; a gain mode selection block connected to an output of the transfer gate, the gain mode selection block comprising: a first switch connected between a first node and a second node, the first node being connected to a first capacitor and the second node being connected to a second capacitor; a second switch connected between the second node and a third node, the third node being connected to a third capacitor; An image sensor comprising:

10. The image sensor of claim 9 , wherein the transfer gate is connected to the first node of the gain mode selection block.

11. 10. The image sensor of claim 9, wherein each of the first switch and the second switch is a field effect transistor (FET).

12. 10. The image sensor of claim 9, wherein the at least one pixel further comprises a resistive element connected between the output of the photodetector and the third node.

13. The image sensor of claim 12 , wherein the resistive element is a FET.

14. 10. The image sensor of claim 9, wherein the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor.

15. The image sensor of claim 9 , wherein the at least one pixel further comprises a reset switch connected to any node of the gain mode selection block.

16. A pixel of a pixel array in a CCD device, comprising: a photodetector; a transfer gate having a first terminal connected to the output of the photodetector; a first capacitor connected to the second terminal of the transfer gate; a first switch having a first terminal connected to the second terminal of the transfer gate; a second capacitor connected to the second terminal of the first switch; a second switch having a first terminal connected to the second terminal of the first switch; a third capacitor connected to the second terminal of the second switch; A pixel comprising:

17. 17. The pixel of claim 16, further comprising a resistive element connected between the output of the photodetector and the second terminal of the second switch.

18. The pixel of claim 17 , wherein the resistive element is a FET.

19. 17. The pixel of claim 16, wherein the third capacitor has a higher capacitance than the second capacitor, and the second capacitor has a higher capacitance than the first capacitor.

20. The pixel of claim 16 , wherein the second terminal of the transfer gate is further connected to the gate of an amplifier FET.

Images