Quantum mechanical logic for classical computation

Abstract

In one aspect, a method for compressing a classical binary data input includes: obtaining a classical binary data input; performing a classical operation on the classical binary data input to obtain metadata for the classical binary data input, the metadata including a statistical operator, the classical operation being based on an ensemble interpretation of quantum mechanics; applying a swap gate to the metadata to compress the metadata, the swap gate swapping data as a one-way function, the application of the swap gate being defined by a value of the statistical operator; and providing the compressed metadata as a compressed classical binary data input.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Patent Application No. 18 / 147,453, filed December 28, 2022, which claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 413,198, filed October 4, 2022, the entirety of which is incorporated herein by reference. [Background technology]

[0002] The ensemble interpretation of quantum mechanics states that quantum multi-element (QME) systems can be identified by the derivation of statistical observable properties, or simply mathematical objects known as statistical probabilities, instead of exhaustively enumerating all qubit combinations. Statistical probabilities are generated by statistical operators, which are dynamically defined variables for a quantum system. The generation and definition of statistical probabilities for quantum states replaces the requirement to list the qubit states and gate corrections of a QME system. This allows a QME system to be defined solely by its statistical probabilities, rather than the states of its individual qubits. With this representation, only the metadata of the QME, e.g., statistical probabilities, are stored in storage, resulting in significant savings in storage and memory space. However, while the ensemble interpretation of quantum mechanics is correct in the quantum realm, it cannot be directly applied to classical computation. Summary of the Invention

[0003] This disclosure describes techniques for logical reverse computing and circular compression and decompression.

[0004] In general, one innovative aspect of the subject matter described herein can be embodied in a method for compressing a classical binary data input, the method including: obtaining a classical binary data input; performing a classical operation on the classical binary data input to obtain metadata for the classical binary data input, the metadata including a statistical operator, the classical operation being based on an ensemble interpretation of quantum mechanics; applying a swap gate to the metadata to compress the metadata, the swap gate swapping data as a one-way function, the application of the swap gate being defined by a value of the statistical operator; and providing the compressed metadata as a compressed classical binary data input.

[0005] Other embodiments of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method. One or more computer systems can be configured to perform particular operations or actions by virtue of software, firmware, hardware, or a combination thereof installed on the system that causes the system to perform the operations during operation. One or more computer programs can be configured to perform particular operations or actions by including instructions that, when executed by a data processing device (e.g., one or more computers or computer processors), cause the device to perform the operations.

[0006] In general, another innovative aspect of the subject matter described herein may be embodied in a method that includes operations of obtaining a classical binary data input and performing a classical operation on the classical binary data input to obtain metadata of the classical binary data input, the metadata including a statistical operator that produces an output having characteristics of the classical binary data input, the classical operation being based on an ensemble interpretation of quantum mechanics, and providing the metadata for use in a subsequent computation.

[0007] Other embodiments of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method. One or more computer systems can be configured to perform particular operations or actions by virtue of software, firmware, hardware, or a combination thereof installed on the system that causes the system to perform the operations during operation. One or more computer programs can be configured to perform particular operations or actions by including instructions that, when executed by a data processing device (e.g., one or more computers or computer processors), cause the device to perform the operations.

[0008] In general, another innovative aspect of the subject matter described in this specification may be embodied in a method that includes operations of receiving metadata for the classical binary data input, the metadata including a statistical operator, the classical operation being based on an ensemble interpretation of quantum mechanics; applying a swap gate to the metadata to compress the metadata, the swap gate swapping data as a one-way function, the application of the swap gate being defined by a value of the statistical operator; and providing the compressed metadata as a compressed classical binary data input.

[0009] Other embodiments of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method. One or more computer systems can be configured to perform particular operations or actions by virtue of software, firmware, hardware, or a combination thereof installed on the system that causes the system to perform the operations during operation. One or more computer programs can be configured to perform particular operations or actions by including instructions that, when executed by a data processing device (e.g., one or more computers or computer processors), cause the device to perform the operations.

[0010] Each of the above and other embodiments may optionally include one or more of the following features, alone or in combination: In some embodiments, the compressed classical binary data input has the same entropy as the classical binary data input.

[0011] In some embodiments, the metadata includes classical binary data input partitioned into a plurality of data packets having a length equal to one or more predetermined sizes, each of the plurality of predetermined sizes corresponding to a respective virtual Hilbert space.

[0012] In some embodiments, the metadata includes values ​​that represent data patterns that occur in classical binary data input.

[0013] In some embodiments, the metadata includes a correlation value representing a virtual quantum entanglement measure of the classical binary data input.

[0014] In some embodiments, the metadata comprises a value representing an occurrence count of a data pattern in the classical binary data input.

[0015] In some embodiments, the counts of occurrences of data patterns in the classical binary data input comprise counts representing unique data patterns in proper or improper subsets of the classical binary data input.

[0016] In some embodiments, the value of the statistical operator comprises a statistical probability generated from a count of occurrences of a data pattern in the classical binary data input.

[0017] In some embodiments, applying a swap gate to the metadata to compress the metadata comprises swapping occurrences of a data pattern having a maximum count with a bit string that is shorter than the data pattern having the maximum count, the bit string comprising a concatenation of i) a virtual quantum entanglement measure of a data pattern having a minimum count and ii) the remaining bits of the data pattern having the minimum count, excluding the final bit of the data pattern having the minimum count.

[0018] In some embodiments, the metadata includes a Classical Quantum Multi-Element (CQME) system, the CQME system including the classical binary data input divided into data packets, each data packet including a correlation value representing a virtual quantum entanglement measure and a data pattern defining a type of the data packet.

[0019] In some embodiments, the value of the statistical operator comprises a probability that defines a statistical characteristic of the CQME.

[0020] In some embodiments, the metadata includes an optimal arithmetic complex that characterizes the classical binary data input and preserves the value of the statistical operator, the optimal arithmetic complex being selected from a plurality of candidate arithmetic complexes, each of the plurality of candidate arithmetic complexes corresponding to a virtual quantum state in a respective virtual Hilbert space.

[0021] In some embodiments, the optimal arithmetic complex i) has the same length as the classical binary data input, ii) has the same entropy as the classical binary data input, and iii) contains at least one singular point.

[0022] In some embodiments, the plurality of candidate arithmetic complexes form a superposition surface of the virtual quantum state.

[0023] In some embodiments, the optimal arithmetic complex is selected from the plurality of candidate arithmetic complexes through virtual time measurements of the virtual quantum states.

[0024] In some embodiments, the method further includes outputting the compressed classical binary data input; and iteratively processing the compressed classical binary data input until a target data compression ratio is achieved, the iterative processing including, for each iteration, performing a classical operation on the classical binary data input for the iteration to generate metadata for the iteration, applying a swap gate to the metadata for the iteration to compress the metadata for the iteration, and providing the compressed metadata for the iteration as input for a subsequent iteration.

[0025] In general, another innovative aspect of the subject matter described herein may be embodied in a method for decompressing a classically compressed binary data input, the method including: obtaining a compressed classical binary data input; generating candidate metadata for the compressed classical binary data input, the metadata including values ​​of a statistical operator for respective portions of the compressed binary data input, the statistical operator being based on an ensemble interpretation of quantum mechanics; applying a kernel filter to the candidate metadata based on the value of the statistical operator to identify valid metadata for the classically compressed binary data input; applying a swap gate to the valid metadata to decompress the valid metadata, the swap gate swapping data as a one-way function, the application of the swap gate being defined by the value of the statistical operator for the valid metadata; and providing the decompressed valid metadata as the decompressed compressed classical binary data input.

[0026] Each of the above and other embodiments may optionally include, alone or in combination, one or more of the following features: In some embodiments, the decompressed compressed classical binary data input has the same entropy as the classically compressed binary data input.

[0027] In some embodiments, providing the decompressed valid metadata as the decompressed compressed classical binary data input comprises performing a logical inverse calculation.

[0028] In some embodiments, applying the kernel filter to the candidate metadata includes identifying metadata corresponding to a portion of the compressed binary data input that: i) does not contain a unique data pattern; ii) satisfies a condition for virtual quantum entanglement; and iii) has a maximum bit length.

[0029] In some embodiments, applying a swap gate to the valid metadata to decompress the valid metadata includes identifying a second most unique data pattern in a portion of the compressed binary data input; identifying a most unique data pattern in a portion of the compressed binary data input; and swapping an occurrence of a data pattern representing a virtual quantum entangled value that occurs before the second most unique data pattern with a bit string longer than the virtual quantum entangled value, wherein the bit string longer than the virtual quantum entangled value corresponds to a data pattern with a highest repeat count; and swapping an occurrence of a data pattern representing a data pattern with a highest repeat count that occurs before the second most unique data pattern and the most unique data pattern with a bit string longer than the data pattern with a highest repeat count, wherein the bit string longer than the data pattern with a highest repeat count corresponds to a concatenation of the virtual quantum entangled value and an inverse of a pattern structure value.

[0030] In some embodiments, the metadata includes, for each of one or more predetermined sizes, a classical binary data input divided into a plurality of data packets having a length equal to the predetermined size, the one or more predetermined sizes corresponding to a respective virtual Hilbert space.

[0031] In some embodiments, the metadata includes values ​​that represent data patterns that occur in classical binary data input.

[0032] In some embodiments, the metadata includes a correlation value representing a virtual quantum entanglement measure of the classical binary data input.

[0033] In some embodiments, the metadata comprises a value representing an occurrence count of a data pattern in the classical binary data input.

[0034] In some embodiments, the counts of occurrences of data patterns in the classical binary data input comprise counts representing unique data patterns in proper or improper subsets of the classical binary data input.

[0035] In some embodiments, the values ​​of the statistical operators include statistical probabilities and identifiers generated from counts of occurrences of data patterns in the classical binary data input.

[0036] In some embodiments, the metadata includes a Classical Quantum Multi-Element (CQME) system, the CQME system including the classical binary data input divided into data packets, each data packet including a correlation value representing a virtual quantum entanglement measure and a data pattern defining a type of the data packet.

[0037] In some embodiments, the value of the statistical operator comprises a probability that defines a statistical characteristic of the CQME.

[0038] In some embodiments, the metadata includes an optimal arithmetic complex that characterizes the classical binary data input and preserves the value of the statistical operator, the optimal arithmetic complex being selected from a plurality of candidate arithmetic complexes, each of the plurality of candidate arithmetic complexes corresponding to a virtual quantum state in a respective virtual Hilbert space.

[0039] In some embodiments, the optimal arithmetic complex i) has the same length as the classical binary data input, ii) has the same entropy as the classical binary data input, and iii) contains at least one singular point.

[0040] In some embodiments, the plurality of candidate arithmetic complexes form a superposition surface of the virtual quantum state.

[0041] In some embodiments, the optimal arithmetic complex is selected from the plurality of candidate arithmetic complexes through virtual time measurements of the virtual quantum states.

[0042] In some embodiments, the method further includes outputting the decompressed classically compressed binary data input and iteratively processing the compressed classical binary data input until a target data decompression rate is achieved, the iterative processing including, for each iteration, generating candidate metadata for the classically compressed binary data input input for the iteration, applying a kernel filter to the candidate metadata for the iteration to identify valid metadata for the iteration, applying a swap gate to the valid metadata to decompress the valid metadata for the iteration, and providing the decompressed valid metadata for the iteration as input for a subsequent iteration.

[0043] In general, another innovative aspect of the subject matter described herein can be embodied in a system including a first chipset, the first chipset including a first data port for receiving input data and a second data port for providing a final arithmetic complex, the first chipset configured to perform an operation including transforming the input data into a final arithmetic complex, the final arithmetic complex including a first intermediate arithmetic element (IAE) data set, a second IAE data set, and a third IAE data set, the final arithmetic complex being a virtual quantum representation of the input data, the first IAE data set including first component values ​​defining virtual quantum entanglement of the input data and second component values ​​defining a data pattern structure of the input data, the second IAE data set including statistical operators defining counts of data patterns associated with the data patterns of the first IAE data set of the input data, and the third IAE data set including an ancillary data set defining statistical probabilities associated with the input data.

[0044] Each of the above and other embodiments may optionally include one or more of the following features, alone or in combination: In some embodiments, the system further includes a second chipset arranged to receive a final arithmetic complex as an input to the second chipset, and the second chipset configured to compress at least a portion of the final arithmetic complex into a compressed data set.

[0045] In some embodiments, the system further includes a third chipset arranged to receive the compressed data set as input to the third chipset, and the third chipset configured to decompress the compressed data set to provide the input data.

[0046] In some embodiments, the first chipset and the second chipset are integrated on a single substrate.

[0047] In some embodiments, transforming the input data into the final arithmetic complex comprises generating a plurality of candidate Hilbert space (HS) data sets from the input data.

[0048] In some embodiments, the first chipset is configured to instantiate a configuration table, the first chipset further including a first memory, a parallel address data bus, and a plurality of HS storage modules, and generating the plurality of candidate HS data sets includes: obtaining the input data from the first memory via the parallel address bus; obtaining a plurality of size parameters from the configuration table; and transmitting a plurality of copies of the input data in parallel from the parallel address bus to the plurality of HS storage modules, respectively, wherein each copy of the plurality of copies of the input data is transmitted at a different bit transmission size according to a respective size parameter from the plurality of size parameters.

[0049] In some embodiments, the system further includes a second memory, and generating the plurality of candidate HS data sets includes generating a plurality of intermediate arithmetic complexes associated with different sizes, each intermediate arithmetic complex including a corresponding data pattern array into which the input data is distributed based on a size associated with the intermediate arithmetic complex, a corresponding statistical operator matrix, and a corresponding ancillary matrix including statistical probabilities of the corresponding data pattern array, and storing the plurality of intermediate arithmetic complexes in the second memory as the plurality of candidate HS data sets.

[0050] In some embodiments, for each intermediate arithmetic complex, the input data is divided into one or more data patterns, each data pattern of the one or more data patterns having a size associated with the intermediate arithmetic complex, the one or more data patterns are each stored across one or more elements of a corresponding data pattern array, and for each intermediate arithmetic complex, the corresponding statistical operator matrix includes, for each different data pattern in the corresponding data pattern array, a count of the data pattern and an index value corresponding to the data pattern.

[0051] In some embodiments, for each data pattern of said one or more data patterns, a leading bit of said data pattern is virtual quantum entanglement and one or more remaining bits of said data pattern are pattern structures.

[0052] In some embodiments, for each intermediate arithmetic complex, the statistical probability of the corresponding ancillary matrix includes the most frequently occurring data pattern in the corresponding data pattern array and the least frequently occurring data pattern in the data pattern array.

[0053] In some embodiments, generating the plurality of intermediate arithmetic complexes includes, for each copy of the input data of the plurality of copies of the input data transmitted from the parallel address bus to the plurality of HS storage modules, detecting a pre-circuit breaker event, detecting a final circuit breaker event, and determining completion of the intermediate arithmetic complex corresponding to the copy of the input data upon detecting the final circuit breaker event.

[0054] In some embodiments, converting the input data into the final arithmetic complex comprises combining the intermediate arithmetic complexes into a final arithmetic complex; and filtering the potential final arithmetic complexes to select the final arithmetic complex.

[0055] In some embodiments, filtering the plurality of potential final arithmetic complexes to select the final arithmetic complex comprises applying fuzzy logic rules to the plurality of potential final arithmetic complexes.

[0056] In some embodiments, the system further includes a second chipset arranged to receive a final arithmetic complex as an input to the second chipset, and the second chipset configured to compress at least a portion of the final arithmetic complex into a compressed data set.

[0057] In some embodiments, the second chipset is configured to compress at least a portion of the final arithmetic complex into a compressed data set based on a statistical probability associated with the first IAE data set.

[0058] In some embodiments, the second chipset includes a plurality of swap gates configured to compress the final arithmetic complex into a compressed data set.

[0059] In some embodiments, the second chipset includes a first error correction module configured to enable processing of data by the plurality of swap gates and disable processing of data by the plurality of swap gates.

[0060] In some embodiments, the first error correction module is configured to identify a least frequently occurring data pattern in the final arithmetic complex and disable processing of data when the least frequently occurring data pattern is identified in the final arithmetic complex.

[0061] In some embodiments, the second chipset includes a second error correction module configured to determine when data is present at an output port of the second chipset and to cause the plurality of swap gates to read new data when it is determined that the data is present at the output port of the second chipset.

[0062] In some embodiments, the plurality of swap gates include a plurality of sub-modules, the plurality of sub-modules including a first swap module configured to identify when a least frequently occurring data pattern of the final arithmetic complex is present and to write the least frequently occurring data pattern to the final arithmetic complex.

[0063] In some embodiments, the plurality of sub-modules include a second swap module configured to identify when a most frequently occurring data pattern of a final arithmetic complex is present and to perform a first swap operation on the final arithmetic complex to obtain at least one first swapped parameter, wherein performing the first swap operation includes replacing a last bit of a least frequently occurring data pattern.

[0064] In some embodiments, the plurality of swap gates are configured to perform a second swap operation on a least frequently occurring data pattern in the final arithmetic complex to obtain at least one second swapped parameter, and the plurality of sub-modules include a third swap module configured to identify when the least frequently occurring data pattern in the final arithmetic complex is present and to store the at least one second swapped parameter in a memory.

[0065] In some embodiments, the plurality of sub-modules includes a fourth swap module configured to pass an else-case data pattern from the final arithmetic complex to the output port of the second chipset, the else-case data pattern including a data pattern not identified by the first sub-module, the second sub-module, and the third sub-module.

[0066] In some embodiments, the second chipset is configured to return the compressed data set to the first chipset.

[0067] In some embodiments, the method further comprises a third chipset configured to decompress the compressed data set to obtain a decompressed data set.

[0068] In some embodiments, the third chipset includes a plurality of reverse unidirectional swap gates configured to decompress the compressed data set.

[0069] In some embodiments, the third chipset is configured to decompress the compressed data set by performing operations including receiving the compressed data set as an input data stream, generating candidate metadata for the compressed data set, and applying a plurality of kernel filters to the candidate metadata to identify valid metadata.

[0070] In some embodiments, applying the plurality of kernel filters to the candidate metadata includes identifying portions of the compressed data set that do not contain unique data patterns, satisfy conditions for virtual quantum entanglement, and have a specified bit length.

[0071] In some embodiments, the third chipset operations further include applying a plurality of inverse unidirectional swap gates to the valid metadata to obtain the decompressed data set.

[0072] In some embodiments, applying the plurality of reverse unidirectional swap gates includes identifying an occurrence of a second most unique data pattern occurring in the compressed data set as a first data event; swapping each occurrence of a data pattern corresponding to a virtual entangled value in the compressed data set prior to the first data event with a first predefined bit string; and swapping each occurrence of a data pattern associated with a highest number of occurrences in the compressed data set prior to the first data event with a second predefined bit string.

[0073] In general, another innovative aspect of the subject matter described herein may be embodied in a chipset configured to perform operations including converting a classical data set to a classical quantum multi-element (CQME) data set and an ancillary matrix containing statistical properties of the CQME data set.

[0074] Each of the above and other embodiments can optionally include one or more of the following features, alone or in combination: In some embodiments, the operation includes compressing the CQME data set.

[0075] In some embodiments, compressing the CQME data set includes applying at least one one-way swap gate to the CQME data set.

[0076] In some embodiments, the operation includes decompressing the compressed CQME data set.

[0077] The subject matter described herein can be implemented in particular embodiments to realize one or more of the following advantages.

[0078] Systems implementing the currently described techniques can achieve the desired amount of lossless data compression. Furthermore, because they do not use classical compression information theory, the compression is endless, in the sense that the compressed data stream can be repeatedly fed for recompression. In classical compression, the algorithm performs a first round of compression and a second round of compression, which has the opposite effect: the second round of compression expands the data instead of compressing it. This occurs because classical compression information theory searches for repetitions or common patterns and then replaces them by referencing an index header. Classical compression changes the entropy of the input file, eliminating repetitions and patterns, limiting the algorithm's ability to perform lookups for repetitions.

[0079] Furthermore, systems implementing the presently described technology can store inputs and outputs in memory as lookup tables. The number of inputs and outputs is theoretically unlimited, but in practice is limited only by the hardware capabilities of the chip. In some embodiments, the lookup tables can be compressed, increasing optimal utilization of storage space and theoretically preventing the module from running out of storage space. Therefore, logical reverse computing is achieved (e.g., as a result of the presently described one-way swap gates) because data is not lost and can be retrieved from the storage memory. Logical reverse computing has further been confirmed, with the presently described AAR, BFX, and rBFX chips generating a lower thermal signature compared to existing classical computing. This is due to the fact that the processor is not configured to recalculate the output from the inputs. Instead, data can simply be looked up, generating significantly less heat than AND, OR, NAND, and other classical gates. Thus, if a closed-state Turing machine is prepared using the AAR, BFX, and rBFX chips for all possible inputs and outputs currently described, the output can be inverted without computation, since the output can be inverted to the input based solely on a memory lookup.

[0080] Furthermore, systems implementing the presently described techniques are capable of transmitting compressed data over wireless, wired, optical, classical, and other non-classical modes, enabling high-speed data transmission, which can be further accelerated by implementing rainbow or lookup tables for frequently occurring data streams.

[0081] Additionally, systems implementing the presently described techniques incorporate various mechanisms for improving processing efficiency, for example, by discarding the processing of some parallel data streams based on corresponding criteria.

[0082] The details of one or more embodiments of the subject matter herein are set forth in the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description and the claims. [Brief explanation of the drawings]

[0083] [Figure 1A] FIG. 1 is a block diagram of an exemplary AAR chipset and BFX chipset that perform data compression. [Figure 1B] FIG. 1 is a block diagram illustrating the connections within a mainboard including an AAR chipset and a BFX chipset. [Figure 2] FIG. 2 is a flow diagram of a high-level exemplary process for data compression. [Figure 3A] 1 illustrates an exemplary application of the presently described technology for high-speed Internet backhaul transmission. [Figure 3B] 1 illustrates an exemplary application of the presently described techniques to achieve a target storage space. [Figure 4] FIG. 1 is a block diagram of an exemplary board design for the AAR chipset. [Figure 5] FIG. 1 is a block diagram illustrating an exemplary arrangement of AAR chip elements. [Figure 6] FIG. 1 is a block diagram illustrating an exemplary address parallel data bus #1 (DB1). [Figure 7] FIG. 1 is a block diagram illustrating an exemplary bit-defined parallel data bus #2 (DB2). [Figure 8] FIG. 2 is a block diagram illustrating exemplary intermediate arithmetic elements IAE[1], IAE[2], and IAE[3]. [Figure 9A] FIG. 1 is a block diagram of an exemplary process for creating a register matrix in IAE [2]. [Figure 9B] FIG. 10 is a block diagram of an exemplary process for filling the register matrix of the IAE [2] with data. [Figure 9C] FIG. 10 is a block diagram showing the completion of the write operation into the Hilbert space of IAE[1] and IAE[2]. [Figure 10] FIG. 1 is a block diagram illustrating an exemplary HS generator architecture. [Figure 11A] FIG. 2 is a block diagram illustrating the operations performed by a super positioning plane (SPP) generator. [Figure 11B] 1 shows an exemplary PCB and FCB detection chart. [Figure 11C] FIG. 1 is a block diagram illustrating an exemplary process for generating an SPP storage matrix and applying fuzzy logic to obtain the final output. [Figure 12A] FIG. 1 is a block diagram illustrating the generation of IAE[1] and IAE[2] from an exemplary input binary stream. [Figure 12B] FIG. 1 is a block diagram illustrating exemplary pattern types, pattern structures, and entangled data patterns (DPs). [Figure 12C] FIG. 10 is a block diagram illustrating reading an exemplary input binary stream and adding a count value to IAE[2]. [Figure 12D] FIG. 10 is a block diagram illustrating an exemplary process for generating superimposed surfaces of intermediate arithmetic complexes and obtaining a final arithmetic complex as an output. [Figure 13] FIG. 1 is a block diagram of an exemplary BFX board design. [Figure 14] FIG. 1 is a block diagram illustrating sub-modules included in a one way swap gate (SWAPG). [Figure 15] FIG. 12B is a block diagram for implementing a one-way swap gate for the example input binary data streams IAE[1] and IAE[3] of FIGS. 12A-12D. [Figure 16] 1 is a flow diagram of a process for compressing an input data stream that has been partitioned into data packets according to a variable SIZE. [Figure 17] FIG. 1 is a flow diagram of a process for compressing classical binary data input. [Figure 18]FIG. 1 is a block diagram of an exemplary rBFX board design. [Figure 19] FIG. 10 is a block diagram showing how data is processed in the rBFX swap gate. [Figure 20] FIG. 17 is a flow diagram of a process for decompressing an exemplary data stream compressed according to the exemplary process of FIG. [Figure 21] FIG. 1 is a flow diagram of a process for decompressing classically compressed binary data input. [Figure 22] For an example bitstream, the value of the variable SIZE is varied to show the compression ratio achieved using the techniques described in this disclosure. [Figure 23] Shows statistics for each round in multiple compression processes. [Figure 24] FIG. 1 is a block diagram of a computing device that can be used to implement the systems and methods described herein. DETAILED DESCRIPTION OF THE INVENTION

[0084] Like reference numbers in the various drawings indicate like elements.

[0085] (overview) This disclosure describes techniques for compressing and decompressing classical data using quantum mechanical principles. In particular, the techniques include embedded hardware and software routines that apply quantum mechanical logic taken from the ensemble interpretation of quantum mechanics and other quantum mechanical principles, such as time measurement, entanglement, and superposition, to classical data streams to achieve logical reverse computing.

[0086] The ensemble interpretation of quantum mechanics states that quantum multi-element (QME) systems can be identified by the derivation of statistical observable properties, or simply mathematical objects known as statistical probabilities, instead of exhaustively enumerating all qubit combinations. Statistical probabilities are generated by statistical operators, which are dynamically defined variables for a quantum system. The generation and definition of statistical probabilities for quantum states replaces the requirement to list the qubit states and gate corrections of a QME system. This allows a QME system to be defined solely by its statistical probabilities, rather than the states of its individual qubits. With this representation, only the metadata of the QME, e.g., statistical probabilities, are stored in storage, resulting in significant savings in storage and memory space. However, while the ensemble interpretation of quantum mechanics is correct in the quantum realm, it cannot be directly applied to classical computation.

[0087] This disclosure includes a novel process that allows classical data to be represented as a classical quantum multi-element (CQME) system (the term "system" in this context is used to refer to the representation of a classical data set as a set of statistical operators and probabilities that characterize the input data). In the CQME representation, the virtual quantum state of each data element is defined by statistical operators and statistical probabilities, and the output is maintained as a classical data stream output. This is achieved by transitioning the classical data using quantum mechanical processes that convert the data into a virtual quantum state, generating statistical operators and probabilities, classical data waves, and superposition planes, and applying fuzzy logic to output the classical input as a CQME in classical form. The final output includes a CQME system and an associated ancillary matrix that contains the statistical properties of the CQME system. This transition is achieved by decomposing the classical data stream into a binary set and then further dividing it into two components: first, a power or virtual quantum entanglement measure, and second, a data pattern (DP) that defines the type of data set. This allows classical data streams to be represented in quantum mechanical form, thereby applying ensemble interpretations to generate statistical operators and represent the data as a CQME system. By representing novel representations of classical data as CQME systems, statistical operators can be dynamically generated to represent the data patterns of the original classical data stream. The distribution of data patterns in CQMEs is represented by probabilities that allow for compression and decompression of the original classical data stream. The CQME system (with data and statistical probabilities) is represented as waves that allow for operations using quantum mechanical principles such as time measurement, wave collapse, and fuzzy logic for compression.

[0088] Representing classical data as a CQME involves constructing a novel interface, referred to in this disclosure as a quantum-classical interface, between the classical data domain and the quantum data domain, which accepts classical data, converts the classical data into a quantum mechanical representation, performs classical and / or quantum operations on the quantum mechanical representation, and outputs the processed data as classical data.

[0089] The techniques described in this disclosure may be implemented using one or more of an Advanced Arithmetic Rotations (AAR) chipset (also referred to as "chip" for short) configured to process classical data input and generate a corresponding CQME data set (also referred to as CQME for short), a Binary Fourier X-gate (BFX) chip configured to compress output received from the AAR chip, and a Reverse Binary Fourier X-gate (rBFX) chip configured to decompress data compressed by the BFX chip.

[0090] The AAR chip receives input data and converts the classical data into a CQME by identifying predefined statistical operators. The AAR chip generates three matrices, IAE[1], IAE[2], and IAE[3], referred to herein as Intermediate Arithmetic Elements (IAEs). These are collectively referred to herein as arithmetic compounds. The first matrix, IAE[1], contains a data stream whose elements are represented by a data pattern containing two components. The first component is a bit representing the power or virtual quantum entanglement value of the data pattern. The second component contains the remaining bits, which define the pattern of the stream. This representation converts the data stream into a CQME for future quantum mechanical applications. Each element of the CQME has a data pattern represented by an index value in the second matrix, IAE[2]. The index value in IAE[2] corresponds to a dynamic memory, called a register value, that holds a count of the repetitions of the data pattern in IAE[1]. The matrix, IAE[2], represents the statistical distribution or statistical operator of the CQME. The third matrix IAE[3] is a two-dimensional matrix generated by the AAR chip and is called the ancilla matrix. The third matrix IAE[3] is populated by the AAR chip to hold the statistical probabilities of the CQME. The AAR chip is thus configured to generate data or CQME in IAE[1] and a series of statistical operators in IAE[2], allowing the AAR chip to generate statistical probabilities of the input data stream and input them to IAE[3].

[0091] The output of the AAR chip can be fed to various applications, separate from the BFX chip. Using the AAR chip's output, each application can independently process the output, such as the statistical probabilities of IAE [3] or the statistical operators of IAE [2], for its own novel application. The AAR chip also performs quantum mechanical logic on the CQME, generating representations of the CQME data as waves and superposition surfaces, creating an array of CQME streams that can represent the input data in terms of statistical probabilities. To find a single optimal and error-free CQME in the IAE [1] or statistical operators in the IAE [2] system, the AAR chip applies logic operations based on quantum mechanical principles, such as time scaling, superposition onto classical data, and fuzzy logic, to the classical data to generate the final output that is fed to the BFX chip.

[0092] The BFX chip accepts CQMEs, such as data from the AAR chip, and compresses them using multiple swap gates (described below with reference to Figures 13 and 14) defined by IAE[3] statistical probabilities. The output of the ancillary matrix is ​​dynamic. The swap gates are one-way arithmetic gates in the BFX chip, unlike traditional classical swap gates. Rather than simply substituting A and B, they are configured to dynamically swap data as one-way functions. These swap gates are dynamically defined by the values ​​of IAE[2] statistical operators (e.g., IAE[3] probabilities) to enable data compression. The compressed data is then rerouted to the AAR chip, where another round of compression begins. The operator can send the data back as many times as necessary to continue data compression or direct it to an external output.

[0093] The rBFX chip is configured to decompress, for example, data output from the BFX chip. The rBFX chip is configured to read the input data and recreate the original output using a logic engine that reinterprets the CQME input into classical data.

[0094] 1A is a block diagram of an exemplary AAR chipset 120 and a BFX chipset 130 performing an exemplary data compression process. FIG. 1A shows one iteration of data compression, where input data 100 is processed to output compressed data 110. However, the exemplary data compression process may be repeated to achieve a target amount of compression, with each iteration providing the compressed data output from the previous iteration as input for the current iteration.

[0095] In stage (A) of the exemplary data compression process, input data 100 is provided from a router or classical computing device to AAR chipset 120 via an input port on mainboard 101. In this example, AAR chip 103 and BFX chip 107 are integrated on one board 101 and may be updated based on specific integration requirements. The input data may include data from any source 100A, such as a network card, serial port, storage device, BUS, wireless, antenna port, or optical fiber. The input port may be a Bluetooth® port, an infrared wired port, a serial port, a wireless port, or any other type of connection for transmitting data.

[0096] In stage (B) of the exemplary data compression process, input data 100 is processed by AAR chipset 120 to generate a data object referred to herein as an arithmetic complex. Figure 1A provides a high-level overview of the operations performed by AAR chipset 120. A detailed description of the operations performed by AAR chipset 120 is described in detail below with reference to Figures 4-11C.

[0097] Input data 100 is sent from the input port to AAR-IP1 input port 102 on AAR chipset 120. In some embodiments, input data 100 may be a non-binary data stream. In these embodiments, AAR chipset 120 may convert input data 100 to a binary format for further processing, for example, using standard techniques.

[0098] To generate the arithmetic complex, the AAR chipset 120 is configured to process input data in binary format and store the processed data in a format referred to herein as Hilbert space (HS). In this disclosure, the term "Hilbert space" is understood to refer to a virtual Hilbert space similar to the state space of pure states of a quantum mechanical system in a mathematically rigorous formulation of quantum mechanics. This similarity will become more apparent, for example, in the discussion of FIG. 4 below. This particular format allows for logical inverse calculations, as described below with reference to FIG. 3B. The AAR chipset 120 is configured to generate a multidimensional variable Temp_VAR Hilbert space having the following elements: (a) input, (b) output, and (c) hidden variables, or references to previous ancillary matrices or IAEs[3] (ancillary matrices and IAEs[3] are described in more detail below). A pointer to the Temp_VAR Hilbert space is stored in the Hilbert space and passed to the AAR chipset 120 for future / further processing. This allows for faster processing of similar inputs with sophisticated lookups, as the Hilbert space contains sophisticated relationships and dot products of previous inputs and outputs. In subsequent iterations of compression, the data, Temp_VAR Hilbert space, is further compressed to minimize space requirements in memory, storage, etc., and may contain several more matrices and their complex dot products that are cross-referenced to identify input and output data. These complex relationship values ​​are held in a Hilbert space defined by a vector value, with a bit size.

[0099] In the first iteration of data compression, the Hilbert space is vector-valued, defined by the input bit size. In subsequent iterations of recompressing the data, the values ​​take the form of scalars that appear when the AAR chipset 120 reroutes the output to the input port. The rerouted data is derived by combining or multiplying several vectors to form scalar values. The partitioning and scalar relationships are stored in a separate Hilbert space for enhanced / accelerated processing, enabling logical inversion. These dot-product scalar values ​​are mapped as interconnected 3D arrays in classical storage and as webs of interconnected states in quantum storage. These values ​​can also be stored as 3D geometric values, which reduces interim memory requirements. A scalar value in a Hilbert space is also defined as the dot product of a state, previous index value, CQME, and an ancillary matrix, forming a Euclidean vector space.

[0100] After the AAR chipset 120 processes the input data 100, the AAR chipset 120 is configured to forward the processed data via three separate outputs 104, AAR-OP1, AAR-OP2, and AAR-OP3, to temporary storage 105. The temporary storage 105 is configured to either hold the value or pass it to the BFX chipset 130 according to operator-defined settings (e.g., see configuration table 403 in FIG. 4 ). The value can be held for a save event or forwarded in real time to the next in-line board / chip for time-critical or real-time processing.

[0101] During stage (C) of the exemplary data compression process, BFX chipset 130 is configured to receive data 106 from temporary storage 105, compress the received data, and write the compressed data as a binary stream 108 to an output port. The output port may be a Bluetooth port, an infrared wired port, a serial port, a wireless port, or any other type of connection for transmitting data. FIG. 1A provides a high-level overview of the operations performed by BFX chipset 130. A detailed description of the operations performed by BFX chipset 130 is described in more detail below with reference to FIGS. 12-14.

[0102] During stage (D) of the exemplary data compression process, the binary stream 108 is passed to an external connection device 109 configured to accept a classical binary stream, such as a network card, a serial port, a storage device, a BUS, a radio, an antenna port, or an optical fiber. The external connection device 109 can then provide a compressed data output 110, for example, as an output to be stored or transmitted to another device, or as an input for a subsequent compression iteration.

[0103] An exemplary data compression process ensures that all application of quantum mechanical, ensemble interpretation, and processing logic to the data occurs in the AAR chip 103 and the BFX chip 107, while preserving the output binary stream 108 as a classical data stream. This process provides a quantum-classical interface that accepts binary input, transforms and applies quantum mechanical logic to the classical data, and outputs a CQME system in classical data form. Thus, an embodiment of the quantum-classical interface generates statistical probabilities for any classical system expressed in classical form as a virtual quantum state description.

[0104] As described above, data compressed by the AAR chipset 120 and the BFX chipset 130, such as data 110, can be decompressed by the rBFX chip. Although not shown in FIG. 1A, the rBFX chip is configured to reuse some components and logic routines from the AAR chip 103 and the BFX chip 107. These components retain the ensemble interpretation and quantum-classical interface properties from the AAR chip 103 or the BFX chip 107 to process input data.

[0105] FIG. 1B shows a block diagram of the connections within the main board 101 of FIG. 1A. The AAR chipset board 150 (see also FIG. 4 below) includes one input port, AAR-IP1 102, and three output ports, AAR-OP1 154a, AAR-OP2 154b, and AAR-OP3 154c. The input port, AAR-IP1 102, receives binary input data for processing by the AAR chip 103. The output ports, AAR-OP1 154a, AAR-OP2 154b, and AAR-OP3 154c, provide data processed by the AAR chip 103 to binary or chemical storage 156. For example, as described above, the output of the AAR chip includes classical values ​​IAE[1], IAE[2], and IAE[3] retrieved from temporary storage 105 of FIG. 1. These classical values ​​(bits) can be stored directly in the binary storage.

[0106] BFX chipset board 152 (see also FIG. 13 below) includes three input ports BFX-IP1, BFX-IP2, and BFX-IP3, e.g., input port 158, and two output ports BFX-OP1 and BFX-OP2, e.g., output port 160. Input ports BFX-IP1, BFX-IP2, and BFX-IP3 receive data from binary or chemical storage 156, e.g., values ​​IAE[1], IAE[2], and IAE[3], for processing by BFX chip 107. Output ports BFX-OP1 and BFX-OP2 provide data processed by BFX chip 107, e.g., compressed arithmetic complex AC and ancillary matrix AM, as compressed data outputs.

[0107] 2 is a flow diagram of a high-level exemplary process 200 for data compression. The exemplary process 200 may be applied to achieve high-speed data transfer, storage, and / or processing. For convenience, the exemplary process 200 is described as being performed by a system including an AAR chipset and a BFX chipset. For example, the AAR chipset and BFX chipset described herein and appropriately programmed in accordance with the present disclosure may perform the exemplary process 200.

[0108] The AAR chip accepts classical data as input and converts the classical data input to binary data (step 201). The AAR chip then processes the binary data to generate a classical data output, e.g., a classical arithmetic complex, or a quantum data output, e.g., a quantum arithmetic complex that can be stored in chemical, quantum, or classical storage (step 202). The operations performed by the AAR chip are classical computational operations and are described in more detail below with reference to Figures 4-11C.

[0109] The BFX chip accepts the output from the AAR chip and processes the output (step 203) to produce classically compressed data (step 204). The BFX chip providing classical data as an output in step 204 ensures that the exemplary process 200 can be applied to any two nodes, points, and / or interfaces that exchange data.

[0110] The operations performed by the BFX chip may include classical or quantum operations. For example, if the BFX chip receives classical data output from the AAR chip, the BFX chip may compress the classical data using a classical one-way swap gate (step 203A). As another example, if the BFX chip receives quantum data output from the AAR chip, the BFX chip may compress the quantum data using a quantum gate (step 203B). The operations performed by the BFX chip are described in further detail below with reference to Figures 12-14.

[0111] The fact that the processing performed in step 203 can occur on a quantum or classical computing device does not change the types of inputs and outputs: that is, exemplary process 200 takes classical data as input and outputs compressed classical data.

[0112] In exemplary process 200, quantum mechanical logic is applied to classical data in step 202 (to generate "quantum-inspired classical data"). While quantum gates can be implemented in step 203B, in some embodiments, step 203A may serve as a default option for classical gates that process the quantum-inspired classical data to obtain an output.

[0113] FIG. 3A illustrates an exemplary application of the presently described compression and decompression techniques for high-speed Internet backhaul transmission. In this example, router A 301 is a general-purpose router that accepts classical data 300 from a source, such as a wireless network, a LAN network, an independent data source, or an optical, chemical, or quantum-classical source. Router A passes the classical data to an AAR+BFX board 302, which compresses the classical data, such as main board 101 in FIG. 1. The compressed data 303 is passed to the Internet, which includes a series of classical general-purpose routers, such as routers that do not include an AAR+BFX board. The general-purpose router bounces the data (304) without compressing or modifying it. The data is then sent to a final transmission endpoint (305). Upon arrival at the final transmission endpoint, the data is fed to an rBFX chip 306, which decompresses the data and forwards it to router B 307 for output or further classical processing.

[0114] FIG. 3B illustrates an exemplary application of the presently described techniques to achieve improved storage space. In this example, a computing device's hard drive stores data. The AAR+BFX board can store data to a storage location through a statistical probability lookup. The lookup may be compressed for further memory savings and can be decompressed by the rBFX board. This is believed to enable the hardware to have unlimited storage space in certain embodiments (the term "unlimited" in this disclosure is understood to refer to an amount of storage space constrained only by the time limits of processing).

[0115] Although not shown in Figures 3A or 3B, other applications of the presently described technology include embedding the chip between two circuits in any device that enables logical inverse calculations or data transfer between nodes, boards, adapters, or terminals. This is possible because the AAR+BFX generates highly compressed data, and a receiver with an rBFX chip can decompress the received stream. This concept can be extrapolated to any system with storage, transmitters, receivers, classical or quantum interfaces integrated with AAR, BFX, or rBFX boards that communicate over the Internet, wired, wireless, optical, radio, microwave, laser, or other data communication protocols and layers.

[0116] As another example, because a quantum-classical interface allows for unlimited storage space, whether disk, chemical, quantum, or other forms, the quantum-classical interface allows the presently described invention to perform logical inverse computations. A quantum-classical interface creates a bridge between chips, memory, disks, network adapters, any type of port, system, device, or node in a classical machine, and has the ability to hold and store inputs and outputs. Therefore, processes sent, performed, read, written, processed, simulated, or passed on to a classical machine are not lost. By providing an output, inputs can be delivered almost instantly by lookup, and vice versa, without the need to process the same input again. This is the core definition of logical inverse computations and the application of the presently described invention.

[0117] AAR Chipset: An Exemplary Technique for CQME Generation with Statistical Operators Using an Ensemble Interpretation of Quantum Mechanics As described above with reference to FIGS. 1 and 2, the AAR chipset is configured to process classical data inputs and generate corresponding classical quantum multi-elements (CQMEs). The CQMEs are part of an object referred to herein as an "arithmetic complex." That is, the AAR chipset processes input data to generate an arithmetic complex that includes a CQME. An arithmetic complex is a mathematical structure that stores matrices as subelements and is generated by logical arithmetic rotations. Each rotation takes an input and generates an arithmetic complex (in this disclosure, the term "rotation" is understood to refer to the complete process the input undergoes to determine the arithmetic complex). By rotating the same input again, a new arithmetic complex can be formed from a previously derived arithmetic complex. This cyclical process of generating arithmetic complexes is referred to herein as Advanced Arithmetic Rotations (AAR).

[0118] An arithmetic complex contains three intermediate arithmetic elements IAE[1], IAE[2], and IAE[3]. The subelements of these three arithmetic complexes are combined to form elements that are quantified by observable statistical patterns in matrices called statistical operators. An arithmetic complex is a combination of a matrix with a CQME, a statistical operator, and an ancillary matrix.

[0119] The intermediate computation element IAE [1] contains the original data, viewed as having quantum properties, as a CQME with statistical operators on the virtual entanglement value (leading bit, e.g., see 818 in FIG. 8 ) and the data pattern (DP) (e.g., see 806 in FIG. 8 ). In this disclosure, the use of the term "quantum entanglement" or "quantum entanglement value" is understood to refer to a correlation or correlation value between objects that is similar to the physical phenomenon of quantum entanglement, and is thus referred to herein as "virtual quantum entanglement" or "virtual quantum entanglement value." This similarity will become more apparent below. See, for example, the definition of IAE [1] below with reference to FIG. 4.

[0120] The intermediate arithmetic element IAE[2] contains register values ​​(e.g., see 817 in FIG. 8) representing statistical operators, including an index (e.g., see 808 in FIG. 8), a repeat count (e.g., see 807 in FIG. 8) of a data pattern in the matrix IAE[1] (e.g., see 806 in FIG. 8).

[0121] The intermediate operation element IAE [3] contains an ancillary matrix that holds statistical probabilities. The virtual quantum state description is mathematically defined by entangled bits of register values ​​(see, for example, 818 in Figure 8). These statistical operators empirically generate the statistical probabilities of decompression.

[0122] Other statistical operators such as entropy are used by the AAR for fuzzy logic rule 2 (see, for example, 419 in Figure 4), the statistical measurements for fuzzy logic rule 3 (see, for example, 420 in Figure 4), the superposition surface representing data elements as waves (see, for example, 414 in Figure 4) and the quantum mechanical logic for time measurements of the pre-circuit breaker (see, for example, 417 in Figure 4), and the final circuit breaker FCB (see, for example, 418 in Figure 4). These operators are generated by the AAR chip and passed to the BFX chip.

[0123] The above process allows classical data to be represented as CQME, or classical data with quantum properties, that can be processed by classical machines and, in the future, used by quantum computers. A quantum computer can then represent this processed data by storing it in a superposition state with low gate error (and potentially zero gate error) because the ancillary matrices define the time measurements for each qubit. This leads to superior fault tolerance and reduced gate error, providing quantum computing storage equivalent to classical storage solutions and enabling logical inversion and its benefits on quantum computers.

[0124] 4 is a block diagram of an exemplary AAR board design. AAR board 421 includes AAR chipset 422 and AAR chip 423. AAR chipset 422 includes AAR chip 423 and supporting components such as memory, tables, buses, and ports. AAR board 421 is configured to interact with other boards and storage devices to implement applications. In this disclosure, AAR board 421 interacts with BFX chip 428 to achieve a target amount of lossless compression.

[0125] The AAR chip 423 can be an integrated or non-integrated chip / processor, a software module, or embedded logic code. The AAR chip 423 includes at least one input port AAR-IP1 427. The input port AAR-IP1 427 is configured to receive an input classical data stream from an input source 401. The AAR chipset 422 includes a module 402 configured to convert the input classical data stream into a binary format and provide the input classical data stream in binary format to the AAR chip 423.

[0126] The AAR chipset 422 includes a built-in configuration table 403 that can be predefined or managed by an operator to define one or more operational parameters. These operational parameters can include the following: Size Bound Value (SIZE), PCB Error (PCBe), Data Save Value (DSV), Number of Rounds of Compression (NRC), Maximum Size of Compression (MAXC), and Standard Deviation Value (SDV). These operational parameters can be defined as follows:

[0127] The parameter Size Bound Value (SIZE) can be defined by an operator and is referred to as "SIZE" throughout the modules of the AAR and BFX chips. SIZE represents the size of an input data item, e.g., the size of the data input provided to various modules of the AAR and BFX chips. The SIZE value is constrained by an upper bound, SIZEUL, and a lower bound, SIZELL. The SIZE value is provided as an input in Hilbert space generation and other modules of the AAR and BFX chips. For example, if an operator specifies generating Hilbert space sizes between 56 and 1280, SIZEUL is equal to 1280 and SIZELL is equal to 56. In the examples described in this disclosure, SIZEUL and SIZELL are typically constrained to 4096 and 2, respectively, although other values ​​can be used.

[0128] The parameter PCB-error (PCBe) defines the time (in milliseconds) allowed before abandoning the stream if a Pre-nucleus Circuit Breaker (PCB) event (more on this later) has not occurred.

[0129] The parameter Data Saving Value (DSV) is used to specify whether AAR chip data routed to the BFX chip should be saved or passed transparently to the BFX chip or other application boards. The parameter DSV can take values ​​such as "pass-through" (e.g., do not save), "save and send," or "save only."

[0130] The parameter Number of Rounds of Compression (NRC) specifies the number of rounds of compression that the BFX chip performs by rerouting data outputs and inputs between the BFX chip and the AAR chip.

[0131] The parameter Maximum Size of Compression (MAXC) allows the operator to specify the target size of compression to be achieved. By defining this parameter, the AAR and BFX chips will reroute the data "n" times until the target compression ratio is achieved.

[0132] The parameter Standard Deviation Value (SDV) specifies the allowable deviation value range applied by Fuzzy Logic Rule 3 (FLR3).

[0133] Returning to FIG. 4 , binary data (e.g., received directly at input port AAR-IP1 427 or at module 402 configured to convert non-binary input data to binary input data) is loaded into FIFO memory 405 as a single first-in, first-out (FIFO) memory stream so that AAR chip 423 can calculate the following values ​​at the designated output port:

[0134] Final arithmetic complex AC in AAR-OP1 FINAL,g ,g represents a global index value for storage (pointer to memory location), parallel processing, and memory tracking. FINAL,g is written according to the value of the operating parameter data storage value (DSV) in the external storage.

[0135] Register values ​​(RV matrix) in AAR-OP2. This RV matrix or IAE[2] includes statistical operators as explained in more detail below.

[0136] The RV matrix can also be used in AAR-OP3 as an ancillary matrix or IAE [3]. The ancillary matrix contains statistical probabilities, as explained in more detail below.

[0137] The data is stored as a FIFO memory stream to ensure that the stream is processed sequentially when accessed by parallel address bus #1 DB1 407. The transmission of data to DB1 407 is managed by queue manager QMGR1 406, which is configured to ensure that the data is (a) defined for each Hilbert space and stored in a FIFO memory, (b) instantly copied by DB1 to all parallel tasks by providing the associated memory address location, and (c) waits for processing until all tasks have written to the SPP storage matrix 414 to ensure an error-free process.

[0138] The AAR chip 423 performs three steps to generate the final AC( During step 1, the AAR chip 423 generates candidate (e.g., all mathematically possible) Hilbert spaces for the data input. During step 2, the AAR chip 423 computes candidate (e.g., all mathematically possible) arithmetic complexes (ACs). During step 3, the AAR chip 423 selects the best arithmetic complex from the candidates computed in step 2. These three steps are explained in detail:

[0139] (Step 1: Generate candidate Hilbert spaces (HS)) During step 1, the AAR chip 423 reads data according to the variable SIZE defined in the configuration table 403. In some embodiments, the variable SIZE can range from 2 to 4096. The parallel address bus #1DB1 407 (see also 602 in FIG. 6) provides the memory location address of data according to the size stored in the FIFO memory from the queue manager QMGR1 406 (see also 601 in FIG. 6) intended for transmission to the input port of the HS data memory 408. (Although one HS data memory, HS DATA#1, is labeled 408 in FIG. 4, it is understood in this disclosure that the label 408 refers to a collection of HS data memories (see also 603 in FIG. 6).) The HS data memories 408 are processing modules that function as temporary storage before passing the data to the bit definition bus 409. Each HS data memory stores data according to its intended size. Therefore, the HS data memories are designed to optimally store the incoming data stream.

[0140] The parallel address bus #1DB1 407 receives address data from the FIFO memory 405 via the queue manager QMGR1 406 at a single input port and sends the data to multiple output ports, e.g., ports 407A, 407B, and 407C. The number of output ports to which the parallel address bus #1DB1 407 sends is equal to the value of the variable SIZEUL specified in the configuration table. The parallel address bus #1DB1 407 is specially designed to spray received data to the output ports over short cables to achieve high-speed transmission rates. This allows the HS data memory 408 (see also 603 in Figure 6 or 701 in Figure 7) to be notified that new data is available for processing.

[0141] The HS data memory port connects to the parallel address bus #1 DB1 407 and is defined according to a predefined bit size (in this example, ranging from 2 to 4096) to enable high-speed copying. The parallel address bus #1 DB1 407 (see also 602 in Figure 6) copies data from the FIFO memory 405 and stores it in memory locations in the HS data memory 408 as defined for sizes 2, 3...4096. This step does not discard or change the structure / order of the input data; it copies the full input data to all memory locations in the HS data memory 408. This is a high-speed data transfer and is a circular buffer filled by the FIFO memory 405 to ensure that the data is in the queue for further processing. The circular buffer is monitored by the queue manager QMGR1 406, which is configured to null out memory locations when data from the HS data memory 408 is passed to the next step (see also 702 in Figure 7), the bit-defined data bus #2 (DB2) 409.

[0142] The bit-defined data bus #2 DB2 includes a number of nodes specified by the variable SIZEUL, e.g., 4095 nodes in this example, and accepts data of various bit transmission sizes. Each custom node is connected to a predefined HS storage space HSS 409a. The custom-sized data is then transmitted from each HS data memory 408 (see also 702 in FIG. 7) to each HSS 409a via a dedicated wire to the bit-defined data bus #2 DB2 409. The HS data memory 408 is not designed to hold large amounts of data and has limited circulating memory (see FIG. 7). The HS data memory 408 continues to read and transmit data to the HSS 409a (via the bit-defined data bus #2 DB2 409) according to the received and transmitted bit sizes. The HSS data reference pointer is maintained in the local AAR memory.

[0143] The data in each HS data memory 408 includes the full input data, which is copied by bit-defined data bus #2 DB2 409 into respective sections (also referred to herein as partitions) of size 2 (SIZELL), 3, 4...4096 (SIZEUL) and stored in respective HSS spaces 409a (see also 703 in Figure 7). As a specific example, data in HS DATA(2) is copied by bit-defined data bus #2 DB2 409 to section 3 (e.g., copied as 000, 010, 110, 010, 101) and includes the full input data (e.g., 000010110010101) stored in HSS(2). This allows the AAR chip 423 to load data as a fixed-size one-dimensional matrix as data elements (E) ranging from 2 to 4096 element lengths (referred to as SIZE), each linked to an element of its own size.

[0144] In embodiments where the length of the data input is not a multiple of the HS size, the data input may be padded with, for example, 0 bits, until the length is a multiple of the HS size.

[0145] Matrix size is kept in local volatile memory (LVM) 410 for backup purposes and is stored in AC FINAL,g Only when is derived, Matrix size is disabled. Matrix size is defined as: Matrix SIZE,g =[E(a) SIZE ,E(b) SIZE ,E(c) SIZE …,E(n) SIZE ] where SIZE represents a value between 2 and 4096, g represents a global identifier, and a, b, c,... n represent individual elements. A global identifier is a pointer to a memory location that holds a specific amount of data. This location is identified by 'g' and accepts a pointer value that is a 256-digit HEX value. This value may increase depending on the onboard memory. The pointer value can be further optimized by advanced memory mapping.

[0146] New element E(n) SIZE has three empty subelement data structures initialized in LVM 410 and of size NULL. The three subelements are defined as intermediate operation elements (IAEs), IAE[1], IAE[2], and IAE[3]. IAE[1] is the sum of E(n) SIZE IAE[1] holds the data from IAE[2], IAE[3] holds the register value of the repeated data pattern (DP) of IAE[1], and IAE[4] holds the ancillary matrix generated using IAE[2] as input. The definitions of these intermediate operation elements are given below and are further described below with reference to Figure 8.

[0147] (IAE[1] and Quantum Multi-Element (CQME) definitions): IAE[1] is a set of elements E(n) of size ranging from SIZELL(2) to SIZEUL(4096) for CQME generation. size Including IAE SIZE The indices of elements from are processed and counted to create the same number of empty elements or register values ​​in IAE[2]. IAE[1] can be defined as: JPEG2025537443000003.jpg3459 In the formula, E is the element read from the input stream, g is the global identifier, s is the size and is a real number between 2 and 4096, and i is the index of the data within element E.

[0148] The elements in the IAE[1] are called Data Patterns (DPs) (see, e.g., 806 in Figure 8). Data Patterns are split into two parts or statistical operators: 1) the entanglement measure or pattern type (PTYP), which is the first bit that holds the virtual entanglement measure of the element (see, e.g., 804 in Figure 8), and 2) the second pattern structure (PSTRUC), which holds the rest of the value (see, e.g., 805 in Figure 8).

[0149] To quantify the statistical operation of power or entangled information (which can be 0 or 1), the logic maintains that two similar PSTRUCs are encoded using inverse PTYPs with similar data patterns. The entanglement value is inspired by quantum mechanics and quantum information theory. The entanglement value is defined in this disclosure as an element PTYP of the IAE [1]. If two elements have identical PSTRUCs but inverse PTYPs, the two elements are defined as entangled in this disclosure. Each element of the IAE is nonlocal because it is defined by an interaction. In classical terms, the interaction is defined as the ability to generate a data pattern according to the HS size. This defines the data of the IAE [1] as a CQME system.

[0150] (IAE[2] definition): Element IAE[2] s,gis a dual-utility one-dimensional value matrix stored in local memory and holding two statistical operators: index and count. The term "dual-utility" means that the value and index position of an element in the matrix can be used as separate processing input(s) for various lookups or other equations / functions. The index position of this element is a value in another matrix, allowing for advanced lookups. For example, in the first matrix (repetition count), index position 1 may hold the value 5. The second matrix may hold the value 1, which is mapped to AA. When the value 5 in the first matrix, index 1, is looked up against the second matrix, the value 1 means 5 in matrix 2, indicating that AA is repeated 5 times.

[0151] Each variable is designed to hold data, and the index of each variable in the matrix provides a reference to a Data Pattern (DP) in IAE[1]. Each unique Data Pattern has an index IAE[2]. s,g The index labels or RVs hold the data pattern counts (e.g., see 807 in FIG. 8) of each of the identical data patterns in IAE[1].

[0152] IAE[2] s,g is IAE[1] s,g When a data pattern is encountered, the index or RV data is updated. The count of the data pattern is i where i represents an index according to the binary nomenclature defined by the size. IAE[2] can be defined as follows: JPEG2025537443000004.jpg3161 where s is the size, g is the global identifier, and i is the array of register values ​​(RVs) that hold the data pattern count. RV is the memory location that holds the data in the matrix. The RV of the index value indicates the type of data pattern (DP) in IAE[1], and the value or RV of the index location is the DP count. RV is specifically used in this disclosure to indicate that memory is dynamically marked or generated to store binary packets of a specific length. This improves the processing speed of the board, as the RV is a simple memory pointer that points to the stored data.

[0153] (IAE[3] and Ancillary Matrix (AM) definition): IAE[3] is a two-dimensional null matrix generated by the AAR chip. The elements IAE[3] are filled in by the AAR chip with statistical probabilities or other data. IAE[3] can be defined as follows: IAE[3] s,g ={R h ,R l ,s} where s represents the size, g represents the global identifier, and R h represents the RV of the largest index from IAE [2], and R l represents the RV with the smallest index from IAE[2]. R l The value is further compressed to 1 bit in the final processing stage of the AAR chip.

[0154] Continuing with the description of Step 1 (Generate Candidate Hilbert Spaces) and returning to Figure 4, if the variable GEN in configuration table 403 is true, then the value of SIZE is assumed to be between the defined size constraints of SZV, or 1 and 4096. If GEN is false, then the value of 'size' is as defined for all values.

[0155] The parallel processing for Hilbert space (HS) generation continues according to the variable GEN by the HS gates (HSG) 411. Each HSG 411 takes data input from its respective HSS 409a and creates three matrices representing IAE[1], IAE[2], and IAE[3] in its local memory 410. This is illustrated and described below with reference to FIG. 9A. Data from each HSS 409a is read and transparently copied to IAE[1] (e.g., without modification or processing, similar to a pass-through gate in signal processing). Based on the respective SIZEs of the HSGs 411, the HSGs 411 initialize the IAE[2] reconfigurable register (RR) value in their respective memories, called Hilbert space reconfigurable registers (HSRRs) 412.

[0156] The Hilbert Space (HS) RR Memory 412 contains dynamic memory blocks that allow for optimal utilization of memory space by generating only the necessary IAE[2] sizes. This allows optimal memory usage customized to requirements. Each HSG 411 places a mathematical null value "0" for all initialized RVs within its respective IAE[2] and its respective IAE[3]. The third IAE element of the Hilbert Space, IAE[3] or AM, is stored as a null matrix and is used to store statistical probabilities in Step 2 (described below).

[0157] Hilbert spaces range in "size" from 2 to 4096 and are stored in LVM 410 as three IAE matrices uniquely identified by a global identifier g. A set of Hilbert spaces can be defined and accessed according to the following identification logic: H s,g ={IAE[1] s,g ,IAE[2] s,g ,IAE[3] s,g} In the formula, s represents the size of the data structure and is a real number between 2 and 4096, and g represents the global index of the Hilbert space.

[0158] (Step 2: Calculate the candidate arithmetic complex (AC)) In step 2, HSG gate 411 generates a statistical operator for each element of IAE[2]. The combination of intermediates IAE[1], IAE[2] and IAE[3] is referred to in this disclosure as an AC including data and statistical operators. INTERIM Also called Intermediate Arithmetic Complex (IAC). FINAL,g and IAC, AC FINAL,g is the final output, but IAC is the final output, i.e., AC FINAL,g are filtered through fuzzy logic modules 415, 419 and 420 to obtain possible candidates to be dropped.

[0159] Each HSG gate 411 creates a respective HSRR 412 as an empty register in IAE[2], stores index values ​​according to the 'size' variable, and stores a NULL or '0' count value in these indices. HSG gate 411 reads data patterns (DPs) (see 911 and 912 in Figure 9B) from the data stream in IAE[1] (see 910 in Figure 9B) via a loop (single-tasking) or in parallel (multitasking) and compares the data across all register values ​​in IAE[2] with the data patterns (DPs). HSG gate 411 increments the count value in IAE[2] for data patterns (see 913 and 914 in Figure 9B) that match the register values ​​(see 915 in Figure 9B).

[0160] At a specified future data write event, one of the register value counts will have an initial NULL value, and at the next write event, all initial NULL values ​​will be absent (all values ​​will be non-NULL). This event is called the Final Circuit Breaker (FCB) event 418 (see also 928 in Figure 9C). This register value (including the initial NULL value) represents the completion of the IAC, and the IAC s,ugwhere 'ug' represents the unique index of the AC and s represents its size. Once the IAC is complete, the HSG gate continues to read data patterns (DP) from the data stream in IAE[1] to create the next IAC until the entire data stream has been read.

[0161] AC FINAL is a set of generated IACs or ACs INTERIM are processed through fuzzy logic rules (FLR) modules 415, 419, 420 to produce a set of generated IACs or ACs. INTERIM is obtained from

[0162] To generate a stream of IACs, each HSG 411 counts the value of the IAE [2] and monitors for a "Pre-nucleus Circuit Breaker" event (PCB), followed by an FCB event. PCB events are monitored to ensure optimal use of the AAR chip 423's memory resources. For example, an operator can define an error control (EC) variable or PCBe (stored in the configuration table 403) that drops a Hilbert space stream if a PCB event does not occur for a defined time or read. In some cases, a PCB event does not occur because the Hilbert space stream does not generate statistical operators that allow the stream to be defined as a CQME. Thus, the absence of a PCB event is an error control to ensure that only Hilbert spaces that may be optimal for the presence of statistical operators and probabilities are processed.

[0163] The error control variables may take on operator-defined values ​​that vary based on the type of input data stream and the processing device. For example, in some embodiments, the error control variables may include variables that define an amount of time. In this example, the stream may be dropped if no PCB event occurs after an adjustable percentage, e.g., 40%, of the processing time defined by the PCBe in the configuration table (403) for an event in which all but one Data Pattern (DP) in IAE[2] contains a NULL value. In other words, the time from the start of reading the stream to the moment when all but one DP in IAE[2] contains a zero value is calculated, and that time is counted as the time for the PCBe. tに You can save it. PCB t +40%*PCB t If no PCB event occurs within the time defined by, the stream is dropped.

[0164] As another example, in some embodiments, the error control variable may include a variable that defines the amount of data read. In this example, if a PCB event does not occur within an adjustable percentage, e.g., 40%, of the size of the data read up to the time of the event, the stream may be dropped. All but one data pattern (DP) in IAE[2] contains a NULL value. In other words, the read size may be calculated from the beginning of the read stream to the moment when all but one DP in IAE[2] each contain a register value of zero, and that size may be stored as a PCB. If a PCB event does not occur within the read size defined by PBCs + 40% * PCBs, the stream is dropped.

[0165] Each HSG 411 selects its first available Hilbert space in memory 410 from a round-robin lookup according to a global index variable. As a check, logic dictates that all register values ​​be initialized with mathematical NULL or '0' values. If memory corruption causes a register value not to represent a NULL or '0' value, all register values ​​(RVs) are initialized with NULL or '0' values. Using unsupervised logic programming, the HSG 411 continues to increment the register values ​​RVs until the NULL or '0' values ​​disappear from all register values ​​except the two register values ​​for the current write event. i (The current write event is a snapshot of the count value of the Data Pattern (DP) in IAE[2].) The next write event increments either the NULL or '0' value in the RV. This event is labeled a "Pre-nucleus Circuit Breaker" (PCB) event and always occurs before the FCB event.

[0166] Register value RV that remains at '0' value during the next write event on PCB i is RV i The register value labeled as PCB_1N (see, for example, 929 in Figure 9C) and which loses a '0' (due to a PCB event) is RV i PCB_1S (see, for example, 930 in Figure 9C). One-dimensional matrix TEMP_FCB g ( g is a global identifier) ​​is initialized with global memory to hold the elements of IAE[1] that will be processed after the PCB event, and will continue to store elements until an FCB event occurs. At an undefined time in the future (after the PCB event), RV i When another write is made to PCB_1N and all other registers have already lost their initial null value status, this register releases its initial null value status. This event is called an FCB event, and the last register with an initial null value is released in RV. s,CB is defined as RV i Equals PCB_1N.

[0167] The AAR chip 423 includes a PCB detection module, e.g., PCB detection module 417, and an FCB detection module, e.g., FCB detection module 418, for each of the n Hilbert spaces. The PCB detection module and the FCB detection module are configured to detect PCB events and FCB events and perform the operations described above. The detection of FCB events by the FCB detection module can be compared to measuring the time of a waveform in quantum mechanics. However, in the case of AAR processing, it is applied to the analysis of classical data. Figure 11B shows data from the example IAE [1] represented as a series of waves.

[0168] In some embodiments, the "read" (value of index i) counter is used to count the number of times the last read was made to the nucleus or RV. s,CB is rolled back by 1 to ensure that

[0169] All RVs in IAE[2] are defined as statistical operators because they hold count values ​​for each register. s,CB or RV i PCB_1N is a termination point and has a count of one singular point (i.e., count 1, which represents a unique data pattern in the data stream corresponding to IAE[2]).

[0170] To generate the statistical probability of the ancillary matrix IAE[3], the processed elements E(a)...E(n) read from IAE[1] before the detection of an FCB event within the selected IAC space are moved and stored in a newly initialized variable Temporary IAE[1] or TIAE[1]. The term "moved" refers to the movement of data, invalidating the original variable.

[0171] The register values ​​(RVs) of the maximum and minimum indices of IAE[2] are identified and used to calculate the statistical operator R h and R l is stored as a value of

[0172] The current snapshot of IAE[2] is moved to Temporary IAE[2] (TIAE[2]).

[0173] R h and R l The value is moved in Temporary IAE[3] (TIAE[3]).

[0174] IAC can be expressed as: IAC s,tg ={TIAE[1] s,tg ,TIAE[2] s,tg ,TIAE[3] s,tg} where s represents the size and tg represents the temporary global identifier.

[0175] This step is repeated to generate several IACs of various sizes until the end of the data is reached in the selected Hilbert space, at which point all generated IACs are combined according to size to form a Potential Final Arithmetic Compound (PFAC) as follows: JPEG2025537443000005.jpg3482 where tg is the generated PFAC s represents the temporary global identifier of the IAC, and tg represents the temporary global identifier of the IAC.

[0176] (Step 3: Select the best arithmetic complex from the candidate arithmetic complexes) The generated IACs are combined to form several potential final arithmetic complexes (see also 1102 in FIG. 11A) according to the size. However, the optimal AC or AC FINAL Only one of these or a combination of SIZEs will form an AC (where optimal is the AC that yields a "true" result for the fuzzy logic rules described below). FINALThree fuzzy logic rules (FLR) are implemented by FLR modules 415, 419, 420 to generate the optimal AC FINAL This helps reduce the number of potential final arithmetic complexes, as it identifies:

[0177] Fuzzy Logic Rule 1 (FLR1)-Matrix size,g The combined PFACs are then compared with the input data and combined into a matrix of various PFACs (of different sizes) 1103 in FIG. 11C. size,g It cannot be smaller or larger. PFAC is a Matrix size,g The length of the data element must match exactly, otherwise the PFAC is dropped from memory. This is achieved by analyzing a superposition plane (SPP) where all (mathematically) possible data element waves are stored.

[0178] Fuzzy Logic Rule 2 (FLR2) - The PFAC filtered by FLR1 is passed to FLR3 if its information gain or entropy has minimal variation compared to the Matrixsize,g entropy.

[0179] Fuzzy Logic Rule 3 (FLR3)-TIAE[2] s,tg The frequency distribution of must ensure that there is at least one singularity (i.e., the count of at least one data pattern is greater than or equal to "1") to form a proper AC.

[0180] Before FLR is applied to the data, a superposition plane (SPP) generator 413 processes the candidate arithmetic complexes. The SPP generator 413 generates a global index for each PFAC. tg The SPP storage matrix 414 is generated to store the SPPs. The SPPs are a series of combinations of IACs generated by the following logic: PFAC s,tg Combine tg is 1 and tgThe maxcount is between s is 2 (or SIZELL) and 4096 (or SIZEUL) PFAC tg,s Add them together to create a CDW combination Close the loop on s maxcount tg Closing the loop on n connected PFACs or CDWs n Output a stream of

[0181] An SPP is a large combination matrix generated from classical data elements using feedforward combination. An SPP can be viewed as a superposition plot of waves generated as a large data set of streams by combining IAC elements. The combination occurs as a feedforward without discretion from the IAC, with each data stream into a potential final arithmetic composite stream called a Classical Data Wave (CDW). The CDW represents the elements, the number of elements, and their size. The feedforward approach allows the SPP generator 413 to create streams of various sizes intended for SPP.

[0182] The AAR chip 423 must obtain a CDW from the SPP array that resembles the input data (after application of fuzzy logic rules) without error. To determine the CDW, the AAR chip is configured to identify statistical properties, such as size and elements (of the IAC), at defined intervals. This defined interval is similar to a "time measurement" in quantum mechanics and is obtained when the fuzzy logic rules FLR1, FLR2, and FLR3 415, 419, 420 are all true for the CDW of the SPP. Each CDW is a set of potentially valid CQMEs, including statistical operators, probabilities, and data that precisely, empirically, and error-free define the input data. A set of combinations of all elements in each IAC is generated and stored in the SPP. FINAL,g is obtained.

[0183] To generate the CDW, all combinations of PFAC(2) size 2 elements are generated, followed by all combinations of PFAC(3) size 3 elements, up to the maximum available size PFAC(x). All PFACs generated in 413 are then processed by 414 to create combinations in a feedforward manner. These processes are described below with reference to Figure 11C.

[0184] The combination produces an SPP where each stream references a set of CDWs: CDW2={PFAC 2,1 - PFAC 2,2 - … PFAC 2,thg} CDW3={PFAC 3,1 - PFAC 3,2 - … PFAC 3,thg} CDW4={PFAC 4,1 - PFAC 4,2 - … PFAC 4,thg} … … … … CDW n ={PFAC n,1 - PFAC n,2 - … PFAC n,thg} Each CDW generated above is stored in the SSP storage 414 (see 1102 in FIG. 11).

[0185] The FLR1 module 415 applies a first FLR to ensure that the data stream is not larger than the original data. A large CDW stream indicates that the combination of CDWs formed using statistical operators is not valid and cannot be integrated into the classical stream.

[0186] The size of the original data input is defined as: |Matrix size .

[0187] CDW nThe size of |CDW| is defined as follows: n .

[0188] To perform FLR1, the FLR1 module 415 applies the following logic to the CDW data set: |Matrix size Size of |CDW n If the size of | is equal to RULE_1=CDW n About "True" Otherwise RULE_1=CDW n About "false" Memory to CDW n Delete Remaining CDW n Processing continues for.

[0189] FLR2 module 419 applies FLR2 | Matrix size Derive the entropy of | and CDW n The entropy is stored as a global variable for lookup. Entropy allows for the calculation of the average level of data noise transmitted from the HS input to the output. The entropy calculation helps understand the change in noise level after data processing and eliminate streams containing a large amount of "surprises." The AAR chip 423 generates several states of the IAE, so reading the entropy level is important. The entropy calculation can later be used to add machine learning (ML) concepts to the AAR. ML can also be used to eliminate noisy data streams or data streams that contain too many "surprises" when the IAE [1] is generated. Therefore, checking the entropy between the current data stream and the input data stream reduces the processing and memory load on this hardware, enabling embedded development as an example application. By comparing this statistical data distribution with the deviation, streams with variance greater than a defined amount are discarded. The combination of elements with the current stream must be close to the input stream.

[0190] The information gain or entropy of the input is denoted by Entropy(T). For more complex systems, other dimensions such as the Vapnik-Chervonenkis dimension or Kolmogrov may also be used, but to avoid complexity, we refer to the first enumeration as the entropy measure as follows. However, other equations and public / open source methods can be used to determine the entropy of a stream being processed or to be processed: JPEG2025537443000006.jpg28161 Enumerate the entropy of the current stream JPEG2025537443000007.jpg23164 To calculate the difference between the two entropies, they are normalized: JPEG2025537443000008.jpg45164

[0191] Δ Entropy If is less than the predefined value, then RULE_2="TRUE" and check whether the data size of the tensor is equal to the data size of the selected stream: JPEG2025537443000009.jpg31164

[0192] If the sizes are equal, RULE_2 = "true" and proceed to check Rule3, otherwise, CDW n Drop from memory.

[0193] The FLR3 module 420 applies a third FLR to represent the data stream when statistical operators described in TIAE [3] are valid and ensemble interpretation techniques are applied.

[0194] TIAE[3] s,tg Now, the selected CDW n For every subelement of (when RULE_1 and RULE_2 are "true"), the following conditions are satisfied: TIAE[3] s,tg The min_value of is a singular point, TIAE[3] s,tg max_value is not a singular point, TIAE[3] s,tg If the SDV of is less than 1.5 (or the value defined in point 32 of the configuration table), the difference between min_value and max_value must be at least 1. TIAE[3] s,tg If the SDV of is greater than 1.5 (according to the SDV of point 32 in the composition table), the difference between min_value and max_value must be at least 2 (according to the SDV of the composition table), The SDV value is listed from the configuration table and can be changed by the operator. If all of the above are "true" and RULE_1="true" and RULE_2="true", then set RULE_3="true", else set RULE_3="false", If any of the rules (RULE_1, RULE_2, or RULE_3) is false, CDW n Drop the stream from memory and proceed to the next analysis.

[0195] The above logic leads to the generation of the optimal AC as shown below: AC FINAL,g ={CDW WHERE RULE_1,RULE_2 & RULE_3 ARE "TRUE”}

[0196] This optimal AC is provided as the final output 416. The AAR chip 423 includes at least three output ports AAR-OP1, AAR-OP2, and AAR-OP3 424, 425, and 426. FINAL has three components for each CDW: IAE[1], IAE[2], and IAE[3], which are written to output ports AAR-OP1, AAR-OP2, and AAR-OP3. The first port AAR-OP1 424 supplies the data stream IAE[1], the second port AAR-OP2 425 supplies the statistical operator on the data stream IAE[2], and the third port AAR-OP3 426 outputs IAE[3].

[0197] The final output 416 may be stored in binary and / or fed to another chipset or device, such as to the BFX chipset 428 for compression. Due to the modular design of the AAR chip, each AC FINAL Multiple inputs and outputs can be processed in parallel via parallel round robin as counter values.

[0198] In embodiments where the final output 416 is provided to the BFX chipset 428 to be compressed, processing by the AAR chip 423 is stopped or continued based on the values ​​of variables defined in the configuration table 403, such as NRC or MAXC. For example, in a time-critical environment, an operator may select 50% compression. However, in an environment such as Glacial storage, an operator may choose to compress the data by 99%.

[0199] (Example Technique for Generating Arithmetic Complexes) Figure 5 shows an example arrangement of AAR chip elements. As mentioned above, the AAR chip performs three steps to generate the optimal arithmetic complex AC FINAL,g In step 1, the parallel address bus #1DB1 407 in FIG. 4 copies the full data input from the FIFO memory 405 to each of a plurality of HS data memories (e.g., HS data #1), each corresponding to a respective size defined in the configuration table 403 in FIG. 4. This creates a plurality of parallel data streams, each of which is processed (in parallel) using a respective AAR chip element, as described above with reference to FIG. 4.

[0200] Figure 5 shows two of these parallel data streams. The first data stream 501 corresponds to the variable SIZE=2 (SIZELL). The second data stream 503 corresponds to the variable SIZE=3. In practical implementations, the AAR chip contains more data streams, for example, 4095 data streams. For clarity, only two data streams are shown in Figure 5.

[0201] The first data stream 501 begins with HS data #1 503, which accepts full data input from parallel address bus #1 DB1 407 in FIG. 4. The data input is then passed to bit-defined data bus #2 504, which divides the data into chunks of respective sizes (T SIZE = 2 in this case) and provides the divided data to HS generator 506. In FIG. 5, each data stream includes a respective bit-defined data bus #2, for example, to implement in-line parallel circuitry. However, in some embodiments, the same bit-defined data bus #2 can be used for each data stream, as shown in FIG. 4. The bit-defined data bus #2 can contribute to technical advantages achieved by the AAR chip, such as faster memory access and the ability to provide additional power to the bus to ensure high-speed transmission in non-embedded environments.

[0202] The HS generator 506 processes the partitioned data using HS storage spaces, such as HSS(1) 409a in Figure 4, HS gates, such as HSG(1) 411 in Figure 4, and Hilbert space reconfigurable registers, such as HSRR(1) 412 in Figure 4, as described above with reference to Figure 4. When the PCB detection module 508 and the FCB detection module 510 detect PCB and FCB events, the corresponding intermediate arithmetic complexes are provided to the overlapping surface generator 512 via data bus #3.

[0203] The overlapping surface generator 512 combines intermediate arithmetic complexes from the different data streams to generate the SPP storage matrix 503 of classical data waves, as described above with reference to FIG.

[0204] The classical data waves in SPP storage matrix 503 are processed using the fuzzy logic rules described above with reference to Figure 4, namely, fuzzy logic rule 1 514, fuzzy logic rule 2 516, and fuzzy logic rule 3 518. The classical data waves that satisfy the three fuzzy logic rules (and their corresponding arithmetic elements IAE[1], IAE[2], and IAE[3]) are provided as final output 520.

[0205] The processing of the second data stream 502 is similar to that described above, except that the data passed between HS Data #2, Bit Definition Data Bus #2, HS Generator, PCB and FCB Detection Module, and Data Bus #3 has a bit size=3 instead of a bit size=2. For the sake of brevity, these details will not be repeated.

[0206] 5 illustrates that in some embodiments, some of the operations used to process parallel data streams may be performed in-line in the parallel circuits, such as the operations performed by components 503, 504, 506, 508, 510, 512, 514, 516, and 518. Other operations may be performed by components shared between the parallel circuits, such as component 503.

[0207] 6 is a block diagram illustrating an exemplary address parallel data bus #1 (DB1) 602. Parallel data bus #1 602 is configured to receive address data, such as FIFO memory location address 601, from a queue manager, such as queue manager 406 of FIG. 4. The address data is stored in FIFO memory 604. To ensure high-speed transmission, FIFO memory 604 stores the data and provides a pointer (memory location) to parallel data bus #1 602 via the queue manager.

[0208] The parallel data bus #1602 is configured to copy received address data to each of the multiple HS data memories 603 via their respective output ports, using short cables for high-speed transmission rates. Copying within the parallel data bus #1602 can be performed over short cables for high-speed transmission rates. The parallel data bus #1602 resembles push-based hardware, initiating copying from the FIFO memory as soon as the queue manager provides a new memory location. This allows the HS data memory 403 (see also 408 in FIG. 4 or 701 in FIG. 7) to be notified that new data is available for processing.

[0209] When the received address data is copied to each of the multiple HS data memories 603, the address data is not split, but the full entry is copied to all memory locations of the HS data memories 603. This is a high-speed data transfer and can be a circular buffer filled by the FIFO memory to ensure the data is in the queue for further processing. The circular buffer is monitored by a queue manager which invalidates memory locations when data from the HS data memories 603 is passed to the next step. The queue manager manages storing data in the FIFO memory, sending it to parallel data bus #1, and removing it from the FIFO memory after parallel data bus #1 has read the data.

[0210] 7 is a block diagram illustrating an exemplary bit-defined parallel data bus #2 (DB2) 702. Bit-defined parallel data bus #702 includes multiple nodes, such as bit ports 704, each configured to receive data over a respective wire from a respective HS data memory of multiple HS data memories 701. HS data memory 701 has a limited-size circular memory 705 from which it reads data transmitted onto bit-defined parallel data bus #2 702.

[0211] Each bit port included in bit-defined parallel data bus #702 accepts data input of a respective size. For example, a 2-bit port accepts data of size 2, a 3-bit port accepts data of size 3, etc. Parallel data bus #2 is configured to pass data transparently from input to output. In the example shown in Figure 7, parallel data bus #2 has 4095 input ports and 4095 output ports (since SIZEUL=4096 in this example).

[0212] Each bit port included in the bit-defined parallel data bus #702 outputs data of a respective size. For example, a 2-bit port outputs data of size 2, a 3-bit port outputs data of size 3, etc. The output data is stored in each HS storage space of the multiple HS storage spaces 703. For example, output from the 2-bit port is stored in the HS(1) storage space, and output from the 3-bit port is stored in the HS(2) storage space.

[0213] 8 is a block diagram illustrating exemplary intermediate arithmetic elements IAE[1], IAE[2], and IAE[3]. The first intermediate arithmetic element IAE[1] 801 includes an original input data stream 817, such as input data received by an AAR chip, and a set of values ​​associated with the original input data stream 817. These values ​​form a quantum-inspired representation, referred to herein as a CQME, of the original input data stream.

[0214] Each set has an associated size, which is specified by a SIZE variable in the AAR chip configuration table. For example, the first intermediate processing element IAE[1] 801 can contain 4096 sets of data. The size associated with a data set specifies the division of the input data stream 817 into blocks. For example, if the size is equal to 2, an input data stream, e.g., 000000011011, can be divided into blocks of length 2, e.g., 00, 00, 00, 01, 10, and 11. As another example, if the size is equal to 3, an input data stream, e.g., 000000011011, can be divided into blocks of length 2, e.g., 000, 000, 011, and 011.

[0215] Each set specifies a number of values ​​corresponding to each block of the divided input data stream for that set, including a pattern type PTYP, e.g., PTYP 804, a pattern structure PSTRUC, e.g., PSTRUC 805, and a data pattern, e.g., Data Pattern 806.

[0216] A data pattern value 806 can be defined for each data set and is based on the size associated with the data set. The data pattern value corresponds to the type of block included in the divided data set (or that can be included in a division of the data set). For example, if the size is 2, the input data stream is divided into blocks of length 2. This means that each block can take on one of the values ​​00, 11, 01, or 10 because the data stream is a binary data stream. These four values ​​00, 11, 01, and 10 are the data patterns (DPs) of the set associated with a size equal to 2. As another example, the data patterns (DPs) of the set associated with a size equal to 3 are 000, 001, 010, 100, 011, 101, 110, and 111.

[0217] A pattern type PTYP may be defined for each block of partitioned data. A block's pattern type PTYP 804 may be considered classically equivalent to a measure of quantum entanglement 818. The pattern type PTYP is a single bit and can therefore take on values ​​0 or 1. The pattern type PTYP is equal to the value of the first bit of each block. For example, the PTYPs of blocks 00, 00, 00, 01, 10, and 11 are 0, 0, 0, 0, 1, and 1, respectively. As another example, the PTYPs of blocks 000, 000, 011, and 011 are 0, 0, 0, 0.

[0218] A pattern structure PSTRUC can be defined for each block of divided data. The pattern structure PSTRUC 805 of a block is a bit string of length SIZE-1 and includes the bits in the block following the block's pattern type PTYP. That is, the pattern structure PSTRUC of a block is equal to the block excluding its first bit. For example, the PSTRUCs of blocks 00, 00, 00, 01, 10, and 11 are 0, 0, 0, 1, 0, and 1, respectively. As another example, the PTYP of blocks 000, 000, 011, 011 is 00, 00, 11, and 11.

[0219] The second intermediate arithmetic element IAE[2] 802 also includes a set of values ​​associated with the original input data stream. As described above, each set has an associated size, and the size associated with the set of values ​​specifies the division of the input data stream 817 into blocks. The values ​​included in each set include counts, such as count 807, and register values, such as register value 808.

[0220] In each set, the register value is an index that references the aforementioned data pattern (DP). That is, the register values ​​in a set with each associated size reference the data pattern (DP) corresponding to the same associated size. For example, if the size is equal to 2, the input data stream is divided into blocks of length 2, and the four values ​​00, 11, 01, and 10 are the data patterns (DP) of the set associated with the size equal to 2. The register values ​​are four indices that reference the four data patterns (DP). The count represents the number of times the data pattern was encountered in the original input data stream. That is, as each block of the divided data set is read, the count value is updated based on the data pattern encountered. For example, if IAE[2] is created, IAE[2] will have a NULL value for each count, and as the input data stream is read, the count is updated based on the data pattern (DP) encountered. For example, after the split input stream 00,00,00,01,10,11 is read, data pattern 00 has a count of 3, data pattern 01 has a count of 1, data pattern 10 has a count of 1, and data pattern 11 has a count of 1.

[0221] The third intermediate arithmetic element IAE[3] 803 is also referred to as the ancillary matrix in this disclosure. The third intermediate arithmetic element IAE[3] 803 is generated by the AAR chip as an unpopulated two-dimensional null matrix. The elements of the ancillary matrix are then populated using IAE[2]. The elements of the ancillary matrix correspond to four variables: a first address pointer in IAE[2] 809 representing the size s; a second address pointer in IAE[2] 811 representing the g global identifier; a maximum register value 810; and a minimum register value 812. These variables are referred to herein as statistical operators because they can be used to empirically generate statistical probabilities of decompression.

[0222] 9A is a block diagram of an exemplary process for creating a register matrix in IAE[2]. In step (A) of the exemplary process, data 901 is read from the current Hilbert space storage HSS. In the example shown in FIG. 9A, data 901 is divided into blocks of size SIZE=2, and the current Hilbert space storage is HSS(1).

[0223] In step (B) of the exemplary process, the read data is stored in the intermediate arithmetic element IAE[1] 902 as a register value R(1,1), etc. At this stage, the entries in IAE[2] 903 and IAE[3] 904 are NULL. In step (C) of the exemplary process, the register size is determined. For the Hilbert storage space HSS(1), the register size is equal to 2.

[0224] During step (D) of the exemplary process, a reconfigurable memory register 909 is created and added to the IAE[2] so that the memory block is designed to hold two bits of data. This ensures optimal use of on-board memory. Box 905 shows an example snapshot of memory storage.

[0225] During stage (E), IAE[2] is prepared in HSS(1). The first column 906 of IAE[2] 911 holds possible data patterns (DP) defined according to the input binary size. The second column 907 holds the index value of the data pattern (DP), and the third column 908 holds the repeat count of the data pattern (DP). The first column 906 represents the dual utility of the matrix. In stage (F), IAE[2] is created in a memory register ready for data input, as described in more detail below with reference to FIG. 9B.

[0226] FIG. 9B is a block diagram of an exemplary process for filling the register matrix of IAE[2] with data. Continuing from FIG. 9A, IAE[2] is configured as a matrix with NULL entries. The entries are updated while data is read from IAE[1] for the current HS storage space. During stage (A) of the exemplary process, an input data stream 910 is read from IAE[1]. As the input data stream is read, it is matched with a data pattern (DP) in real time, and the values ​​of IAE[2] are updated.

[0227] For example, in the example shown in FIG. 9B, in step (B), the first value of the data stream is read (in this specification, the term "value" refers to a portion of divided bits, and the length of that portion is defined by the current SIZE). In this example, the first value is 00. Therefore, in step (C), the count of the data pattern "00" in IAE[2] is incremented by 1. Similarly, in step (D), the second value of the data stream is read. In this example, the second value is also 00. Therefore, in step (E), the count of the data pattern "00" in IAE[2] is again incremented by 1.

[0228] This process is repeated until a PCB event and an FCB event are detected, as described below with reference to FIG. 9C.

[0229] Figure 9C is a block diagram illustrating the completion of a write operation to the Hilbert space of IAE[1] and IAE[2]. Continuing from Figure 9B, the input data stream is read from IAE[1] to the current HS storage space. Data reading does not stop until an FCB event is identified.

[0230] Table 920 shows an example flow of a circuit breaker event. In the first step 922, the count values ​​of registers RV1, RV2, RV3, and RV4 are all NULL. After the first value in the data stream is read, one count is added to the corresponding register. In this example, step 924 adds a count to register RV1. This process is repeated until only two registers have a zero count at a time (i.e., the data pattern (DP) corresponding to these registers has not been read from the data stream). A PCB event 926 is triggered when the next count causes one of the two registers to lose its zero count. When a PCB event is triggered, the register value that lost its '0' in the PCB event is added to RV1. i It is saved as PCB_1S. A PCB event occurs in IAE[2] when only one data pattern holds the value 0 while reading a data stream. This event (PCB) occurs when the previous write event to IAE[2] held two data patterns (DP) containing zero values, while the current write event to IAE[2] holds only one of the previous two data patterns holding a zero value.

[0231] The reading of the data stream continues until only one of the two registers has a zero count. An FCB event 928 is triggered when only one register loses its zero count by the next count. When an FCB event is triggered, the register value that lost its '0' in the FCB event is RV. iIt is saved as PCB_1N. An FCB event is an event that occurs in IAE[2] while reading a data stream when none of the Data Patterns (DP) contain a value of 0. This event (FCB) occurs when the previous write event to IAE[2] contained a Data Pattern containing a value of zero, but the current write event to IAE[2] does not contain any Data Patterns (DP) containing a value of zero.

[0232] In some embodiments, PCB and FCB events do not occur within a predetermined time interval or number of write events, in which case the corresponding data stream is discarded. However, when PCB and FCB events occur, data from IAE[1] is loaded into temporary variables (TIAE[1],[2],[3]) that are passed to SPP storage. FCB events provide a solution to the time interval measurement problem for any overlapping element. In this case, the overlapped stream consists of binary values.

[0233] Figure 10 is a block diagram illustrating an exemplary HS generator architecture. For convenience, Figure 10 shows two data streams arriving from respective HS data memories, e.g., memory 408 in Figure 4. However, as discussed above with reference to Figure 4, the HS generator can process multiple data streams in parallel.

[0234] The first data stream corresponds to SIZE=2 and is processed by a 2-bit HS generator circuit included in the exemplary HS generator architecture. A data stream 1002 with a bit size of 2 is received by the 2-bit HS generator circuit via bit-defined data bus #2. The data stream 1002 is sent to the HS(1) storage space 1006 via a 2-bit port 1004. The data is then sent to an HSG gate, such as an HSG 2 node 1008. The HS gates included in the HS generator are specifically designed to copy a predetermined size of data, e.g., two bits at a time for a 2-bit HS generator circuit, or more generally, n bits at a time for an n-bit HS generator circuit. In other words, the number of nodes on the port of an HS gate varies depending on the HS stream size, e.g., from 2 to 4096. The number of nodes per HS gate is predefined and built into the hardware design. This allows for fast processing and optimal memory allocation because the input, processing, and output sizes are known, without wasting previous milliseconds defining variable sizes and memory allocation.

[0235] The Hilbert Space (HS) gate sends data to the IAE[2] register 1010, which is transparently added to IAE[1] 1012. The data pattern of the elements in IAE[1] 1012 is read (as described above with reference to Figures 9A-9C) and its repetition count is stored in IAE[2] 1010.

[0236] The HS generator has the ability to fill data in IAE[2] in parallel by implementing dedicated wires from the HS storage space to the corresponding IAE[2]. The logic for the number of parallel wires is implemented as shown in Table 1 in Figure 10.

[0237] Figure 11A is a block diagram illustrating the operations performed by the Superposition Plane (SPP) Generator. The SPP Generator reads data from each HS storage space (for each value of the SIZE variable). The SPP Generator generates all possible data combinations (similar to generating wave superposition data) and stores the combinations in the SPP storage. The SPP Generator can generate all possible combinations from TIAE[1] while creating references between applicable TIAE[2] and TIAE[3].

[0238] FIG. 11B shows an example PCB and FCB detection chart, plotting data from IAE[1] on a map to represent a series of waves. Each chart in FIG. 11B includes an X-axis representing register values ​​and a Y-axis representing data pattern counts. Chart 1 corresponds to the initialization of IAE[2], when no split data is read from the input data stream. In Chart 1, the waves are silent / decaying. Chart 2 corresponds to the time after split data is read from the input data stream and the corresponding data pattern count is added to IAE[2]. In Chart 2, the waves begin to rise with the addition of a new count to the data pattern register value. Chart 3 corresponds to an undefined time in the future when only two data pattern register values ​​are NULL. Two NULL data pattern register values ​​are circled in Chart 3. Chart 4 corresponds to the time when one of the two data pattern register values ​​that was NULL in Chart 3 has a count added to it and is no longer NULL. Therefore, a PCB event has occurred at the time corresponding to Chart 3. Chart 5 corresponds to the time when the remaining data pattern register value is NULL. In Chart 5, the NULL data pattern register value is circled. Chart 6 corresponds to the point in time when the remaining data pattern register value has a count added to it and is no longer NULL, i.e., there is no data pattern register value with a NULL count. Therefore, the FCB event occurred at the time corresponding to Chart 5.

[0239] The events shown in Chart 3 (PCB Events) and Charts 5 and 6 (FCB Events) are timed events that force the AAR chip to terminate reading the input data stream, ideally resulting in a quantum system outcome. The detection of an FCB event triggers the creation of an IAC (Quantum Information Theory Inspired Array). By construction, when the wave function is positive for an FCB event (i.e., when the count contained in the IAE[2] matrix has one null value), there is a certain probability that the current time frame will generate an IAC accompanied by a wave read operation by the AAR chip.

[0240] FIG. 11C is a block diagram illustrating an exemplary process for generating an SPP storage matrix and applying fuzzy logic to obtain the final output.

[0241] In step 1103 of the process, IACs of size 2 are combined to form PFACs. In Figure 11C, each dot represents an IAC, and combinations of dots joined together as a string represent PFACs.

[0242] In step 1104 of the process, a set of combinations of all elements in each IAC is generated and stored in the SPP. FINAL,g To generate the CDW, all combinations of size 2 elements of PFAC(2) are generated, followed by all combinations of size 3 elements of PFAC(3), up to the maximum available size PFAC(x). In step 1104, all PFACs of all IAC sizes are generated for incorporation by overlap surface generator 413 of FIG. 4.

[0243] In steps 1105, 1106, 1107, and 1108, all generated PFACs are processed by creating combinations in a feedforward manner. The generation is not limited to these example techniques, but is a broad combination-driven process that generates candidate combinations (CDWs) of all IACs in all PFACs. As an example, in step 1105, a first stream of SPPs or CDWs is generated for size 3, which has three IACs or combinations 1: element 1 in PFAC (size 1), element 2 in PFAC (size 2), and element 3 in PFAC (size 3). As another example, in step 1106, a second stream of SPPs or CDWs is generated for size 3, which has three IACs: element 2 in PFAC (size 1), element 2 in PFAC (size 2), and element 3 in PFAC (size 3). This is performed for all sizes by exhaustive combinations and creating several CDWs that are saved in the SPP in step 1109.

[0244] In steps 1110, 1112, and 1114, fuzzy logic rules are applied to the stored combinations. The application of a first fuzzy logic rule, FLR1, removes combinations that do not meet the length requirement described above with reference to Figure 4. The application of a second fuzzy logic rule, FLR2, removes combinations that do not meet the entropy requirement described above with reference to Figure 4. The application of a third fuzzy logic rule, FLR3, removes combinations that do not meet the frequency distribution requirement described above with reference to Figure 4. After steps 1110, 1112, and 1114, a final output stream with the correct statistical properties is obtained in step 1116.

[0245] FIG. 12A is a block diagram illustrating the generation of IAE[1] and IAE[2] from an exemplary input binary stream. In this example, the input data is a binary stream 1200. Step (A) shows how the input data is split to generate IAE[1]. The binary stream is split according to the value of the SIZE variable. In FIG. 12A, for illustrative purposes, the binary stream 1200 is split into SIZE=2 and SIZE=3. For example, with SIZE=2, the binary stream 0000000110... is split as 00,00,00,01,10,..., and with SIZE=3, the binary stream is split as 000,000,011,.... The split data is inserted into an IAE[1] matrix of SIZE=2 and an IAE[1] matrix of SIZE=3, respectively. The IAE[1] matrix is ​​a one-dimensional linear matrix.

[0246] Stage (B) shows the possible Data Patterns (DP) for SIZE=2 and SIZE=3. Classical mathematics defines the number of possible Data Patterns (DP) for each size. For SIZE=2, the possible Data Patterns (DP) are limited to four: 00, 01, 10, and 11. For SIZE=3, the possible Data Patterns (DP) are limited to eight: 000, 001, 010, 100, 110, 101, 001, and 111.

[0247] Step (C) shows an example of an IAE[2] matrix generated for the data shown in steps (A) and (B). For SIZE=2, the IAE[2] matrix has four index positions, each representing a different data pattern. For SIZE=3, the IAE[2] matrix has eight index positions, each representing a different data pattern. When the IAE[2] matrix is ​​created, all index position counts are NULL. Populating the entries of the IAE[2] matrix is ​​described below with reference to Figure 12C.

[0248] Figure 12B is a block diagram illustrating the pattern type, pattern structure, and entangled data pattern (DP) for the example input binary stream of Figure 12A. As discussed above with reference to Figure 4, the data pattern (DP) for any value of the SIZE variable has two components: PTYP and PSTRUC. PTYP is a (classical) measure of quantum entanglement or pattern type, given by the first bit of the data pattern. PSTRUC holds the remaining bits of the data pattern.

[0249] Table (A) in Figure 12B shows possible data patterns (DP) when SIZE=2. As an example, Table (B) shows the PTYP and PSTRUC of data pattern 10. In this example, the first bit is "1", which is PTYP. The remaining bits of the data pattern are "1", which is PSTRUC.

[0250] Table (B) in Figure 12B shows possible data patterns (DP) when SIZE = 3. As an example, PTYP and PSTRUC of data pattern 101 are shown in Table (E). In this example, the first bit is "1", which is PTYP. The remaining bits of the data pattern are "01", which is PSTRUC.

[0251] Table (C) in Figure 12B shows possible data patterns (DP) when SIZE=4. As an example, Table (F) shows the PTYP and PSTRUC of the data pattern 0000. In this example, the first bit is "0", which is PTYP. The remaining bits of the data pattern are "000", which is PSTRUC.

[0252] 12B also shows how two data patterns (DPs) correlate or (classically) entangle. In this disclosure, a data pattern is defined as correlated or entangled with another data pattern if the other data pattern has an inverse PTYP and an identical PSTRUC.

[0253] For example, table (G) contains data pattern 00. This data pattern is entangled with data pattern 10 shown in table (D) because PTYP of data pattern 00 is 0 (the opposite of PTYP of data pattern 10) and PSTRUV of data pattern 00 is 0 (the same as PSTRUC of data pattern 10).

[0254] As another example, table (H) contains data pattern 001. This data pattern is entangled with data pattern 101 shown in table (E) because PTYP of data pattern 001 is 0 (the opposite of PTYP of data pattern 101) and PSTRUV of data pattern 001 is 01 (the same as PSTRUC of data pattern 101).

[0255] As another example, table (I) contains data pattern 1000. This data pattern is entangled with data pattern 0000 shown in table (F) because PTYP of data pattern 1000 is 1 (the opposite of PTYP of data pattern 0000) and PSTRUV of data pattern 1000 is 000 (the same as PSTRUC of data pattern 0000).

[0256] The definition of classical entanglement used in this disclosure is similar to quantum entanglement of electrons, where the electrons have opposite spins but similar properties. PTYP can be thought of as the spin value, and PSTRUC as the electronic structure common to two Data Patterns (DPs). For every binary Data Pattern (DP), there are an equal number of PSTRUC values ​​with distinct PTYP values. Therefore, each Data Pattern is entangled with each other for any binary size up to a minimum of SIZE=2.

[0257] FIG. 12C is a block diagram illustrating reading the exemplary input binary stream of FIGS. 12A and 12B and adding a count value to IAE[2]. In FIG. 12C, Table (A) represents IAE[1]. For illustrative purposes, the table is divided into two sections. The first section of Table (A) contains step numbers, and the second section of Table (A) contains input data values ​​separated by commas. Each comma-separated value is hereinafter referred to as a packet. While FIG. 12C illustrates reading an exemplary input binary stream with SIZE=2, this technique is applicable to any binary size.

[0258] The IAE[1] input data stream (Table A in Figure 12C) is read and added to the IAE[2] matrix, Table (B) in Figure 12C. The IAE[2] matrix is ​​divided into three sections: Data Pattern Index, Data Pattern (DP), and Remaining Step Data. The Remaining Step Data is displayed in two columns. The first column represents the step number (similar to Step in Table (A)). The second column contains rows containing snapshots of the IAE[2] count data. The IAE[2] matrix is ​​shown in Table (C) and has four index values, each representing a respective data pattern of SIZE=2 binary.

[0259] In step 1 (shown in both Table (A) and Table (B)), the IAE[2] matrix is ​​created as a matrix of NULL values, as described above with reference to FIG. 12A. In step 2, the first 2 bits of the data packet are read. In this example, the first data packet is 00. Therefore, a count of data pattern 00 at index 1 is added to IAE[2]. In step 3, the second data packet is read. In this example, the second data packet is also 00. Therefore, another count of data pattern 00 at index 1 is added to IAE[2]. Therefore, the count of data pattern 00 at index 1 is 2. All other indices remain as NULL counts. In step 4, the third data packet is read. In this example, the third data packet is also 00. Therefore, another count of data pattern 00 at index 1 is added to IAE[2]. Therefore, the count of data pattern 00 at index 1 is 3. All other indices remain as NULL counts.

[0260] In step 5, the fourth data packet is read. In this example, the fourth data packet is 01. Therefore, the count of data pattern 01 at index 2 is added to IAE[2]. Therefore, the count of data pattern 00 at index 1 is 3, the count of data pattern 01 at index 2 is 1, and the other two indexes 3 and 4 still have NULL counts.

[0261] In step 6, the fifth data packet is read. In this example, the fifth data packet is 10. Therefore, the count of data pattern 10 at index 3 is added to IAE[2]. Therefore, data pattern 00 at index 1 has a count of 3, data pattern 01 at index 2 has a count of 1, data pattern 10 at index 3 has a count of 1, and data pattern 11 at index 4 still has a count of NULL. As discussed above with reference to Figure 4, the logic implemented by the AAR chip at this point indicates that a PCB event has occurred (because IAE[2] has lost all but one NULL value). Furthermore, in the next step (step 7), that one NULL value is lost. This confirms the PCB event.

[0262] In step 7, the sixth data packet is read. In this example, the sixth data packet is 11. Therefore, the count of data pattern 11 at index 4 is added to IAE[2]. Thus, data pattern 00 at index 1 has a count of 3, data pattern 01 at index 2 has a count of 1, data pattern 10 at index 3 has a count of 1, and data pattern 11 at index 4 has a count of 1. As discussed above with reference to FIG. 9C, the logic implemented by the AAR chip at this point indicates that an FCB event has occurred (because IAE[2] has lost all NULL values).

[0263] When an FCB event is detected, the stream of data that was read is assigned an index (s, g), where s represents the size (SIZE=2 in this case) and g is a global identifier. The count value of the data stream is stored in IAE[2] as shown in table (C). Then, the data or properties of the data stored in IAE[2] are copied to IAE[3] as shown in table (D). The copied data are called the statistical probabilities of the stream. These statistical probabilities are calculated using the value of the SIZE variable (SIZE=2 in this case), the global identifier g (a pointer to the memory location where the stream is stored), and the variable R representing the maximum register value. h(In this case, the maximum register value is 00 because the data pattern 00 has the maximum count), and a variable R representing the index of the minimum value. l (In this case, data pattern 11 has the lowest count and is the last pattern read before the FCB event. In some embodiments, the last pattern read before the FCB may be marked in the IAE[2] matrix or sent directly to the IAE[3] matrix.)

[0264] After IAE[2] and IAE[3] are updated and saved, reading of the input binary stream resumes and new IAE[2] and IAE[3] matrices are created and updated accordingly. This process is repeated until the complete input binary stream is read.

[0265] FIG. 12D is a block diagram illustrating an exemplary process for generating superimposed surfaces of intermediate arithmetic complexes and obtaining a final arithmetic complex as an output.

[0266] In step (A), data associated with the streams generated according to the process described above with reference to Figure 12C is stored in the SPP generator. The streams are stored as Intermediate Arithmetic Compounds (IAC), where each IAC includes the stream (IAE[1]), a size, a global identifier, IAE[2], and IAE[3].

[0267] In step (B), the IACs are indiscriminately combined to generate different combinations of IACs. In step (C), the combined IACs are stored as SPP storage matrices of different lengths. Each combination of streams in the SPP storage matrix is ​​subjected to fuzzy logic analysis in step (D) to generate a final arithmetic composite output.

[0268] (BFX Chip: An exemplary compression technique of CQME for realizing logical inverse calculations) As described above with reference to Figures 1 and 2, the Binary Fourier X-gate (BFX) chip is configured to accept input data, such as data received from the AAR chip described above, and compress the data by applying principles of the ensemble interpretation of quantum mechanics.

[0269] For example, the output from the AAR chip can be accepted by the BFX chip at three ports. That is, the input data stream (originally received as input by the AAR chip) can be provided at one input port BFX-IP1, the IAE [2] statistical operator can be provided at a second input port BFX-IP2, and the statistical probability can be provided at a third input port BFX-IP3. The BFX chip generates a compressed CQME data stream using the statistical probability. Data from the first input port BFX-IP1 and the third input port BFX-IP3 can be sent to a specially designed one-way swap gate (SWAPG) that compresses the data using the statistical probability. The BFX chip outputs the CQME at the first output port BFX-OP1. The BFX chip also outputs the ancillary matrix at the second output port BFX-OP2. The output can be stored in local memory and / or sent to an external device. The two output streams can be combined without a delimiter, allowing the external device to treat the output as a single stream.

[0270] In some embodiments, the external device can be, for example, an AAR chip for performing another round of compression. That is, because classical compression information theory is not used, the compressed data stream output can be repeatedly provided for recompression. In classical compression, the algorithm performs a first round of compression and a second round of compression, which has the opposite effect: the second round of compression expands the size instead of compressing the data. This occurs because classical compression information theory searches for repetitions or common patterns and then replaces them by referencing an index header. Classical compression changes the entropy of the input file, so that repetitions and patterns no longer exist, limiting the algorithm's ability to perform lookups for repetitions.

[0271] The application of the principles of ensemble interpretation of quantum mechanics ensures that the entropy of the CQME data stream remains unchanged and can be compressed again. The BFX chip can receive data in binary format, process it using ensemble interpretation and other principles of quantum mechanics, and provide output in binary format, thus forming a quantum-classical interface, similar to the AAR chip. The BFX chip can store inputs and outputs in memory as lookup tables. The number of inputs and outputs is theoretically unlimited, but in practice is limited only by the chip's hardware capabilities. In some embodiments, the lookup tables can be compressed to increase optimal use of storage space and theoretically prevent the module from running out of storage space. Therefore, data can be retrieved from storage memory without loss, enabling logical inverse calculations.

[0272] The processes and components described below with reference to the BFX chip are designed to interact with the processes and components described above with reference to the AAR chip, but can also accept appropriate data inputs from other sources.

[0273] 13 is a block diagram of an exemplary BFX board design. The BFX board includes a BFX chipset 1302 and a BFX chip 1304. The BFX chipset 1302 includes the BFX chip 1304 and supporting components such as memory, tables, buses, and ports. The BFX board is configured to interact with other boards and storage devices to implement various applications. In this disclosure, the BFX board interacts with the AAR chip to achieve a target amount of lossless compression.

[0274] The BFX chip 1304 may be implemented as a hardware gate, or an embedded or non-embedded chip / processor. The BFX chip may also be implemented as a software module or embedded logic code designed to accept data input and produce output in binary without storing the data (binary or quantum).

[0275] The BFX chipset 1302 includes three input ports BFX-IP1, BFX-IP2, and BFX-IP3. Each input port can receive a respective data input. For example, input port BFX-IP1 can receive IAE[1], which includes the input data stream originally received as input by the AAR chip, for example. Input port BFX-IP2 can receive a matrix IAE[2], which includes statistical operators for the input data stream. Input port BFX-IP3 can receive IAE[3], which includes statistical probabilities for the input data stream. The BFX chipset 1302 includes a preprocessor 1306 configured to process the data inputs received by input ports BFX-IP1, BFX-IP2, and BFX-IP3. For example, the preprocessor 1306 can be configured to accept inputs and store the inputs in a matrix, referred to herein as BFXINP. This matrix can be represented by the following structure: BFXINP s,tg ={IAE[1] s,tg ,IAE[2] s,tg ,IAE[3] s,tg} where tg represents the temporary global identifier of the input and s represents its size.

[0276] The data compression process performed by the BFX chipset does not require access to the statistical operators received in IAE [2]. Thus, in some embodiments, preprocessor 1306 can read data BFX-IP1, BFX-IP2, and BFX-IP3 and discard 1308 data read from BFX-IP2.

[0277] The preprocessor 1306 processes the data element IAE[1] s,tg and IAE[3] s,tg to a FIFO memory 1310 included in the BFX chip 1304. The FIFO memory 1310 stores IAE[1] and IAE[3]. A queue manager 1312 included in the BFX chip 1304 manages the transmission of IAE[1] and IAE[3] to other components within the BFX chip 1304. For example, the FIFO memory 1310 can directly pass IAE[3] to the output port BFX-OP2 via the queue manager 1312 once processing of IAE[1] is completed by the one-way swap gate (SWAPG) 1316. Furthermore, the FIFO memory 1310 can directly pass IAE[3] to the output port BFX-OP2, so that IAE[3] can be provided to the rBFX chip for subsequent calculation, e.g., decompression. The queue manager 1312 in FIG. 13 provides functionality similar to the queue manager QMGR1 in the AAR chip, as described above with reference to FIG. 4.

[0278] The FIFO memory 1310 copies the data elements IAE[1] and IAE[3] to the BFX local volatile memory (BFXLVM) 1314 via the queue manager 1312 and the data parser 1318. The data parser 1318 analyzes the data according to its size and sends it to the swap gate.

[0279] The BFXLVM 1314 is configured to operate in conjunction with a one-way swap gate (SWAPG) 1316. The BFX chip 1304 is configured to perform multiple operations within the BFXLVM 1314 to generate input data for the SWAPG 1316.

[0280] For example, the BFX chip 1304 is s,tg .IAE[3] s, .{R h})) and stores the identified RV of the maximum index value as Binary Value High (BVALH).

[0281] Furthermore, the BFX chip 1304 s,tg .IAE[3] s, .{R l})) and storing the identified RV with the lowest index value as a Binary Value Low (BVALL).

[0282] Furthermore, the BFX chip 1304 is configured to analyze the data pattern of BVALL to obtain the values ​​of PTYP and PSTRUC, then the BFX chip 1304 removes the last bit of PSTRUC, concatenates PTYP with the remaining PSTRUC value, and saves the value as the variable L_PSTRUCT.

[0283] Furthermore, the BFX chip 1304 is configured to analyze the data pattern of BVALL to obtain the values ​​of PTYP and PSTRUC. Next, the BFXLVM 1314 deletes the last bit of PSTRUC, replaces the deleted last bit with the inverse value, and concatenates PTYP and the new PSTRUC to generate the variable L_BVALL.

[0284] Then the BFX chip is streamed by SWAPG1316 BFXINP s,tgThe SWAPG1316 is configured to perform multiple swapping operations to compress the IAE (1). To perform the compression, the SWAPG1316 uses multiple sub-modules of the BFX chip. The sub-modules include a first error correction module (E), a second error correction module (F), an LE swap module (A), an L swap module (B), an H swap module (C), and an internal serial port module called an other module (D).

[0285] Figure 14 is a block diagram illustrating the sub-modules included in the one-way swap gate SWAPG 1316 of Figure 13. An Error Correction 1 (EC1) module 1401 is configured to enable SWAPG to terminate processing when a defined value of BVALL or LG is encountered, pausing operation until new data is available.

[0286] The Error Correction 1 (EC1) module 1401 ensures synchronized event processing, starting the process of one task at a time to avoid data and / or memory corruption. The Error Correction 2 (EC2) module is configured to monitor when data is written to BFX-OP1 and cause SWAPG to read the new data. This also ensures that SWAPG (One-Way One-Task Gate) reads one data element (i.e., one data pattern packet) at a time.

[0287] The L-Swap (LG) module 1404 is configured to determine if the input data is equal to BVALL, stop processing, write the output of BVALL 1413 from IAE[3] to BFX-OP1 1416, and wait for additional data to arrive.

[0288] The H-Swap (HG) module 1405 is configured to determine whether the input data is equal to BVALH and write the output of L_PSTRUCT 1414 to BFX-OP1 1416 .

[0289] The LE swap (LE) module 1406 is configured to determine if the input data is equal to L_BVALL and write the output of BVALH 1415 to BFX-OP1 1416 .

[0290] Another port module 1407 is an internal serial port built into SWAPG and acts as an "else" case. If the input data does not match any of the existing gates (LG, HG, LE), the other port module passes the input data to BFX-OP1 1416 (1412).

[0291] The output 1416 written to BFX-OP1 is OUT_IAE[1] g The data is copied to the output port OUT_IAE[1] (1417). The 'g' represents a global identifier, allowing multiple streams to be stored in local volatile memory. The data copy to the output port OUT_IAE[1] can be provided to an external device 1418.

[0292] Returning to Figure 13, the output from the one-way swap gate 1316 is forwarded to the BFXLVM. Because processing data through the swap gate is a sequential process, the swap gate output is forwarded to the BFXLVM 1314, where it is stored and pushed to the final output port once the buffer is complete. This does not mean that data is sent to the output port after a full input is complete, but rather that it is sent according to the buffer within the BFX board. The buffer size is dynamic and may vary depending on the particular implementation.

[0293] When the data is pushed to the final port, the statistical probability stored in IAE[3] is R h , size, and R l Only the last bit of R h Value (RHV), last bit R l PSTRUC(LBP), the term for LBP, Int1 is called size(SZ) and stores the size(s).

[0294] The output can be rerouted to the AAR chipset for another round of compression according to the calculation rules defined in the operator configuration table. g and IAE[3] g is written to BFX-OP1 and BFX-OP2. The rerouting of data depends on user input regarding compression level, such as a compression value between 1% and 99%.

[0295] In some embodiments, the BFX board may include a heat sink that provides liquid, air, or metal-based cooling. In some embodiments, the BFX board may include a service port that allows connection of a device to check the health of the hardware and perform debugging in the event of a failure.

[0296] Figure 15 is a block diagram for implementing a one-way swap gate on the exemplary input binary data streams IAE[1] and IAE[3] of Figures 12A-12D. In Figure 15, box (A) illustrates the exemplary input binary data stream IAE[1]. Box (B) illustrates the IAE[3] associated with the input binary data stream, as described above with reference to Figure 12D.

[0297] As described above with reference to Figure 13, the BFX chip uses the data in IAE[3] to generate the input configuration for the LG Swap, HG Swap, and LE Swap modules included in the one-way swap gate. This configuration is shown in Listing (C) of Figure 15. In this example, BVALL is equal to 11 (see IAE[2] in Figure 12C) and is marked in RBFXLVM as an FCB at index position 04. This value is copied and stored in IAE[3]. l According to the logic implemented by the BFX chip, the LG swap module stops processing data when the input value is 11. Similarly, BVALH is equal to 00. This means that the maximum repeat count of the Data Pattern (DP) in IAE[1] is R h=00 and has a count value of 3. Therefore, the HS swap module replaces the data pattern 00 with the value 1 (L_PSTRUCT is calculated according to the following logic in this example): the value of L_PSTRUC is the value of BVALL minus the last bit of PSTRUC. In this case, the length of PSTRUC is 1, so only the PTYP value of BVALL ("1") becomes the value L_PSTRUC). L_BVALL is equal to the inverse of the last bit of PSTRUC of BVALL ("0") concatenated with the PSTRUC of BVALL ("1"), resulting in L_BVALL being 10.

[0298] Therefore, the LE swap module replaces the data pattern 10 with BVALH, which is 00.

[0299] In summary, the operation of a swap gate can be explained as follows: reading the data pattern 11 means stop, reading 00 means replace 00 with 1, and reading 10 means replace 10 with 00. Box (F) shows a compressed version of the input data stream shown in box (E). As shown, application of the one-way swap gate compresses 12 bits into 7 bits.

[0300] 16 is a flow diagram of a process 1600 for compressing an input data stream divided into data packets according to a variable SIZE. For convenience, the process 1600 is described as being performed by a system including an AAR chip and a BFX chip located in one or more locations. For example, a system including the AAR chipset of FIG. 4 and the BFX chipset of FIG. 13, and appropriately programmed, can perform the exemplary process 1600.

[0301] The system reads the input data stream to identify PCB events (step 1602). A first example of an input data stream split into data packets of SIZE=4 is shown below: 0000 0000 0000 0001 0000 0100 1111 0101 0000 0001 0000 0000 0000 0000 0000 0100 0001 0100 0000 0000 0000 0000 0000 0000 0101 0000 0100 1011 0000 0001 0000 0010 0001 0100 0000 0011 0001 0100 0000 0000 0000 1000 0000 0000 0000 1000 0000 0000 1111 1010 1000 0001 0111 1101 0101 0011 0111 1011 0011 0010 0101 0010 1001 1100 1110 1010 0000 0000 0000 0000 0000 0000 0101 1001 0000 0001 0000 0000 0000 0000 0001 0110 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 1101 1000 0001 1011 1000 0000 0101 0000 0000 0000 0000 0101 1111 0101 1111 0100 1101 0100 0001 0100 0011 0100 1111 0101 0011 0101 1000 0010 1111 0010 1110 0101 1111 0110 0100 0110 1101 0110 0111 0011 0010 0110 1010 0110 1111 0110 1000 0110 1110 0010 1110 0111 0000 0111 1001 0101 0101 0101 0100 0000 1101 0000 0000 0000 0111 0111 1000 1100

[0302] In this first example, the input data stream contains 173 data packets, so the bit length is (173*4) = 692. Furthermore, in this first example, the data pattern 1110 first appears in the 65th data packet, so a PCB event is identified when the data pattern 1110 is read: 0000 0000 0000 0001 0000 0100 1111 0101 0000 0001 0000 0000 0000 0000 0000 0100 0001 0100 0000 0000 0000 0000 0000 0101 0000 0100 1011 0000 0001 0000 0010 0001 0100 0000 0011 0001 0100 0000 0000 0000 1000 0000 0000 1000 0000 0000 1111 1010 1000 0001 0111 1101 0101 0011 0111 1011 0011 0010 0101 0010 1001 1100 1110…

[0303] The system continues reading the input data stream and identifies the FCB event (step 1604). In this first example, the system reads 17 more data packets before the FCB event is detected. In this first example, the data pattern 0110 first appears in the 82nd data packet, so the FCB event is identified when the data pattern 0110 is read: …1010 0000 0000 0000 0000 0000 0000 0101 1001 0000 0001 0000 0000 0000 0000 0001 0110…

[0304] After the FCB event is detected, the system finishes reading the input data. Therefore, the read portion of the input data stream is the first 82 data packets of the input data stream, which contains 82*4=328 bits: 0000 0000 0000 0001 0000 0100 1111 0101 0000 0001 0000 0000 0000 0000 0000 0100 0001 0100 0000 0000 0000 0000 0000 0101 0000 0100 1011 0000 0001 0000 0010 0001 0100 0000 0011 0001 0100 0000 0000 0000 1000 0000 0000 1000 0000 0000 1111 1010 1000 0001 0111 1101 0101 0011 0111 1011 0011 0010 0101 0010 1001 1100 1110 1010 0000 0000 0000 0000 0000 0000 0101 1001 0000 0001 0000 0000 0000 0000 0001 0110

[0305] The system generates an IAE[2] matrix for the read portion of the input data stream (step 1606). In this first example, the IAE[2] matrix is ​​given by: [Table 1]

[0306] The system generates an IAE[3] matrix for the read portion of the input data stream (step 1608). In this first example, the IAE[3] matrix is ​​given by: [Table 2]

[0307] The system then programs the one-way swap gate using IAE[3] (step 1610). In this first example, -Variable Binary Value High (BVALH) = 0000 (PTYP = 0, PSTRUC = 000) - Variable Binary Value Low (BVALL) = 0110 (PTYP = 0, PSTRUC = 110), where BVALL is 0110 because data pattern 0110 was the last data pattern to update the NULL count to 1 (data patterns 1100, 1101, and 1110 also have counts of "1," but these counts were changed from NULL to 1 before the count of data pattern 0110 was changed). This logic applies in a similar context in this disclosure. -Variable L_PSTRUCT = (copy all bits except the last bit of BVALL), in other words (delete the end of PSTRUC and concatenate PTYP+REMAINING PSTRUC) = 011. -Variable L_BVALL = (first 3 bits of BVALL + inverse of last bit of BVALL), or in other words (delete the end of PSTRUC and replace it with its inverse value, concatenate PTYP + NEW PSTRUC) = 0111.

[0308] So the rule set for a one-way swap gate is given by: -H swap or (HG) module: Replace BVALH with L_PSTRUCT (0000 is replaced with 011) -LE swap or (LE) module: Replace L_BVALL with BVALH (0111 is replaced with 0000) -L swap or (LG) module: Complete the stream (stop at 0110) when BVALL is encountered -Other: If none of the above applies, pass the data.

[0309] The system applies the programmed one-way swap gate to the read portion of the input data stream to compress the read portion of the input stream (step 1612). In the first example, the following compressed data stream is obtained: 011 011 011 0001 011 0100 1111 0101 011 0001 011 011 011 011 011 0100 0001 0100 011 011 011 011 011 011 0101 011 0100 1011 011 0001 011 0010 0001 0100 011 0011 0001 0100 011 011 011 1000 011 011 011 1000 011 011 1111 1010 1000 0001 0000 1101 0101 0011 0000 1011 0011 0010 0101 0010 1001 1100 1110 1010 0000 0000 0000 0000 0000 0000 0101 1001 0000 0001 0000 0000 0000 0000 0001 0110

[0310] This compressed data stream has an output size of 300 bits, so the compression ratio is

[0311] (Original stream size - Compressed stream size) / Original stream size, which in this example is (328 - 300) / 328 = 8.53%.

[0312] The system may repeat steps 1602-1612 until the entire input data stream has been read.

[0313] A second example of an input data stream split into data packets of SIZE=4 is shown below: 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 1101 1000 0001 1011 1000 0000 0101 0000 0000 0000 0000 0101 1111 0101 1111 0100 1101 0100 0001 0100 0011 0100 1111 0101 0011 0101 1000 0010 1111 0010 1110 0101 1111 0110 0100 0110 1101 0110 0111 0011 0010 0110 1010 0110 1111 0110 1000 0110 1110 0010 1110 0111 0000 0111 1001 0101 0101 0101 0100 0000 1101 0000 0000 0000 0111 0111 1000 1100

[0314] In this second example, a PCB event is identified when the data pattern 1001 is read: 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 1101 1000 0001 1011 1000 0000 0101 0000 0000 0000 0000 0101 1111 0101 1111 0100 1101 0100 0001 0100 0011 0100 1111 0101 0011 0101 1000 0010 1111 0010 1110 0101 1111 0110 0100 0110 1101 0110 0111 0011 0010 0110 1010 0110 1111 0110 1000 0110 1110 0010 1110 0111 0000 0111 1001…

[0315] An FCB event is identified when the data pattern 1100 is read: …0101 0101 0101 0100 0000 1101 0000 0000 0000 0111 0111 1000 1100…

[0316] So the read portion of the input data stream is the first 91 data packets of the input data stream, which contains 91*4=364 bits: 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 1101 1000 0001 1011 1000 0000 0101 0000 0000 0000 0000 0101 1111 0101 1111 0100 1101 0100 0001 0100 0011 0100 1111 0101 0011 0101 1000 0010 1111 0010 1110 0101 1111 0110 0100 0110 1101 0110 0111 0011 0010 0110 1010 0110 1111 0110 1000 0110 1110 0010 1110 0111 0000 0111 1001 0101 0101 0101 0100 0000 1101 0000 0000 0000 0111 0111 1000 1100

[0317] In this second example, the IAE[2] matrix is ​​given by: [Table 3]

[0318] In this second example, the IAE[3] matrix is ​​given by: [Table 4]

[0319] In this second example, the variables needed to program the one-way swap gate are given as follows: -Binary Value High(BVALH)=0000(PTYP=0, PSTRUC=000) -Binary Value Low(BVALL)=1100(PTYP=1, PSTRUC=100) -L_PSTRUCT=(copy all bits except the last bit of BVALL), or (delete the end of PSTRUC and concatenate PTYP+REMAINING PSTRUC)=110 -L_BVALL=(first 3 bits of BVALL + inverse of last bit of BVALL), or (delete the end of PSTRUC, replace with its inverse value, concatenate PTYP+NEW PSTRUC)=1101 And the rule set for the one-way swap gate is given by: -H swap or (HG) module: replace BVALH with L_PSTRUCT, in other words (0000 is replaced with 110) -LE swap or (LE) module: replace L_BVALL with BVALH, in other words (1101 with 0000) -L swap or (LG) module: Complete the stream (stop at 0110) when BVALL is encountered -Other: If none of the above applies, pass the data

[0320] Application of the programmed one-way swap gate to the read portion of the input stream produces the following compressed data stream: 110 110 0010 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 1110 0000 1000 0001 1011 1000 110 0101 110 110 110 110 0101 1111 0101 1111 0100 0000 0100 0001 0100 0011 0100 1111 0101 0011 0101 1000 0010 1111 0010 1110 0101 1111 0110 0100 0110 0000 0110 0111 0011 0010 0110 1010 0110 1111 0110 1000 0110 1110 0010 1110 0111 110 0111 1001 0101 0101 0101 0100 0000 1101 0000 0000 0000 0111 0111 1000 1100

[0321] This compressed data stream has an output size of 338 bits, so the compression ratio is

[0322] (original stream size - compressed stream size) / original stream size, which in this example is (364 - 338) / 364 = 7.14%.

[0323] FIG. 17 is a flow diagram of a process 1700 for compressing a classical binary data input. For convenience, the process 1700 is described as being performed by a system including an AAR chip and a BFX chip located in one or more locations. For example, a system including the AAR chipset of FIG. 4 and the BFX chipset of FIG. 13 , when appropriately programmed, can perform the exemplary process 1700. The exemplary process 1700 can be combined with any of the techniques described in this disclosure, such as those described above with reference to FIGS. 1A-16.

[0324] The system receives a classical binary data input (step 1702). The system performs a classical operation on the classical binary data input and obtains metadata for the classical binary data input (step 1704). The classical operation is based on an ensemble interpretation of quantum mechanics, for example, as described above with reference to FIGS. 1A-12D.

[0325] The metadata includes the intermediate arithmetic elements (IAEs), IAE[1], IAE[2], and IAE[3], described above with reference to FIGS. 1A-16. For example, the metadata includes the classical binary data input obtained in step 1702, divided into multiple data packets of length equal to the predetermined size, for each of one or more predetermined sizes corresponding to respective virtual Hilbert spaces (e.g., the metadata includes multiple IAE[1] matrices). Each data packet has a respective data pattern defining the type of data packet, and the data pattern is predefined based on the size of the corresponding virtual Hilbert space. For example, for a virtual Hilbert space of size 2, each data packet has a data pattern from the set {00, 10, 01, 11}. The data patterns were described in more detail above with reference to FIG. 8. Furthermore, each data packet has a respective correlation value representing a measure of virtual quantum entanglement. The correlation value and virtual quantum entanglement were described in more detail above with reference to FIGS. 8 and 12B. The classical binary data input divided into data packets forms a classical quantum multi-element (CQME) system. Each data packet includes a correlation value representing a virtual entanglement measure and a data pattern that defines the type of data packet.

[0326] The metadata further includes values ​​representing data patterns (DPs) that appear in the classical binary data input and values ​​representing counts of occurrences of the data patterns (DPs) in the classical binary data input (e.g., the metadata includes multiple IAE[2] matrices). The values ​​representing the data patterns (DPs) that appear in the classical binary data input are directly determined by the size of the respective virtual Hilbert spaces and are independent of the particular classical binary data input. The values ​​representing counts of occurrences of the data patterns (DPs) in the classical binary data input are determined by the classical binary data input and are obtained by reading the classical binary data input and detecting PCB and FCB events, for example, as described above with reference to Figures 4, 9B, and 11C.

[0327] By construction, the occurrence count of a data pattern (DP) in a classical binary data input includes counts representing unique data patterns (DP) in a proper or improper subset of the classical binary data input. This is because the generation of each IAE[2] matrix terminates when a proper or improper subset of the classical binary data input contains one unique data pattern. See, for example, Figure 15. The occurrence count of a data pattern (DP) in a classical binary data input is called the statistical operator of the classical binary data input. The occurrence count of a data pattern (DP) in a classical binary data input is called the value of the statistical operator because it characterizes the classical binary data input.

[0328] The metadata further includes values ​​representing statistical probabilities of classical binary data inputs (e.g., the metadata includes multiple IAE[3] matrices). The values ​​representing statistical probabilities of classical binary data inputs are based on the values ​​of statistical operators and include data patterns (DPs) corresponding to maximum and minimum occurrence counts. See, for example, FIG. 16. These statistical probabilities define the statistical properties of the CQME.

[0329] The metadata includes an optimal arithmetic complex that characterizes the classical binary data input and preserves the values ​​of the statistical operators. The optimal arithmetic complex is selected from a plurality of candidate arithmetic complexes that form a superposition surface of the virtual quantum state. Each of the plurality of candidate arithmetic complexes corresponds to a virtual quantum state in a respective virtual Hilbert space. The optimal arithmetic complex is selected from the plurality of candidate arithmetic complexes through virtual time measurements of the virtual quantum state. The optimal arithmetic complex i) has the same length as the classical binary data input, ii) has the same entropy as the classical binary data input, and iii) includes at least one singularity. It has been described above with reference to FIGS. 4 and 11A that selecting the optimal arithmetic complex is selecting from a plurality of candidate arithmetic complexes that form a superposition surface of the virtual quantum state.

[0330] The system compresses the metadata by applying a swap gate to the metadata (step 1706). The swap gate swaps data as a one-way function, and the application of the swap gate is defined by the value of a statistical operator included in the metadata. For example, applying the one-way swap gate to the metadata swaps occurrences of the data pattern (DP) with the highest occurrence count (specified in the metadata) with a bit string that is shorter than the data pattern (DP) with the maximum count. The bit string includes a concatenation of i) the virtual entanglement measure of the data pattern (DP) with the lowest occurrence count (specified in the metadata) and ii) the remaining bits of the data pattern (DP) with the lowest occurrence count, excluding the final bit of the data pattern (DP) with the lowest occurrence count (specified in the metadata). See, for example, the example provided with reference to FIG. 16.

[0331] The system provides the compressed metadata as compressed classical binary data input, step 1708. As described above with reference to Figure 4, by construction, the compressed classical binary data input has the same entropy as the classical binary data input.

[0332] In some embodiments, the system can output a compressed classical binary data input. In other embodiments, the system can iteratively process the compressed classical binary data input until a target data compression ratio is achieved. For example, in each iteration, the system can perform classical operations on the classical binary data input for the iteration to generate metadata for the iteration, apply a swap gate to the metadata for the iteration to compress the metadata for the iteration, and provide the compressed metadata for the iteration as input for the subsequent iteration.

[0333] (rBFX Chipset: Exemplary Techniques for Data Decompression) Data compressed by the AAR and BFX chipsets can be decompressed by a Reverse Binary Fourier X-gate (rBFX) chip. The rBFX chip is configured to read compressed data input (in the form of a CQME system) and decompress the data using a logic engine that interprets the CQME system and converts it to classical data. The rBFX chip reuses some components and logic routines from the AAR and BFX chips. These components preserve the ensemble interpretation and quantum-classical interface properties described above from the AAR or BFX chip to process the input data.

[0334] For example, the rBFX chip is configured to receive input data as a concatenation of a series of intermediate arithmetic complexes (IACs), each of which is part of the input data stream and includes a header (ancillary matrix / IAE[3]) plus data (IAE[1]). The rBFX chip is configured to convert the input data into a binary, unbounded data stream. A first predetermined number of bits (7 bits) is sent to a first rBFX chip input port RBFX-IP1, and the remainder of the stream is sent to a second rBFX chip input port RBFX-IP2. The rBFX chip loads the data from the input port into memory and generates candidate metadata from the data, such as values ​​of statistical operators based on a virtual quantum entanglement measure, occurrence counts of data patterns (DPs) including unique data patterns (DPs), and the size of the virtual quantum Hilbert space described above with reference to the AAR and BFX chips. The data from the input port and the candidate metadata are processed using a kernel filter to identify correct metadata from the candidate metadata. The correct metadata is then used to apply a reverse one-way swap gate to decompress the data.

[0335] The kernel filter and the inverse one-way swap gate are defined using a value referred to herein as L_STRUC. L_STRUC is a value analogous to the ensemble interpretation of quantum mechanics, where quantum entanglement can occur not only through a single observation but also through multiple observation states. This quantum mechanical property is analogous to the removal of the final bit during compression in the BFX chip and the widespread deployment of uniqueness across compression due to the detection of PCB and FCB events. This property also extends to the rBFX chip, as it assumes a value for L_STRUC. This specification ensures that when a chunk of size - 1 is read, a "valid" L_STRUC repetition is the only element read. For example, if the size element is equal to 4, the L_STRUC size is 3, and the preprocessor gate described below reads a chunk of size 3 with the first three elements equal to 000 (as an example), then the maximum possible repetition of the final data stream within the preprocessor gate will be equal to the valid L_STRUC. There is no deviation from this logic, as several advanced statistical methods have been introduced from AAR to BFX to enable data reading at the preprocessor gate to derive a valid L_STRUC.

[0336] In some embodiments, the output of the decompressed data stream can be repeatedly fed for re-decompression, since application of the principles of the presently described ensemble interpretation of quantum mechanics ensures that the entropy of the CQME data stream remains unchanged and can be decompressed again.

[0337] The rBFX chip can receive data in binary format, process the data using ensemble interpretations and other principles of quantum mechanics, and provide output in binary format, forming a quantum-classical interface. The rBFX chip can store inputs and outputs in memory as lookup tables. The number of inputs and outputs is theoretically unlimited, but in practice is limited only by the chip's hardware capabilities. Therefore, data can be retrieved from storage memory without loss, enabling logical inverse calculations.

[0338] The processes and components described below with reference to the rBFX chip are designed to interact with the processes and components described herein with reference to the AAR chip and BFX chip, although the rBFX chip can also accept appropriate data input from other sources.

[0339] 18 is a block diagram of an exemplary rBFX board design. The rBFX board includes an rBFX chipset and an rBFX chip. The rBFX chipset includes the rBFX chip and auxiliary components such as memory, tables, buses, and ports. The rBFX board is configured to interact with other boards and storage devices to implement various applications. In this disclosure, the rBFX board interacts with the rBFX chip to decompress compressed data.

[0340] The rBFX chip can be implemented as a hardware gate, or an embedded or non-embedded chip / processor. The rBFX chip can also be implemented as a software module or embedded logic code designed to accept data input and produce output in binary without storing the data (binary or quantum).

[0341] The rBFX chipset, as previously described, includes two input ports, rBFX-IP1 1802 and rBFX-IP2 1803. Input ports 1802, 1803 can receive data input from input interface 1801 and provide the received data input to rBFX chipset module 1804, which converts the data input to binary format. The converted data, referred to herein as the Input Stream (INS), is stored in onboard FIFO memory 1805 included in the rBFX chip.

[0342] The stored data includes multiple matrices, each of which is referred to herein as an Input Data Array (IDA). Each IDA contains a respective IAE[1] and IAE[3] matrix, denoted as follows: IDA n ={IAE[1] n ,IAE[3] n} where n represents a unique identifier. The input stream (INS) is formed from a combination of input data arrays (IDA) and can be expressed as follows: IDA1+IDA2+…+IDA n , i.e., INS=∫ n IDA n An input stream (INS) represents a CQME stream containing non-delimited input data arrays (IDAs) or elements. These elements in the stream contain a fixed-length (AM or IAE[3]) header, as follows: [Table 5] Last bit R l PSTRUC LBP is defined as a single bit equal to the last bit of PSTRUC.

[0343] To begin the decompression process, the rBFX chip is configured to parse the header by reading from the beginning of the input stream (INS). The following information is extracted: -Final bit R l PSTRUC(LBP): R of elements generated by the BFX chip and stored in IAE[3] or BVALH (defined above with reference to the AAR chip). l Defines the last bit of -R h Value (RHV): defines the maximum repeat value generated by the BFX chip and stored in IAE[3]. - Size (SZ): The size SZ of L_STRUC is determined by all possible binary combinations generated by Size (defined below) and is equivalent to the L_PSTRUC value in the AAR chip (in this disclosure, the term "L_STRUC" is used primarily in the context of the rBFX chip, and the term "L_PSTRUC" is used primarily in the context of the AAR or BFX chip). Size=SZ(at header 0x0003)-1 -Header length (HL): The length of the header (len) is 2 bits, or the sum of the lengths of DOP+LBP+SZ. HL=len(LBP)+len(RHV)+len(size)=7bits.

[0344] The rBFX chip contains a Configuration Variable Array 1 (CVAR1) 1806. CVAR1 1806 contains data representing FCB, L_STRUC, RHV, and L_ENT. L_ENT is defined as the entanglement value L_STRUC concatenated with the entanglement value LBP (from the header). The value of LBP is obtained from the header, while the value of L_STRUC is dynamically generated depending on the value of the size variable. The definition of the data stored in CVAR1 1806 is shown below:

[0345] The value of L_STRUC is determined by all possible binary combinations generated by the size, where size = SZ(Header 0x0003)-1.

[0346] The FCB value is generated by concatenating the assumed value of L_STRUC with the defined value of LBP (from the header).

[0347] The RHV value is provided by the IAE[3] or header at position 0x0002.

[0348] The L_ENT value is generated by concatenating the entanglement values ​​of L_STRUCi and LBP.

[0349] The rBFX chip is configured to provide the data stored in CVAR1 1806 to local memory RBFXLVM 1808. The rBFX chip then begins a two-step process to decompress the data.

[0350] In the first step, the rBFX chip begins extracting the IDAs. The input stream (INS) and the input matrix of pre-processor gate (PSG) inputs, or (PSGINi), (where "i" is a unique identifier), are sent to the pre-processor gate (PSG) 1509, which generates multiple input data arrays (IDAs). These input data arrays (IDAs) are sent to the rBFX swap gate (RSG) 1817 for data decompression.

[0351] To start decompression, rBFX initializes the variable PSGINi, which is a matrix of possible L_STRUCi values ​​according to the formula: i PSGIN i= ∫ L_STRUC i i=1

[0352] Value L_STRUC i teeth 、The Input Data Array (IDA) is extracted from the Input Stream (INS) via the following logical process:

[0353] The memory pointer containing the input stream (INS) from RBFX local memory (RBFXLVM) is PSGIN i The header location (LOC) is sent to the PSG along with the input of successive values ​​from the STRUCTURE. On the first read, the header location (LOC) is set to '1'. When the IDA is validated for a subsequent read event, the value of the header location (LOC) is updated. The data is read sequentially according to the size (SZ) and the L_STRUCTURE is set to '0'. iは The processed data is added to IAE[1], and a repeating data pattern (DP) is inserted in IAE[2], just like the AAR process. rBFX generates IAE[2] to obtain the PCB and FCB of IAE[1]. When rBFX encounters an FCB, it pauses reading the input stream (INS) and writes the read data to TEMP_IAE[1]. i Go to PCB i and FCB i TEMP_IDA i Store it as a unique matrix.

[0354] This is repeated for all L_STRUC values ​​and saved as a matrix Temporary L_STRUC(TLS) 1810. i TLS i =∫ TEMP_IDA i i=1

[0355] To select a valid IDA, the rBFX chip uses TLS i18. The KF1 is configured to pass the matrix to Kernel Filter #1 (KF1) 1811. In some cases, multiple Input Data Arrays (IDAs) are obtained as output from KF1. The multiple Input Data Arrays (IDAs) are sent to Kernel Filter #2 (KF2) 1815, or otherwise to RSG 1817. The dotted lines between 1813, 1815, and 1817 in FIG. 18 indicate that this is an optional step in case multiple Input Data Arrays (IDAs) are enumerated by KF1.

[0356] To process data through Kernel Filter 1 (KF1) 1811, the rBFX chip is configured to perform the following operations in IAE [2]:

[0357] Process 1 (KF1P1) 1812 determines whether the value of L_ENT is the maximum in IAE[2].

[0358] Process 2 (KF1P2) 1813 determines whether all index values ​​of IAE[2] are greater than 1.

[0359] The IDAs for which the above two processes (KF1P1 and KF1P2) are positive are saved in RBFXLVM1808.

[0360] Processing of data through Kernel Filter 2 (KF2) 1815 analyzes multiple Input Data Arrays (IDAs) and selects the IDA occupying the larger size in bits or data length as the final output.

[0361] The variable LOC is updated according to the bit size of the last IDA so that the PSG1809 can continue reading the input stream (INS) from the LOC offset to get the next valid IDA.

[0362] In the second step of the two-step process of decompressing the data, the rBFX chip processes the data through the rBFX swap gate 1817.

[0363] Figure 19 is a block diagram showing how data is processed in the rBFX swap gate. i The matrix 1901 is fed as an input to the rBFX Swap Gate (RSG) Input Port (RSGIP) 1902. The Data Parser Module (DPM) 1903 reads the data, splits it, and i , FCB i , and RHV 1904 (enumerated from the header) are stored in RSG Local Memory (RSGLM) 1905. Once the values ​​are stored, the DPM passes IAE[1] and enumerates the decompressed data in the following sequence: RSGLM is discarded once the FCB is received by the DPM.

[0364] The following switches are built into the RSG: The condition check 1919 is a binary switch (BINS) that detects the occurrence of PCBs and FCBs 1909, 1912 and data types for fast swaps 1917, 1918. The Data Parser Module (DPM) 1920 is a module configured to read data from the RSGIP, extract it according to the SZ (header 0x0003), and send it to the appropriate swap switch. - L_ENT Swap (LENS) 1921 is configured to swap the value of L_STRUC with RHV 1906. -High RV Swap(HRVS)1922 is R h It is configured to swap the value of value (RHV) (header 0x0002) with L_ENT1907. -Other Swap (OTHS) 1925 is configured to move data 1908 from input via 1924 to RSGOP without processing.

[0365] The DPM 1920 is configured to extract data according to the value of the variable SZ and perform the following processing: PCBBINS: Compare whether the data is equal to PCB (1909). If it is equal (1910), forward the data to LENS BINS. If not (1911), pass the data to FCB check. FCBBINS: Compare whether the data is equal to the FCB (1912). If yes, pass the data to OTHS (1914), clear the data in RSGLM (1913), and write a new TLS to RSG so that RSGOP can write the data to RBFX-OP1 (1915). i If not, pass the data to the next module / gate (LENS check, 1917). LENS BINS: If the input data is equal to L_ENT, send the data to LENS 1923, otherwise pass the data to HRVS check (1918). HRVS BINS: If the input data is equal to the RHV, send the data to the HRVS (1924).

[0366] If the data does not meet the above two conditions, the data is passed to OTHS (1925) and the system waits for new received data.

[0367] When IAE[1] encounters an FCB in the input data stream, it indicates that the final output (decompressed) data is available in RSGOP (1824 in FIG. 18) which is directed to RBF-OP1 (1825 in FIG. 18).

[0368] Figure 20 is a flow diagram of a process 2000 for decompressing an exemplary data stream, such as a data stream compressed according to exemplary process 1600 of Figure 16. For convenience, process 2000 will be described as being performed by a system including an rBFX chip. For example, a system including an appropriately programmed rBFX chipset of Figure 18 can perform exemplary process 2000.

[0369] The system prepares a decompressed input stream (INS) of size 4 and an L_STRUC array (step 2002). The system processes the input stream (INS) and the L_STRUC array using a preprocessor gate (PSG) (step 2004). The system identifies L_STRUC values ​​that satisfy a first kernel filter and selects the identified L_STRUC with the largest size as the final L_STRUC (step 2006). The system replaces L_STRUC in the input data array (IDA) that matches the final L_STRUC with L_ENT to obtain the output IDA (step 2008). The system processes TLS1 using an rBFX swap gate to detect PCB events in IDA (step 2010). The system converts all instances of L_STRUC before a PCB event occurs in IDA to RHV, converts all instances of RHV before a PCB event occurs to L_ENT, and passes all other values ​​(before and after the PCB event) to the rBFX chip output port to obtain decompressed data (step 2012). The system can repeat steps 2002-2012 until all compressed portions of the original input data stream have been decompressed.

[0370] Figure 21 is a flow diagram of a process for decompressing a compressed classical binary data input. For convenience, process 2100 is described as being performed by a system including an rBFX chip. For example, a system including the rBFX chipset of Figure 18, appropriately programmed, can perform exemplary process 2100. Exemplary process 2100 can be combined with any of the techniques described in this disclosure, such as those described above with reference to Figures 1A-20.

[0371] The system obtains a compressed classical binary data input (step 2102). For example, the system may receive a classical binary data input compressed by a BFX chip.

[0372] The system generates candidate metadata for the compressed classical binary data input (step 2104). The metadata includes values ​​of statistical operators for each portion of the compressed binary data input, where the statistical operators are based on an ensemble interpretation of quantum mechanics. Exemplary metadata is described throughout this disclosure, for example, with reference to the exemplary process 1700 of FIG. 17.

[0373] The system applies a kernel filter to the candidate metadata based on the value of the statistical operator to identify valid metadata for the classically compressed binary data input (step 2106). Applying the kernel filter to the candidate metadata includes identifying metadata that: i) does not contain a unique data pattern; ii) satisfies a condition for virtual quantum entanglement; and iii) has a maximum bit length. For example, the system may process the candidate metadata using KF1P1, KF1P2, and KF2, as described above with reference to FIG. 18.

[0374] The system applies a swap gate to the valid metadata and decompresses the valid metadata (step 2108). The swap gate swaps data as a one-way function, and the application of the swap gate is defined by the value of a statistical operator on the valid metadata. To apply the swap gate, the system may first identify occurrences of PCB events, e.g., occurrences of the second most unique data pattern, in the current portion of the compressed binary data input, and then identify occurrences of FCB events, e.g., occurrences of the most unique data pattern, in the current portion of the compressed binary data input. Next, the system may swap occurrences of L_STRUC (a data pattern representing a virtual quantum entanglement value) that occur before the PCB event with a bit string longer than L_STRUC, where the bit string longer than L_STRUC is equal to RHV (the data pattern with the most repeating values). The system may also swap occurrences of RHV that occur before the PCB event with a bit string longer than RHV, where the bit string longer than RHV is referred to herein as L_ENT and is equal to the concatenation of the inverse values ​​of L_STRUC and L_ENT. The one-way swap gate implemented by the rBFX chip was described in further detail above with reference to FIGS.

[0375] The system provides the decompressed valid metadata as decompressed compressed classical binary data input (step 2110). As described above, the decompression process performed by the rBFX chip reuses the techniques, definitions, and logic routines of the AAR and BFX chips. Thus, by construction, the decompressed classical data produced by the rBFX chip has the same entropy as the classically compressed data received in step 2102, as described herein with reference to the AAR and BFX chips. This allows the AAR, BFX, and rBFX chips to perform logical inverse calculations.

[0376] In some embodiments, the system can directly output the decompressed compressed classical binary data input, while in other embodiments, the system can iteratively process the decompressed compressed classical binary data input until a target data decompression rate is achieved.

[0377] Figure 22 shows the compression ratios achieved for an example bitstream using the techniques described in this disclosure for different values ​​of the variable SIZE. Examples #1 and #2 show compression results for the same first input string, where the first input string has a large median in the statistical distribution of the data pattern (DP). Examples #3 and #4 show compression results for the same second input string, where the second input string has a small median in the statistical distribution of the data pattern (DP).

[0378] In Example #1, the input stream is loaded into IAE[1] as a two-bit split stream. IAE[2] generates a count of the data pattern (DP) and stores the count of the data pattern. In the third row of the table in Example #1, the variable R h The distribution of has a value of 8 / 19, where 8 is the highest occurrence repetition number and 19 is the total count of binary packets. h The distribution of is at 42.10% of the IAE [1], so 8 bits are removed from a total of 392 bits. Therefore, applying the compression technique described here results in a compression of 21.05%. Note that R h Note that the distribution of is 42.10% (01 data pattern) which is 8 divided by 19. h One bit can be removed from a packet, resulting in an 8-bit compression, so for this example stream, this one round removes 8 bits or 21.05% of the total 38 bits.

[0379] In Example #2, the input stream is loaded into IAE[1] as a 4-bit split stream. IAE[2] generates a count of the data pattern (DP) and stores the count of the data pattern. In the third row of the table in Example #1, the variable R hThe distribution of R has values ​​from 16 to 100, where 16 is the highest occurrence repetition number and 100 is the total count of binary packets. h The distribution is at 16% of the IAE [1], so 16 bits are removed from a total of 400 bits. Applying the compression technique currently described results in a compression of 4.00%.

[0380] In Example #3, the input stream is loaded into IAE[1] as a two-bit split stream. IAE[2] generates a count of the data pattern (DP) and stores the count of the data pattern. In the third row of the table in Example #1, the variable R h The distribution of has a value of 3 / 7, where 3 is the highest occurrence repetition number and 7 is the total count of binary packets. R h The distribution is at 42.85% of the IAE [1], which removes 3 bits from a total of 14 bits, resulting in a compression of 21.42% when applying the compression technique currently described.

[0381] In Example #4, the input stream is loaded into IAE[1] as a 4-bit split stream. IAE[2] generates a count of the data pattern (DP) and stores the count of the data pattern. In the third row of the table in Example #1, the variable R h The distribution has a value of 4 / 37, where 4 is the highest occurrence repetition and 37 is the total count of binary packets. R h The distribution is at 10.81% of the IAE [1], which removes 4 bits from a total of 148 bits. Applying the compression technique described here results in a compression of 2.70%.

[0382] Examples #3 and #4 show that the distribution of data patterns (DP) does not deviate by more than +2 from the median of 2. In Example 3, R h The distribution is at 42.85%, resulting in a compression of 2.14%, and in Example 4, R h The distribution is at 10.81% and results in a compression of 2.70%.

[0383] Figure 23 shows round-by-round statistics for multiple compression processes. Analysis Table #1 is conservative and shows R values ​​between 2 and 10%. h Assuming a distribution, it shows a minimum of 1% compression. Analysis Table #2 shows the R h The distribution of values ​​shows average values ​​between 10-20% and 5-2%. The analysis table shows conservative results, and practical application of the currently described techniques would result in an average compression of 2% per round.

[0384] The embodiments and functional operations of the subject matter described in this disclosure can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware including the structures and structural equivalents disclosed in this disclosure, or a combination of one or more of them. The embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, i.e., as one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by or to control the operation of a data processing apparatus. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, such as a mechanically generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0385] The term "data processing apparatus" refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. An apparatus may also be or further include special-purpose logic circuitry, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). That is, some or all of the operations of each of the AAR chip, BFX chip, and rBFX chip described herein may be performed by a general-purpose processor or a special-purpose processor.

[0386] In addition to the hardware, the apparatus may optionally include code that establishes an execution environment for the computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or any combination of one or more of these.

[0387] A computer program may also be referred to or described as a program, software, software application, module, software module, script, or code, and may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and may be arranged in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored as part of a file that holds other programs or data, such as one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple cooperating files, such as files that store one or more modules, subprograms, or portions of code. A computer program may be arranged to be executed on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0388] The processes and logic flows described in this disclosure can be performed by one or more programmable computers executing one or more computer programs, which perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), or an apparatus can be implemented as special purpose logic circuitry.

[0389] 24 is a block diagram of computing devices 2400, 2450 that may be used to implement the systems and methods described herein, either as a client or as a server or servers. Computing device 2400 is intended to represent various forms of digital computers or processors, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Computing device 2450 is intended to represent various forms of mobile devices, such as personal digital assistants, mobile phones, smartphones, smartwatches, head-worn devices, and other similar computing devices. The components, their connections and relationships, and their functions illustrated herein are exemplary and are not intended to limit the embodiments described and / or claimed herein.

[0390] Computing device 2400 includes processor 2402, memory 2404, storage device 2406, high-speed interface 2408 connecting memory 2404 and high-speed expansion port 2410, and low-speed interface 2412 connecting low-speed bus 2414 and storage device 2406. Components 2402, 2404, 2406, 2408, 2410, and 2412 are interconnected using various buses and may be implemented on a common motherboard or in other suitable manners. Processor 2402 can process instructions for execution within computing device 2400, including instructions stored in memory 2404 or storage device 2406, for displaying graphical information for a GUI on an external input / output device, such as display 2416 coupled to high-speed interface 2408. In other embodiments, multiple processors and / or multiple buses may be used, along with multiple memories and types of memory, as appropriate. Additionally, multiple computing devices 2400 may be connected together, each providing a portion of the required operations (eg, as a bank of servers, a group of blade servers, or a multi-processor system).

[0391] The memory 2404 stores information within the computing device 2400. In one embodiment, the memory 2404 is a computer-readable medium. In one embodiment, the memory 2404 is a volatile memory unit. In another embodiment, the memory 2404 is a non-volatile memory unit.

[0392] The storage device 2406 can provide mass storage for the computing device 2400. In one embodiment, the storage device 2406 is a computer-readable medium. In various different embodiments, the storage device 2406 may be a floppy disk device, a hard disk device, an optical disk device, or an array of devices including a tape device, a flash memory or other similar solid-state memory device, or a device in a storage area network or other configuration. In one embodiment, a computer program product is tangibly embodied in an information carrier. The computer program product includes instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer-readable or machine-readable medium, such as memory 2404, the storage device 2406, or memory on the processor 2402.

[0393] High-speed controller 2408 manages bandwidth-intensive operations of computing device 2400, while low-speed controller 2412 manages relatively low-bandwidth operations. This load sharing is exemplary only. In one embodiment, high-speed controller 2408 is coupled to memory 2404, display 2416 (e.g., via a graphics processor or accelerator), and high-speed expansion port 2410, which can accept various expansion cards (not shown). In this embodiment, low-speed controller 2412 is coupled to storage device 2406 and low-speed expansion port 2414. The low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), can be coupled to one or more input / output devices, such as a keyboard, pointing device, scanner, etc., or to a network device, such as a switch or router, via, for example, a network adapter.

[0394] Computing device 2400, as shown, may be implemented in many different forms. For example, it may be implemented as a standard server 2420, or multiple times within a group of such servers. It may also be implemented as part of a rack server system 2424. It may also be implemented in a personal computer such as a laptop computer 2422. Alternatively, components from computing device 2400 may be combined with other components in a mobile device (not shown), such as device 2450. Each such device may include one or more of computing devices 2400, 2450, and an entire system may be made up of multiple computing devices 2400, 2450 communicating with each other.

[0395] Computing device 2450 includes components such as a processor 2452, memory 2464, input / output devices such as a display 2454, a communication interface 2466, and a transceiver 2468. Device 2450 may also include a storage device such as a microdrive or other device to provide additional storage. Components 2450, 2452, 2464, 2454, 2466, and 2468 are interconnected using various buses, and some of the components may be implemented on a common motherboard or in other suitable manner.

[0396] The processor 2452 can process instructions for execution within the computing device 2450, including instructions stored in the memory 2464. The processor may include separate analog and digital processors. The processor can provide coordination of other components of the device 2450, such as, for example, the user interface, applications executed by the device 2450, and control of wireless communications by the device 2450.

[0397] The processor 2452 can communicate with a user via a control interface 2458 and a display interface 2456 coupled to a display 2454. The display 2454 can be, for example, a TFT LCD display, an OLED display, or other suitable display technology. The display interface 2456 may include appropriate circuitry for driving the display 2454 to present graphics and other information to the user. The control interface 2458 can receive commands from a user and convert them for transmission to the processor 2452. Additionally, an external interface 2462 is provided in communication with the processor 2452 to enable short-range communication between the device 2450 and other devices. The external interface 2462 can provide, for example, wired communication (e.g., via a docking procedure) or wireless communication (e.g., via Bluetooth or other similar technology).

[0398] Memory 2464 stores information within computing device 2450. In one embodiment, memory 2464 is a computer-readable medium. In one embodiment, memory 2464 is one or more volatile memory units. In another embodiment, memory 2464 is one or more nonvolatile memory units. Further, expansion memory 2474 may be provided and connected to device 2450 via expansion interface 2472, which may include, for example, a SIMM card interface. Such expansion memory 2474 may provide extra storage space for device 2450 or store applications or other information for device 2450. Specifically, expansion memory 2474 may include instructions that perform or supplement the processes described above, and may also include secure information. Thus, for example, expansion memory 2474 may be provided as a security module for device 2450 and may be programmed with instructions that enable secure use of device 2450. Furthermore, secure applications may be provided via a SIMM card along with additional information, such as placing identifying information on the SIMM card in an unhackable manner.

[0399] The memory may include, for example, flash memory and / or MRAM memory, as described below. In one embodiment, a computer program product is tangibly embodied in an information carrier. The computer program product includes instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer-readable or machine-readable medium, such as memory 2464, expansion memory 2474, or memory on processor 2452.

[0400] Device 2450 can communicate wirelessly via communication interface 2466, which may optionally include digital signal processing circuitry. Communication interface 2466 can provide for communication in various modes or protocols, such as GSM voice calls, SMS, EMS, or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA4000, or GPRS. Such communication may occur, for example, via radio frequency transceiver 2468. Additionally, short-range communication may occur using Bluetooth, Wi-Fi, or other similar transceivers (not shown). Additionally, GPS receiver module 2470 can provide additional wireless data to device 2450, which may be used as appropriate by applications executing on device 2450.

[0401] Device 2450 may also perform voice communications using voice codec 2460, which may receive voice information from a user and convert it into usable digital information. Similarly, voice codec 2460 may also generate audible sounds for the user, such as through a speaker in the handset of device 2450. Such sounds may include sounds from a voice call, recorded sounds (such as voice messages, music files, etc.), or sounds generated by applications running on device 2450.

[0402] The computing device 2450, as shown, may be implemented in many different forms, such as a mobile phone, or as part of a smartphone 2482, personal digital assistant, or other similar mobile device.

[0403] Various implementations of the systems and techniques described herein can be realized in digital electronic circuitry, integrated circuits, specially designed application specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may be special purpose or general purpose, and may include implementations in one or more computer programs executable and / or interpretable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0404] These computer programs (also known as programs, software, software applications, or code) contain machine instructions for a programmable processor and may be implemented in a high-level procedural and / or object-oriented programming language, and / or assembly / machine language. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device (e.g., magnetic disk, optical disk, memory, programmable logic device (PLD), etc.) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0405] To provide for user interaction, the systems and techniques described herein can be implemented on a computer having a display device (e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) by which the user can provide input to the computer. Other types of devices can be used to provide for user interaction. For example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, tactile feedback), and input from the user can be received in any form, including acoustic input, voice input, and tactile input.

[0406] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or that includes middleware components (e.g., an application server), or that includes front-end components (e.g., a client computer having a graphical user interface or web browser through which a user can interact with an implementation of the systems and techniques described herein), or that includes any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form of medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), and the Internet.

[0407] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0408] A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, the various flow forms illustrated above may be used with steps reordered, or steps added or deleted. Also, while several applications of the payment system and method have been described, it will be recognized that many other applications are contemplated. Accordingly, other embodiments are within the scope of the following claims.

[0409] While the present disclosure includes many specific implementation details, these should not be construed as limitations on the scope of what is claimed, but rather as descriptions of features specific to particular embodiments. Certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in multiple embodiments, or in any suitable subcombination. Furthermore, although features are described above as acting in a particular combination, even if initially claimed as such, one or more features of a claimed combination may, in some cases, be removed from the combination, and the claimed combination may become a subcombination or a variation of a subcombination.

[0410] Similarly, although acts are depicted in a particular order in the figures, this should not be understood as requiring that such acts be performed in the particular order or sequence shown, or that all of the acts shown be performed, to achieve desired results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged in multiple software products.

[0411] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A computer implementation method for compressing classical binary data input, Obtaining classical binary data input, Performing classical operations on the classical binary data input in order to obtain metadata for the classical binary data input, wherein the metadata includes statistical operators, and the classical operations are based on the ensemble interpretation of quantum mechanics. To compress the metadata, a swap gate is applied to the metadata, wherein the swap gate swaps data as a one-way function, and the application of the swap gate is defined by the value of the statistical operator. The compressed metadata is supplied as compressed classical binary data input. Computer implementation methods including

2. The method according to claim 1, wherein the compressed classical binary data input has the same entropy as the classical binary data input.

3. The method according to claim 1, wherein the metadata includes classical binary data input divided into a plurality of data packets having a length equal to one or more predetermined sizes, each of which one or more predetermined sizes corresponds to a virtual Hilbert space.

4. The method according to claim 1, wherein the metadata includes values ​​representing data patterns that appear in classical binary data input.

5. The method according to claim 1, wherein the metadata includes a correlation value representing the virtual quantum entanglement measure of the classical binary data input.

6. The method according to claim 1, wherein the metadata includes a value representing the occurrence count of the data pattern in the classical binary data input.

7. The method according to claim 6, wherein the occurrence count of the data pattern in the classical binary data input includes a count representing a unique data pattern in a proper subset or a non-proper subset of the classical binary data input.

8. The method according to claim 6, wherein the value of the statistical operator includes a statistical probability generated from the occurrence count of the data pattern in the classical binary data input.

9. The method according to claim 6, wherein applying a swap gate to the metadata to compress the metadata includes swapping occurrences of data patterns having the maximum count with a bit sequence shorter than the data pattern having the maximum count, the bit sequence comprising i) the virtual entanglement measure of the data pattern having the minimum count and ii) the remaining bits of the data pattern having the minimum count, excluding the last bit of the data pattern having the minimum count.

10. The method according to claim 1, wherein the metadata includes a classical quantum multi-element (CQME) system, the CQME system includes the classical binary data input divided into data packets, each data packet including a correlation value representing a virtual quantum entanglement measure and a data pattern defining the type of the data packet.

11. The method according to claim 10, wherein the value of the statistical operator includes a probability that defines the statistical properties of the CQME.

12. The method according to claim 1, wherein the metadata includes an optimal arithmetic complex that characterizes the classical binary data input and stores the values ​​of the statistical operators, the optimal arithmetic complex is selected from a plurality of candidate arithmetic complexes, each of which corresponds to a virtual quantum state in its respective virtual Hilbert space.

13. The method according to claim 12, wherein the optimal arithmetic complex i) has the same length as the classical binary data input, ii) has the same entropy as the classical binary data input, and iii) includes at least one singularity.

14. The method according to claim 12, wherein the plurality of candidate arithmetic complexes form a superposition surface of the virtual quantum states.

15. The method according to claim 12, wherein the optimal arithmetic complex is selected from the plurality of candidate arithmetic complexes through a virtual time measurement of the virtual quantum state.

16. Outputting the compressed classical binary data input, or The compressed classical binary data input is iterated through until the target data compression ratio is achieved, wherein each iteration is performed as follows: To generate metadata for the iteration, classical operations are performed on the classical binary data input for the iteration, To compress the metadata for the iterations, a swap gate is applied to the metadata for the iterations, To supply the compressed metadata for the iteration as input for subsequent iterations. The iterative process includes the above-mentioned process The method according to claim 1, further comprising:

17. A system comprising one or more computers and one or more storage devices that store instructions operable to cause the one or more computers to perform operations according to the method of claim 1 when executed by the one or more computers.

18. A computer-readable storage medium that is executable by a processing device and stores instructions that cause the processing device to perform an operation according to the method described in claim 1.

19. Obtaining classical binary data input, Performing classical operations on the classical binary data input in order to obtain metadata for the classical binary data input, wherein the metadata includes statistical operators that produce an output having the characteristics of the classical binary data input, and the classical operations are performed based on the ensemble interpretation of quantum mechanics. To supply the metadata for use in subsequent calculations Computer implementation methods including

20. A system comprising one or more computers and one or more storage devices that store instructions operable to cause the one or more computers to perform operations according to the method of claim 19 when executed by the one or more computers.

21. A computer implementation method for decompressing classical compressed binary data input, Obtaining compressed classical binary data input, The process involves generating candidate metadata for the compressed classical binary data input, wherein the metadata includes values ​​for statistical operators for each portion of the compressed binary data input, and the statistical operators are generated based on the ensemble interpretation of quantum mechanics. In order to identify valid metadata for the classical compressed binary data input, a kernel filter is applied to the candidate metadata based on the value of the statistical operator, Applying a swap gate to the valid metadata in order to decompress the valid metadata, wherein the swap gate swaps data as a one-way function, and the application of the swap gate is defined by the value of the statistical operator to the valid metadata. The decompressed valid metadata is supplied as the decompressed compressed classical binary data input. Computer implementation methods including

22. The method according to claim 21, wherein the decompressed compressed classical binary data input has the same entropy as the classical compressed binary data input.

23. The method according to claim 21, wherein supplying the decompressed valid metadata as the decompressed compressed classical binary data input comprises performing a logical inverse calculation.

24. The method according to claim 21, wherein applying the kernel filter to the candidate metadata includes identifying metadata corresponding to a portion of a compressed binary data input that i) does not contain a unique data pattern, ii) satisfies the conditions for virtual quantum entanglement, and iii) has the maximum bit length.

25. Applying a swap gate to the valid metadata in order to decompress the valid metadata is In a portion of the compressed binary data input, the second most unique data pattern is identified, In a portion of the compressed binary data input, the most unique data pattern is identified, The swap involves swapping the occurrence of a data pattern representing a virtual quantum entanglement value that appears before the second most unique data pattern with a bit sequence longer than the virtual quantum entanglement value, wherein the bit sequence longer than the virtual quantum entanglement value corresponds to the data pattern with the most repetitions. The swap involves swapping the occurrence of the second most unique data pattern and the data pattern that appears before the most unique data pattern with a bit string longer than the data pattern with the most repetition count, wherein the bit string longer than the data pattern with the most repetition count corresponds to the concatenation of the virtual quantum entanglement value and the inverse value of the pattern structure value. The method according to claim 21, including the method described in claim 21.

26. The method according to claim 21, wherein the metadata includes classical binary data input divided into a plurality of data packets having a length equal to one or more predetermined sizes, each of which one or more predetermined sizes corresponds to a virtual Hilbert space.

27. The method according to claim 21, wherein the metadata includes values ​​representing data patterns that appear in the classical binary data input.

28. The method according to claim 21, wherein the metadata includes a correlation value representing the virtual quantum entanglement measure of the classical binary data input.

29. The method according to claim 21, wherein the metadata includes a value representing the occurrence count of the data pattern in the classical binary data input.

30. The method according to claim 29, wherein the occurrence count of the data pattern in the classical binary data input includes a count representing a unique data pattern in a proper subset or a non-proper subset of the classical binary data input.

31. The method according to claim 29, wherein the value of the statistical operator includes a statistical probability and an identifier generated from the occurrence count of the data pattern in the classical binary data input.

32. The method according to claim 21, wherein the metadata comprises a classical quantum many-element (CQME) system, the CQME system comprises the classical binary data input divided into data packets, each data packet comprising a correlation value representing a virtual quantum entanglement measure and a data pattern defining the type of the data packet.

33. The method according to claim 32, wherein the value of the statistical operator includes a probability that defines the statistical properties of the CQME.

34. The method according to claim 21, wherein the metadata includes an optimal arithmetic complex that characterizes the classical binary data input and stores the values ​​of the statistical operators, the optimal arithmetic complex is selected from a plurality of candidate arithmetic complexes, each of which corresponds to a virtual quantum state in its respective virtual Hilbert space.

35. The method according to claim 34, wherein the optimal arithmetic complex i) has the same length as the classical binary data input, ii) has the same entropy as the classical binary data input, and iii) includes at least one singularity.

36. The method according to claim 34, wherein the plurality of candidate arithmetic complexes form a superposition surface of the virtual quantum states.

37. The method according to claim 34, wherein the optimal arithmetic complex is selected from the plurality of candidate arithmetic complexes through a virtual time measurement of the virtual quantum state.

38. Outputting the decompressed classical compressed binary data input, or The compressed classical binary data input is iterated through until the target data decompression rate is achieved, wherein each iteration of the iteration is performed as follows: To generate candidate metadata for the classical compressed binary data input that is input for the aforementioned iteration, In order to identify metadata valid for the iteration, a kernel filter is applied to the candidate metadata for the iteration, To decompress the valid metadata for the aforementioned iteration, a swap gate is applied to the valid metadata, To supply the decompressed valid metadata for the iteration as input for subsequent iterations. Iterative processing, including The method according to claim 21, further comprising:

39. A system comprising one or more computers and one or more storage devices that store instructions operable to cause the one or more computers to perform operations according to the method of claim 21 when executed by the one or more computers.

40. A computer-readable storage medium that is executable by a processing device and stores instructions that cause the processing device to perform an operation according to the method described in claim 21.

41. A computer implementation method for compressing classical binary data input, Receiving metadata of the aforementioned classical binary data input, wherein the metadata includes statistical operators and the classical operations are based on the ensemble interpretation of quantum mechanics, To compress the metadata, a swap gate is applied to the metadata, wherein the swap gate swaps data as a one-way function, and the application of the swap gate is defined by the value of the statistical operator. The compressed metadata is supplied as compressed classical binary data input. Computer implementation methods including

42. A system comprising one or more computers and one or more storage devices that store instructions operable to cause the one or more computers to perform operations according to the method of claim 41 when executed by the one or more computers.

43. A computer-readable storage medium that is executable by a processing device and stores instructions that cause the processing device to perform an operation according to the method described in claim 41.

44. A first chipset comprising a first data port for receiving input data and a second data port for supplying a final arithmetic complex, The first chipset is configured to perform operations including converting the input data into a final arithmetic complex, the final arithmetic complex comprising a first intermediate arithmetic element (IAE) dataset, a second IAE dataset, and a third IAE dataset, the final arithmetic complex being a virtual quantum representation of the input data. The first IAE dataset includes a first component value that defines the virtual quantum entanglement of the input data, and a second component value that defines the structure of the data pattern of the input data. The second IAE dataset includes a statistical operator that defines a count of data patterns associated with the data patterns of the first IAE dataset of the input data, The third IAE dataset includes an ancilla dataset that defines the statistical probabilities associated with the input data. system.

45. The system according to claim 44, further comprising a second chipset, the second chipset being configured to receive a final arithmetic complex as input to the second chipset, and the second chipset being configured to compress at least a portion of the final arithmetic complex into a compressed dataset.

46. The system according to claim 45, further comprising a third chipset, the third chipset being arranged to receive the compressed dataset as input to the third chipset, and the third chipset being configured to decompress the compressed dataset as input data.

47. The system according to claim 45, wherein the first chipset and the second chipset are integrated on a single substrate.

48. The system according to claim 44, wherein converting the input data into the final arithmetic complex includes generating a plurality of candidate Hilbert space (HS) datasets from the input data.

49. The first chipset is configured to create an instance of the configuration table, and the first chipset, The first memory and Parallel address data bus and Multiple HS storage modules and It further includes, The generation of the aforementioned multiple candidate HS datasets is The input data is obtained from the first memory via a parallel address bus, Obtaining multiple size parameters from the aforementioned configuration table, The process involves transmitting multiple copies of the input data in parallel to the multiple HS storage modules via a parallel address bus, wherein each copy of the input data is transmitted with a different bit transmission size according to the respective size parameters from the multiple size parameters. The system according to claim 48.

50. Including a second memory, generating the plurality of candidate HS datasets is, The process involves generating multiple intermediate arithmetic complexes associated with different sizes, Each intermediate arithmetic processor is: A corresponding data pattern array in which the input data is distributed based on the size associated with the intermediate arithmetic complex, The corresponding statistical operator matrix, The corresponding ancila matrix contains the statistical probabilities of the corresponding data pattern array and Including generating, The plurality of intermediate arithmetic complexes are stored in the second memory as the plurality of candidate HS datasets, including, The system according to claim 48.

51. For each intermediate arithmetic complex, the input data is divided into one or more data patterns, each of the one or more data patterns has a size associated with the intermediate arithmetic complex, and each of the one or more data patterns is stored across one or more elements of the corresponding data pattern array. For each intermediate arithmetic complex, the corresponding statistical operator matrix includes, for each different data pattern in the corresponding data pattern array, the count of the data pattern and the index value corresponding to the data pattern. The system according to claim 50.

52. The system according to claim 51, wherein for each of the one or more data patterns, the leading bit of the data pattern is virtual quantum entanglement, and the remaining one or more bits of the data pattern are a pattern structure.

53. The system according to claim 52, wherein for each intermediate arithmetic complex, the statistical probability of the corresponding ancilla matrix includes the data pattern with the highest frequency of occurrence in the corresponding data pattern array and the data pattern with the lowest frequency of occurrence in the data pattern array.

54. The generation of the plurality of intermediate arithmetic complexes is performed for each copy of the plurality of copies of the input data that are transmitted from the parallel address bus to the plurality of HS storage modules, Detecting pre-circuit breaker events, To detect the final circuit breaker event, Upon detecting the final circuit breaker event, the completion of the intermediate arithmetic complex corresponding to the copy of the input data is confirmed. The system according to claim 50, including the system described in claim 50.

55. Converting the aforementioned input data into the final arithmetic complex is, The above-mentioned multiple intermediate arithmetic complexes are combined to form multiple candidate final arithmetic complexes, In order to select the aforementioned final arithmetic complex, the plurality of candidate final arithmetic complexes are filtered. The system according to claim 50, including the system described in claim 50.

56. The system according to claim 55, wherein filtering the plurality of candidate final arithmetic complexes in order to select the final arithmetic complexes includes applying fuzzy logic rules to the plurality of candidate final arithmetic complexes.

57. The system according to claim 56, further comprising a second chipset, the second chipset being configured to receive a final arithmetic complex as input to the second chipset, and the second chipset being configured to compress at least a portion of the final arithmetic complex into a compressed dataset.

58. The system according to claim 57, wherein the second chipset is configured to compress at least a portion of the final arithmetic complex into a compressed dataset based on statistical probabilities associated with the first IAE dataset.

59. The system according to claim 58, wherein the second chipset includes a plurality of swap gates configured to compress the final arithmetic complex into a compressed dataset.

60. The system according to claim 59, wherein the second chipset includes a first error correction module configured to enable and disable data processing by the plurality of swap gates.

61. The first error correction module described above is: Identify the least frequently occurring data pattern in the aforementioned final arithmetic complex, When the least frequent data pattern is identified in the final arithmetic complex, the processing of the data is disabled. The system according to claim 60, configured as described above.

62. The second chipset is, The moment when data is present at the output port of the second chipset is determined, When it is determined that the data is present at the output port of the second chipset, the plurality of swap gates are instructed to read the new data. The system according to claim 61, comprising a second error correction module configured as such.

63. The plurality of swap gates include a plurality of submodules, and the plurality of submodules are Identify the point in time when the least frequently occurring data pattern in the aforementioned final arithmetic complex exists. The least frequently occurring data pattern is written to the final arithmetic complex. The system according to claim 59, comprising a first swap module configured as such.

64. The aforementioned multiple submodules are, Identify the point in time where the most frequently occurring data pattern of the final arithmetic complex exists. Performing a first swap operation on the final arithmetic complex to obtain at least one first swapped parameter, wherein the first swap operation includes performing a first swap operation that replaces the last bit of the least frequent data pattern. The system according to claim 63, comprising a second swap module configured as such.

65. The plurality of swap gates are configured to perform a second swap operation on the least frequently occurring data pattern in the final arithmetic complex in order to obtain at least one second swapped parameter, and the plurality of submodules are configured Identify the point in time when the least frequently occurring pattern exists among the data patterns of the final arithmetic complex. The at least one second swapped parameter is stored in memory. The system according to claim 64, comprising a third swap module configured as such.

66. The system according to claim 65, wherein the plurality of submodules include a fourth swap module configured to pass else-case data patterns from the final arithmetic complex to the output port of the second chipset, the else-case data patterns include data patterns not identified by the first submodule, the second submodule, and the third submodule.

67. The system according to claim 57, wherein the second chipset is configured to return the compressed dataset to the first chipset.

68. The system according to claim 57, further comprising a third chipset configured to decompress the compressed dataset and obtain the decompressed dataset.

69. The system according to claim 68, wherein the third chipset includes a plurality of inverse unidirectional swap gates configured to decompress the compressed dataset.

70. The third chipset described above is The compressed dataset is received as an input data stream, To generate candidate metadata for the compressed dataset, In order to identify valid metadata, multiple kernel filters are applied to the candidate metadata. The system according to claim 68, configured to decompress the compressed dataset by performing an operation including the following.

71. Applying the multiple kernel filters to the candidate metadata means Identifying a portion of a compressed dataset that does not contain a unique data pattern, satisfies the conditions for virtual quantum entanglement, and has a specified bit length. The system according to claim 70, including the system described in claim 70.

72. The operation of the third chipset is as follows: To obtain the decompressed dataset, multiple inverse one-way swap gates are applied to the valid metadata. The system according to claim 70, further comprising:

73. Applying the aforementioned multiple inverse one-way swap gates means Identifying the occurrence of the second most unique data pattern within the compressed dataset as the first data event, Swapping each occurrence of the data pattern corresponding to the virtual quantum entanglement value in the compressed dataset prior to the first data event with a first predefined bit sequence, Swapping each occurrence of the data pattern associated with the most frequent occurrences in the compressed dataset prior to the first data event with a second predefined bit sequence. The system according to claim 72, including the following:

74. A chipset configured to perform operations including converting a classical dataset into a classical quantum multi-element (CQME) dataset and an ancilla matrix containing the statistical properties of the CQME dataset.

75. The chipset according to claim 74, wherein the calculation includes compressing the CQME dataset.

76. The chipset according to claim 75, wherein compressing the CQME dataset includes applying at least one one-way swap gate to the CQME dataset.

77. The chipset according to claim 75, wherein the calculation includes decompressing the compressed CQME dataset.

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