Solar cell manufacturing method, solar cell and battery module

Abstract

This application discloses a method for manufacturing a solar cell, a solar cell, and a battery module. The method for manufacturing a solar cell includes the steps of: forming an emitter layer having an opposite conductivity type to that of the semiconductor substrate on one side of a semiconductor substrate; forming a passivation layer on the emitter layer; forming an insulating layer on the passivation layer; forming main grids on the insulating layer, the main grids extending in a first direction and spaced apart in a second direction different from the first direction; and forming finger grids on the insulating layer, the main grids extending in the second direction and spaced apart in the first direction. The main grids extend toward the emitter layer, and the extension depth of the main grids is 90% or less of the thickness of the passivation layer and greater than 20% of the thickness of the insulating layer.

Description

[Technical Field]

[0001] The present application relates to the technical field of solar cells, and in particular to a method for manufacturing a solar cell, a solar cell, and a battery module.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of Chinese Patent Application No. 202311296304.2, filed on October 8, 2023, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Solar cells are semiconductor devices that can convert light energy into electrical energy. Specifically, when light shines on a solar cell, the semiconductor substrate contained in the solar cell absorbs photons and generates electron-hole pairs. The electron-hole pairs are separated by the built-in electric field of the PN junction, and are extracted through the emitter and backfield of the solar cell, respectively, and finally collected by electrode structures on the semiconductor substrate.

[0004] The electrode structure generally includes a main grid and finger grids formed by integral printing, and since corrosion occurs during the sintering process, both the main grid and the finger grids may come into contact with the silicon substrate.

[0005] However, contact between the main grid and the silicon substrate will seriously damage the passivation layer, which will cause a decrease in open circuit voltage (Uoc) and further affect the photoelectric conversion efficiency. Summary of the Invention

[0006] The present application aims to provide a method for manufacturing a solar cell, a solar cell, and a battery module that reduce or eliminate damage to the passivation layer, increase the open-circuit voltage, and reduce the impact on photoelectric conversion efficiency.

[0007] To achieve the above object, the present application provides, in a first aspect, a method for manufacturing a solar cell, the method comprising the following steps:

[0008] First, a semiconductor substrate is provided. Next, an emitter layer is formed on one side of the semiconductor substrate. The semiconductor substrate and the emitter layer have opposite conductivity types. Next, a passivation layer is formed on the emitter layer. Next, an insulating layer is formed on the passivation layer. Next, main grids are formed on the insulating layer. The main grids extend in a first direction and are spaced apart in a second direction different from the first direction. Next, finger grids are formed on the insulating layer. The finger grids extend in the second direction and are spaced apart in the first direction. Each main grid intersects with multiple finger grids, and the finger grids penetrate the passivation layer and the insulating layer to connect to the emitter layer. The main grids extend toward the emitter layer, and the extending depth of the main grids is 90% or less of the thickness of the passivation layer and greater than 20% of the thickness of the insulating layer, and the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer all coincide with the direction toward the semiconductor substrate.

[0009] In the solar cell manufacturing method provided by the present application, the main grid is formed on the insulating layer and extends toward the emitter layer, and the extending depth of the main grid is not more than 90% of the thickness of the passivation layer and is greater than 20% of the thickness of the insulating layer. Therefore, in this case, a part of the extending main grid (i.e., a part of the main grid) may be located only in the insulating layer, or may be located in both the insulating layer and the passivation layer, but the extending depth does not exceed 90% of the thickness of the passivation layer.

[0010] When the extended portion of the main grid is located only within the insulating layer, the passivation layer is not destroyed by the main grid, ensuring the passivation effect of the passivation layer, which can increase the open-circuit voltage and reduce or eliminate the impact on photoelectric conversion efficiency.

[0011] When the extended portion of the main grid is located within both the insulating layer and the passivation layer but does not exceed 90% of the thickness of the passivation layer, compared to the prior art where the main grid penetrates the passivation layer to connect to the silicon substrate, this reduces the degree of damage to the passivation layer by the main grid and ensures the passivation effect of the passivation layer. This increases the open-circuit voltage and reduces the impact on photovoltaic conversion efficiency. Furthermore, since the main grid is connected to both the insulating layer and the passivation layer, this ensures the mechanical performance of the main grid and improves its tensile resistance. This reduces or eliminates the possibility of the main grid peeling off from the solar cell, ensuring the quality and performance of the solar cell.

[0012] In one embodiment, the ratio of the extension depth of the main grid in the passivation layer to the thickness of the passivation layer is 20% or more.

[0013] When adopting the above technical solution, the main grid is connected to both the insulating layer and the passivation layer, which ensures the mechanical performance of the main grid, improves the tensile resistance characteristics of the main grid, reduces or eliminates the probability of the main grid peeling off from the solar cell, and further ensures the quality and performance of the solar cell.

[0014] In one embodiment, the main grid extends to zero depth in the passivation layer.

[0015] The above technical solution can avoid the damage to the passivation layer caused by the main grid and ensure the passivation effect of the passivation layer, thereby increasing the open circuit voltage and avoiding the impact on photoelectric conversion efficiency.

[0016] In one embodiment, when the thickness of the passivation layer is 5 nm to 20 nm, the extension depth of the main grid in the passivation layer is 1 nm to 18 nm.

[0017] The above technical solution, with a depth of 1 nm or more, ensures that the main grid is connected to both the insulating layer and the passivation layer. This ensures the mechanical performance of the main grid, improves its tensile resistance, reduces or eliminates the possibility of the main grid peeling off from the solar cell, and ensures the quality and performance of the solar cell. Furthermore, the depth of 18 nm or less reduces the degree of damage to the passivation layer caused by the main grid, ensures the passivation effect of the passivation layer, increases the open-circuit voltage, and reduces the impact on photovoltaic conversion efficiency.

[0018] In one embodiment, the insulating layer has a thickness of 40 nm or more and 100 nm or less.

[0019] In one embodiment, the main grid includes main-grid connection lines and pads, the pads being spaced apart from the main-grid connection lines in a first direction, the pads having widths greater than the widths of the main-grid connection lines, and the width directions of the pads and the main-grid connection lines both coinciding with a second direction.

[0020] When adopting the above technical solution, even if the number of main grid connecting lines is the same, the width of the main grid connecting lines is equal to the width of the pads, thereby ensuring that the current collection capacity of the main grid connecting lines meets actual requirements, while reducing the amount of raw materials used in manufacturing the main grid connecting lines and saving raw material costs. This also reduces the shading of the semiconductor substrate caused by the main grid connecting lines, increasing the light-receiving area of ​​the semiconductor substrate and improving the photoelectric conversion efficiency of the solar cell. Furthermore, during subsequent manufacturing of the battery module, ribbons need to be connected to the pads. In this case, the width of the main grid connecting lines is equal to the width of the pads, making it easier to connect the ribbons to the pads, reducing manufacturing difficulties and improving manufacturing efficiency.

[0021] In one embodiment, the number of the main grids is 8 to 25, and / or the width of the main grid connection lines is 35 to 60 μm, and the width of the pads is 0.6 to 1.3 mm.

[0022] When adopting the above technical solution, the area of ​​the semiconductor substrate shielded by the main grids can be controlled by controlling the number of main grids, the width of the main grid connecting lines, and the width of the pads, thereby increasing the amount of light incident on the semiconductor substrate, increasing the light-receiving area of ​​the semiconductor substrate, and improving the cell efficiency of the solar cell.

[0023] In one embodiment, the number of the finger grids is 100 or more and 200 or less, the width of the finger grid is 20 μm or more and 45 μm or less, and the width direction of the finger grid coincides with the first direction.

[0024] When the above technical solution is adopted, the current collection ability of the finger grid can be improved, and the cell efficiency of the solar cell can be improved.

[0025] In one embodiment, the step of forming the main grid on the insulating layer includes the following steps: first, printing a main grid material on the insulating layer to form an initial main grid; then processing the initial main grid to form a main grid; the ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.1, and the width direction of the main grid and the width direction of the initial main grid both coincide with the second direction.

[0026] By adopting the above technical solution, by controlling the extension size of the final main grid in the second direction, it is possible to reduce the adverse effects on the insulating layer and / or passivation layer, thereby reducing the adverse effects on the anti-reflection effect and / or passivation effect of the solar cell, as well as to reduce the shading of the semiconductor substrate by the main grid, increase the light-receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0027] In one embodiment, the step of forming a finger grid on the insulating layer includes the following steps: first, printing a finger grid material on the insulating layer to form an initial finger grid; then processing the initial finger grid to form a finger grid; a ratio of the width of the finger grid to the width of the initial finger grid is greater than 1 and less than or equal to 1.2, and the width direction of the finger grid and the width direction of the initial finger grid both coincide with the first direction.

[0028] When adopting the above technical solution, by controlling the extension size of the finally formed finger grid in the second direction, it is possible to reduce the adverse effects on the insulating layer and / or passivation layer, and reduce the adverse effects on the anti-reflection effect and / or passivation effect of the solar cell, as well as to reduce the shading of the semiconductor substrate by the finger grid, increase the light-receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0029] In one embodiment, the metal solids content of the main grid material is less than the metal solids content of the finger grid material.

[0030] When adopting the above technical solution, the extension depth of the main grid into the emitter layer is smaller than the extension depth of the finger grid into the emitter layer, which reduces the degree of damage to the passivation layer by the main grid and ensures the passivation effect of the passivation layer. Furthermore, even if the metal solid content of the finger grid material is the same, the cost of the main grid material can be reduced, compared to the prior art where the metal solid content of the main grid material and the finger grid material is the same, and the manufacturing cost of the solar cell can be reduced. In addition, the extension depth of the finger grid into the emitter layer in this application can be ensured to be identical or approximately identical to the extension depth of the finger grid into the emitter layer in the prior art, ensuring the performance of the finger grid remains unchanged.

[0031] In a second aspect, the present application further provides a solar cell. The solar cell includes a semiconductor substrate, an emitter layer, a passivation layer, an insulating layer, a main grid, and a finger grid. The emitter layer is located on one side of the semiconductor substrate, and the semiconductor substrate and the emitter layer have opposite conductivity types. The passivation layer is located on the emitter layer, and the insulating layer is located on the passivation layer. The main grid is located on the insulating layer, extends in a first direction, and is spaced apart in a second direction different from the first direction. The finger grids are located on the insulating layer, extends in the second direction, and is spaced apart in the first direction. Each main grid intersects with a plurality of finger grids, and the finger grids are connected to the emitter layer through the passivation layer and the insulating layer. The main grid extends toward the emitter layer, and the extending depth of the main grid is 90% or less of the thickness of the passivation layer and is greater than 20% of the thickness of the insulating layer, and the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer all coincide with the direction toward the semiconductor substrate.

[0032] In the solar cell provided by the present application, the main grid is formed on the insulating layer and extends toward the emitter layer, and the extending depth of the main grid is not more than 90% of the thickness of the passivation layer and is greater than 20% of the thickness of the insulating layer. Therefore, in this case, a part of the extending main grid (i.e., a part of the main grid) may be located only in the insulating layer, or may be located in both the insulating layer and the passivation layer, but the extending depth does not exceed 90% of the thickness of the passivation layer.

[0033] When the extended portion of the main grid is located only within the insulating layer, the passivation layer is not destroyed by the main grid, ensuring the passivation effect of the passivation layer, which can increase the open-circuit voltage and reduce or eliminate the impact on photoelectric conversion efficiency.

[0034] When the extended portion of the main grid is located within both the insulating layer and the passivation layer but does not exceed 90% of the thickness of the passivation layer, compared to the prior art where the main grid penetrates the passivation layer to connect to the silicon substrate, this reduces the degree of damage to the passivation layer by the main grid and ensures the passivation effect of the passivation layer. This increases the open-circuit voltage and reduces the impact on photovoltaic conversion efficiency. Furthermore, since the main grid is connected to both the insulating layer and the passivation layer, this ensures the mechanical performance of the main grid and improves its tensile resistance. This reduces or eliminates the possibility of the main grid peeling off from the solar cell, ensuring the quality and performance of the solar cell.

[0035] In one embodiment, the emitter layer is located on the non-light-receiving surface of the solar cell.

[0036] In one embodiment, the emitter layer is formed by doping the original structure of the semiconductor substrate or by a deposition process on the surface of the semiconductor substrate.

[0037] In one embodiment, the ratio of the extension depth of the main grid in the passivation layer to the thickness of the passivation layer is 20% or more.

[0038] When adopting the above technical solution, the main grid is connected to both the insulating layer and the passivation layer, which ensures the mechanical performance of the main grid, improves the tensile resistance characteristics of the main grid, reduces or eliminates the probability of the main grid peeling off from the solar cell, and further ensures the quality and performance of the solar cell.

[0039] In one embodiment, the main grid extends to zero depth in the passivation layer.

[0040] The above technical solution can avoid the damage to the passivation layer caused by the main grid and ensure the passivation effect of the passivation layer, thereby increasing the open circuit voltage and avoiding the impact on photoelectric conversion efficiency.

[0041] In one embodiment, when the thickness of the passivation layer is 5 nm to 20 nm, the extension depth of the main grid in the passivation layer is 1 nm to 18 nm.

[0042] The above technical solution, with a depth of 1 nm or more, ensures that the main grid is connected to both the insulating layer and the passivation layer. This ensures the mechanical performance of the main grid, improves its tensile resistance, reduces or eliminates the possibility of the main grid peeling off from the solar cell, and ensures the quality and performance of the solar cell. Furthermore, the depth of 18 nm or less reduces the degree of damage to the passivation layer caused by the main grid, ensures the passivation effect of the passivation layer, increases the open-circuit voltage, and reduces the impact on photovoltaic conversion efficiency.

[0043] In one embodiment, the thickness of the insulating layer is 40 nm or more and 100 nm or less.

[0044] In one embodiment, the main grid includes main-grid connection lines and pads, the pads being spaced apart from the main-grid connection lines in a first direction, the pads having widths greater than the widths of the main-grid connection lines, and the width directions of the pads and the main-grid connection lines both coinciding with a second direction.

[0045] When adopting the above technical solution, even if the number of main grid connecting lines is the same, the width of the main grid connecting lines is equal to the width of the pads, thereby ensuring that the current collection capacity of the main grid connecting lines meets actual requirements, while reducing the amount of raw materials used in manufacturing the main grid connecting lines and saving raw material costs. This also reduces the shading of the semiconductor substrate caused by the main grid connecting lines, increasing the light-receiving area of ​​the semiconductor substrate and improving the photoelectric conversion efficiency of the solar cell. Furthermore, during subsequent manufacturing of the battery module, ribbons need to be connected to the pads. In this case, the width of the main grid connecting lines is equal to the width of the pads, making it easier to connect the ribbons to the pads, reducing manufacturing difficulties and improving manufacturing efficiency.

[0046] In one embodiment, the number of the main grids is 8 to 25, and / or the width of the main grid connection lines is 35 to 60 μm, and the width of the pads is 0.6 to 1.3 mm.

[0047] When adopting the above technical solution, the area of ​​the semiconductor substrate shielded by the main grids can be controlled by controlling the number of main grids, the width of the main grid connecting lines, and the width of the pads, thereby increasing the amount of light incident on the semiconductor substrate, increasing the light-receiving area of ​​the semiconductor substrate, and improving the cell efficiency of the solar cell.

[0048] In one embodiment, the number of the finger grids is 100 or more and 200 or less, the width of the finger grid is 20 μm or more and 45 μm or less, and the width direction of the finger grid coincides with the first direction.

[0049] When the above technical solution is adopted, the current collection ability of the finger grid can be improved, and the cell efficiency of the solar cell can be improved.

[0050] In a third aspect, the present application further provides a battery module, which includes a plurality of ribbons and a plurality of solar cells according to the above technical solution arranged at intervals, and the ribbons are correspondingly connected to a main grid.

[0051] Compared with the prior art, the beneficial effects of the battery module provided by the present application are the same as those of the solar cell described in the above technical solutions, so they will not be repeated here.

[0052] In one embodiment, when the main grid includes main-grid connecting lines and pads, the ribbon is attached to the pad in the first direction to cover the main-grid connecting lines, the maximum width of the ribbon is equal to or less than the width of the pad, and the width direction of the ribbon and the width direction of the pad both coincide with the second direction.

[0053] When the above technical solution is adopted, the shielding of the semiconductor substrate by the ribbons can be reduced, the light-receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0054] In one embodiment, the width of the ribbon is equal to or less than the width of the main grid connecting lines, and the width direction of the ribbon and the width direction of the main grid connecting lines both coincide with the second direction.

[0055] When the above technical solution is adopted, the shielding of the semiconductor substrate by the ribbons can be reduced, the light-receiving area of ​​the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0056] In one embodiment, the ratio of the width of the ribbon to the width of the main grid connecting line is 50% or more and 90% or less.

[0057] When adopting the above technical solution, the ribbon includes a metal core layer and a solder layer located on the outer surface of the core layer. Therefore, during the actual process of welding the ribbon and the pad, the solder layer melts due to heat and has a certain fluidity. Since the above ratio is between 50% and 90%, the interface between the ribbon and the main grid connecting wire can be provided with sufficient fluidity space for the flowing solder to distribute. In this case, the solder is prevented from flowing onto the semiconductor substrate, preventing contamination and obstruction of the semiconductor substrate by the solder, and further ensuring the quality and performance of the solar cell. [Brief explanation of the drawings]

[0058] The drawings described herein are intended to provide a further understanding of the present application and constitute a part of this application. The schematic examples of the present application and the description thereof are for the purpose of illustrating the present application and are not to be construed as undue limitations on the present application. [Figure 1] FIG. 1 is a structural schematic diagram of a solar cell according to the prior art. [Figure 2] 1 is a structural schematic diagram of a solar cell according to an embodiment of the present application. [Figure 3] 2 is a second schematic diagram of the structure of a solar cell in an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0059] In order to make the technical problems, technical solutions and beneficial effects of the present application clearer and easier to understand, the present application will be described in more detail below with reference to the drawings and examples. Note that the specific examples described herein are merely for the purpose of interpreting the present application, and are not intended to limit the present application.

[0060] It should be noted that when an element is described as being "fixed" or "mounted" on another element, it may be directly located on the other element or indirectly located on the other element. When an element is described as being "connected" to another element, it may be directly connected to the other element or indirectly connected to the other element.

[0061] It should be noted that the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or suggesting the relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature qualified as "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise clearly and specifically limited, "plurality" means two or more. Unless otherwise clearly and specifically limited, "several" means one or more.

[0062] In describing this application, it should be understood that the directions and positional relationships indicated by terms such as "upper," "lower," "front," "rear," "left," and "right" are based on the directions and positional relationships shown in the drawings, and are intended merely to facilitate and simplify the description of this application, and are not intended to indicate or suggest that the devices or elements referred to necessarily have a particular orientation or are constructed and operated in a particular orientation, and should not be understood as limiting this application.

[0063] In the description of this application, it should be explained that unless otherwise clearly specified or limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, or an integral connection. They may also refer to a mechanical connection or an electrical connection. They may also refer to a direct connection, an indirect connection via an intermediate medium, or an internal communication between two elements or an interactive relationship between two elements. Those skilled in the art can understand the specific meanings of the above terms in this application according to specific circumstances.

[0064] Screen printing is a key process control in the manufacturing and production of solar cells and is primarily used to form solar cell electrodes. Specifically, printing is performed using the basic principle that the mesh in the patterned section of the screen allows the paste to pass through, while the mesh in the non-patterned section prevents the paste from passing through. During printing, paste is poured into one end of the screen, and a squeegee is moved to the other end of the screen while applying a certain amount of pressure to the paste area on the screen. The moving squeegee pushes the paste through the mesh in the patterned section onto the substrate, forming the required pattern. Typical solar cell screen printing uses the mainstream SP (Single Print) method, i.e., integrated main grid and finger grid printing. The screen is designed to accommodate both the main grid and finger grid, and a single print creates a lap joint between the main grid lines and finger grid lines from the paste. After printing, the paste comes into contact with an insulating layer (e.g., SiNx), and the phosphate glass component contained in the paste is corrosive, corroding the SiNx and the underlying passivation layer (e.g., AlOx) at the contact surface, causing the Ag in the paste to form a silver-silicon alloy with Si, which in turn forms a good ohmic contact.

[0065] Specifically, in the conventional screen-printing process for electrode fabrication and formation, a battery with a single printing of an integrated paste is placed in a sintering furnace. The first sintering stage is carried out at temperatures between 200°C and 400°C, during which organic binders such as ethyl cellulose and polyvinyl alcohol are burned off. The second stage, carried out at temperatures between 600°C and 900°C, is a critical step in forming the electrode. During this stage, the phosphate glass frit transforms from a solid state to a molten state at high temperatures, corroding the insulating layer (e.g., SiNx) and opening windows. This advances, entraining the metallic conductive silver particles and melting and corroding the underlying dielectric film (e.g., AlOx). The silver particles melt or undergo other reactions during firing, bringing them into contact with the underlying film layer. During this process, the main grid formed by the integrated SP printing also corrodes the underlying layers, penetrating the insulating layer and passivation layer (the passivation layer is typically 5 nm to 20 nm thick), ultimately reaching the same depth as the finger grid. That is, during the sintering process, as corrosion occurs, both the main grid and the finger grid come into contact with the silicon substrate. However, the main grid severely damages the passivation layer when it comes into contact with the silicon substrate. This results in a decrease in the open-circuit voltage (Uoc) and further impacts the photoelectric conversion efficiency. Referring to Figure 1, the main grid 5 comes into contact with the emitter layer 2 on the silicon substrate (i.e., semiconductor substrate 1), which also results in a decrease in the open-circuit voltage (Uoc) and further impacts the photoelectric conversion efficiency. It should be noted that the emitter layer 2 can be formed by doping the original structure of the single-crystal silicon semiconductor substrate using common methods, such as diffusion or ion implantation, or it can be an additional layer formed on the surface of the original single-crystal silicon semiconductor substrate by a deposition process, such as LPCVD or PECVD.

[0066] In order to solve the above technical problems, in a first aspect, an embodiment of the present application provides a method for manufacturing a solar cell, the method comprising the following steps:

[0067] 2 and 3, first, a semiconductor substrate 1 is provided.

[0068] In practical applications, the specific structure of the semiconductor substrate can be determined according to the actual application scenario and is not specifically limited herein. For example, the semiconductor substrate may be a semiconductor substrate only. For example, the semiconductor substrate may be a substrate made of a semiconductor material such as a monocrystalline silicon substrate, a polycrystalline silicon substrate, or an amorphous silicon substrate. In terms of conductivity, the semiconductor substrate may be an N-type conductive substrate or a P-type conductive substrate. In terms of structure, the first surface of the semiconductor substrate may be a textured surface to improve the light trapping effect of the light-receiving surface of the solar cell and improve the light utilization efficiency of the solar cell. Of course, the first surface of the semiconductor substrate may be flat. The second surface of the semiconductor substrate may be a polished surface or a textured surface and is not specifically limited herein. Furthermore, the size of the semiconductor substrate may be 182 mm, 210 mm, or other rectangular semiconductor substrates. The thickness of the semiconductor substrate is generally 100 μm or more and 180 μm or less.

[0069] Next, an emitter layer 2 is formed on one surface of the semiconductor substrate 1. The semiconductor substrate 1 and the emitter layer 2 have opposite conductivity types, and the emitter layer 2 and the semiconductor substrate 1 together form a PN junction.

[0070] For example, the emitter layer is a region doped with impurities having a second conductivity type (e.g., N-type) opposite to the first conductivity type (e.g., P-type) of the semiconductor substrate. Furthermore, the emitter layer may be formed by doping the original structure of the single-crystal silicon semiconductor substrate using a method commonly used in the industry, such as diffusion or ion implantation. It may also be an additional layer formed on the surface of the original single-crystal silicon semiconductor substrate by a process such as deposition. Furthermore, the emitter layer is located on the light-receiving surface of the semiconductor substrate. Other descriptions of the emitter layer can be found in the prior art, and are not specifically limited herein.

[0071] Next, a passivation layer 3 is formed on the emitter layer 2 .

[0072] For example, the material of the passivation layer 3 may include one or more of aluminum oxide, zinc oxide, and silicon nitride.

[0073] Next, the insulating layer 4 is formed on the passivation layer 3 .

[0074] For example, the material of the insulating layer 4 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0075] Next, the main grids 5 are formed on the insulating layer 4. The main grids 5 extend in a first direction and are spaced apart from each other in a second direction different from the first direction.

[0076] For example, the first direction A and the second direction B may be any two directions parallel to the surface of the semiconductor substrate and different from each other. Preferably, referring to FIG. 3, the first direction A and the second direction B are perpendicular to each other.

[0077] Next, finger grids 6 are formed on the insulating layer 4. The finger grids 6 extend in the second direction and are spaced apart in the first direction. Each main grid 5 intersects with a plurality of finger grids 6, and the finger grids 6 penetrate the passivation layer 3 and the insulating layer 4 and connect to the emitter layer 2.

[0078] For example, facing the semiconductor substrate 1, the finger grid may be connected to the emitter layer through openings in the passivation and insulating layers, through through holes in the passivation and insulating layers, or by other methods. Other methods may include deposition processes such as PVD and CVD, and electroplating methods. Note that the connection method is not limited to the above as long as it can realize the connection between the finger grid and the emitter layer.

[0079] The main grid 5 extends in direction C toward the emitter layer 2, and the extending depth D1 of the main grid 5 is 90% or less of the thickness D2 of the passivation layer 3 and is greater than 20% of the thickness D3 of the insulating layer 4. The depth direction, the thickness direction of the passivation layer 3, and the thickness direction of the insulating layer 4 all coincide with the direction toward the semiconductor substrate 1. For example, the extending depth of the main grid 5 may be 0%, 10%, 15%, 30%, 50%, 80%, 90%, etc. of the thickness of the passivation layer 3.

[0080] In the solar cell manufacturing method provided by the embodiment of the present application, the main grid 5 is formed on the insulating layer 4 and extends toward the emitter layer 2, and the extending depth of the main grid 5 is 90% or less of the thickness of the passivation layer 3 and is greater than 20% of the thickness of the insulating layer. Therefore, in this case, a part of the extended main grid 5 (i.e., a part of the main grid) may be located only in the insulating layer 4, or may be located in both the insulating layer 4 and the passivation layer 3, but the extending depth does not exceed 90% of the thickness of the passivation layer 3.

[0081] When the extended portion of the main grid 5 is located only within the insulating layer 4, the main grid 5 does not destroy the passivation layer 3, ensuring the passivation effect of the passivation layer 3. This can increase the open-circuit voltage and reduce or eliminate the impact on photoelectric conversion efficiency.

[0082] The extended portion of the main grid 5 is located within both the insulating layer 4 and the passivation layer 3, but is less than 90% of the thickness of the passivation layer 3. This reduces the degree of damage to the passivation layer 3 caused by the main grid 5, thereby ensuring the passivation effect of the passivation layer 3, as opposed to the prior art, where the main grid 5 penetrates the passivation layer 3 to connect to the silicon substrate. This increases the open-circuit voltage and reduces the impact on photovoltaic conversion efficiency. Furthermore, when the battery module is subsequently manufactured and electrically connected, the main grid 5 is covered by the ribbon. Mechanical effects of the ribbon (including, but not limited to, mismatches in stress and expansion coefficients) can be detrimental to the main grid 5 (e.g., the main grid 5 may peel off from the solar cell). If the extended portion of the main grid 5 is located within both the insulating layer 4 and the passivation layer 3 but does not exceed 90% of the thickness of the passivation layer 3, the main grid 5 is connected to both the insulating layer 4 and the passivation layer 3. This ensures the mechanical performance of the main grid 5 and improves the tensile resistance of the main grid 5. This reduces or eliminates the possibility of the main grid 5 peeling off from the solar cell, ensuring the quality and performance of the solar cell.

[0083] In one alternative, the solar cell may be a back-contact solar cell, where the emitter layer is located on the non-light-receiving side of the solar cell, the emitter layer comprises a doping type opposite to that of the semiconductor substrate, and the emitter layer may be formed by doping the original structure of the semiconductor substrate or by an additional deposition process, such as LPCVD, PECVD, etc.

[0084] 2, in one possible embodiment, the ratio of the depth of the main grid 5 within the passivation layer 3 to the thickness of the passivation layer 3 is 20% or more. For example, the ratio may be 20%, 30%, 35%, 46%, 50%, etc. In this case, the main grid 5 is connected to both the insulating layer 4 and the passivation layer 3. This ensures the mechanical performance of the main grid 5, improves the tensile resistance of the main grid 5, reduces or eliminates the probability of the main grid 5 peeling off from the solar cell, and further ensures the quality and performance of the solar cell.

[0085] With reference to the above description, when the main grid 5 extends into the passivation layer 3, the ratio of the extension depth of the main grid 5 in the passivation layer 3 to the thickness of the passivation layer 3 is 20% or more and 90% or less.

[0086] In one possible embodiment, the main grid 5 extends to a depth of 0 within the passivation layer 3. That is, the main grid 5 is located only within the insulating layer 4, specifically, the main grid 5 is located only within the insulating layer 4, or the main grid 5 is located at the interface between the insulating layer 4 and the passivation layer 3, or the main grid 5 is located only on the surface of the insulating layer 4. In this case, damage to the passivation layer 3 by the main grid 5 can be avoided, and the passivation effect of the passivation layer 3 can be ensured. This can increase the open-circuit voltage and avoid affecting the photoelectric conversion efficiency.

[0087] In one possible embodiment, when the thickness of the passivation layer is 5 nm to 20 nm, the extension depth of the main grid in the passivation layer is 1 nm to 18 nm, for example, 1 nm, 5 nm, 9 nm, 13 nm, 15 nm, or 18 nm.

[0088] A depth of 1 nm or more ensures that the main grid is connected to both the insulating layer and the passivation layer. This ensures the mechanical performance of the main grid, improves its tensile resistance, reduces or eliminates the possibility of the main grid peeling from the solar cell, and ensures the quality and performance of the solar cell. Furthermore, a depth of 18 nm or less reduces the degree of damage to the passivation layer caused by the main grid, ensures the passivation effect of the passivation layer, increases the open-circuit voltage, and reduces the impact on photovoltaic conversion efficiency. Furthermore, a passivation layer with a thickness of 2 nm or more can be prevented from being damaged.

[0089] In one possible embodiment, the emitter layer includes a heavily doped region and a lightly doped region, and the finger grid is connected to the heavily doped region to form an alloy region, the depth of the alloy region in the emitter layer being smaller than the emitter junction depth of the emitter layer, and both the depth direction and the emitter junction depth direction are aligned toward the semiconductor substrate.

[0090] In one alternative embodiment, when the emitter junction depth is 300 nm to 1200 nm, the alloy region in the emitter extends to a depth of 50 nm to 1000 nm. For example, the alloy region in the emitter may extend to a depth of 50 nm, 80 nm, 100 nm, 260 nm, 390 nm, 550 nm, or 1000 nm. Because the depth is 50 nm or greater, the finger grid forms an alloy with the semiconductor substrate, enabling good ohmic contact.

[0091] Preferably, when the junction depth of the emitter is 300 nm or more and 1200 nm or less, the depth to which the alloy region extends in the emitter is 50 nm or more and 100 nm or less.

[0092] In one possible embodiment, the thickness of the insulating layer is 40 nm to 100 nm, for example, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0093] 3, in one possible embodiment, each main grid 5 includes a main grid connection line 50 and a pad 51. The pads 51 are spaced apart from the main grid connection line 50 in the first direction, the width of the pads 51 is greater than the width of the main grid connection line 50, and the width directions of the pads 51 and the main grid connection line 50 both coincide with the second direction.

[0094] 2 and 3, even if the number of main grid connection lines 50 is the same, the width of the main grid connection lines 50 is equal to the width of the pads 51. This ensures that the current collection capacity of the main grid connection lines 50 meets actual requirements, while reducing the amount of material used in manufacturing the main grid connection lines 50 and saving material costs. This also reduces the shielding of the semiconductor substrate 1 by the main grid connection lines 50, increasing the light-receiving area of ​​the semiconductor substrate 1 and improving the photoelectric conversion efficiency of the solar cell. Furthermore, ribbons must be connected to the pads 51 during subsequent battery module manufacturing. In this case, the width of the main grid connection lines 50 is equal to the width of the pads 51, which simplifies the connection of the ribbons to the pads 51, reducing manufacturing difficulty and improving manufacturing efficiency. The specific structures and materials of the main grid connection lines 50 and pads 51 may refer to the prior art and are not specifically limited herein.

[0095] In one alternative embodiment, referring to FIG. 3 , the number of main grids 5 is 8 to 25 inclusive. For example, the number of main grids 5 may be 8, 10, 12, 15, 18, 20, 22, or 25, etc. And / or the width of the main-grid connecting lines 50 is 35 μm to 60 μm inclusive. For example, the width of the main-grid connecting lines 50 may be 35 μm, 40 μm, 45 μm, 52 μm, 55 μm, or 60 μm, etc. The width of the pads 51 is 0.6 mm to 1.3 mm inclusive. For example, the width of the pads 51 may be 0.6 mm, 0.8 mm, 1.0 mm, 1.16 mm, 1.23 mm, or 1.3 mm, etc.

[0096] By controlling the number of main grids 5, the width of the main grid connection lines, and the width of the pads, it is possible to control the area shielded by the main grids 5 onto the semiconductor substrate 1. In this case, the amount of light incident on the semiconductor substrate 1 can be increased, the light-receiving area of ​​the semiconductor substrate 1 can be increased, and the cell efficiency of the solar cell can be improved.

[0097] In one possible embodiment, referring to FIG. 3 , the number of finger grids 6 is between 100 and 200. For example, the number of finger grids 6 may be 100, 120, 150, 180, 195, or 200. The width of each finger grid 6 is between 20 μm and 45 μm, and the width direction of the finger grid 6 coincides with the first direction. For example, the width of the finger grid 6 may be 20 μm, 26 μm, 30 μm, 36 μm, 40 μm, or 45 μm. In this case, the current collection ability of the finger grid 6 can be improved, thereby improving the cell efficiency of the solar cell.

[0098] In one possible embodiment, the step of forming the main grid on the insulating layer includes the following steps:

[0099] First, a main grid material is printed on an insulating layer to form an initial main grid.

[0100] For example, the main grid material may contain glass frit and metal. For example, the glass frit may include one or more of PbO, BO, NaO, LiO, BiO, WO, TeO, and Te / W. The metal may include, but is not limited to, silver. Furthermore, the main grid material may be printed by screen printing. The specific printing process may be based on prior art and is not specifically limited herein.

[0101] The initial main grid is then processed to form the main grid.

[0102] The ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.1, and the width direction of the main grid and the width direction of the initial main grid both coincide with the second direction. For example, the ratio may be 1.01, 1.02, 1.04, 1.05, 1.08, 1.09, or 1.1.

[0103] In the actual manufacturing process of the main grid, the main grid not only extends toward the emitter layer but also extends toward the second direction. Therefore, by controlling the extension size of the final main grid in the second direction, it is possible to reduce adverse effects on the insulating layer and / or passivation layer, thereby reducing adverse effects on the anti-reflection effect and / or passivation effect of the solar cell, as well as to reduce the shading of the semiconductor substrate by the main grid, increase the light-receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0104] It should be noted that the main grid does not extend into the semiconductor substrate, which means that the metal component (e.g., silver) in the main grid material does not penetrate into the interface of the semiconductor substrate, or that the metal component (e.g., silver) in the main grid material does not form an alloy (e.g., silver-silicon alloy) with the semiconductor material in the semiconductor substrate.

[0105] Preferably, the ratio of the width of the main grid to the width of the initial main grid is greater than 1 and not greater than 1.05. For example, the ratio may be 1.01, 1.02, 1.03, 1.04, 1.05, or the like.

[0106] In one possible embodiment, the step of forming a finger grid on the insulating layer includes the following steps:

[0107] First, a finger grid material is printed on an insulating layer to form an initial finger grid.

[0108] For example, the finger-grid raw material contains glass frit and metal. For example, the glass frit may include one or more of PbO, BO, NaO, LiO, BiO, WO, TeO, and Te / W. The metal may include, but is not limited to, silver. Furthermore, the finger-grid raw material may be printed by screen printing. Specific printing processes may be referred to in the prior art and are not specifically limited herein.

[0109] The initial finger grid is then processed to form the finger grid.

[0110] The ratio of the width of the finger grid to the width of the initial finger grid is greater than 1 and less than or equal to 1.2, and the width direction of the finger grid and the width direction of the initial finger grid both coincide with the first direction. For example, the ratio may be 1.01, 1.02, 1.04, 1.05, 1.08, 1.09, 1.1, or 1.2.

[0111] In actual manufacturing process of the finger grids, the finger grids extend in the second direction, and the corrosivity of the finger grid raw material is greater than that of the main grid raw material. Therefore, by controlling the extension size of the final finger grids in the second direction, it is possible to reduce the adverse effects on the insulating layer and / or passivation layer, and thus the anti-reflection effect and / or passivation effect of the solar cell. It is also possible to reduce the shading of the semiconductor substrate by the finger grids, increase the light-receiving area of ​​the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0112] Furthermore, the finger grid extends to the emitter layer. Due to the windowing effect of the phosphate glass, the metal components in the finger grid raw material penetrate the emitter layer and form an alloy (e.g., a silver-silicon alloy) with the semiconductor components. The area where the silver-silicon alloy is formed significantly improves contact performance, and the silver-silicon alloy distribution area is located within the area covered by the finger grid. The silver-silicon alloy distribution area can be continuous, or due to the transition of silver particles, the silver-silicon alloy distribution can be in a discrete, discontinuous form, or both forms can coexist. The depth of the silver-silicon alloy distribution area can be adjusted depending on the process and the composition of the finger grid raw material. Generally, the higher the glass frit content, the stronger the finger grid's elongation performance.

[0113] Furthermore, the heavily doped region is generally located below the finger grid, but may also be located below the main grid. In the embodiment of the present application, it is preferable that the heavily doped region is located below the finger grid, and that no heavily doped region is provided below the main grid. The silver-silicon alloy is distributed in the heavily doped region, but may migrate laterally beyond the heavily doped region and infiltrate into adjacent lightly doped regions. However, the content of the excess portion is small and generally discrete. The total amount of silver-silicon alloy that infiltrates into adjacent lightly doped regions is 10% or less of the total silver-silicon alloy, and even 5% or 2% or less. Excessive infiltration of the silver-silicon alloy into adjacent lightly doped regions can cause adverse effects.

[0114] Preferably, the ratio of the width of the finger grid to the width of the initial finger grid is greater than 1 and less than or equal to 1.08. For example, the ratio may be 1.01, 1.02, 1.03, 1.04, 1.05, 1.06, 1.07, 1.08, or the like.

[0115] In one alternative embodiment, the metal solids content of the main grid material is less than the metal solids content of the finger grid material. Illustratively, the silver solids content of the main grid material is less than the silver solids content of the finger grid material.

[0116] In this case, the extension depth of the main grid into the emitter layer is smaller than the extension depth of the finger grid into the emitter layer. This reduces the degree of damage to the passivation layer by the main grid and ensures the passivation effect of the passivation layer. Furthermore, even if the metal solid content of the finger grid material is the same, the cost of the main grid material can be reduced, thereby reducing the manufacturing cost of the solar cell, compared to the prior art, where the metal solid content of the main grid material and the finger grid material is the same. In addition, the extension depth of the finger grid into the emitter layer in the embodiment of the present application is ensured to be identical or approximately identical to the extension depth of the finger grid into the emitter layer in the prior art, ensuring the performance of the finger grid remains unchanged.

[0117] The extension depth of the main grid and finger grids can be adjusted by controlling the specific composition of the main grid raw material and finger grid raw material, for example, by increasing the glass frit content or metal content in the main grid raw material and finger grid raw material.

[0118] In a second aspect, an embodiment of the present application further provides a solar cell. Referring to FIGS. 2 and 3, the solar cell includes a semiconductor substrate 1, an emitter layer 2, a passivation layer 3, an insulating layer 4, a main grid 5, and a finger grid 6. The emitter layer 2 is located on one side of the semiconductor substrate 1, and the semiconductor substrate 1 and the emitter layer 2 have opposite conductivity types, forming a PN junction together. The passivation layer 3 is located on the emitter layer 2, and the insulating layer 4 is located on the passivation layer 3. The main grid 5 is located on the insulating layer 4, extends in a first direction, and is spaced apart in a second direction different from the first direction. The finger grid 6 is located on the insulating layer 4, extends in the second direction, and is spaced apart in the first direction. Each main grid 5 intersects with a plurality of finger grids 6, and the finger grids 6 penetrate the passivation layer 3 and the insulating layer 4 to connect to the emitter layer 2. The main grid 5 extends toward the emitter layer 2, and the extending depth D1 of the main grid 5 is 90% or less of the thickness D2 of the passivation layer 3 and is greater than 20% of the thickness D3 of the insulating layer 4, and the depth direction, the thickness direction of the passivation layer 3, and the thickness direction of the insulating layer 4 all coincide with the direction toward the semiconductor substrate 1. For example, the extending depth of the main grid 5 may be 0%, 10%, 15%, 30%, 50%, 80%, or 90% of the thickness of the passivation layer 3.

[0119] For information related to the semiconductor substrate 1, emitter layer 2, passivation layer 3, and insulating layer 4, please refer to the description of the first aspect and will not be described again here. Furthermore, the first direction and the second direction may be any two different directions parallel to the surface of the semiconductor substrate 1. Preferably, referring to FIG. 3, the first direction A and the second direction B are perpendicular to each other.

[0120] In the solar cell provided by the embodiment of the present application, the main grid 5 is formed on the insulating layer 4 and extends toward the emitter layer 2, and the extending depth of the main grid 5 is 90% or less of the thickness of the passivation layer 3 and is greater than 20% of the thickness of the insulating layer 2. Therefore, in this case, a part of the extended main grid 5 (i.e., a part of the main grid) may be located only in the insulating layer 4, or may be located in both the insulating layer 4 and the passivation layer 3, but the extending depth does not exceed 90% of the thickness of the passivation layer 3.

[0121] When the extended portion of the main grid 5 is located only within the insulating layer 4, the main grid 5 does not destroy the passivation layer 3, ensuring the passivation effect of the passivation layer 3. This can increase the open-circuit voltage and reduce or eliminate the impact on photoelectric conversion efficiency.

[0122] The extended portion of the main grid 5, located within both the insulating layer 4 and the passivation layer 3 but not exceeding 90% of the thickness of the passivation layer 3, reduces the degree of damage to the passivation layer 3 caused by the main grid 5 and ensures the passivation effect of the passivation layer 3, as opposed to the prior art in which the main grid 5 penetrates the passivation layer 3 and connects to the silicon substrate. This increases the open-circuit voltage and reduces the impact on photovoltaic conversion efficiency. Furthermore, the main grid 5 is connected to both the insulating layer 4 and the passivation layer 3, ensuring the mechanical performance of the main grid 5 and improving its tensile resistance. This reduces or eliminates the possibility of the main grid 5 peeling off from the solar cell, ensuring the quality and performance of the solar cell.

[0123] 2, in one possible embodiment, the ratio of the depth of the main grid 5 within the passivation layer 3 to the thickness of the passivation layer 3 is 20% or more. For example, the ratio may be 20%, 30%, 35%, 46%, 50%, etc. In this case, the main grid 5 is connected to both the insulating layer 4 and the passivation layer 3. This ensures the mechanical performance of the main grid 5, improves the tensile resistance of the main grid 5, reduces or eliminates the possibility of the main grid 5 peeling off from the solar cell, and further ensures the quality and performance of the solar cell.

[0124] With reference to the above description, when the main grid 5 extends into the passivation layer 3, the ratio of the extension depth of the main grid 5 in the passivation layer 3 to the thickness of the passivation layer 3 is 20% or more and 90% or less.

[0125] In one possible embodiment, the main grid extends to a depth of 0 within the passivation layer. That is, the main grid is located only within the insulating layer, specifically, only within the insulating layer, or only at the interface between the insulating layer and the passivation layer, or only on the surface of the insulating layer. In this case, damage to the passivation layer by the main grid can be avoided, and the passivation effect of the passivation layer can be ensured. This can increase the open-circuit voltage and avoid affecting the photoelectric conversion efficiency.

[0126] In one possible embodiment, when the thickness of the passivation layer is between 5 nm and 20 nm, the extension depth of the main grid into the passivation layer is between 1 nm and 18 nm, for example, the extension depth of the main grid into the passivation layer may be 1 nm, 5 nm, 9 nm, 13 nm, 15 nm, or 18 nm.

[0127] The depth of 1 nm or more ensures that the main grid is connected to both the insulating layer and the passivation layer. This ensures the mechanical performance of the main grid, improves its tensile resistance, reduces or eliminates the possibility of the main grid peeling from the solar cell, and ensures the quality and performance of the solar cell. Furthermore, the depth of 18 nm or less reduces the degree of damage to the passivation layer caused by the main grid, ensures the passivation effect of the passivation layer, increases the open-circuit voltage, and reduces the impact on photovoltaic conversion efficiency.

[0128] In one possible embodiment, the emitter layer includes a heavily doped region and a lightly doped region, and the finger grid is connected to the heavily doped region to form an alloy region, the depth of the alloy region in the emitter layer being smaller than the emitter junction depth of the emitter layer, and both the depth direction and the emitter junction depth direction are aligned toward the semiconductor substrate.

[0129] In one alternative embodiment, when the emitter junction depth is 300 nm to 1200 nm, the alloy region in the emitter extends to a depth of 50 nm to 1000 nm. For example, the alloy region in the emitter may extend to a depth of 50 nm, 80 nm, 100 nm, 260 nm, 390 nm, 550 nm, or 1000 nm. Because the depth is 50 nm or greater, the finger grid forms an alloy with the semiconductor substrate, enabling good ohmic contact.

[0130] Preferably, when the junction depth of the emitter is 300 nm or more and 1200 nm or less, the depth to which the alloy region extends in the emitter is 50 nm or more and 100 nm or less.

[0131] In one possible embodiment, the thickness of the insulating layer is 40 nm to 100 nm, for example, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0132] 3, in one possible embodiment, each main grid 5 includes a main grid connection line 50 and a pad 51. The pads 51 are spaced apart from the main grid connection line 50 in the first direction, the width of the pads 51 is greater than the width of the main grid connection line 50, and the width directions of the pads 51 and the main grid connection line 50 both coincide with the second direction.

[0133] Although the number of main grid connection lines 50 is the same, the width of each main grid connection line 50 is equal to the width of each pad 51. This ensures that the current collection capacity of each main grid connection line 50 meets actual requirements, while reducing the amount of material used in manufacturing the main grid connection lines 50 and saving material costs. This also reduces the amount of shielding of the semiconductor substrate 1 by the main grid connection lines 50, increasing the light-receiving area of ​​the semiconductor substrate 1 and improving the photoelectric conversion efficiency of the solar cell. Furthermore, ribbons must be connected to the pads 51 during subsequent battery module manufacturing. In this case, the width of each main grid connection line 50 is equal to the width of each pad 51, making it easier to connect the ribbons to the pads 51, reducing manufacturing difficulty and improving manufacturing efficiency. The specific structures and materials of the main grid connection lines 50 and pads 51 can be referenced in the prior art and are not specifically limited herein.

[0134] 3, in one alternative embodiment, the number of the main grids 5 is equal to or greater than 8 and equal to or less than 25. For example, the number of the main grids 5 may be 8, 10, 12, 15, 18, 20, 22, 25, etc.

[0135] And / or, the width of the main grid connection lines 50 is 35 μm or more and 60 μm or less. For example, the width of the main grid connection lines 50 may be 35 μm, 40 μm, 45 μm, 52 μm, 55 μm, or 60 μm. The width of the pads 51 is 0.6 mm or more and 1.3 mm or less. For example, the width of the pads 51 may be 0.6 mm, 0.8 mm, 1.0 mm, 1.16 mm, 1.23 mm, or 1.3 mm.

[0136] By controlling the number of main grids 5, the width of the main grid connection lines, and the width of the pads, it is possible to control the area shielded by the main grids 5 onto the semiconductor substrate 1. In this case, the amount of light incident on the semiconductor substrate 1 can be increased, the light-receiving area of ​​the semiconductor substrate 1 can be increased, and the cell efficiency of the solar cell can be improved.

[0137] In one possible embodiment, referring to FIG. 3 , the number of finger grids 6 is between 100 and 200. For example, the number of finger grids 6 may be 100, 120, 150, 180, 195, or 200. The width of each finger grid 6 is between 20 μm and 45 μm, and the width direction of the finger grid 6 coincides with the first direction. For example, the width of the finger grid 6 may be 20 μm, 26 μm, 30 μm, 36 μm, 40 μm, or 45 μm. In this case, the current collection ability of the finger grid 6 can be improved, thereby improving the cell efficiency of the solar cell.

[0138] In a third aspect, an embodiment of the present application further provides a battery module, which includes a plurality of ribbons and a plurality of solar cells described in the above technical solution arranged at intervals, and the ribbons are correspondingly connected to a main grid.

[0139] The beneficial effects of the battery module provided by the embodiments of the present application are the same as those of the solar cell described in the above technical solutions, so they will not be repeated here.

[0140] In one possible embodiment, when the main grid includes a main-grid connecting line and a pad, a ribbon is attached to the pad in the first direction to cover the main-grid connecting line, the maximum width of the ribbon is equal to or less than the width of the pad, and the width directions of the ribbon and the pad are both aligned with the second direction. In this case, the shielding of the semiconductor substrate by the ribbon is reduced, the light-receiving area of ​​the semiconductor substrate is increased, and the photoelectric conversion efficiency of the solar cell is improved.

[0141] In one alternative embodiment, the width of the ribbon is equal to or less than the width of the main-grid connecting lines, and the width directions of the ribbon and the main-grid connecting lines are both aligned with the second direction, thereby reducing the shading of the semiconductor substrate by the ribbon, increasing the light-receiving area of ​​the semiconductor substrate, and improving the photoelectric conversion efficiency of the solar cell.

[0142] In one alternative embodiment, the ratio of the width of the ribbon to the width of the grid connection line is 50% or more and 90% or less, for example, the ratio may be 50%, 60%, 65%, 70%, 80%, or 90%, etc.

[0143] Because the ribbon includes a metal core layer and a solder layer located on the outer surface of the core layer, the solder layer melts with heat during the actual process of welding the ribbon and pad, and has a certain degree of fluidity. Because the ratio is between 50% and 90%, the flowing solder can be provided with sufficient space to distribute at the interface between the ribbon and the main grid connecting wire. This prevents the solder from flowing onto the semiconductor substrate, preventing contamination or obstruction of the semiconductor substrate by the solder, and further ensuring the quality and performance of the solar cell.

[0144] In the present application, the number of ribbons is the same as the number of main grid connection lines.

[0145] In the above description of the embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

[0146] The above description is merely a specific embodiment of the present application, and the scope of protection of the present application is not limited thereto. Any modifications or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed by the present application are included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims set forth below. [Explanation of symbols]

[0147] 1. Semiconductor substrate 2 Emitter layer 3 Passivation Layer 4. Insulation layer 5 Main Grid 6 Finger Grid 50 Main Grid Connection Wire 51 Pad

Claims

1. providing a semiconductor substrate; forming an emitter layer having a conductivity type opposite to that of the semiconductor substrate on one surface of the semiconductor substrate; forming a passivation layer on the emitter layer; forming an insulating layer on the passivation layer; forming main grids on the insulating layer, the main grids extending in a first direction and spaced apart in a second direction different from the first direction; forming finger grids on the insulating layer, the finger grids extending in a second direction and spaced apart in the first direction, each of the main grids intersecting a plurality of the finger grids, the finger grids passing through the passivation layer and the insulating layer and connected to the emitter layer; a main grid extending toward the emitter layer, a depth of the main grid in the insulating layer that is greater than 20% of the thickness of the insulating layer, and a depth of the main grid in the passivation layer that is not greater than 90% of the thickness of the passivation layer, and a depth direction of the main grid, a thickness direction of the passivation layer, and a thickness direction of the insulating layer all coincide with a direction toward the semiconductor substrate.

2. the ratio of the extension depth of the main grid in the passivation layer to the thickness of the passivation layer is 20% or more, or 2. The method for manufacturing a solar cell according to claim 1, wherein the extension depth of the main grid in the passivation layer is zero.

3. 2. The method for manufacturing a solar cell according to claim 1, wherein when the thickness of the passivation layer is 5 nm or more and 20 nm or less, the extension depth of the main grid in the passivation layer is 1 nm or more and 18 nm or less.

4. the main grid includes a main grid connection line and a pad; the pads are spaced apart from each other in the first direction from the main grid connection line; 2. The method for manufacturing a solar cell according to claim 1, wherein the width of the pad is larger than the width of the main-grid connection line, and the width direction of the pad and the width direction of the main-grid connection line both coincide with the second direction.

5. The step of forming a main grid on the insulating layer includes: printing a main grid material on the insulating layer to form an initial main grid; processing the initial main grid to form the main grid; 2. The method for manufacturing a solar cell according to claim 1, wherein a ratio of a width of the main grid to a width of the initial main grid is greater than 1 and is not greater than 1.1, and a width direction of the main grid and a width direction of the initial main grid both coincide with the second direction.

6. The step of forming a finger grid on the insulating layer comprises: printing a finger grid material on the insulating layer to form an initial finger grid; processing the initial finger grid to form the finger grid; 6. The method for manufacturing a solar cell according to claim 5, wherein a ratio of a width of the finger grid to a width of the initial finger grid is greater than 1 and not more than 1.2, and the width direction of the finger grid and the width direction of the initial finger grid both coincide with the first direction.

7. 7. The method for manufacturing a solar cell according to claim 6, wherein the metal solid content in the main grid raw material is less than the metal solid content in the finger grid raw material.

8. a semiconductor substrate; an emitter layer located on one surface of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate; a passivation layer located on the emitter layer; an insulating layer located on the passivation layer; a main grid located on the insulating layer, extending in a first direction and spaced apart from one another in a second direction different from the first direction; a finger grid located on the insulating layer, extending in the second direction and spaced apart in the first direction; Each of the main grids intersects with a plurality of the finger grids, and the finger grids penetrate the passivation layer and the insulating layer and are connected to the emitter layer; a main grid extending toward the emitter layer, a depth of the main grid in the insulating layer that is greater than 20% of the thickness of the insulating layer, and a depth of the main grid in the passivation layer that is not greater than 90% of the thickness of the passivation layer, and a depth direction of the main grid, a thickness direction of the passivation layer, and a thickness direction of the insulating layer all coincide with a direction toward the semiconductor substrate.

9. 9. The solar cell according to claim 8, wherein the emitter layer is located on a non-light-receiving surface of the solar cell.

10. 9. The solar cell according to claim 8, wherein the emitter layer is formed by doping the original structure of the semiconductor substrate or by a deposition process on the surface of the semiconductor substrate.

11. the ratio of the extension depth of the main grid in the passivation layer to the thickness of the passivation layer is 20% or more, or 9. The solar cell according to claim 8, wherein the extension depth of the main grid in the passivation layer is zero.

12. 9. The solar cell according to claim 8, wherein when the thickness of the passivation layer is 5 nm to 20 nm, the extension depth of the main grid in the passivation layer is 1 nm to 18 nm.

13. 9. The solar cell according to claim 8, wherein the insulating layer has a thickness of 40 nm to 100 nm.

14. the main grid includes a main grid connection line and a pad; the pads are spaced apart from each other in the first direction from the main grid connection line; 9. The solar cell according to claim 8, wherein the width of the pad is larger than the width of the main grid connection line, and the width direction of the pad and the width direction of the main grid connection line both coincide with the second direction.

15. the number of main grids is between 8 and 25, and / or 15. The solar cell according to claim 14, wherein the width of the main grid connection line is 35 μm or more and 60 μm or less, and the width of the pad is 0.6 mm or more and 1.3 mm or less.

16. The number of the finger grids is 100 or more and 200 or less, 16. The solar cell according to claim 8, 14 or 15, wherein the width of the finger-grid is 20 μm or more and 45 μm or less, and the width direction of the finger-grid coincides with the first direction.

17. a plurality of ribbons and a plurality of solar cells according to any one of claims 8 to 16 arranged at intervals; The ribbons are connected to the main grids in a corresponding manner.

18. 18. The battery module of claim 17, wherein, when the main grid includes a main-grid connection line and a pad, the ribbon is attached to the pad in the first direction and covers the main-grid connection line, the maximum width of the ribbon is equal to or less than the width of the pad, and both the width direction of the ribbon and the width direction of the pad coincide with the second direction.

19. 19. The battery module of claim 18, wherein a width of the ribbon is equal to or less than a width of the main-grid connection line, and a width direction of the ribbon and a width direction of the main-grid connection line both coincide with the second direction.

20. 20. The battery module according to claim 18 or 19, wherein a ratio of the width of the ribbon to the width of the main-grid connecting line is 50% or more and 90% or less.

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