Integrated circuits and related manufacturing methods

Abstract

Disclosed is an integrated circuit (IC) comprising at least one p-type thin film transistor (TFT) and at least one additional electronic device formed on a substrate. The at least one p-type TFT comprises a channel region formed from at least partially crystalline silicon. The partially crystalline silicon may comprise low temperature polycrystalline silicon (LTPS). The channel region of the at least one p-type TFT may be between 1 and 40 cm 2 The at least one further electronic device may be formed from at least partially crystalline silicon having a charge carrier mobility in the range encompassing .times. ...

Description

[Technical Field]

[0001] The present disclosure relates to integrated circuits (ICs) and methods of manufacturing such ICs. The present invention particularly, but not exclusively, relates to integrated circuits comprising one or more p-type thin film transistors (TFTs) and related methods of manufacturing integrated circuits comprising one or more p-type TFTs. [Background technology]

[0002] Historically, IC fabrication has largely involved the use of single-crystal wafers of semiconductor material, such as silicon (c-Si) or gallium arsenide (GaAs), as substrates on which microelectronic circuits are fabricated to form ICs. Such wafers typically have extremely high levels of purity and, due to their single-crystal structure, exhibit relatively high charge mobility compared to amorphous semiconductors.

[0003] During the manufacturing process, devices such as diodes, transistors, capacitors, and resistors are typically constructed by forming p-type, n-type, and / or undoped semiconductor regions in a semiconductor substrate using appropriate doping, and / or by forming other functions using other materials (e.g., insulators / dielectrics and / or conductive materials) using appropriate manufacturing processes. The locations of the n-type, p-type, and / or undoped regions and the patterns of insulating and / or conductive materials in each layer that defines the device, and the interconnectivity between them, are typically defined using appropriate photolithographic processes.

[0004] One fundamental electronic component that typically forms part of such integrated circuits, particularly for logic circuits and other digital electronic applications, is the so-called field-effect transistor (FET). FETs can be used in a wide range of circuits, for example, as voltage-controlled switches and / or voltage-controlled resistors. FETs generally have three terminals: a source, a drain, and a gate. The gate typically includes a conductive gate electrode formed on a layer of insulator (dielectric) material disposed on a semiconductor material between the source and drain. An electric field resulting from a voltage applied to the gate causes the formation and / or modulates the conductivity of a conductive channel beneath the gate (typically at the interface between the insulator and the semiconductor) in a channel region extending from the source to the drain, thereby allowing current to flow. If the semiconductor material beneath the device's gate is undoped or positively doped and a positive gate voltage is required to form a channel of negative charge (electrons), such a device may be referred to as an "n-type" or "n-channel" device. If the semiconductor material under the gate of the device is undoped or negatively doped, and a negative gate voltage is required to form a channel of positive charges (called holes), such a device may be called a "p-type" or "p-channel" device.

[0005] Such FETs may be referred to in several different ways, for example, as metal-insulator-semiconductor FETs (MISFETs), metal-oxide-semiconductor FETs (MOSFETs), metal-oxide-semiconductor transistors (MOSTs), etc. It will be understood that the terms MOSFET or MOST have become so broadly used that they are also used to refer to devices that do not have a strictly metal-oxide-semiconductor structure (e.g., including gate electrodes that are not strictly metals (e.g., very heavily doped polysilicon) and / or gate insulators that are not strictly oxides (e.g., nitrides)).

[0006] However, while the fabrication of MOSFETs on single-crystal semiconductor substrates has wide applications, there are also a wide range of applications in which it would be beneficial to be able to fabricate FETs on other substrates, including insulating substrates. For example, there are many applications for FETs fabricated on rigid substrates (e.g., formed from rigid glass) or flexible substrates (e.g., formed from layers of polymer-based materials). In particular, flexible substrate-based circuits are emerging as an important technology for the fabrication of low-cost flexible ICs that can be relatively easily incorporated into everyday objects.

[0007] A flexible circuit element or structure, such as a flexible integrated circuit (e.g., flexible IC or FlexIC), is a patterned arrangement of circuits and components provided on a flexible base material with or without a flexible overlay. The circuits patterned on each flexible circuit element may include any of resistors, capacitors, transistors, diodes, inductors, conductors, etc. The flexible base material (or flexible substrate) may be a polymer layer.

[0008] In its simplest form, a FET fabricated on such a substrate includes a thin semiconductor layer on the substrate that functions as a channel region, conductive regions at either end of the channel region that function as a source and drain, a thin layer of insulating material on the channel region that functions as a gate dielectric, and a conductive material on the gate dielectric that functions as a gate electrode. Because of the physical properties of these FETs, they are commonly referred to as thin film transistors (TFTs).

[0009] Many different types of materials have been used for the thin semiconductor layer that serves as the channel region of TFTs, including amorphous silicon (α-Si), microcrystalline silicon (also called nanocrystalline silicon), which contains small crystals (typically on the order of a few nanometers) embedded in an amorphous matrix, and polycrystalline silicon (also called polysilicon or poly-Si), which is formed from silicon crystals of different orientations (typically on the order of 1 μm). α-Si has the advantage that high-quality, large-area α-Si films can be fabricated relatively inexpensively at low temperatures (e.g., using plasma-enhanced chemical vapor deposition (PECVD)). Hydrogenated α-Si:H TFTs can also exhibit relatively low off-state currents, making them particularly well suited for use as pixel switches in imaging arrays. α-Si has relatively low carrier mobility, limiting its use in applications such as high-speed switching. When fabricated correctly, microcrystalline silicon is generally more stable than α-Si:H, has better mobility than α-Si:H, and can be deposited relatively inexpensively using methods similar to α-Si. Polysilicon is characterized by very high charge carrier mobility and is much more stable than α-Si (but much lower than crystalline silicon), making it suitable for fabricating highly complex and high-speed TFT-based electronic circuits.

[0010] One method of forming polysilicon involves solid-phase crystallization of a deposited layer of amorphous silicon by thermal annealing the amorphous silicon (traditionally above 900°C), causing crystals to form in various orientations by nucleation and growth. However, many types of substrates on which it is desirable to form TFTs cannot withstand such high temperatures, so techniques have been developed to form polysilicon for such TFTs at much lower temperatures (<~650°C, or even lower in the case of flexible polymer-based substrates). Polycrystalline silicon formed in this manner is known in the art as low-temperature polycrystalline silicon (LTPS). Formation of LTPS typically involves, for example, deposition of α-Si at relatively low temperatures (<~400°C), followed by crystallization into polysilicon using an excimer (gas) or blue (diode) laser with no (or only minimal) heating of the substrate.

[0011] LTPS is relatively expensive and difficult to scale due to the need for laser annealing, but TFTs fabricated using LTPS tend to have superior on-currents, meaning that smaller TFTs with lower parasitic capacitance can be used. Higher currents and lower parasitic capacitance both contribute to faster switching.

[0012] In recent years, n-type "semiconductor oxide-based" TFTs have been developed that use indium gallium zinc oxide (IGZO) as the active layer. IGZO is an oxide-based semiconductor material consisting of a form of zinc oxide (ZnO) doped with indium and gallium. This material allows it to be deposited in a uniform amorphous phase on temperature-sensitive substrates while maintaining the oxide's relatively high carrier mobility (typically 20–50 times that of α-Si). Oxide-based technology also offers the significant advantage of extremely low off-state current compared to both α-Si:H and LTPS. However, while n-type oxide (e.g., IGZO)-based TFTs are promising, p-type oxide (e.g., copper(I) oxide (CuO), tin monoxide (SnO), or nickel oxide (NiO)) TFTs with comparable or sufficient performance and TFT stability have yet to be realized. This means that oxide-based TFTs are not suitable for applications requiring circuitry containing complementary n-type and p-type TFTs (known as complementary metal-oxide semiconductor or "CMOS").

[0013] It can thus be seen that various different techniques for implementing TFT-based ICs have various different problems associated with them, and none of them is ideal. Accordingly, there is a need for alternative techniques for implementing TFT-based ICs, and related apparatus and / or devices, that at least partially address or ameliorate one or more of the above-mentioned conflicting problems. Summary of the Invention

[0014] The present invention aims to provide a method and apparatus / device that contributes at least in part to meeting the above needs.

[0015] Aspects of the invention are set out in the accompanying independent claims, and other optional but advantageous features are set out in the accompanying dependent claims.

[0016] In one example described herein, an integrated circuit (IC) is provided that includes at least one p-type thin film transistor "TFT" formed on a substrate and at least one further electronic device, wherein the at least one p-type TFT includes a channel region formed from at least partially crystalline silicon, and the partially crystalline silicon is formed from amorphous silicon using a process that maintains the substrate at a temperature below 650°C, and the channel region of the at least one p-type TFT is formed from at least partially crystalline silicon having a charge carrier mobility within the range of 1 to 40 cm 2 / V·s.

[0017] In one example described herein, an integrated circuit (IC) is provided that includes at least one p-type thin film transistor "TFT" fabricated on a substrate and at least one further electronic device, wherein the at least one p-type TFT includes a channel region formed from at least partially crystalline silicon, and the partially crystalline silicon is formed from amorphous silicon using a process that maintains the substrate at a temperature below 650°C, and the at least one further electronic device includes at least one n-type TFT, and the at least one n-type TFT includes a channel region formed from a semiconductor oxide.

[0018] The at least one further electronic device may include at least one n-type TFT, and the at least one n-type TFT may include a channel region formed from a semiconductor oxide.

[0019] The channel region of the at least one p-type TFT may be formed from at least partially crystalline silicon having a charge carrier mobility within a range of 1 to 20 times, optionally within a range of 1 to 15 times, 1 to 10 times, or 1 to 5 times, the charge carrier mobility of the semiconductor oxide from which the channel region of the at least one n-type TFT is formed. The at least one p-type TFT may have a first channel length and the at least one n-type TFT may have a second channel length. The first channel length may be greater than the second channel length. The first channel length may be greater than 1 μm and the second channel length may be less than 1 μm. The second channel length may be less than 0.6 μm. The channel length of the at least one p-type TFT or the first channel length may be between 0.05 μm and 0.6 μm.

[0020] The first and second channel lengths may be mutually configured to ensure that the minimum of a first maximum drain-source current for a given gate voltage magnitude for the p-type device and a second maximum drain-source current for the n-type device is within 25% of the maximum of the first and second maximum drain-source currents. The first and second channel lengths may be mutually configured to ensure that the second maximum drain-source current is the same as or greater than the second maximum drain-source current.

[0021] The at least one p-type TFT may have a p-type TFT gate insulator and the at least one n-type TFT may have an n-type TFT gate insulator formed from a different insulator layer than the first gate insulator. The p-type TFT gate insulator may have a first thickness and the n-type TFT gate insulator may have a second thickness different from the first thickness. The first thickness and the second thickness may be mutually configured to ensure that a minimum value of a first parasitic capacitance associated with the p-type TFT gate insulator and a second parasitic capacitance associated with the n-type TFT gate insulator is within 20% of a maximum value of the first parasitic capacitance and the second parasitic capacitance.

[0022] The p-type TFT first gate insulator may be a first material having a first dielectric constant and the n-type TFT gate insulator may be a second material having a second dielectric constant different from the first dielectric constant. The first material may have a first dielectric constant and the second material may have a second dielectric constant, and the first and second dielectric constants may be mutually configured to ensure that a minimum of a first parasitic capacitance associated with the p-type TFT gate insulator and a second parasitic capacitance associated with the n-type TFT gate insulator is within 20% of a maximum of the first and second parasitic capacitances.

[0023] The at least one further electronic device may comprise at least one resistor formed from a semiconductor oxide that forms part of a common fabrication layer with the semiconductor oxide in which the channel region of the n-type TFT is formed.

[0024] The at least one p-type TFT and the at least one n-type TFT may have their respective gate insulators formed from the same insulator layer. The at least one semiconductor oxide in which the channel region of the n-type TFT is formed may be provided directly on the substrate or on a barrier layer formed directly on the substrate. The at least one semiconductor oxide in which the channel region of the n-type TFT is formed may be formed on an insulator layer provided between the substrate and the at least one semiconductor oxide. The source and drain regions of the at least one n-type TFT may be formed from the at least one semiconductor oxide at either end of the channel region. The source and drain regions of the at least one n-type TFT may be formed from respective regions of the at least one semiconductor oxide, which have been irradiated with electromagnetic radiation to change the electrical properties of the regions of the at least one semiconductor oxide and make them conductive. The at least one semiconductor oxide may be a metal oxide semiconductor. The at least one semiconductor oxide may be indium gallium zinc oxide (IGZO).

[0025] The at least one p-type thin film transistor "TFT" and the at least one n-type thin film transistor are interconnected to form a circuit comprising at least one complementary metal oxide semiconductor "CMOS" circuit. The at least one CMOS circuit may comprise at least one CMOS inverter circuit. The at least partially crystalline silicon in which the channel region of the p-type TFT is formed may be formed directly on the substrate or on a barrier layer formed directly on the substrate. Source and drain regions of the at least one p-type TFT may be formed from the at least partially crystalline silicon at either end of the channel region. The source and drain regions of the at least one p-type TFT may be formed from respective regions of the at least partially crystalline silicon that have been irradiated with electromagnetic radiation to change the partial crystalline silicon electrical properties of those regions of the at least partially crystalline silicon, making them more conductive. The source and drain regions of the at least one p-type TFT may be formed from respective regions of the at least partially crystalline silicon, the regions being doped to change the electrical properties of the at least partially crystalline silicon to make the regions of the at least partially crystalline silicon more conductive. The at least partially crystalline silicon may include polycrystalline silicon. The polycrystalline silicon may be low-temperature polycrystalline silicon (LTPS). The at least partially crystalline silicon may be formed from amorphous silicon using a laser. The at least partially crystalline silicon may be formed from amorphous silicon using an excimer laser, a blue light-emitting diode (LED), or a blue solid-state laser.

[0026] The at least one further electronic device may comprise at least one resistor. The at least one resistor may include at least one resistor formed from at least partially crystalline silicon. The at least one resistor may include at least one resistor formed from at least partially crystalline silicon forming part of a common fabrication layer with the at least partially crystalline silicon in which the channel region of the at least one p-type TFT is formed. The at least one resistor may include at least one resistor formed from a semiconductor oxide material.

[0027] The at least one further electronic device may comprise at least one capacitor having a first capacitor plate, a second plate formed of a metal, and a capacitor insulator disposed between the first and second capacitor plates. The at least one capacitor may comprise at least one capacitor in which the first capacitor plate is formed of a semiconductor material and the second plate is formed of a metallic material. The first capacitor plate may be formed of at least partially crystalline silicon of the same type as the at least partially crystalline silicon in which the channel region of the at least one p-type TFT is formed. The at least one capacitor may comprise at least one capacitor in which the first capacitor plate and the second capacitor plate are each formed of a respective metallic material.

[0028] The substrate may be a flexible substrate. The substrate may be made of polyimide. The substrate may be a rigid substrate. The substrate may be made of glass. A barrier layer may be formed on the substrate.

[0029] In one example described in this specification, a method of manufacturing an integrated circuit (IC) includes providing a substrate and manufacturing the IC on the substrate, the IC including at least one p-type thin film transistor "TFT" and at least one further electronic device, the method of at least one p-type TFT including forming a first layer, the first layer including amorphous silicon, maintaining the substrate at a temperature below 650 °C, treating the first layer to convert the amorphous silicon to at least partially crystalline silicon, patterning the first layer before or after the conversion to at least partially crystalline silicon to form at least one semiconductor region, and manufacturing the at least one p-type TFT, the channel region of the at least one p-type TFT being formed from the at least partially crystalline silicon of the at least one semiconductor region, the step of treating the first layer being configured to produce at least partially crystalline silicon in the at least one semiconductor region that forms the channel region of the at least one p-type TFT having a charge carrier mobility within the range of 1 to 40 cm 2 / V·s when the at least one p-type TFT is manufactured.

[0030] In one example described herein, a method of manufacturing an integrated circuit (IC) is provided, comprising providing a substrate and fabricating the IC on the substrate, the IC comprising at least one p-type thin film transistor "TFT" and at least one further electronic device, the at least one p-type TFT comprising: forming a first layer, the first layer comprising amorphous silicon; treating the first layer to convert the amorphous silicon to at least partially crystalline silicon using a process that maintains the substrate at a temperature less than 650° C.; and patterning the first layer, before or after the conversion to at least partially crystalline silicon, to form at least one semiconductor region. and fabricating the at least one p-type TFT, wherein a channel region of the at least one p-type TFT is formed from the at least partially crystalline silicon of the at least one semiconductor region; and the at least one further electronic device comprises an n-type TFT, the at least one n-type TFT being fabricated by forming a second layer, the second layer comprising a semiconductor oxide, and patterning the second layer to form at least one semiconductor oxide region; and fabricating the at least one n-type TFT, wherein a channel region of the at least one n-type TFT is formed from the semiconductor oxide of the at least one semiconductor oxide region.

[0031] The at least one further electronic device may comprise an n-type TFT, wherein the at least one n-type TFT is fabricated by: forming a second layer, the second layer comprising a semiconductor oxide; patterning the second layer to form at least one semiconductor oxide region; and fabricating the at least one n-type TFT, wherein a channel region of the at least one n-type TFT is formed from the semiconductor oxide of the at least one semiconductor oxide region.

[0032] The treating of the first layer may be configured to produce partially crystalline silicon in the at least one semiconductor region forming the channel region of the at least one p-type TFT having a charge carrier mobility in the range of 1 to 20 times, optionally in the range of 1 to 15 times, in the range of 1 to 10 times, or in the range of 1 to 5 times that of the semiconductor oxide in which the channel region of the at least one n-type TFT is formed.

[0033] The at least one p-type thin film transistor "TFT" and the at least one n-type thin film transistor may be interconnected to form a circuit comprising at least one complementary metal oxide semiconductor "CMOS" circuit, which may comprise at least one CMOS inverter circuit.

[0034] In one example described herein, a method for manufacturing an integrated circuit (IC) is provided, comprising providing a substrate and fabricating any IC on the substrate from multiple layers as described above. [Brief explanation of the drawings]

[0035] Examples of various integrated circuits and associated manufacturing processes will now be described, by way of example only, with reference to the accompanying drawings, in which: [Figures 1A-1F] 1A-1F illustrate a method for fabricating an integrated electronic circuit comprising a low-temperature polysilicon (LTPS) p-type thin-film transistor (TFT) combined with a resistor. [Figures 2A-2F] 2A-2F show a method for manufacturing an integrated electronic circuit comprising an LTPSp-type TFT combined with a first type n-type TFT. [Figures 3A-3F] 3A-3F show a method for manufacturing an integrated electronic circuit comprising an LTPSp TFT combined with a first type of capacitor. [Figures 4A-4F] 4A-4F show a method for manufacturing an integrated electronic circuit comprising an LTPSp-type TFT combined with an n-type TFT of a second type. [Figures 5A-5E]5A-5E show a method for manufacturing an integrated electronic circuit comprising an LTPSp TFT combined with a second type of capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0036] overview 1A-1F, 2A-2F, 3A-3F, 4A-4F, and 5A-5E illustrate several different manufacturing processes that may be used in the fabrication of one or more integrated circuits (ICs). Each of the exemplary manufacturing processes illustrated in the figures relates to providing an electronic circuit comprising a p-type (also known as a "p-channel") thin-film transistor (TFT) having a channel region formed using low-temperature polysilicon (LTPS), in combination with at least one other electronic component (e.g., a resistor, another TFT, a capacitor, etc.). For ease of explanation, such TFTs will be referred to herein as LTPSTFTs.

[0037] As one skilled in the art will readily appreciate, while the different processes and associated combinations of electronic components are shown separately for clarity of explanation, it will be understood that the various processes may be integrated into a single manufacturing process to form more complex integrated circuits including any desired combination of one or more p-type TFTs with one or more other electronic components (e.g., one or more resistors of the same or different type, one or more n-type (or "n-channel") TFTs of the same or different type, one or more capacitors of the same or different type, etc.) It will also be understood, as one skilled in the art will readily appreciate, that the various processes may be integrated to provide multiple, essentially separate integrated circuits (e.g., for providing different, complementary functions) as part of a single IC chip.

[0038] 1A-1F illustrate a method for fabricating an integrated electronic circuit comprising an LTPS p-type TFT in combination with a resistor. Beneficially, as described in more detail below, the resistor is formed from the same source material (polysilicon) as the channel (and source and drain) regions of the p-type TFT, thereby providing a simple, low-cost fabrication procedure involving relatively few steps. It will be appreciated that resistors are basic electronic circuit components that can be used as building blocks in many different electronic circuits performing many different functions.

[0039] 2A-2F illustrate a method for fabricating an integrated electronic circuit comprising an LTPS p-type TFT in combination with a first type n-type TFT. Beneficially, as described in more detail below, the first type n-type TFT is a semiconductor oxide-based TFT (formed using indium gallium zinc oxide (IGZO) in the illustrated example). Also, somewhat counterintuitively, LTPS is intentionally formed to have a lower carrier mobility than currently possible with LTPS (and thus relatively close to that of the channel region of the n-type TFT), thereby enabling the fabrication of complementary p-type and n-type TFTs with similar properties (e.g., for the purposes of providing CMOS-based electronic circuits). It will be appreciated that there are many different electronic circuits that could benefit from the ability to fabricate such complementary p-type and n-type TFTs (i.e., CMOS).

[0040] 3A-3F illustrate a method for fabricating an integrated electronic circuit comprising an LTPS p-type TFT in combination with a first type of capacitor. Beneficially, as described in more detail below, the first type of capacitor is formed as a semiconductor-insulator-metal capacitor (SIMCap) in which the semiconductor forms one of the capacitor's contact "plates" and is fabricated from the same source material (LTPS polysilicon) as the channel (and source and drain) regions of the p-type TFT, thereby providing a simple, low-cost fabrication procedure involving relatively few steps. It will be appreciated that capacitors are basic electronic circuit components that can be used as building blocks in many different electronic circuits performing many different functions.

[0041] 4A-4F illustrate a method for fabricating an integrated electronic circuit comprising an LTPSp-type TFT in combination with a second-type n-type TFT. Beneficially, as described in more detail below, the second-type n-type TFT is another semiconductor oxide-based TFT (formed using indium gallium zinc oxide (IGZO) in the illustrated example). However, unlike the first-type n-type TFT, the second-type TFT does not share the same gate dielectric as the LTPSp-type TFT. This allows for independent control of the thickness of each TFT's respective gate dielectric (and / or possibly the use of different materials with different dielectric constants), and therefore independent control of at least some of the electrical properties associated with the gate dielectric (e.g., turn-on voltage and / or capacitance associated with the gate dielectric), for example, to balance the properties of different transistor types. Also, somewhat counterintuitively, as with the first type of complementary TFT, LTPS is intentionally formed to have a carrier mobility lower than that currently possible with LTPS (and therefore relatively close to that of the channel region of an n-type TFT), thereby making it possible to fabricate complementary p-type and n-type TFTs with similar properties (e.g., for the purposes of providing CMOS-based electronic circuits). It will be appreciated that there are many different electronic circuits that could benefit from the ability to fabricate such complementary p-type and n-type TFTs (i.e., CMOS).

[0042] 5A-5E illustrate a method for fabricating an integrated electronic circuit comprising an LTPS p-type TFT in combination with a third-type n-type TFT and a second-type capacitor. Beneficially, as described in more detail below, the third-type n-type TFT is another semiconductor oxide-based TFT (formed using indium gallium zinc oxide (IGZO) in the illustrated example). Like the second-type n-type TFT, the third-type TFT does not share the same gate dielectric as the LTPS p-type TFT, thereby allowing independent control of the thickness and / or material of each gate dielectric. Also, somewhat counterintuitively, like the first-type complementary TFT, LTPS is intentionally formed to have lower carrier mobilities than currently possible with LTPS (and thus relatively close to those of the channel region of the n-type TFT), thereby enabling the fabrication of complementary p-type and n-type TFTs with similar properties (e.g., for the purpose of providing CMOS-based electronic circuits). It will be appreciated that there are many different electronic circuits that could benefit from the ability to create such complementary p-type and n-type TFTs (ie, CMOS).

[0043] Beneficially, the second type of capacitor in this example is formed as a metal-insulator-metal capacitor (MIMCap), with the insulator of the capacitor also forming the gate dielectric of the third type of n-type TFT. It will be appreciated that capacitors are basic electronic circuit components that can be used as building blocks in many different electronic circuits performing many different functions.

[0044] Thus, in summary, the various examples described herein demonstrate how a simplified low-temperature polysilicon (LTPS) process can be used to form p-type TFTs in combination with several different devices. This process can be combined with processes for forming semiconductor oxide-based n-type TFTs (e.g., formed from IGZO, etc.), thereby beneficially supporting the fabrication of complementary devices arranged to form CMOS-based circuits, such as CMOS inverters (and other circuits using complementary devices), on flexible substrates as part of flexible integrated circuits (e.g., FlexICs, etc.). However, it will be appreciated that the described process is not limited to flexible substrates and can be used to form ICs with CMOS-based or other circuits on rigid substrates, such as glass, or any other rigid substrate. It will also be appreciated that the disclosed technology has a wide range of potential applications, such as displays, product packaging, medical devices, etc.

[0045] In particular, by fabricating p-type TFTs from what are considered "low-performance" LTPS layers with carrier mobilities relatively close to those exhibited by the semiconductor oxides used in any n-type TFT (e.g., within about an order of magnitude of each other), this technology ameliorates some of the problems typically associated with LTPS. The desired "low" carrier mobility can be achieved, for example, by annealing with a blue LED or blue laser diode and / or by using plasma-based doping. At the same time, the relatively low mobility enables the formation of p-type LTPSTFTs and n-type semiconductor oxide-based TFTs of similar size (e.g., within about an order of magnitude of each other) with similar performance characteristics. Thus, ICs formed using the disclosed technology can take advantage of the low off-current offered by n-type semiconductor oxide-based TFTs while still retaining the ability to fabricate CMOS-based circuits (and other circuits using complementary devices).

[0046] The charge mobility (or "charge carrier mobility" or "mobility") of LTPS used in p-type TFTs is, for example, about 1 to 200 cm, depending on the charge mobility of the semiconducting oxide used in n-type TFTs. 2 / V·s (for example, within a 10% tolerance), but preferably close to that of the channel region of the n-type TFT (for example, about 1 to 40 cm 2 / V·s - within a tolerance of, for example, 10%. The charge mobility of LTPS is, for example, 1.5 to 39 cm 2 / V·s, 2~38cm 2 / V·s, 2.5~37cm 2 / V·s, 3~36cm 2 / V·s, 3.5~35.5cm 2 / V·s, 4~35cm 2 / V·s, 4.5~35cm 2 / V·s, 5~34cm 2 / V·s, 5.5~33cm 2 / V·s, 6~32cm 2 / V·s, 6.5~31cm 2 / V·s, 7~30cm 2 / V·s, 7.5~29cm 2 / V·s, 8~28cm 2 / V·s, 8.5~27cm 2 / V·s, 9~26cm 2 / V·s, 9.5~25cm 2 / V·s, 10~24cm 2 / V·s, or 11~23cm 2 / V·s, for example, 1 to 40 cm 2 / V·s charge mobility.

[0047] The charge mobility of LTPS can be, for example, a factor of 1 to 20 times that of the semiconductor oxide used in n-type TFTs. For example, the charge mobility of LTPS can be 2 to 19 times, 3 to 18 times, 4 to 17 times, 5 to 16 times, 6 to 15 times, 7 to 14 times, 8 to 13 times, 9 to 12 times, or 10 to 11 times that of the semiconductor oxide used in n-type TFTs. The charge mobility of LTPS can be 1 to 15 times that of the semiconductor oxide used in n-type TFTs. For example, the charge mobility of LTPS can be 2 to 14 times, 3 to 13 times, 4 to 12 times, 5 to 11 times, 6 to 10 times, or 7 to 9 times that of the semiconductor oxide used in n-type TFTs. The charge mobility of LTPS can be 1 to 10 times that of the semiconductor oxide used in n-type TFTs. For example, the charge mobility of LTPS may be 2 to 9 times, 3 to 8 times, 4 to 7 times, or 5 to 6 times that of the semiconductor oxide used in n-type TFTs. The charge mobility of LTPS may be 1 to 5 times that of the semiconductor oxide used in n-type TFTs. For example, the charge mobility of LTPS may be 1.5 to 4.5 times, 2 to 4 times, or 2.5 to 3.5 times that of the semiconductor oxide used in n-type TFTs.

[0048] As will be explained in more detail, using the techniques introduced above and described in more detail below, it is possible to integrate a relatively small semiconductor oxide (e.g., IGZO) based n-type TFT (e.g., where the n-type TFT has a channel length between 0.1 μm and 5 μm, such as between 0.2 μm and 1 μm, or between 0.3 μm and 0.6 μm) with a larger LTPS based p-type TFT. Low mobility of semiconductor oxides (>50 cm for LTPS) 2 / V·s, compared to typically ~10 cm 2 / V s), Reduce and / or offset the differential effects of parasitic capacitance, and / or offsetting differences in gate insulator capacitance; It has been proven to be useful.

[0049] In other words, it can be seen that CMOS capability with reasonably balanced p-type and n-type devices can be achieved by leveraging the ability to fabricate semiconductor oxide (IGZO)-based devices at dimensions smaller than those typically achievable for LTPS (e.g., due to limitations in known LTPS fabrication techniques hindered by grain boundary limitations of the fabricated LTPS channel, which poses challenges to fabricating TFT channel lengths less than 1 μm when using the highest mobility LTPS that is generally preferred for improved device performance).

[0050] LTPS P-type TFT and LTPS resistor The method of manufacturing an integrated electronic circuit comprising an LTPSp TFT combined with a resistor, as introduced above, will now be described by way of example with reference to FIGS. 1A-1F, which show an IC generally formed at 100.

[0051] 1A, a substrate is first prepared. The substrate 103 can be formed from any suitable rigid or flexible material, but typically includes polyimide (PI) or glass. The substrate can be of any suitable thickness, for example, 700 μm glass or 1-500 μm polyimide.

[0052] A barrier layer (or "buffer layer" or "underlayer") may be deposited on the substrate 103 before the formation of electronic components begins. If a barrier layer is provided on the substrate (e.g., between the component devices and the substrate), the barrier layer may be, for example, a thin (e.g., ∼200 nm) silicon nitride (SiN x ) layer, and possibly a silicon dioxide (SiO2) interfacial layer (e.g., ~50 nm, etc.), although this is by way of example only and the barrier layer may include other materials as described below.

[0053] A blanket layer of amorphous silicon of appropriate thickness is deposited on the substrate 103 (or on the barrier layer) using any suitable deposition technique (e.g., physical vapor deposition (e.g., sputtering, pulsed laser, evaporation), chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)), coating (e.g., spin-on), and / or any other suitable process). The amorphous silicon layer can have a thickness of, for example, less than 200 nm (e.g., 20-30 nm, 50 nm, or 100 nm).

[0054] Next, the desired properties are determined, for example, by IGZO (typically 10 cm 2 / V s), e.g., the 1–40 cm mentioned above. 2 The amorphous silicon is crystallized to form LTPS with a mobility in the range of 1 / V·s. Crystallization is achieved using appropriate "low-temperature" techniques compatible with the requirements of the LTPS and the substrate being used. This can include, for example, annealing with a laser (e.g., an excimer (gas) laser or a blue solid-state (diode) laser) or a blue light-emitting diode (LED) or lamp, or, where appropriate, "low-temperature" thermal annealing. Deposition and / or crystallization conditions can be adjusted to help achieve the desired mobility. The amorphous silicon / LTPS may also be appropriately doped.

[0055] The LTPS layer is then patterned (e.g., using appropriate masks and photolithography techniques) to form a plurality of LTPS islands 101, 102. Each LTPS island 101, 102 can have the same or different dimensions. The first LTPS island 101 has dimensions (length / width / cross-sectional area) defined to allow for the fabrication of a p-type TFT having a channel region / channel with the required dimensions (e.g., channel length in the range of 1 to 20 μm). The second LTPS island 102 has dimensions (length / width / cross-sectional area) defined to allow for the fabrication of a resistor with the required resistance value.

[0056] 1B, a blanket insulator / dielectric layer 104 is subsequently deposited over the first LTPS island 101 and the second LTPS island 102, and the substrate 103. A portion of this insulator / dielectric layer 104 will ultimately form the gate dielectric of the p-type TFT. This insulator / dielectric layer 104 can be made of, for example, SiO2, HfO2, SiN x and / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The insulator / dielectric layer 104 may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a sub-layer of SiO2 and a SiN x wherein the thickness of each sub-layer may be the same or different.

[0057] 1C , a gate electrode 105 is formed over the first LTPS island 101 and on a portion of the insulator / dielectric layer 104 that covers the LTPS island 101. The gate electrode 105 is positioned in vertical alignment (in the orientation shown in FIG. 1C ) with the portion of the first LTPS island 101 that will ultimately form the channel region of the completed p-type TFT when completed. Similarly, the gate electrode 105 has dimensions (length / width / cross-sectional area) that correspond to the desired dimensions of the channel region of the completed p-type TFT when completed. However, while the gate-channel region alignment and corresponding dimensions allow the gate to be used essentially as a mask to define the channel region as part of a self-aligned process as described herein, it will be understood that in an alternative (non-self-aligned) method, the gate electrode may be formed later and instead a photoresist cap may be used in place of the gate material to mask the channel region.

[0058] The gate electrode 105 may be formed, for example, by first depositing a suitable layer of conductive material to a suitable thickness using any suitable deposition technique (e.g., by evaporation or sputtering). The conductive material may include, for example, a layer of metal (e.g., molybdenum (Mo)) having a thickness of, for example, 1200 Å. However, this is by way of example only, and the conductive layer may include other materials, as described below. The conductive material of the gate electrode is then patterned (e.g., using appropriate masks and photolithography techniques) to form the gate electrode 105.

[0059] Next, as shown in FIG. 1D, the structure is irradiated with electromagnetic radiation (e.g., ultraviolet (UV) light). The electromagnetic radiation converts any unshielded semiconducting LTPS to a form with higher conductivity (ohmic, e.g., ∼1 Ω / □). This conversion process may also contribute to the release of dopants from the surrounding material. The electromagnetic radiation is not stopped by the material of the dielectric layer 104, but is stopped by the material of the gate electrode 105. Thus, the region of the first (p-type TFT) LTPS island 101 directly under the gate electrode 105 is shielded from the electromagnetic radiation by the material of the gate electrode 105 and remains semiconducting. In contrast, the regions 106a and 106b of the first (p-type TFT) LTPS island 101 not directly under the gate electrode 105 are not shielded from the electromagnetic radiation and are converted. These conductive regions 106a and 106b will ultimately become the source and drain regions of the p-type TFT upon completion. Similarly, the second (resistive) LTPS island 102 can be transformed without being shielded from electromagnetic radiation, thus forming a resistor having a resistance value determined at least in part by the dimensions of the second (resistive) LTPS island 102.

[0060] As shown in FIG. 1E, following irradiation, the insulator / dielectric layer 104 is patterned and etched to form vias 108a, 108b, 108c, and 108d that extend through the insulator / dielectric layer 104 to provide electrical connection to the source and drain regions 106a, 106b (vias 108a and 108b) of the completed p-type TFT and to either end of the completed second (resistor) LTPS island 102, i.e., the completed LTPS resistor (vias 108c and 108d).

[0061] An etch stop layer 107 is formed (e.g., by depositing and patterning a suitable material) over the gate electrode 105 to provide protection during the subsequent metal etch. It will be appreciated that in an alternative (non-self-aligned) method, the gate electrode may not be formed at this stage, in which case no etch stop is required (although any mask used during irradiation would of course need to be removed).

[0062] Referring to FIG. 1F, a further layer of conductive material is deposited (e.g., by sputtering). The conductive material may include a metal (e.g., molybdenum (Mo)) layer having a thickness of, for example, 150 nm. However, this is merely an example, and the conductive layer may include other materials, as described below. The conductive material is then patterned (e.g., using appropriate masks and photolithography techniques) to form source and drain electrodes 109a and 109b for connection to source and drain regions 106a and 106b of the p-type TFT, respectively, through vias 108a and 108b, and resistor contacts / electrodes for connection to either end of second (resistor) LTPS island 102 (i.e., the completed LTPS resistor) through vias 108c and 108d. Etch stop layer 107 may then be removed. It will be understood that, in an alternative (non-self-aligned) method, a gate electrode may be formed at this stage.

[0063] It will be understood that in this process other metal features (tracking, capacitor plates, etc.) may be formed in the same layer, and this process may (optionally) be used to form the anode of a metal-semiconductor (Schottky) diode, if desired.

[0064] Thus, as shown in FIG. 1F, the integrated electronic circuit comprises an LTPSp TFT 110 combined with a resistor 111 .

[0065] Complementary LTPS P-type TFTs and semiconducting oxide-based N-type TFTs The method of manufacturing an integrated electronic circuit comprising an LTPS p-type TFT combined with a semiconducting oxide-based n-type TFT, as introduced above, will now be described by way of example with reference to Figures 2A-2F, which show an IC formed generally at 200.

[0066] 2A, a substrate 203 is first prepared. The substrate 203 can be formed from any suitable rigid or flexible material, but typically includes polyimide (PI) or glass. The substrate 203 can be of any suitable thickness, for example, 700 μm glass or 1 to 500 μm polyimide.

[0067] A barrier layer (or "buffer layer" or "underlayer") may be deposited on the substrate 203 before the formation of electronic components begins. If a barrier layer is provided on the substrate (e.g., between the component devices and the substrate), the barrier layer may be, for example, a thin (e.g., ∼200 nm) silicon nitride (SiN x ) layer, and possibly a silicon dioxide (SiO2) interfacial layer (e.g., ~50 nm, etc.), although this is by way of example only and the barrier layer may include other materials as described below.

[0068] A blanket layer of amorphous silicon of appropriate thickness is deposited on the substrate 203 (or on the barrier layer) using any suitable deposition technique (e.g., physical vapor deposition (e.g., sputtering, pulsed laser, evaporation), chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)), coating (e.g., spin-on), and / or any other suitable process). The amorphous silicon layer can have a thickness of, for example, less than 200 nm (e.g., 20-30 nm, 50 nm, or 100 nm).

[0069] Next, the desired properties are determined, for example, by IGZO (typically 10 cm 2 / V s), e.g., the 1–40 cm mentioned above. 2 The amorphous silicon is crystallized to form LTPS with a mobility in the range of 1 / V·s. Crystallization is achieved using appropriate "low-temperature" techniques compatible with the requirements of the LTPS and the substrate being used. This can include, for example, annealing with a laser (e.g., an excimer (gas) laser or a blue solid-state (diode) laser) or a blue light-emitting diode (LED) or lamp, or, where appropriate, "low-temperature" thermal annealing. Deposition and / or crystallization conditions can be adjusted to help achieve the desired mobility. The amorphous silicon / LTPS may also be appropriately doped.

[0070] The LTPS layer is then patterned (e.g., using an appropriate mask and photolithography techniques) to form one or more LTPS islands 201. The LTPS islands 201 include at least one LTPS island 201 having dimensions (length / width / cross-sectional area) defined to enable the fabrication of a p-type TFT having a channel region / channel with the required dimensions (e.g., channel length in the region of 1-20 μm).

[0071] A layer of semiconductor oxide (e.g., IGZO) suitable for forming the channel region of a semiconductor oxide-based n-type TFT is then deposited (e.g., using a suitable deposition technique, such as reactive sputtering) to an appropriate thickness (e.g., about 20 nm) and patterned (e.g., using a suitable mask and photolithography techniques) to form one or more semiconductor oxide islands 202 suitable for forming the channel region of the n-type TFT. At least one semiconductor oxide island 202 has dimensions (length / width / cross-sectional area) defined to enable the fabrication of an n-type TFT having a channel region / channel with the required dimensions (e.g., a channel length of 0.1 μm to 5 μm, such as 0.2 μm to 1 μm or 0.3 μm to 0.6 μm). It will be understood that the LTPS island 201 and the semiconductor oxide island 202 may have the same dimensions, but the dimensions of the LTPS island 201 may differ from the dimensions of the semiconductor oxide island 202. In particular, the relative dimensions of the islands 201, 202 can be designed to produce p-type and n-type TFTs with similar performance characteristics, particularly taking into account the difference in mobility between LTPS and semiconductor oxides (e.g., IGZO).

[0072] Although not shown, it will be understood that one or more LTPS-based resistors can be fabricated in parallel (e.g., from one or more additional LTPS islands) as described above with respect to Figures 1A-1F. Similarly, one or more semiconductor oxide-based resistors can be fabricated in parallel in much the same manner as described for the LTPS-based resistors with respect to Figures 1A-1F, but starting with one or more semiconductor oxide islands as opposed to LTPS islands.

[0073] 2B, a blanket insulator / dielectric layer 204 is subsequently deposited over the LTPS and semiconductor oxide islands 201 and 202 and the substrate 203. A portion of this insulator / dielectric layer 204 will ultimately form the gate dielectric for the p-type TFT, and another portion of this insulator / dielectric layer 204 will ultimately form the gate dielectric for the n-type TFT. This insulator / dielectric layer 204 can be made of, for example, SiO2, HfO2, SiN xand / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The insulator / dielectric layer 204 may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a sub-layer of SiO2 and a SiN x wherein the thickness of each sub-layer may be the same or different.

[0074] 2C, each gate electrode 205a, 205b is formed across the LTPS island 201 for the p-type TFT and the semiconductor oxide island 202 for the n-type TFT, respectively, on the respective portion of the insulator / dielectric layer 204 covering each island. Each gate electrode 205a, 205b is positioned in vertical alignment (in the orientation shown in FIG. 2C) with the portion of the corresponding island 201, 202 that will ultimately form the channel region of the corresponding completed p-type or n-type TFT, respectively. Similarly, each gate electrode 205a, 205b has dimensions (length / width / cross-sectional area) that correspond to the desired dimensions of the channel region of the corresponding completed p-type or n-type TFT, respectively, when completed. However, although the alignment and corresponding dimensions of the gate-channel regions allow each gate to be used essentially as a mask to define a corresponding channel region as part of a self-aligned process as described herein, it will be understood that in an alternative (non-self-aligned) method, the gate electrode may be formed later and instead a photoresist cap may be used in place of the gate material to mask the channel region.

[0075] The gate electrodes 205 a, 205 b may be formed, for example, by first depositing a suitable layer of conductive material to a suitable thickness using any suitable deposition technique (e.g., by evaporation or sputtering). The conductive material may include, for example, a layer of metal (e.g., molybdenum (Mo)) having a thickness of, for example, 1200 Å. However, this is by way of example only, and the conductive layer may include other materials, as described below. The conductive material of the gate electrodes is then patterned (e.g., using appropriate masks and photolithography techniques) to form the gate electrodes.

[0076] Next, as shown in FIG. 2D, the structure is irradiated with electromagnetic radiation (e.g., ultraviolet (UV) light). The electromagnetic radiation converts any unshielded semiconducting LTPS and any unshielded semiconducting oxide to a form with higher conductivity (ohmic, e.g., ∼1 Ω / □). This conversion process may also be contributed to by the release of dopants from the surrounding materials. The electromagnetic radiation is not stopped by the material of the dielectric layer 204, but by the material of the gate electrodes 205a and 205b. Thus, the region of the LTPS island 201 directly under the gate electrode 205a for the p-type TFT is shielded from the electromagnetic radiation by the material of that gate electrode 205a and remains in a semiconducting state. Similarly, the region of the semiconducting oxide island 202 directly under the gate electrode 205b for the n-type TFT is shielded from the electromagnetic radiation by the material of that gate electrode 205b and remains in a semiconducting state.

[0077] In contrast, regions 206a and 206b of LTPS island 201 for the p-type TFT that are not directly under corresponding gate electrode 205a are converted without being shielded from electromagnetic radiation. These conductive regions 206a and 206b will ultimately become the source and drain regions of the p-type TFT when completed. Similarly, regions 206c and 206d of semiconductor oxide island 202 for the n-type TFT that are not directly under corresponding gate electrode 205b are converted without being shielded from electromagnetic radiation. These conductive regions 206c and 206d will ultimately become the source and drain regions of the n-type TFT when completed.

[0078] As shown in FIG. 2E, following irradiation, insulator / dielectric layer 204 is patterned and etched to form vias 208a, 208b, 208c, and 208d that extend through insulator / dielectric layer 204 to provide electrical connection to source and drain regions 206a, 206b (vias 208a and 208b) of the completed p-type TFT and to source and drain regions 206c, 206d (vias 208c and 208d) of the completed n-type TFT.

[0079] A respective etch stop layer portion 207 a, 207 b is formed over each of the gate electrodes 205 a, 205 b (e.g., by depositing and patterning a suitable material) to provide protection during the subsequent metal etch. It will be appreciated that in an alternative (non-self-aligned) method, the gate electrodes may not be formed at this stage, in which case no etch stop is required (although any mask used during irradiation would of course need to be removed).

[0080] Referring to FIG. 2F, a further layer of conductive material is deposited (e.g., by sputtering). The conductive material may include a metal (e.g., molybdenum (Mo)) layer having a thickness of, for example, 150 nm. However, this is merely an example, and the conductive layer may include other materials, as described below. The conductive material is then patterned (e.g., using appropriate masks and photolithography techniques) to form source and drain electrodes 209a and 209b for connecting to source and drain regions 206a and 206b of the p-type TFT, respectively, through vias 208a and 208b, and source and drain electrodes 209c and 209d for connecting to source and drain regions 206c and 206d of the n-type TFT, respectively, through vias 208c and 208d. Etch stop layer portions 207a and 207b may then be removed. It will be understood that, in an alternative (non-self-aligned) manner, gate electrodes may be formed at this stage.

[0081] It will be understood that in this process other metal features (tracking, capacitor plates, etc.) may be formed in the same layer, and this process may (optionally) be used to form the anode of a metal-semiconductor (Schottky) diode, if desired.

[0082] Thus, as shown in FIG. 2F, the integrated electronic circuit comprises an LTPSp-type TFT 210 combined with a semiconducting oxide-based n-type TFT 211 .

[0083] LTPS P-type TFT and SIMCap A method for manufacturing an integrated electronic circuit comprising an LTPSp TFT combined with a capacitor of the first type introduced above will now be described by way of example with reference to Figures 3A to 3F, which show an IC formed generally at 300.

[0084] Referring to Figure 3A, a substrate is first prepared. The substrate 303 can be formed from any suitable rigid or flexible material, but typically includes polyimide (PI) or glass. The substrate can be of any suitable thickness, for example, 700 μm glass or 1-500 μm polyimide.

[0085] A barrier layer (or "buffer layer" or "underlayer") may be deposited on the substrate 303 before the formation of electronic components begins. If a barrier layer is provided on the substrate (e.g., between the component devices and the substrate), the barrier layer may be, for example, a thin (e.g., ∼200 nm) silicon nitride (SiN x ) layer, and possibly a silicon dioxide (SiO2) interfacial layer (e.g., ~50 nm, etc.), although this is by way of example only and the barrier layer may include other materials as described below.

[0086] A blanket layer of amorphous silicon of appropriate thickness is deposited on the substrate 303 (or on the barrier layer) using any suitable deposition technique (e.g., physical vapor deposition (e.g., sputtering, pulsed laser, evaporation), chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)), coating (e.g., spin-on), and / or any other suitable process). The amorphous silicon layer can have a thickness of, for example, less than 200 nm (e.g., 20-30 nm, 50 nm, or 100 nm).

[0087] Next, the desired properties are determined, for example, by IGZO (typically 10 cm 2 / V s), e.g., the 1–40 cm mentioned above. 2The amorphous silicon is crystallized to form LTPS with a conductivity in the range of 1 / V·s. Crystallization is achieved using appropriate "low-temperature" techniques compatible with the requirements of the LTPS and the substrate being used. This can include, for example, annealing with a laser (e.g., an excimer (gas) laser or a blue solid-state (diode) laser) or a blue light-emitting diode (LED) or lamp, or, where appropriate, "low-temperature" thermal annealing. Deposition and / or crystallization conditions can be adjusted to help achieve the desired mobility. The amorphous silicon / LTPS may also be appropriately doped.

[0088] The LTPS layer is then patterned (e.g., using appropriate masks and photolithography techniques) to form multiple LTPS islands 301, 302. Each LTPS island 301, 302 can have the same or different dimensions. The first LTPS island 301 has dimensions (length / width / cross-sectional area) defined to enable the fabrication of a p-type TFT having a channel region / channel with the required dimensions (e.g., channel length in the 1-20 μm range). The second LTPS island 302 has dimensions (length / width / cross-sectional area) defined to enable the second LTPS island 302 to form one plate of a capacitor with the required capacitance.

[0089] 3B, a blanket insulator / dielectric layer 304 is subsequently deposited over the first and second LTPS islands 301 and 302 and the substrate 303. A portion of this insulator / dielectric layer 304 will ultimately form the gate dielectric of the p-type TFT. This insulator / dielectric layer 304 can be made of, for example, SiO2, HfO2, SiN xand / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The insulator / dielectric layer 304 may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a SiO2 sub-layer and a SiNx sub-layer, and the thicknesses of each sub-layer may be the same or different.

[0090] Referring to Figure 3C, a gate electrode 305 is formed over a first LTPS island 301 and on a portion of the insulator / dielectric layer 304 that covers the LTPS island 301. The gate electrode 305 is positioned in vertical alignment (in the orientation shown in Figure 3C) with the portion of the first LTPS island 301 that will ultimately form the channel region of the completed p-type TFT when completed. Similarly, the gate electrode 305 has dimensions (length / width / cross-sectional area) that correspond to the desired dimensions of the channel region of the completed p-type TFT when completed. However, while the gate-channel region alignment and corresponding dimensions allow the gate to be used essentially as a mask to define the channel region as part of a self-aligned process as described herein, it will be understood that in an alternative (non-self-aligned) method, the gate electrode may be formed later and instead a photoresist cap may be used in place of the gate material to mask the channel region.

[0091] The gate electrode 305 may be formed, for example, by first depositing a suitable layer of conductive material to a suitable thickness using any suitable deposition technique (e.g., by evaporation or sputtering). The conductive material may include, for example, a layer of metal (e.g., molybdenum (Mo)) having a thickness of, for example, 1200 Å. However, this is by way of example only, and the conductive layer may include other materials, as described below. The conductive material of the gate electrode is then patterned (e.g., using appropriate masks and photolithography techniques) to form the gate electrode.

[0092] Next, as shown in FIG. 3D, the structure is irradiated with electromagnetic radiation (e.g., ultraviolet (UV) light). The electromagnetic radiation converts the unshielded semiconducting LTPS to a form with higher conductivity (ohmic, e.g., ∼1 Ω / □). This conversion process may also be contributed to by the release of dopants from the surrounding materials. The electromagnetic radiation is not stopped by the material of the dielectric layer 304, but by the material of the gate electrode 305. Thus, the region of the first (p-type TFT) LTPS island 301 directly under the gate electrode 305 is shielded from the electromagnetic radiation by the material of the gate electrode 305 and remains semiconducting. In contrast, regions 306a and 306b of the first (p-type TFT) LTPS island 301 not directly under the gate electrode 305 are not shielded from the electromagnetic radiation and are converted. These conductive regions 306a and 306b will ultimately become the source and drain regions of the p-type TFT upon completion. Similarly, the second (capacitor plate) LTPS island 302 can be transformed without being shielded from electromagnetic radiation, thus forming the first ("lower") capacitor plate of a capacitor having a capacitance determined at least in part by the dimensions of the second (capacitor plate) LTPS island 302.

[0093] As shown in FIG. 3E, following irradiation, the insulator / dielectric layer 304 is patterned and etched to form vias 308a, 308b, and 308d that extend through the insulator / dielectric layer 304 to provide electrical connection to the source and drain regions 306a, 306b (vias 308a and 308b) of the completed p-type TFT, and to the second (capacitor plate) LTPS island 302, i.e., the first (“lower”) capacitor plate (via 308d).

[0094] An etch stop layer 307 is formed (e.g., by depositing and patterning a suitable material) over the gate electrode 305 to provide protection during the subsequent metal etch. It will be appreciated that in an alternative (non-self-aligned) method, the gate electrode may not be formed at this stage, in which case no etch stop is required (although any mask used during irradiation would of course need to be removed).

[0095] 3F, a further layer of conductive material is deposited (e.g., by sputtering). The conductive material may include, for example, a metal (e.g., molybdenum (Mo)) layer having a thickness of, for example, 150 nm. However, this is by way of example only, and the conductive layer may include other materials, as described below. The conductive material is then patterned (e.g., using appropriate masks and photolithography techniques) to form source and drain electrodes 309a and 309b for connecting to source and drain regions 306a and 306b of the p-type TFT, respectively, through vias 308a and 308b; a first capacitor contact / electrode 309d for connecting to the second (capacitor plate) LTPS island 302, i.e., the first ("lower") capacitor plate (through via 308d); a second ("upper" or "top") capacitor plate 309e vertically aligned (in the orientation shown in FIG. 3F ) with the first ("lower") capacitor plate formed by the second LTPS island 302; and a second capacitor contact / electrode 309c for connecting to the second ("upper" or "top") capacitor plate 309e. The etch stop layer 307 may then be removed. It will be understood that, in an alternative (non-self-aligned) manner, a gate electrode may be formed at this stage.

[0096] It will be understood that in this process other metal features (tracking, capacitor plates, etc.) may be formed in the same layer, and this process may (optionally) be used to form the anode of a metal-semiconductor (Schottky) diode, if desired.

[0097] Thus, as shown in FIG. 3F, the integrated electronic circuit comprises an LTPSp TFT 310 combined with a capacitor 311 of the SIMCap type.

[0098] Complementary LTPS P-type TFTs and semiconducting oxide-based N-type TFTs with different dielectrics The method of manufacturing an integrated electronic circuit comprising an LTPS p-type TFT combined with a semiconducting oxide-based n-type TFT, where the n-type TFT does not share the same gate dielectric as the LTPS p-type TFT, introduced above, will now be described by way of example with reference to Figures 4A-4F, which show an IC formed generally at 400.

[0099] 4A, a substrate 403 is first prepared. The substrate 403 can be formed from any suitable rigid or flexible material, but typically includes polyimide (PI) or glass. The substrate 403 can be of any suitable thickness, for example, 700 μm glass or 1 to 500 μm polyimide.

[0100] A barrier layer (or "buffer layer" or "underlayer") may be deposited on the substrate 403 before the formation of electronic components begins. If a barrier layer is provided on the substrate (e.g., between the component devices and the substrate), the barrier layer may be, for example, a thin (e.g., ∼200 nm) silicon nitride (SiN x ) layer, and possibly a silicon dioxide (SiO2) interfacial layer (e.g., ~50 nm, etc.), although this is by way of example only and the barrier layer may include other materials as described below.

[0101] A blanket layer of amorphous silicon of appropriate thickness is deposited on the substrate 403 (or on the barrier layer) using any suitable deposition technique (e.g., physical vapor deposition (e.g., sputtering, pulsed laser, evaporation), chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)), coating (e.g., spin-on), and / or any other suitable process). The amorphous silicon layer can have a thickness of, for example, less than 200 nm (e.g., 20-30 nm, 50 nm, or 100 nm).

[0102] Next, the desired properties are determined, for example, by IGZO (typically 10 cm 2 / V s), e.g., the 1–40 cm mentioned above. 2 The amorphous silicon is crystallized to form LTPS with a mobility in the range of 1 / V·s. Crystallization is achieved using appropriate "low-temperature" techniques compatible with the requirements of the LTPS and the substrate being used. This can include, for example, annealing with a laser (e.g., an excimer (gas) laser or a blue solid-state (diode) laser) or a blue light-emitting diode (LED) or lamp, or, where appropriate, "low-temperature" thermal annealing. Deposition and / or crystallization conditions can be adjusted to help achieve the desired mobility. The amorphous silicon / LTPS may also be appropriately doped.

[0103] The LTPS layer is then patterned (e.g., using appropriate masks and photolithography techniques) to form one or more LTPS islands 401. The LTPS island 401 includes at least one LTPS island 401 having dimensions (length / width / cross-sectional area) defined to enable fabrication of a p-type TFT having a channel region / channel with the required dimensions (e.g., channel length in the region of 1-20 μm). Although not shown, it will be understood that one or more LTPS-based resistors can be fabricated in parallel (e.g., from one or more additional LTPS islands) as described above with respect to FIGS. 1A-1F. Similarly, one or more SIMCaps can be fabricated in parallel (e.g., from one or more additional LTPS islands) as described above with respect to FIGS. 2A-2F.

[0104] A first insulator / dielectric layer 404a is then deposited covering the LTPS island 401 and the substrate 403. A portion of this insulator / dielectric layer 404a will eventually form the gate dielectric of the p-type TFT. This insulator / dielectric layer 404a can be made of, for example, SiO2, HfO2, SiN xand / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The insulator / dielectric layer 404a may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a sub-layer of SiO2 and a SiN x wherein the thickness of each sub-layer may be the same or different.

[0105] Referring to FIG. 4B, a layer of semiconductor oxide (e.g., IGZO) suitable for forming the channel region of a semiconductor oxide-based n-type TFT is deposited (e.g., using a suitable deposition technique, such as reactive sputtering) to an appropriate thickness (e.g., about 20 nm) and patterned (e.g., using a suitable mask and photolithography techniques) to form one or more semiconductor oxide islands 402 suitable for forming the channel region of an n-type TFT. At least one semiconductor oxide island 402 has dimensions (length / width / cross-sectional area) defined to enable fabrication of an n-type TFT having a channel region / channel with the required dimensions (e.g., a channel length of 0.1 μm to 5 μm, such as 0.2 μm to 1 μm or 0.3 μm to 0.6 μm). It will be understood that the LTPS island 401 and the semiconductor oxide island 402 may have the same dimensions, but the dimensions of the LTPS island 401 may differ from the dimensions of the semiconductor oxide island 402. In particular, the relative dimensions of the islands 401, 402 can be designed to produce p-type and n-type TFTs with similar performance characteristics, particularly taking into account the difference in mobility between LTPS and semiconductor oxides (e.g., IGZO).

[0106] It will be appreciated that one or more semiconductor oxide-based resistors may be fabricated in parallel in much the same manner as described for the LTPS-based resistor with respect to Figures 1A-1F, but starting with one or more additional semiconductor oxide islands formed on the first insulator / dielectric layer 404a, as opposed to LTPS islands formed on the substrate 403.

[0107] A second insulator / dielectric layer 404b is subsequently deposited over the semiconductor oxide island 402 and the previously formed first insulator / dielectric layer 404. A portion of this second insulator / dielectric layer 404b will ultimately form the gate dielectric of the n-type TFT. This second insulator / dielectric layer 404b can be made of, for example, SiO2, HfO2, SiN x and / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The second insulator / dielectric layer 404b may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a sub-layer of SiO2 and a SiN x The first insulating / dielectric layer 404a and the second insulating / dielectric layer 404b may have different thicknesses and / or may be formed of different materials.

[0108] The relationship between the thickness of the portion of the second insulator / dielectric layer 404b that ultimately forms the gate dielectric for the n-type TFT and the thickness of the portion of the first insulator / dielectric layer 404a that ultimately forms the gate dielectric for the p-type TFT may be configured to result in similar parasitic gate dielectric capacitances for the n-type and p-type TFTs (e.g., minimum values ​​within 20% (or more preferably within 15% or 10%) of maximum values) even when their respective channel lengths are different. It will be appreciated, however, that this similarity in the relationship between the parasitic gate dielectric capacitances may be achieved by using different dielectrics having different dielectric constants in conjunction with (or instead of) the gate dielectric thicknesses.

[0109] The second insulating / dielectric layer 404b is then patterned and etched (e.g., using appropriate masks and photolithographic techniques) to expose the first insulating / dielectric layer 404a over the area where the p-type TFT is formed (i.e., over the LTPS island 401 and surrounding areas), and possibly over any LTPS islands for forming resistors and / or SIMCaps as described above.

[0110] Referring to FIG. 4C , each gate electrode 405 a and 405 b is formed over the LTPS island 401 for the p-type TFT and the semiconductor oxide island 402 for the n-type TFT. Each gate electrode 405 a and 405 b is formed on the corresponding portion of the first insulator / dielectric layer 404 a or second insulator / dielectric layer 404 b that overlies the island. Each gate electrode 405 a, 405 b is positioned in vertical alignment (as oriented in FIG. 4C ) with the portion of the corresponding island 401, 402 that will ultimately form the channel region of the corresponding completed p-type or n-type TFT. Similarly, each gate electrode 405 a, 405 b has dimensions (length / width / cross-sectional area) that correspond to the desired dimensions of the channel region of the corresponding completed p-type or n-type TFT. However, although the alignment and corresponding dimensions of the gate-channel regions allow each gate to be used essentially as a mask to define a corresponding channel region as part of a self-aligned process as described herein, it will be understood that in an alternative (non-self-aligned) method, the gate electrode may be formed later and instead a photoresist cap may be used in place of the gate material to mask the channel region.

[0111] The gate electrodes 405 a, 405 b may be formed, for example, by first depositing a suitable layer of conductive material to a suitable thickness using any suitable deposition technique (e.g., by evaporation or sputtering). The conductive material may include, for example, a layer of metal (e.g., molybdenum (Mo)) having a thickness of, for example, 1200 Å. However, this is by way of example only, and the conductive layer may include other materials, as described below. The conductive material of the gate electrodes is then patterned (e.g., using appropriate masks and photolithography techniques) to form the gate electrodes 405 a, 405 b.

[0112] Next, as shown in FIG. 4D, the structure is irradiated with electromagnetic radiation (e.g., ultraviolet (UV) light). The electromagnetic radiation converts any unshielded semiconducting LTPS and any unshielded semiconducting oxide to a form with higher conductivity (ohmic, e.g., ∼1 Ω / □). This conversion process may also be contributed to by the release of dopants from the surrounding materials. The electromagnetic radiation is not stopped by the material of dielectric layer 404a, but by the material of gate electrodes 405a and 405b. Thus, the region of LTPS island 401 directly under gate electrode 405a for the p-type TFT is shielded from electromagnetic radiation by the material of gate electrode 405a and remains semiconducting. Similarly, the region of semiconducting oxide island 402 directly under gate electrode 405b for the n-type TFT is shielded from electromagnetic radiation by the material of gate electrode 405b and remains semiconducting.

[0113] In contrast, regions 406a and 406b of the LTPS island 401 for the p-type TFT that are not directly under the corresponding gate electrode 405a are converted without being shielded from electromagnetic radiation. These conductive regions 406a and 406b will ultimately become the source and drain regions of the p-type TFT when completed. Similarly, regions 406c and 406d of the semiconductor oxide island 402 for the n-type TFT that are not directly under the corresponding gate electrode 405b are converted without being shielded from electromagnetic radiation. These conductive regions 406c and 406d will ultimately become the source and drain regions of the n-type TFT when completed.

[0114] As shown in FIG. 4E, following irradiation, the dielectric layers 404a and 404b are patterned and etched to form vias 408a, 408b through the first insulator / dielectric layer 404a and vias 408c, 408d through the second insulator / dielectric layer 404b, providing electrical connection to the source and drain regions 406a, 406b (vias 408a and 408b) of the completed p-type TFT and to the source and drain regions 406c, 406d (vias 408c and 408d) of the completed n-type TFT.

[0115] A respective etch stop layer portion 407 a, 407 b is formed (e.g., by depositing and patterning an appropriate material) over each of the gate electrodes 405 a, 405 b to provide protection during a subsequent metal etch. It will be appreciated that in an alternative (non-self-aligned) method, the gate electrodes may not be formed at this stage, in which case no etch stop is required (although any mask used during irradiation would of course need to be removed).

[0116] Referring to FIG. 4F, a further layer of conductive material is deposited (e.g., by sputtering). The conductive material may include, for example, a metal (e.g., molybdenum (Mo)) layer having a thickness of, for example, 150 nm. However, this is merely an example, and the conductive layer may include other materials, as described below. The conductive material is then patterned (e.g., using appropriate masks and photolithography techniques) to form source and drain electrodes 409a and 409b for connecting to source and drain regions 406a and 406b of the p-type TFT, respectively, through vias 408a and 408b, and source and drain electrodes 409c and 409d for connecting to source and drain regions 406c and 406d of the n-type TFT, respectively, through vias 408c and 408d. Etch stop layer portions 407a and 407b may then be removed. It will be understood that, in an alternative (non-self-aligned) manner, gate electrodes may be formed at this stage.

[0117] It will be understood that in this process other metal features (tracking, capacitor plates, etc.) may be formed in the same layer, and this process may (optionally) be used to form the anode of a metal-semiconductor (Schottky) diode, if desired.

[0118] Thus, as shown in FIG. 4F, an integrated electronic circuit comprises an LTPS p-type TFT 410 combined with a semiconducting oxide-based n-type TFT 411 that does not share the same gate dielectric as the p-type TFT 410.

[0119] Complementary LTPS P-type TFTs and semiconducting oxide-based N-type TFTs with MIMCap The method of manufacturing an integrated electronic circuit comprising an LTPSp-type TFT combined with a semiconductor oxide-based n-type TFT and a MIMCap, as introduced above, will now be described by way of example with reference to Figures 5A-5E, which show an IC formed generally at 500.

[0120] 5A, a substrate 503 is first prepared. The substrate 503 can be formed from any suitable rigid or flexible material, but typically includes polyimide (PI) or glass. The substrate 503 can be of any suitable thickness, for example, 700 μm glass or 1 to 500 μm polyimide.

[0121] A barrier layer (or "buffer layer" or "underlayer") may be deposited on the substrate 503 before the formation of electronic components begins. If a barrier layer is provided on the substrate (e.g., between the component devices and the substrate), the barrier layer may be, for example, a thin (e.g., ∼200 nm) silicon nitride (SiN x ) layer, and possibly a silicon dioxide (SiO2) interfacial layer (e.g., ~50 nm, etc.), although this is by way of example only and the barrier layer may include other materials as described below.

[0122] A blanket layer of amorphous silicon of appropriate thickness is deposited on the substrate 503 (or on the barrier layer) using any suitable deposition technique (e.g., physical vapor deposition (e.g., sputtering, pulsed laser, evaporation), chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)), coating (e.g., spin-on), and / or any other suitable process). The amorphous silicon layer can have a thickness of, for example, less than 200 nm (e.g., 20-30 nm, 50 nm, or 100 nm).

[0123] Next, the desired properties are determined, for example, by IGZO (typically 10 cm 2 / V s), e.g., the 1–40 cm mentioned above. 2The amorphous silicon is crystallized to form LTPS with a mobility in the range of 1 / V·s. Crystallization is achieved using appropriate "low-temperature" techniques compatible with the requirements of the LTPS and the substrate being used. This can include, for example, annealing with a laser (e.g., an excimer (gas) laser or a blue solid-state (diode) laser) or a blue light-emitting diode (LED) or lamp, or, where appropriate, "low-temperature" thermal annealing. Deposition and / or crystallization conditions can be adjusted to help achieve the desired mobility. The amorphous silicon / LTPS may also be appropriately doped.

[0124] The LTPS layer is then patterned (e.g., using appropriate masks and photolithography techniques) to form one or more LTPS islands 501. The LTPS island 501 includes at least one LTPS island 501 having dimensions (length / width / cross-sectional area) defined to enable fabrication of a p-type TFT having a channel region / channel with the required dimensions (e.g., channel length in the region of 1-20 μm). Although not shown, it will be understood that one or more LTPS-based resistors can be fabricated in parallel (e.g., from one or more additional LTPS islands) as described above with respect to FIGS. 1A-1F. Similarly, one or more SIMCaps can be fabricated in parallel (e.g., from one or more additional LTPS islands) as described above with respect to FIGS. 2A-2F.

[0125] A first insulator / dielectric layer 504a is then deposited covering the LTPS island 501 and the substrate 503. A portion of this insulator / dielectric layer 504a will eventually form the gate dielectric of the p-type TFT. This insulator / dielectric layer 504a can be made of, for example, SiO2, HfO2, SiN xand / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The insulator / dielectric layer 504a may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a sub-layer of SiO2 and a SiN x wherein the thickness of each sub-layer may be the same or different.

[0126] Referring to FIG. 5B, a layer of semiconductor oxide (e.g., IGZO) suitable for forming the channel region of a semiconductor oxide-based n-type TFT is deposited (e.g., using a suitable deposition technique, such as reactive sputtering) to an appropriate thickness (e.g., about 20 nm) and patterned (e.g., using a suitable mask and photolithography techniques) to form one or more semiconductor oxide islands 502 suitable for forming the channel region of an n-type TFT. At least one semiconductor oxide island 502 has dimensions (length / width / cross-sectional area) defined to enable fabrication of an n-type TFT having a channel region / channel with the required dimensions (e.g., a channel length of 0.1 μm to 5 μm, such as 0.2 μm to 1 μm, or 0.3 μm to 0.6 μm). It will be understood that the LTPS island 501 and the semiconductor oxide island 502 may have the same dimensions, but the dimensions of the LTPS island 501 may differ from the dimensions of the semiconductor oxide island 502. In particular, the relative dimensions of the islands 501, 502 can be designed to produce p-type and n-type TFTs with similar performance characteristics, particularly taking into account the difference in mobility between LTPS and semiconductor oxides (e.g., IGZO).

[0127] One or more semiconductor oxide-based resistors may be fabricated in parallel in much the same manner as described for the LTPS-based resistor with respect to FIGS. 1A-1F, but it will be understood that starting with one or more additional semiconductor oxide islands formed on the first insulator / dielectric layer 504a, as opposed to LTPS islands formed on the substrate 503.

[0128] At this stage, as shown in Figures 5D and 5E, several electrodes 505a, 509c, 509d, 513 are also formed (ie, earlier than the process of Figures 4A-4F).

[0129] Electrodes 505a, 509c, 509d, 513 include a gate electrode 505a for a p-type TFT formed over the LTPS island 501 for the p-type TFT on top of the portion of the first insulator / dielectric layer 504a that covers the LTPS island 501. The gate electrode 505a for the p-type TFT is positioned in vertical alignment (in the orientation shown in FIG. 5B ) with the portion of the LTPS island 501 for the p-type TFT that will ultimately form the channel region of the completed p-type TFT when completed. Similarly, the gate electrode 505a for the p-type TFT has dimensions (length / width / cross-sectional area) that correspond to the desired dimensions of the channel region of the completed p-type TFT when completed.

[0130] Additionally, electrodes 505a, 509c, 509d, 513 include a source electrode 509c and a drain electrode 509d for the n-type TFT formed on respective portions of first insulator / dielectric layer 504a (and on respective ends of semiconductor oxide island 502) at (and overlapping with) either end of semiconductor oxide island 502 for the n-type TFT.

[0131] Together, electrodes 505a, 509c, 509d, 513 comprise a first capacitor electrode 513 for forming a first ("lower") capacitor plate of MIMCap 512 (shown only in FIG. 5E).

[0132] The electrodes 505a, 509c, 509d, 513 may be formed, for example, by first depositing a suitable layer of conductive material to a suitable thickness using any suitable deposition technique (e.g., by evaporation or sputtering). The conductive material may include, for example, a layer of metal (e.g., molybdenum (Mo)) having a thickness of, for example, 1200 Å. However, this is by way of example only, and the conductive layer may include other materials, as described below. The conductive material of the gate electrode is then patterned (e.g., using appropriate masks and photolithography techniques) to form the gate electrode.

[0133] 5C, a second insulator / dielectric layer 504' is subsequently deposited over the semiconductor oxide island 502, the previously formed first insulator / dielectric layer 504a, and the previously formed electrodes 505a, 509c, 509d, 513. Portions of this second insulator / dielectric layer 504b will ultimately form the gate dielectric of the n-type TFT and the capacitor dielectric of the MIMCap 512 (shown only in FIG. 5E). This second insulator / dielectric layer 504b may be made of, for example, SiO2, HfO2, SiN x and / or an Al2O3 layer (or any suitable combination thereof). However, these are just a few examples, and the insulator / dielectric layer may include other materials as described below. The second insulator / dielectric layer 504b may be of any suitable thickness depending on the material; for example, the dielectric layer may have a thickness of 100-1200 Å. The dielectric layer may also include a sub-layer of SiO2 and a SiN x The first insulating / dielectric layer 504a and the second insulating / dielectric layer 504b may include sub-layers, each of which may have the same or different thickness. The first insulating / dielectric layer 504a and the second insulating / dielectric layer 504b may have different thicknesses and / or may be formed of different materials.

[0134] The relationship between the thickness of the portion of the second insulator / dielectric layer 504b that ultimately forms the gate dielectric for the n-type TFT and the thickness of the portion of the first insulator / dielectric layer 504a that ultimately forms the gate dielectric for the p-type TFT may be configured to result in similar parasitic gate dielectric capacitances for the n-type and p-type TFTs (e.g., minimum values ​​within 20% (or more preferably within 15% or 10%) of maximum values) even when their respective channel lengths are different. It will be appreciated, however, that this similarity in the relationship between the parasitic gate dielectric capacitances may be achieved by using different dielectrics having different dielectric constants in conjunction with (or instead of) the gate dielectric thicknesses.

[0135] The second insulator / dielectric layer 504b is then patterned and etched (e.g., using appropriate masks and photolithography techniques) to form an etch stop layer and vias 508a, 508b through both the first insulator / dielectric layer 504a and the second insulator / dielectric layer 504b, which, when completed, provide electrical connection to the source and drain regions of the p-type TFT. It will be understood that forming the vias 508a, 508b may include patterning (e.g., using a mask and appropriate photolithography techniques) and then etching the second insulator / dielectric layer 504b, and then using the patterned second insulator / dielectric layer 504b as a mask to etch the first insulator / dielectric layer 504a.

[0136] Next, the structure is irradiated with electromagnetic radiation (e.g., ultraviolet (UV) light), as shown in FIG. 5D. In this example, the electromagnetic radiation is configured, e.g., by appropriate wavelength selection, to convert any unshielded semiconducting LTPS to a form with higher conductivity (ohmic, e.g., ∼1 Ω / □), but not any unshielded semiconducting oxide. For example, the irradiation wavelength can be selected such that the electrical properties of the LTPS are altered by irradiation, but not the semiconducting oxide material. For example, metal oxide semiconductors such as IGZO are substantially transparent at wavelengths greater than ∼300 nm, whereas the electrical properties of crystallized amorphous silicon are affected by UV irradiation at wavelengths of 300 nm or greater. In one example, irradiation from a green laser, e.g., having a wavelength of 532 nm, can be used.

[0137] The conversion process may also contribute to the release of dopants from the surrounding material. Electromagnetic radiation is not stopped by the material of the dielectric layer 504a, but is stopped by the material of the gate electrode 505a of the p-type TFT. Therefore, the region of the LTPS island 501 directly under the gate electrode 505a for the p-type TFT is shielded from electromagnetic radiation by the material of that gate electrode 505a and remains semiconducting.

[0138] In contrast, regions 506a and 506b of the LTPS island 501 for the p-type TFT that are not directly under the corresponding gate electrode 505a are not shielded from electromagnetic radiation but are converted. These conductive regions 506a and 506b will ultimately become the source and drain regions of the p-type TFT when completed. In this example, the semiconductor oxide island 502 for the n-type is not shielded from electromagnetic radiation but is not converted by the selected electromagnetic radiation.

[0139] As shown in FIG. 5E, following irradiation, a further layer of conductive material is deposited (e.g., by sputtering). The conductive material may include, for example, a layer of metal (e.g., molybdenum (Mo)) having a thickness of, for example, 150 nm. However, this is merely an example, and the conductive layer may include other materials, as described below. The conductive material is then patterned (e.g., using appropriate masks and photolithography techniques) to form source and drain electrodes 509a and 509b for connecting to source and drain regions 506a and 506b of the p-type TFT, respectively, through vias 508a and 508b, a gate electrode 505b for the n-type TFT, and a second capacitor electrode 505c for forming the second (“upper” or “top”) capacitor plate of MIMCap 512.

[0140] It will be appreciated that during this step, other metal features (tracking, capacitor plates, etc.) may be formed in the same layer. This step may also (optionally) be used to form the anodes of metal-semiconductor (Schottky) diodes, if desired. Those skilled in the art will appreciate that connections to previously formed electrodes 505a, 509c, 509d, 513 may be provided by removing second insulator / dielectric layer 504b at appropriate locations (e.g., using a mask and appropriate photolithography techniques).

[0141] Thus, as shown in FIG. 5E, the integrated electronic circuit comprises an LTPS p-type TFT 510 combined with a semiconducting oxide-based n-type TFT 511 that does not share the same gate dielectric as the p-type TFT 510 and MIMCap 512.

[0142] Example scenario As mentioned above, using the techniques introduced above and described in more detail below, integrating a relatively small semiconductor oxide (e.g., IGZO) based n-type TFT (e.g., <0.6 μm channel length) with a larger LTPS based p-type TFT (e.g., ∼1 μm channel length) can overcome the lower mobility of the semiconductor oxide (e.g., >50 cm for LTPS).2 / V·s, typically ~10 cm 2 / V·s), reducing and / or offsetting the differential effects of parasitic capacitance, and / or offsetting differences in gate insulator capacitance. However, it should be understood that these mobilities, and those listed in the various scenarios below, are examples to help illustrate how the ability to integrate smaller semiconductor oxide n-type TFTs with larger LTPS p-type TFTs (whose minimum size is limited by grain size) can provide advantages in terms of balancing device performance and reducing undesirable parasitic effects. In practice, both LTPS and IGZO can have a wide range of carrier mobilities. For example, LTPS typically has much higher mobility, but can be fabricated with lower mobility (as discussed above) by design to help balance CMOS device performance and / or reduce parasitic effects. IGZO may have even lower charge mobility in some cases.

[0143] These advantages are further illustrated by way of example with reference to several simplified hypothetical scenarios. Each scenario involves a CMOS pairing of an IGZO-based TFT with an LTPS p-type TFT. The charge carrier mobility of the IGZO forming the n-type TFT is 10 cm (e.g., at a gate voltage of 3 V). 2 / V·s, while the charge carrier mobility of the LTPS forming the p-type TFT is assumed to be 50 cm (for example, at a gate voltage of −3 V). 2 It is assumed that the σ is / V·s.

[0144] In these scenarios, the gate insulator (C ox The parasitic load of the gate oxide scaling factor (proportional to the parasitic capacitance associated with the gate oxide), the maximum drain-source current (I max ) maximum current (I max ) scaling factor, and C ox I against maxPerformance is measured by referring to three parameters:

[0145] As will be appreciated by those skilled in the art, in general, for circuit applications requiring complementary p-type and n-type TFTs (e.g., CMOS-based inverters), the parasitic gate oxide scaling factor load should be similar (ideally the same) for each TFT. Additionally, lower values ​​of the parasitic gate oxide scaling factor load are beneficial.

[0146] As will be appreciated by those skilled in the art, generally, for circuit applications requiring complementary p-type and n-type TFTs (e.g., CMOS), I max The scaling factor should be similar (ideally the same) for each TFT. max Higher values ​​of the scaling factor are advantageous (i.e., higher I max However, if the p-type and n-type TFTs have different values, the I max The higher the value of the scaling factor (i.e., the higher the I max It is preferred to have a value of

[0147] As will be appreciated by those skilled in the art, generally, for circuit applications requiring complementary p-type and n-type TFTs (e.g., CMOS), C ox I against max The ratio of C should be similar (ideally the same) for each TFT. ox I against max The higher the ratio, the more advantageous it is.

[0148] Scenario 1 In the first scenario, the dimensions of the IGZO n-type TFT and the LTPS p-type TFT are the same, as shown in Table 1. The gate insulators of the IGZO n-type TFT and the LTPS p-type TFT are made of the same material and have the same thickness. This scenario can occur, for example, when both TFTs share a gate insulator layer. JPEG2025538644000002.jpg72170

[0149] As shown in Table 1, the parasitic loads of the gate oxide scaling factors of the two TFTs are the same and well balanced. However, the I max The scaling factor is 20% of that of p-type TFT, and C ox vs. I max The ratio is 20% of the p-type TFT.

[0150] Therefore, in this scenario, the IGZOn TFT max It can be seen that the inverter performance is limited by the "inferior" IGZO n-type TFT configuration, since

[0151] Scenario 2 In the second scenario, as shown in Table 2, the area of ​​the IGZOn TFT is five times that of the LTPS p-TFT because the IGZO n-TFT has a channel width (i.e., width-to-length ratio) that is five times that of the LTPS p-TFT. The gate insulators of the IGZOn TFT and the LTPS p-TFT are made of the same material and have the same thickness. This scenario can occur, for example, when both TFTs share a gate insulator layer. JPEG2025538644000003.jpg72170

[0152] As shown in Table 2, in this scenario, the I max The scaling factors are the same and balanced. However, the parasitic load of the gate oxide scaling factor of the n-type TFT is five times that of the p-type TFT, and the C ox vs. I maxThe ratio is 20% of the p-type TFT.

[0153] Therefore, in this scenario, the width-to-length ratio of the lower mobility "inferior" IGZOn TFT is set to the I of the two TFTs (as in the conventional approach). max When scaling up to match the scaling factor and balancing the configuration, the inverter performance is limited by the "inferior" IGZO n-TFT due to the higher parasitic load of the gate oxide scaling factor on the IGZO n-TFT.

[0154] Scenario 3 In the third scenario, the dimensions of the IGZOn TFT and the LTPS p-type TFT are the same, as shown in Table 3. However, the gate insulators of the IGZO n-type TFT and the LTPS p-type TFT are made of different materials, and the gate insulator of the IGZOn TFT has a dielectric constant (k) twice that of the LTPS p-type TFT. The thickness of the gate insulator of the LTPS p-type TFT is assumed to be larger than that of the IGZOn TFT due to the use of a low-k SiOx material. This scenario can occur, for example, when both TFTs do not share a gate insulator layer. JPEG2025538644000004.jpg72170

[0155] As shown in Table 3, in this scenario, the I max The scaling factors are the same and balanced. However, I max The scaling factor is lower than that in Scenario 2. The parasitic load on the gate oxide scaling factor of the n-type TFT is five times that of the p-type TFT, and the C ox vs. I max The ratio is 20% of the p-type TFT.

[0156] Therefore, in this scenario, the LTPSp TFT has a thicker, lower dielectric constant (k) insulator (SiOx) (commonly used in LTPS TFTs). However, in this scenario, the inverter performance is still limited by the "inferior" IGZO n-TFT due to the higher parasitic load of the gate oxide scaling factor of the IGZO n-TFT. Furthermore, the inverter performance is affected by the lower I of the LTPSp TFT. max Limited by the scaling factor.

[0157] Scenario 4 In the fourth scenario, as shown in Table 4, the area of ​​the IGZO n-type TFT is 20% of the area of ​​the LTPS p-type TFT because the IGZO n-type TFT has a channel length that is 20% of the LTPS p-type TFT. The gate insulators of the IGZO n-type TFT and the LTPS p-type TFT are made of the same material and have the same thickness. This scenario can occur, for example, when both TFTs share a gate insulator layer. JPEG2025538644000005.jpg72170

[0158] As shown in Table 4, in this scenario, the I max The scaling factors are the same, well balanced, and significantly higher than in the previous scenario. The parasitic load on the gate oxide scaling factor for p-type TFTs is 20% of that for p-type TFTs, and C for n-type TFTs. ox vs. I max The ratio is five times that of p-type TFTs.

[0159] Therefore, in this scenario, we take advantage of the ability to scale the size of the IGZO n-type TFT down compared to the LTPS p-type TFT to ensure that inverter performance is no longer limited by the low-mobility IGZO n-type TFT. Thus, in this case, it is the parasitic loading of the LTPS p-type TFT that is the limiting factor, and the IGZO n-type TFT is no longer the bottleneck.

[0160] Scenario 5 In the fifth scenario, as shown in Table 5, the area of ​​the IGZOn TFT is 20% of the area of ​​the LTPS p-type TFT because the IGZO n-type TFT has a channel length that is 20% of that of the LTPS p-type TFT. However, the gate insulators of the IGZOn TFT and the LTPS p-type TFT are made of different materials, and the gate insulator of the IGZO n-type TFT has a dielectric constant (k) twice that of the LTPS p-type TFT. However, the gate insulating film thickness of the LTPS p-type TFT is the same as that of the IGZO n-type TFT. This scenario can occur, for example, when both TFTs do not share a gate insulating layer. JPEG2025538644000006.jpg72170

[0161] As shown in Table 5, in this scenario, the I max The scaling factor is twice that of p-type TFT. max The scaling factor is lower than in the previous scenario, but still relatively large. The parasitic load on the gate oxide scaling factor of the p-type TFT is 40% of that of the p-type TFT (so they are closer to each other). ox vs. I max The ratio is five times that of p-type TFTs.

[0162] Therefore, this scenario also takes advantage of the ability to scale the size of the IGZO n-TFT down compared to the LTPS p-TFT to ensure that inverter performance is no longer limited by the low-mobility IGZO n-TFT. Thus, in this case, it is the parasitic loading of the LTPS p-TFT that is the limiting factor, and the IGZO n-TFT is no longer the bottleneck.

[0163] Scenario 6 In the sixth scenario, as shown in Table 6, the area of ​​the IGZOn TFT is 20% of the area of ​​the LTPS p-type TFT because the IGZO n-type TFT has a channel length that is 20% of that of the LTPS p-type TFT. However, the gate insulators of the IGZOn TFT and the LTPS p-type TFT are formed of different materials, and the gate insulator of the IGZO n-type TFT has a dielectric constant (k) twice that of the LTPS p-type TFT. The thickness of the gate insulator of the LTPS p-type TFT is assumed to be greater than that of the IGZO n-type TFT because a low-k SiOx material is used. This scenario can occur, for example, when both TFTs do not share a gate insulator layer. JPEG2025538644000007.jpg72170

[0164] As shown in Table 6, the parasitic loads of the gate oxide scaling factors of the two TFTs are the same and balanced. However, in this scenario, the I max The scaling factor is 5 times that of p-type TFTs, and the I max The scaling factor is lower than in the previous scenario. ox vs. I max The ratio is five times that of p-type TFTs.

[0165] Therefore, this scenario also takes advantage of the ability to scale the size of the IGZO n-TFT down compared to the LTPS p-TFT to ensure that inverter performance is no longer limited by the low-mobility IGZO n-TFT. Thus, in this case, it is the parasitic loading of the LTPS p-TFT that is the limiting factor, and the IGZO n-TFT is no longer the bottleneck.

[0166] Scenario 7 In the seventh scenario, as shown in Table 7, the area of ​​the IGZOn TFT is 40% of the area of ​​the LTPS p-type TFT because the IGZO n-type TFT has a channel length that is 40% of that of the LTPS p-type TFT. The gate insulators of the IGZO n-type TFT and the LTPS p-type TFT are formed of different materials, and the gate insulator of the IGZOn TFT has a dielectric constant (k) twice that of the LTPS p-type TFT. The thickness of the gate insulator of the LTPS p-type TFT is assumed to be greater than that of the IGZO n-type TFT because a low-k SiOx material is used. This scenario can occur, for example, when both TFTs do not share a gate insulator layer. JPEG2025538644000008.jpg72170

[0167] As shown in Table 7, the parasitic loads of the gate oxide scaling factors of the two TFTs are the same and balanced. Also, in this scenario, the I max Although the scaling factor is higher than that of p-type TFTs, it is still close to that of p-type TFTs, so it is roughly balanced. ox vs. I max The ratio is close to that of p-type TFT. max The scaling factor is lower than in the previous scenario, but this is offset by the balance between the two devices.

[0168] Therefore, this scenario also takes advantage of the ability to scale the size of the IGZO n-TFT down compared to the LTPS p-TFT to ensure that inverter performance is no longer limited by the low-mobility IGZO On TFT. Thus, control of the IGZO On TFT dimensions (including gate insulator thickness) allows for a close match between the LTPS p-TFT and the IGZO n-TFT, rather than IGZO being the limiting factor.

[0169] Summary In summary, therefore, it can be seen that the ability to control the size (as well as thickness) of IGZO TFTs smaller than that of LTPS TFTs (the minimum size of which is limited by the grain size of LTPS) can be beneficially used to avoid limitations arising from the lower IGZO mobility and to help ensure balanced complementary TFTs despite differences in the underlying materials used to fabricate them.

[0170] The relationship between the channel region / channel dimensions (length and / or width) of an n-type TFT and the channel region / channel dimensions (length and / or width) of a p-type TFT is such that similar performance characteristics (e.g., maximum drain-source current I for a given magnitude of gate voltage) are achieved for the n-type and p-type TFTs. max ), for example, the minimum value being within 25% (or more preferably 20%, 15%, or 10%) of the maximum value. Also, the relationship between the dimensions (length and / or width) of the channel region / channel of the n-type TFT and the dimensions (length and / or width) of the channel region / channel of the p-type TFT may be configured to affect the performance characteristics of the n-type and p-type TFTs (e.g., the maximum drain-source current I for a given magnitude of gate voltage). max ) are not the same, the n-type TFT will have superior performance characteristics (e.g., maximum drain-source current I for a given gate voltage magnitude). max ) can be configured to ensure that the

[0171] Variations and Substitutions Detailed examples have been described above. Those skilled in the art will appreciate that many variations and alternatives may be made to the above examples while still benefiting from the improvements embodied therein.

[0172] For example, TFT channel lengths of <1 μm are difficult to achieve using higher-mobility LTPS, but lower-mobility LTPS has much smaller grains, thereby allowing smaller p-type TFTs to be fabricated (e.g., potentially with channel lengths between 0.05 μm and 0.6 μm). This can be used in the above example to help offset some of the performance loss resulting from using lower-mobility materials to help balance complementary TFTs. This allows, for example, n-type and p-type TFTs of similar dimensions to be fabricated from semiconductor oxide and LTPS materials, respectively, that have similar mobilities, provide similar performance, and exhibit similar parasitic effects (i.e., avoiding the need to use devices with different dimensions).

[0173] It will also be understood that, while the procedure described above processes the amorphous silicon layer to form LTPS before patterning, patterning could potentially occur while the silicon is still amorphous, and patterning could occur subsequently. Also, rather than depositing, crystallizing, and then patterning amorphous silicon, a variation could include depositing a blanket layer of amorphous silicon (which may then be crystallized), then depositing at least one blanket dielectric layer, and then patterning both of them using the same mask. This allows the top surface of the amorphous / polycrystalline silicon in the channel (i.e., the gate interface) to be pure (i.e., unaffected by the patterning process). An n-type material can then be deposited on the same substrate as the p-type material.

[0174] In accordance with the above description, it can be seen that there is provided an electronic circuit (IC) comprising a thin film transistor (TFT), the TFT being a p-type TFT and comprising a first semiconductor body fabricated from low temperature polysilicon (LTPS), which may include a channel region for forming a channel having a length of 0.5 to 20 μm.

[0175] The channel length can be 0.1 to 19.5 μm, for example, 0.15 to 18.5 μm, 0.2 to 18 μm, 0.25 to 17.5 μm, 0.3 to 17 μm, 0.35 to 16.5 μm, 0.4 to 16 μm, 0.45 to 15.5 μm, 0.5 to 15 μm, 0.55 to 14.5 μm, 0.6 to 14 μm, 0.65 to 13.5 μm, 0.7 to 13 μm, 0.75 to 12.5 μm, 0.8 to 12 μm, 0.85 to 11.5 μm, 0.9 to 11 μm, 0.95 to 10 μm, or 1 to 9.5 μm.

[0176] The channel length can be 0.05 to 9 μm, for example, 0.055 to 5 μm, 0.1 to 4.5 μm, 0.15 to 4 μm, 0.2 to 3.5 μm, 0.25 to 3 μm, 0.3 to 2.5 μm, 0.35 to 2 μm, or 0.4 to 1.5 μm. For example, the channel length can be 0.05 to 0.6 μm, for example, 0.1 to 0.55 μm, 0.15 to 0.5 μm, 0.2 to 0.45 μm, 0.25 to 0.4 μm, or 0.3 to 0.35 μm.

[0177] A p-type TFT may have a channel region and / or source and drain regions formed from doped LTPS. The doping may include, for example, one or more of phosphorus ions, BF ions, or any other dopant or doping ions known to those skilled in the art.

[0178] The channel region of a p-type TFT is 1 to 200 cm 2 / V·s charge carrier mobility.

[0179] The channel region of a p-type TFT is 0.5 to 500 cm 2 / V·s, e.g., 1.5 to 195 cm 2 / V·s, 2~190cm 2 / V·s, 2.5~185cm 2 / V·s, 3~180cm 2 / V·s, 3.5~175cm 2 / V·s, 4~170cm 2 / V·s, 5~165cm 2 / V·s, 5.5~160cm 2 / V·s, 6~155cm 2 / V·s, 6.5~150cm 2 / V·s, 7~145cm 2 / V·s, 7.5~140cm 2 / V·s, 8~135cm 2 / V·s, 8~130cm 2 / V·s, 8.5~125cm 2 / V·s, 9~120cm 2 / V·s, 9.5~115cm 2 / V·s, 10~110cm 2 / V·s, 10.5~105cm 2 / V·s, 11~100cm 2 / V·s, 11.5~95cm 2 / V·s, 12~90cm 2 / V·s, or 12.5~85cm 2 / V·s.

[0180] The charge carrier mobility of LTPS is 1 to 40 cm 2 / V·s, e.g., 1.5~39cm 2 / V·s, 2~38cm 2 / V·s, 2.5~37cm 2 / V·s, 3~36cm 2 / V·s, 3.5~35.5cm 2 / V·s, 4~35cm 2 / V·s, 4.5~35cm 2 / V·s, 5~34cm 2 / V·s, 5.5~33cm 2 / V·s, 6~32cm 2 / V·s, 6.5~31cm 2 / V·s, 7~30cm 2 / V·s, 7.5~29cm 2 / V·s, 8~28cm 2 / V·s, 8.5~27cm 2 / V·s, 9~26cm 2 / V·s, 9.5~25cm 2 / V·s, 10~24cm 2 / V·s, or 11~23cm 2 / V·s.

[0181] The channel region of a p-type TFT is 1 to 30 cm 2 / V·s, e.g., 1.5~29cm 2 / V·s, 2~28cm 2 / V·s, 2.5~27cm 2 / V·s, 3~26cm 2 / V·s, 3.5~25.5cm 2 / V·s, 4~25cm 2 / V·s, 4.5~25cm 2 / V·s, 5~24cm 2 / V·s, 5.5~23cm 2 / V·s, 6~22cm 2 / V·s, 6.5~21cm 2 / V·s, 7~20cm 2 / V·s, 7.5~19cm 2 / V·s, 8~18cm 2 / V·s, 8.5~17cm 2 / V·s, 9~16cm 2 / V·s, 9.5~15cm 2 / V·s, 10~14cm 2 / V·s, or 11-13cm 2 / V·s.

[0182] The electronic circuit may include a first terminal and a second terminal. The first terminal and the second terminal may be formed of the same material or different materials. One or both of the first terminal and the second terminal may be formed of one or more of LTPS, doped LTPS, metal alloys such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W:MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; or semiconductor materials. Preferably, one or both of the first terminal and the second terminal are formed of LTPS or doped LTPS.

[0183] The first terminal may be provided at a first end of the channel region of the p-type TFT, and the second terminal may be provided at a second end of the channel region of the p-type TFT opposite the first end. The first terminal, the LTPS channel region, and the second terminal may be contiguous. A portion of the first terminal region of the first semiconductor body may overlap the first terminal. At least a portion of the second terminal region of the first semiconductor body may overlap the second terminal. At least a portion of the first terminal region and at least a portion of the second terminal region of the semiconductor body may overlap the first terminal and the second terminal, respectively.

[0184] The first semiconductor body may include a first terminal and a second terminal in a first terminal region and a second terminal region, respectively. The first terminal region and the second terminal region may be formed by selective processing of the first terminal region and the second terminal region of the first semiconductor body. The selective processing may include irradiation or thermal or laser annealing of the first terminal region and the second terminal region of the first semiconductor body. The irradiation may be selective UV irradiation.

[0185] The channel length L of a p-type TFT can be defined by the distance between the first terminal and the second terminal, or the distance between the first terminal region and the second terminal region.

[0186] The p-type TFT may further include a gate electrode.

[0187] The p-type TFT gate electrode may be formed from one or more materials selected from Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; or semiconductor materials such as amorphous, microcrystalline, or nanocrystalline Si; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, and rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, and polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2 and GeSbTe; and perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, and CsSnI3.

[0188] The p-type TFT gate electrode may be formed from one or more of amorphous silicon, polycrystalline silicon, microcrystalline silicon, or nanocrystalline silicon.

[0189] As described above in connection with Figures 1F, 2F, 3F, 4F, and 5E, a p-type TFT may be provided on a substrate. The p-type TFT may include a channel region, a first terminal, a second terminal, an insulating layer provided across the first terminal, the second terminal, and the channel region, and a source electrode and a drain electrode provided in a contact via. A gate electrode may be provided on the insulating layer across the channel region. The channel region may have a channel length L of 0.05 to 0.6 µm and a width of 1 to 40 cm, as described above. 2 / V·s charge carrier mobility.

[0190] The source and drain electrodes may be made of any of a variety of materials, including Au, Ti, Al, Mo, Pt, Ag, Cu, Ni, Cr, Ta, and W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, metal oxides (ZnO, SnO, NiO, SnO, CuO, InO, LiZnO, InSnO(ITO), InZnO(IZO), HfInZnO(HIZO), and InGaZnO(IGZO), etc.); and metal oxynitrides (e.g., Zn x O y N z ); inorganic semiconductors such as amorphous, microcrystalline or nanocrystalline silicon; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2, GeSbTe; and perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3.

[0191] The electronic circuit may comprise, or may further comprise, one or more of a second TFT, a resistor, and a capacitor.

[0192] The electronic circuit may comprise, or may further comprise, one or more of a second p-type TFT, an n-type TFT, a first type resistor, a second type resistor, a semiconductor-insulator-metal capacitor (SIMCap), or a metal-insulator-metal capacitor (MIMCap).

[0193] If the electronic circuit further comprises a resistor of the first type, the resistor of the first type may comprise a resistor body made from the LTPS used to form the first semiconductor body of the p-type TFT.

[0194] The first type resistor may include a third terminal and a fourth terminal. The third terminal and the fourth terminal may be formed of the same material or different materials. One or both of the first terminal and the second terminal may be formed of one or more of LTPS, doped LTPS, Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; or semiconductor materials. Preferably, one or both of the third terminal and the fourth terminal are formed of LTPS or doped LTPS.

[0195] The resistor body may include a third terminal and a fourth terminal at a first terminal region of the resistor body and a second terminal region of the resistor body, respectively. The first terminal region and the second terminal region may be formed by selective processing of the first terminal region and the second terminal region of the resistor body. The selective processing may include irradiation or thermal or laser annealing of the first terminal region and the second terminal region of the resistor body. The irradiation may be selective UV irradiation.

[0196] As described with particular reference to FIG. 1F, one example of an electronic circuit according to the present disclosure includes a p-type TFT and a first type resistor disposed on a substrate. The p-type TFT includes a channel region, a first terminal, a second terminal, an insulating layer disposed across the first terminal, the second terminal, and the channel region, and source and drain electrodes disposed in corresponding contact vias. A gate electrode is disposed on the insulating layer across the channel region. The channel region has a channel length L of 0.05 to 0.6 μm and a drain width of 1 to 40 cm, as described above. 2 / V·s. The first type resistor comprises a resistor body, an insulating layer disposed over the semiconductor body, and first and second electrodes disposed in corresponding contact vias.

[0197] If the electronic circuitry comprises or further comprises a SIMCap, the SIMCap may comprise a semiconductor capacitor plate which may be made from the LTPS used in p-type TFTs.

[0198] The SIMCap may include, for example, a first capacitor contact. The first capacitor contact may be disposed across at least a portion of the semiconductor capacitor plate. The first capacitor contact may be disposed across the semiconductor capacitor plate. The first capacitor contact may be disposed across a substantial portion of the semiconductor capacitor plate. The first capacitor contact may be disposed at least partially across the semiconductor capacitor plate. The first capacitor contact may be disposed completely across the semiconductor capacitor plate. The first capacitor contact may be formed from one or more of LTPS, doped LTPS, Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; or semiconductor materials.

[0199] The resistor body of the first type resistor and / or the semiconductor capacitor plate of the SIMCap may have a lower resistivity than the channel region of the first p-type TFT.

[0200] As described with particular reference to FIG. 3F, one example of an electronic circuit according to the present disclosure includes a p-type TFT and a semiconductor-insulator-metal capacitor (SIMCap) disposed on a substrate. The p-type TFT includes a channel region, a first terminal, a second terminal, an insulating layer disposed across the first terminal, the second terminal, and the channel region, and source and drain electrodes disposed in corresponding contact vias. A gate electrode is disposed on the insulating layer across the channel region. The channel region has a channel length L of 0.05 to 0.6 μm and a width of 1 to 40 cm, as described above. 2 / V·s. The SIMCap comprises a semiconductor body, an insulating layer disposed over the semiconductor body, a first capacitor electrode, a second capacitor electrode disposed in a corresponding contact via, and a capacitor top contact (vertical contact) disposed at least partially over the semiconductor body. The capacitor top contact also functions as a capacitor top plate and is disposed at least partially over the semiconductor body which functions as a lower capacitor plate. A further capacitor contact is in electrical contact with the lower capacitor plate.

[0201] Where the electronic circuitry comprises or further comprises an n-type TFT, the n-type TFT may comprise an n-type TFT semiconductor body.

[0202] The n-type TFT may have a fifth terminal and a sixth terminal. The n-type TFT semiconductor body may further have a fifth and sixth terminal. The fifth terminal may be provided at a first end of the n-type TFT semiconductor body, and the second terminal may be provided at a second end of the n-type TFT semiconductor body opposite the first end. The fifth terminal, the n-type TFT semiconductor body, and the sixth terminal may be contiguous. A portion of the first terminal region of the n-type TFT semiconductor body may overlap with the fifth terminal. At least a portion of the second terminal region of the n-type TFT semiconductor body may overlap with the sixth terminal. At least a portion of the first terminal region and at least a portion of the second terminal region of the n-type TFT semiconductor body may overlap with the fifth terminal and the sixth terminal, respectively. The n-type TFT semiconductor body may have the fifth terminal and the sixth terminal in the first terminal region and the second terminal region, respectively. The first terminal region and the second terminal region may be formed by selective processing of the first terminal region and the second terminal region of the n-type TFT semiconductor body. The selective treatment may include irradiation of the first terminal region and the second terminal region of the first semiconductor body, or thermal or laser annealing. The irradiation may be selective UV irradiation.

[0203] The n-type TFT may further comprise a gate electrode.

[0204] The n-type TFT gate electrode can be made of any of a variety of materials, including Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, and W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb; metal oxides (ZnO, SnO, NiO, SnO, CuO, InO, LiZnO, InSnO(ITO), InZnO(IZO), HfInZnO(HIZO), InGaZnO(IGZO), etc.); and metal oxynitrides (e.g., Zn x O y N z ); inorganic semiconductors such as amorphous, microcrystalline or nanocrystalline silicon; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2, GeSbTe; and perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3.

[0205] As described above, when the electronic circuit includes p-type and n-type TFTs, the p-type and n-type TFTs may be vertically stacked (not shown). However, the p-type and n-type TFTs may be disposed laterally relative to one another (as shown in and described with reference to FIGS. 2F, 4F, and 5E). The p-type and n-type TFTs disposed laterally relative to one another may be disposed in the same lateral plane (as shown in and described with reference to FIG. 2F) or in different lateral planes (as shown in and described with reference to FIGS. 4F and 5E).

[0206] As mentioned above, the electronic circuitry may comprise hybrid complementary metal oxide semiconductor (CMOS) circuitry, which may comprise p-type and n-type TFTs according to the present disclosure.

[0207] As described with particular reference to FIG. 2F, in one example of an electronic circuit according to the present disclosure, a p-type TFT and an n-type TFT are provided on a substrate. In this example, the p-type TFT and the n-type TFT are provided in the same plane. The p-type TFT includes a channel region, a first terminal, a second terminal, an insulating layer provided across the first terminal, the second terminal, and the channel region, and a source electrode and a drain electrode provided in contact with the corresponding vias. A gate electrode is provided on the insulating layer across the channel region. As described above, the channel region has a channel length L of 0.05 to 0.6 μm and a width of 1 to 40 cm. 2 / V·s. The n-type TFT includes an n-type TFT semiconductor body, a fifth terminal, a sixth terminal, an insulating layer disposed over the n-type TFT semiconductor body, and source and drain electrodes disposed in corresponding contact vias.

[0208] As described with particular reference to FIG. 4F, in one example of an electronic circuit according to the present disclosure, the electronic circuit comprises a p-type TFT disposed on a substrate and an n-type TFT disposed on an insulator layer disposed on the substrate. Thus, the p-type TFT and the n-type TFT are not in the same plane but are laterally offset relative to each other. The p-type TFT comprises a channel region, a first terminal, a second terminal, an insulating layer (which is also the insulating layer on which the n-type TFT is formed) disposed over the first terminal, a second terminal, a channel, and source and drain electrodes disposed in corresponding contact vias. A gate electrode is disposed on the insulating layer over the channel. The channel region, as described above, has a channel length L of 0.05 to 0.6 μm and a gate electrode width of 1 to 40 cm. 2 / V·s. The n-type TFT comprises an n-type TFT semiconductor body, a fifth terminal, a sixth terminal, a further insulating layer disposed over the n-type TFT semiconductor body, and source and drain electrodes disposed in corresponding contact vias.

[0209] If the electronic circuit further comprises a second type resistor, the second type resistor may comprise a second type resistor body made from the same material used to form the n-type TFT semiconductor body.

[0210] The second type resistor may have a seventh terminal and an eighth terminal. The seventh terminal may be provided at a first terminal of the resistor body of the second type resistor, and the second terminal may be provided at a second terminal of the resistor body of the second type resistor opposite the first terminal. The seventh terminal, the resistor body of the second type resistor, and the eighth terminal may be contiguous. A portion of the first terminal region of the resistor body of the second type resistor may overlap with the seventh terminal. At least a portion of the second terminal region of the resistor body of the second type resistor may overlap with the eighth terminal. At least a portion of the first terminal region and at least a portion of the second terminal region of the resistor body of the second type resistor may overlap with the seventh terminal and the eighth terminal, respectively.

[0211] The resistor body of the second type resistor may further comprise a seventh terminal and an eighth terminal. The resistor body of the second type resistor comprises the seventh terminal and the eighth terminal in the first terminal region and the second terminal region, respectively. The first terminal region and the second terminal region may be formed by selective processing of the first terminal region and the second terminal region of the n-type semiconductor body. The selective processing may include irradiation or thermal or laser annealing of the first terminal region and the second terminal region of the first semiconductor body. The irradiation may be selective UV irradiation.

[0212] The electronic circuit may comprise or further comprise a MIMCap, which may comprise an insulating or dielectric body.

[0213] The insulator or dielectric body of MIMCap is made of Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5;Al2PO x Metal phosphates such as HfSO x metal sulfates / sulfites such as; metal nitrides such as AlN; AlO x N y Metal oxynitrides such as SiO2, Si3N4, SiN xThe dielectric layer may be formed from one or more dielectric materials selected from one or more of: inorganic insulators such as spin-on glass (e.g., polyhydroxybenzyl silylsesquioxane, HSQ), polymeric dielectric materials (e.g., Cytop, commercially available amorphous fluoropolymers), 1-methoxy-2-propyl acetate (SU-8), benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinyl pyrrolidone, polyvinyl phenol, polyvinyl chloride, polystyrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone, etc.; UV-curable resins; nanoimprint resists; or photoresists. The dielectric material may have a relatively low dielectric constant (low-κ, e.g., Cytop, HSQ, parylene) or a relatively high dielectric constant (high-κ, e.g., TaO, HfO), or any other insulating oxide, oxynitride, silicate, etc. The semiconductor body of the MIMCap may be formed from one or more layers of metal, such as titanium, steel, gold, etc. The semiconductor body may control the migration of chemical elements, such as metal, hydrogen, or oxygen, to or from the component layers of the flexible IC.

[0214] The MIMCap may comprise a first capacitor (or "vertical") contact (top contact). The first capacitor contact may be provided over at least a portion of the semiconductor body of the MIMCap. The MIMCap contact may be provided over the n-type semiconductor body. The first capacitor contact may be provided over a substantial portion of the semiconductor body of the MIMCap. The first capacitor contact may be provided at least partially over the first capacitor semiconductor body. The first capacitor contact may be provided completely over the n-type semiconductor body. The first capacitor contact may be made of any of the following materials: Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, metal oxides (ZnO, SnO, NiO, SnO, CuO, InO, LiZnO, ZnSnO, InSnO(ITO), InZnO(IZO), HfInZnO(HIZO), InGaZnO(IGZO), etc.); metal oxynitrides (e.g., Zn x O y N z ); inorganic semiconductors; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, and rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, and polycarbazole; 2D materials such as graphene; and chalcogenides such as MoS2.

[0215] As described with particular reference to FIG. 5E, in one example of an electronic circuit according to the present disclosure, the electronic circuit includes a p-type TFT, an n-type TFT, and a MIMCap provided on a substrate. The n-type TFT and the MIMCap are provided on an insulator layer (which functions as a gate dielectric for the p-type TFT) provided on the substrate. The p-type TFT includes a channel, a first terminal, a second terminal, an insulating layer provided across the first terminal, the second terminal, and the channel, and source and drain electrodes provided in corresponding contact vias. A gate electrode is provided on the insulating layer across the channel region. The channel region has a channel length L of 0.05 to 0.6 μm and a gate width of 1 to 40 cm, as described above. 2 / V·s. The n-type TFT includes an n-type TFT semiconductor body, an insulating layer disposed over the n-type TFT semiconductor body, a source electrode, and a drain electrode. The MIMCap includes a lower electrode plate disposed on a substrate, an insulating layer disposed over the lower electrode plate, and a capacitor upper contact disposed on the insulating layer over the lower electrode plate.

[0216] The insulator layers described herein, such as insulator layers 104, 204, 304, 404a, 404b, 504a, and 504b, are formed from one or more dielectric materials and / or layers, examples of which include metal oxides such as Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5; Al2PO x Metal phosphates such as HfSO x metal sulfates / sulfites such as; metal nitrides such as AlN; AlO x N y Metal oxynitrides such as SiO2, Si3N4, SiN xExamples of suitable insulating materials include inorganic insulators such as spin-on glass (e.g., polyhydroxybenzyl silylsesquioxane, HSQ), polymer dielectric materials (e.g., Cytop, commercially available amorphous fluoropolymers), 1-methoxy-2-propyl acetate (SU-8), benzocyclobutene (BCB), polyimide, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinyl pyrrolidone, polyvinyl phenol, polyvinyl chloride, polystyrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicone, etc.; UV-curable resins; nanoimprint resists; or photoresists. The insulating material may have a relatively low dielectric constant (low-κ, e.g., Cytop, HSQ, parylene) or a relatively high dielectric constant (high-κ, e.g., Ta2O5, HfO2), or any other insulating oxide, oxynitride, silicate, etc. The insulating layer may control the migration of chemical elements such as metal, hydrogen, or oxygen to or from component layers of the flexible IC. Insulator layers such as insulator layers 104, 204, 304, 404a, 404b, 504a, 505' may be formed from one or more of SiO2, HfO2, and Al2O3.

[0217] As explained above, the substrate may further comprise a barrier layer (also called an interfacial layer (intermediate layer)), and the p-type TFT is provided on the upper surface of the barrier layer (interfacial layer or intermediate layer), the upper surface of which is positioned approximately parallel to the upper surface of the substrate on which the aforementioned electrical components are formed or provided.

[0218] If a barrier layer is provided on the substrate (e.g., between the component device and the substrate), it may be a metal oxide such as Al2O3, ZrO2, HfO2, Y2O3, Si3N5, TiO2, Ta2O5 or any other suitable metal oxide; Al2PO x or other suitable metal phosphates; HfSO x metal sulfates or sulfites, such as AlN, TiN, ZrN, TaN, HfN, or other suitable metal nitrides; AlO x Ny or other suitable metal oxynitrides; SiO2, Si3N4, SiN x or other suitable inorganic insulators; spin-on glasses such as polyhydroxybenzylsilsesquioxane or other suitable spin-on glasses; or polymeric dielectric materials such as amorphous fluoropolymers (Cytop®), bisphenol A novolac epoxy (SU-8), benzocyclobutene (BCB), polyimides, polymethyl methacrylate, polybutyl methacrylate, polyethyl methacrylate, polyvinyl acetate, polyvinylpyrrolidone, polyvinyl alcohol, polyvinylphenol, polyvinyl chloride, polystyrene, polyethylene, polycarbonate, parylene, silicone, or other suitable polymeric dielectric materials. It will be understood that the materials listed herein are provided by way of example only and are not an exhaustive list of possible materials that may be used in the barrier layer.

[0219] The second type of resistor body is made of GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, metal oxides (ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO(ITO), InZnO(IZO), HfInZnO(HIZO), InGaZnO(IGZO), etc.); metal oxynitrides (e.g., ZnxOyNz); inorganic semiconductors such as amorphous, microcrystalline or nanocrystalline Si; CuPc, The semiconductor materials may be selected from one or more of the following: inorganic semiconductors such as pentacene, PTCDA, methylene blue, orange G, and rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, and polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2 and GeSbTe; and perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, and CsSnI3. These semiconductor materials may be doped or contain a doping gradient. Further processing, such as annealing (thermal, laser), may be applied to the component layers to change their semiconductor properties. In some embodiments, the n-type resistor body may be formed from IGZO.

[0220] As mentioned above, the substrate may be a flexible substrate. The substrate may be formed from one or more materials selected from, for example, polyethylene naphthalate, polyethylene terephthalate; polymethyl methacrylate; polymethyl methacrylate; polycarbonate, polyvinyl alcohol; polyvinyl acetate; polyvinyl pyrrolidone; polyvinyl pyrrolidone; polyvinyl phenol; polyvinyl chloride; polystyrene; polyimide, polyamide (e.g., nylon); poly(hydroxy ether); polyurethane; polysulfone; parylene; polyarylate; polyether ether ketone (PEEK); acrylonitrile butadiene styrene; 1-methoxy-2-propyl acetate (SU-8); polyhydroxybenzylsilsesquioxane (HSQ); benzocyclobutene (BCB); UV-curable resin; nanoimprint resist; photoresist; polymer foil; paper; insulator-coated metal (e.g., coated stainless steel); and cellulose.

[0221] As mentioned above, the electronic circuit formed is an integrated circuit (IC). The electronic circuit may be a thin film IC and / or a flexible IC.

[0222] Also disclosed herein is a method for fabricating an electronic circuit comprising a semiconductor body for a p-type TFT, the method including depositing one or more layers of amorphous silicon (a-Si) on a substrate, crystallizing the one or more layers of amorphous silicon, and patterning the one or more layers of crystallized amorphous silicon to provide a semiconductor body having a channel length of at least 0.05-0.6 μm.

[0223] Also disclosed herein is a method for manufacturing an electronic circuit comprising a p-type TFT, the method including: depositing one or more layers of amorphous silicon on a substrate; crystallizing the one or more layers of amorphous silicon; patterning the one or more layers of crystallized amorphous silicon to provide at least a first semiconductor body; and forming a p-type TFT having a channel region formed from the semiconductor body, the channel region having a channel length of 0.5 to 20 μm.

[0224] The channel length can be 0.1 to 19.5 μm, for example, 0.15 to 18.5 μm, 0.2 to 18 μm, 0.25 to 17.5 μm, 0.3 to 17 μm, 0.35 to 16.5 μm, 0.4 to 16 μm, 0.45 to 15.5 μm, 0.5 to 15 μm, 0.55 to 14.5 μm, 0.6 to 14 μm, 0.65 to 13.5 μm, 0.7 to 13 μm, 0.75 to 12.5 μm, 0.8 to 12 μm, 0.85 to 11.5 μm, 0.9 to 11 μm, 0.95 to 10 μm, or 1 to 9.5 μm.

[0225] The channel length can be 0.05 to 9 μm, for example, 0.055 to 5 μm, 0.1 to 4.5 μm, 0.15 to 4 μm, 0.2 to 3.5 μm, 0.25 to 3 μm, 0.3 to 2.5 μm, 0.35 to 2 μm, 0.4 to 1.5 μm, etc. For example, the channel length can be 0.05 to 0.6 μm, for example, 0.1 to 0.55 μm, 0.15 to 0.5 μm, 0.2 to 0.45 μm, 0.25 to 0.4 μm, 0.3 to 0.35 μm.

[0226] A p-type TFT may have a channel region and / or source and drain regions formed from doped LTPS, which may include, for example, one or more of phosphorus ions, BF ions, or any other dopant or doping ions known to those skilled in the art.

[0227] The channel region of a p-type TFT is 1 to 200 cm 2 / V·s charge carrier mobility.

[0228] The channel region of a p-type TFT is 0.5 to 200 cm 2 / V·s, e.g., 1.5 to 195 cm 2 / V·s, 2~190cm 2 / V·s, 2.5~185cm 2 / V·s, 3~180cm 2 / V·s, 3.5~175cm 2 / V·s, 4~170cm 2 / V·s, 5~165cm 2 / V·s, 5.5~160cm 2 / V·s, 5.5~160cm 2 / V·s, 6~155cm 2 / V·s, 6.5~150cm 2 / V·s, 7~145cm 2 / V·s, 7.5~140cm 2 / V·s, 8~135cm 2 / V·s, 8~130cm 2 / V·s, 8.5~125cm 2 / V·s, 9~120cm 2 / V·s, 9.5~115cm 2 / V·s, 10~110cm 2 / V·s, 10.5~105cm 2 / V·s, 11~100cm 2 / V·s, 11.5~95cm 2 / V·s, 12~90cm 2 / V·s, or 12.5~85cm 2 / V·s charge carrier mobility.

[0229] The charge carrier mobility of LTPS is, for example, 1 to 40 cm 2 / V·s, e.g., 1.5~39cm 2 / V·s, 2~38cm 2 / V·s, 2.5~37cm 2 / V·s, 3~36cm 2 / V·s, 3.5~35.5cm 2 / V·s, 4~35cm 2 / V·s, 4.5~35cm 2 / V·s, 5~34cm 2 / V·s, 5.5~33cm 2 / V·s, 6~32cm 2 / V·s, 6.5~31cm 2 / V·s, 7~30cm 2 / V·s, 7.5~29cm 2 / V·s, 8~28cm 2 / V·s, 8.5~27cm 2 / V·s, 9~26cm 2 / V·s, 9.5~25cm 2 / V·s, 10~24cm 2 / V·s, or 11~23cm 2 / V·s.

[0230] The channel region of a p-type TFT is 1 to 30 cm 2 / V·s, e.g., 1.5~29cm 2 / V·s, 2~28cm 2 / V·s, 2.5~27cm 2 / V·s, 3~26cm 2 / V·s, 3.5~25.5cm 2 / V·s, 4~25cm 2 / V·s, 4.5~25cm 2 / V·s, 5~24cm 2 / V·s, 5.5~23cm 2 / V·s, 6~22cm 2 / V·s, 6.5~21cm 2 / V·s, 7~20cm 2 / V·s, 7.5~19cm 2 / V·s, 8~18cm 2 / V·s, 8.5~17cm 2 / V·s, 9~16cm 2 / V·s, 9.5~15cm 2 / V·s, 10~14cm 2 / V·s, or 11-13cm 2 / V·s.

[0231] The amorphous silicon may be doped or undoped a-Si.

[0232] A method for manufacturing an electronic circuit may include depositing a layer of doped amorphous silicon on a substrate, patterning the layer of (undoped) amorphous silicon to form first and second terminal regions, depositing a layer of amorphous silicon over the first and second terminal regions, crystallizing the layer of amorphous silicon, and patterning the crystallized layer of polysilicon to provide a semiconductor body having a channel extending between the first and second terminal regions.

[0233] In the described example, amorphous silicon is deposited and subsequently crystallized. For example, as described above in connection with Figures 1A-1F, in one exemplary method for fabricating electronic circuits according to the present disclosure, a layer of amorphous silicon is deposited on a substrate and subsequently crystallized and patterned to form a semiconductor body having a channel length of 0.5-20 μm. The amorphous silicon may be deposited by plasma-enhanced chemical vapor deposition (PECVD). Crystallization of the amorphous silicon may be performed, for example, by one or more of laser annealing, excimer laser annealing (ELA), blue laser annealing (BLA), single-area excimer laser crystallization (SAELC), U-crystallization, selective laser sintering, metal-induced crystallization (MIC), metal-induced lateral crystallization, and continuous-grain crystalline silicon.

[0234] In the described example, layers of various materials (including semiconducting, insulating, and conductive materials) are formed and patterned. For example, an insulating layer is subsequently deposited over the semiconductor body and substrate, as described above in connection with Figures 1A-1F. A gate electrode is formed on the insulating layer over the semiconductor body.

[0235] It will be appreciated that various materials can be deposited and patterned in layers using known thin film deposition and lithography techniques. For example, materials can be deposited in layers by techniques such as evaporation (physical, e.g., sputtering, or chemical, e.g., PECVD), vacuum deposition (e.g., thermal or e-beam evaporation), coating (spin, dip, blade, bar, spray, slot-die), printing (jet, gravure, offset, screen, flexography), pulsed laser deposition (PLD), atomic layer deposition (ALD), and / or other currently known techniques. Patterning of deposited materials can be performed by CBD (coat, bake, develop) and photolithography (i.e., exposure), e-beam lithography, x-ray lithography, ion beam lithography, printing, and / or other currently known techniques. Patterning can be combined with wet and / or dry (plasma) etching, ablation, milling, and / or lift-off patterning, where applicable.

[0236] The gate electrode described herein may be, for any example, made of, for example, Au, Ti, Al, Mo, Pt, Pd, Cr, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, metal oxides (ZnO, SnO, NiO, SnO, CuO, InO, LiZnO, ZnSnO, InSnO(ITO), InZnO(IZO), HfInZnO(HIZO), InGaZnO(IGZO), and the like); metal oxynitrides (e.g., Zn x O y N z); inorganic semiconductors such as amorphous, microcrystalline or nanocrystalline Si; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2, GeSbTe; and perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3.

[0237] It is understood that the crystallized amorphous silicon semiconductor body may be, for example, an LTPS island as described herein. The crystallized amorphous silicon semiconductor body is irradiated, and the gate electrode is used as a mask to shield regions of the crystallized amorphous silicon semiconductor body to form the channel region of a p-type TFT, thereby exposing regions at the termination of the crystallized amorphous semiconductor body that are more conductive / less resistive than the shielded (channel) region of the crystallized amorphous semiconductor body. The exposed regions at the termination can therefore function as the first and second terminals (e.g., source and drain terminals) of the p-type TFT.

[0238] As described above, the irradiation may include irradiating the crystallized amorphous semiconductor body with a UV light source. The UV light source may be an excimer lamp or an excimer laser. The UV light source may emit UV light at wavelengths of, for example, 190-1100 nm, such as 193-1064 nm, 193-355 nm, 350-500 nm, 355-495 nm, or 266-350 nm. The UV light source may be a solid-state or pulsed excimer Nd:YAG laser, XeCl and KrF pulsed excimer laser, CW green laser, and CW diode laser. Methods for annealing semiconductor materials are known to those skilled in the art and are provided, for example, in WO 2012 / 131395 A1 and SPIEVol. 8968, 89680U (March 6, 2014), which are incorporated herein by reference.

[0239] As described herein, an etch stop layer may be deposited and formed on the gate electrode, and a through via may be formed in the insulating layer. A layer of conductive material may then be deposited and patterned to form various contacts (and / or source and drain electrodes) in the via. The etch stop layer may be formed from an etch stop material commonly known to those skilled in the art, such as, for example, a metal nitride such as TiN or TaN.

[0240] The contacts and / or source and drain electrodes may be made of Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, and AlSi; transparent conductive oxides such as ITO, IZO, and AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, and graphene; conductive polymers such as polyaniline and PEDOT:PSS; GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, metal oxides (ZnO, SnO, NiO, SnO, CuO, InO, LiZnO, ZnSnO, InSnO(ITO), InZnO(IZO), HfInZnO(H)). metal oxynitrides (e.g., ZnxOyNz); inorganic semiconductors such as amorphous, microcrystalline, or nanocrystalline Si; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, and rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, and polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2 and GeSbTe; and perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, and CsSnI3.

[0241] As described with particular reference to Figures 1A-1F, one exemplary method for fabricating electronic circuits according to the present disclosure fabricates electronic circuits in which p-type TFTs and associated resistors are formed using the same material. Specifically, with reference to Figure 1A, a layer of amorphous silicon is deposited on a substrate 103 and subsequently crystallized and patterned to form first and second semiconductor bodies 101 and 102, each having a p-type semiconductor body length of 0.05-0.6 µm. Subsequently, as shown in Figure 1B, an insulating layer 104 is deposited over the first and second semiconductor bodies 101 and 102 and the substrate 103. Then, as shown in Figure 1C, a gate electrode 105 is formed on the insulating layer 104 over the first semiconductor body 101.

[0242] These semiconductor bodies 101, 102 are then irradiated. In the case of the first semiconductor body 101, the gate electrode acts as a mask to shield the channel of the semiconductor body, thereby exposing regions of the semiconductor body's terminations 106a, 106b, which are more conductive / less resistive than the channel of the semiconductor body 101. Thus, as shown in FIG. 1D, the exposed regions at the terminations can function as the first terminal 106a and second terminal 106b of a p-type TFT. The second semiconductor body 102 (for forming a resistor) is fully exposed to irradiation, forming a semiconductor body 106c that is more conductive / less resistive than the original crystallized amorphous silicon semiconductor body 102. Subsequently, as shown in FIG. 1E, an etch stop layer 107 is deposited and formed on the gate electrode 105, and through vias 108a, 108b, 108c, and 108d are formed in the insulating layer 104. A layer of conductive material is then deposited and patterned to form contacts (or source and drain electrodes) 109a, 109b, 109c, and 109d in vias 108a-d, as shown in FIG. 1F.

[0243] As described with particular reference to Figures 2A-2F, one exemplary method for fabricating an electronic circuit according to the present disclosure forms an electronic circuit comprising a p-type TFT and an n-type TFT. Referring to Figure 2A, a layer of amorphous silicon is deposited on a substrate 203, then crystallized and patterned to form a first semiconductor body 201 having a channel length of 0.5-20 μm. A layer of semiconductor material, such as a metal oxide semiconductor, is deposited and patterned to form a second n-type TFT semiconductor body 202.

[0244] The second n-type TFT semiconductor body may be made of GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, metal oxides (ZnO, SnO, NiO, SnO, CuO, InO, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO), etc.); metal oxynitrides (e.g., Zn x O y N z The n-type resistor may be formed from semiconductor materials selected from one or more of: inorganic semiconductors such as amorphous, microcrystalline, or nanocrystalline Si; organic semiconductors such as CuPc, pentacene, PTCDA, methylene blue, orange G, or rubrene; polymer semiconductors such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, or polycarbazole; 2D materials such as graphene; chalcogenides such as MoS2 or GeSbTe; or perovskites such as SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, or CsSnI3. These semiconductor materials may be doped or contain a doping gradient. Further processing, such as annealing (thermal, laser), may be applied to the component layers to change their semiconductor properties. In some embodiments, the n-type resistor body may be formed from IGZO.

[0245] As shown in Figure 2B, an insulating layer 204 is then deposited over the first and second semiconductor bodies 201, 202 and the substrate 203. In Figure 2C, gate electrodes 205a, 205b are formed on the insulating layer 204 over the semiconductor bodies 201, 202, respectively.

[0246] The first semiconductor body 201 and the second n-type TFT semiconductor body 202 are then illuminated. The gate electrodes 205a and 205b act as masks to shield the channel of each semiconductor (and any resistive) body, thereby exposing regions at the terminations 206a, 206b, 206c, and 206d of the semiconductor bodies that are more conductive / less resistive than the channel regions or semiconductor bodies of the respective first semiconductor body 201 and second semiconductor body 202. Thus, as shown in Figure 2D, the exposed regions at the terminations may function as the first terminal 206a and the second terminal 206b of the p-type TFT (crystallized amorphous silicon semiconductor body, first semiconductor body) and the second terminal 206c and the third terminal 206d of the n-type TFT (n-type TFT semiconductor body, second semiconductor body, metal oxide semiconductor body), respectively.

[0247] An etch stop layer is then deposited and formed on the gate electrodes 205a and 205b, and through vias 208a-d are formed in the insulating layer 204 (FIG. 2E). A layer of conductive material is then deposited and patterned to form contacts (or source and drain electrodes) 209a-d to the vias 208a-d, as shown in FIG. 2F.

[0248] 4A-4F, one exemplary method for fabricating an electronic circuit according to the present disclosure forms a separate electronic circuit including a p-type TFT and an n-type TFT. Referring to FIG. 4A, a layer of amorphous silicon is deposited on a substrate 403, then crystallized and patterned to form a first semiconductor body 401 having a channel length of 0.5-20 μm. An insulating layer 404a is then deposited over the first semiconductor body 401 and substrate 403.

[0249] A layer of semiconductor oxide material, such as a metal oxide semiconductor, is deposited and patterned on the insulating layer 404a to form a second n-type TFT semiconductor body 402. A second insulator layer 404b is then deposited over the second n-type TFT semiconductor body 402 (FIG. 4B).

[0250] In FIG. 4C, gate electrodes 405a, 405b are formed over first semiconductor body 401 and second n-type TFT semiconductor body 402, respectively, on insulating layers 404a and 404b, respectively.

[0251] The insulating layers 404a and 404b may be formed from the same material, or may be formed from different materials. The insulating layers 404a and 404b may be formed from the same material or different materials.

[0252] The first semiconductor body 401 and the second n-type TFT semiconductor body 402 are then illuminated. The gate electrodes 405a and 405b act as masks that shield the channels of the respective resistor bodies, thereby exposing areas of the resistor body terminations 406a, 406b, 406c, 406d that are more conductive / less resistive than the channels or semiconductor bodies of the respective first semiconductor body 401 and second semiconductor body 402. Thus, as shown in Figure 4D, the exposed areas at the terminations may function as the first terminal 406a and the second terminal 406b of the p-type TFT (crystallized amorphous silicon semiconductor body, first semiconductor body) and the second terminal 406c and the third terminal 406d of the n-type TFT (n-type TFT semiconductor body, second semiconductor body, metal oxide semiconductor body), respectively.

[0253] Subsequently, an etch stop layer 407 is deposited and formed on the gate electrodes 405a, 405b, and through vias 408a-d are formed in the insulating layer 404a (FIG. 4E). A layer of conductive material is then deposited and patterned to form contacts (or source and drain electrodes) 409a-d to the vias 408a-d, as shown in FIG. 4F.

[0254] 3A-3F, one exemplary method for fabricating an electronic circuit according to the present disclosure forms an electronic circuit comprising a p-type TFT and a SIMCap. Referring to FIG. 3A, a layer of amorphous silicon is deposited on a substrate 303, and then crystallized and patterned to form a first semiconductor body 301 and a second semiconductor body 302.

[0255] 3B, an insulating layer 304 is then deposited over the first semiconductor body 301, the second semiconductor body 302, and the substrate 303. In FIG. 3C, a gate electrode 305 is formed on the insulating layer 304 over the first semiconductor body 301.

[0256] The first semiconductor body 301 and the second semiconductor body 302 are then irradiated. The gate electrode 305 acts as a mask to shield the channel of the first semiconductor body, thereby exposing regions at the terminations 306a, 306b of the first semiconductor body that are more conductive / less resistive than the channel region of the first semiconductor body 301. The exposed regions at the terminations may therefore function as the first terminal 306a and the second terminal 306b of a p-type TFT (crystallized polysilicon semiconductor body, first semiconductor body). The second semiconductor body 302 (to form the plates of the capacitor) is fully exposed to the irradiation, forming a semiconductor body 306c that is more conductive / less resistive than the original crystallized polysilicon semiconductor body 302, as shown in FIG. 3D.

[0257] Subsequently, as shown in FIG. 3E, an etch stop layer 307 is deposited and formed on the gate electrode 305, and through vias 308a-c are formed in the insulating layer 304. Then, as shown in FIG. 3F, a layer of conductive material is deposited and patterned to form contacts (or source and drain electrodes) 309a, b, and d to the vias 308a, b, and d. Capacitor contact 309c also functions as the capacitor top plate and is at least partially disposed across the second semiconductor body 306c, which functions as the conductive bottom plate. Capacitor contact 309d is in electrical contact with the bottom capacitor plate 306c.

[0258] A top contact for a SIMCap, such as top contact 309c, may be formed from one or more of LTPS, doped LTPS, Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi; transparent conductive oxides such as ITO, IZO, AZO; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene; conductive polymers such as polyaniline, PEDOT:PSS; or semiconductor materials.

[0259] As described with particular reference to Figures 5A-5E, one exemplary method for fabricating an electronic circuit according to the present disclosure forms an electronic circuit including a p-type TFT, an n-type transistor, and a MIMCap. Referring to Figure 5A, a layer of a-Si (amorphous silicon) is deposited on a substrate 503, then crystallized and patterned to form a first semiconductor body 501 having a channel length of 0.05-0.6 μm. An insulating layer 504a is then deposited over the crystallized polysilicon semiconductor body 501 and the substrate 503.

[0260] A layer of semiconductor material, such as a metal oxide semiconductor, is deposited and patterned on the insulator layer 504a to form a second n-type TFT semiconductor body 502. As shown in Figure 5B, a gate electrode 505a is formed on the insulator layer 504 over the first semiconductor body 501, and source and drain electrodes (or contacts) 509c and 509d for the second n-type TFT are formed, and a MIMCap lower electrode plate 513 (not shown) is formed.

[0261] 5C, an etch stop layer 507 is deposited and formed on the gate electrode 505, the source and drain electrodes 509a and 509b, and the MIMcap lower electrode plate 513 (not shown). Through vias 508a, 508b are formed in the insulating layer 504.

[0262] The first semiconductor body 501 and the second n-type TFT semiconductor body 502 are then illuminated. The gate electrode 505 acts as a mask to shield the channel of the first semiconductor body 501, thereby exposing areas at the semiconductor body terminations 506a, 506b, which are more conductive / less resistive than the channel of the crystallized amorphous silicon first semiconductor body 501. The exposed areas at the terminations may therefore function as the first and second terminals 506a, 506b of the p-type TFT (crystallized amorphous silicon semiconductor body, first semiconductor body). The second semiconductor body 502 (of the n-type transistor) is fully exposed to illumination, but the wavelength of the light source illumination is selected such that the material of the second n-type TFT semiconductor body is transparent to such illumination, as shown in FIG. 5D. For example, the illumination wavelength and material of the second n-type TFT semiconductor body may be selected such that such illumination changes the electrical properties of the first semiconductor body but not the material of the second n-type TFT semiconductor body. For example, metal oxide semiconductors such as IGZO are substantially transparent to wavelengths above 300 nm, whereas the electrical properties of crystallized amorphous silicon are affected by UV illumination at wavelengths of 300 nm. In one example, illumination from a green laser having a wavelength of, for example, 532 nm may be used.

[0263] Subsequently, source and drain electrodes for the crystallized a-Si semiconductor bodies 509a, 509b are formed, along with a top gate electrode for n-type transistor 505b and a top plate contact for MIMcap 505c, as shown in FIG. 5E.

[0264] In some embodiments, a top contact for a MIMCap, such as top contact 309c, can be formed from one or more of LTPS, doped LTPS, Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W; metal alloys such as MoNi, MoCr, AlSi, etc.; transparent conductive oxides such as ITO, IZO, AZO, etc.; metal nitrides such as TiN; carbon materials such as carbon black, carbon nanotubes, graphene, etc.; conductive polymers such as polyaniline, PEDOT:PSS, etc.; or semiconductor materials.

[0265] Methods for fabricating p-type transistors are described in Schalberger et al., IMID / IDMC Digest, pp. 1645-1648, (2006); Baur et al., Society for Information Display (SID) digest, May 2005, Vol. 36, Issue 1, pages 1266-1269; and Schalberger et al., Society for Information Display (SID) digest, May 2010, Vol. 41, Issue 1, pages 909-912, which are incorporated herein by reference. For example, the method of the present disclosure may include depositing a highly doped layer of silicon, e.g., highly phosphorus-doped silicon, on a substrate. Using patterning techniques known to those skilled in the art, the layer of highly doped silicon is patterned to provide islands on which source and drain electrodes are later formed on the p-type TFT. Amorphous silicon is then deposited over the islands and substrate, followed by a dehydration treatment at 450°C and crystallization using, for example, single-area excimer laser crystallization (SAELC). Without wishing to be bound by theory, it is believed that during crystallization, some of the phosphorus in the islands may diffuse laterally across the amorphous silicon, resulting in lightly doped drain (LDD) structures at either end of the amorphous silicon structure (once crystallized). The resulting polysilicon layer is then patterned, followed by the deposition and patterning of a silane-based oxide.

[0266] Throughout this specification, the term "connected" is understood to mean a direct connection, such as an electrical, mechanical, or magnetic connection, between the things connected. The term "coupled" is understood to mean a direct or indirect connection (i.e., via one or more passive or active intermediary devices). The term "scaling" may generally be understood to refer to converting one layout pitch to another. Furthermore, unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" merely indicates that different instances of similar objects are being referenced and is not intended to imply that the objects so described must be in a given sequence, either in time, space, order, or in any other manner. Orientation terms such as "horizontal" are understood with respect to a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical," as defined above, may refer to a direction perpendicular to the horizontal. Prepositions such as "on," "side," "higher," "upper," "lower," "over," "bottom," and "under" may be understood with reference to a conventional plane or surface on top of a wafer or substrate, regardless of the orientation of the electrical interconnect or electronic package.

[0267] The drawings herein are not limited to the elements shown, but may include additional elements or omit elements. Also, the drawings are not to scale, and the size of certain elements may be exaggerated for illustrative purposes.

[0268] Throughout the description and claims of this specification, the words "comprise" and "contain" and variations thereof mean "including but not limited to" and are not intended to exclude (do not exclude) other elements, integers, or steps. Throughout the description and claims of this specification, the singular includes the plural unless the context requires otherwise. In particular, where the indefinite article is used, it is to be understood that the specification contemplates the plural as well as the singular, unless the context requires otherwise.

[0269] As used herein, the terms "A, B, or C" or "at least one of A, B, and / or C," etc., may include all possible combinations of A, B, and C. When an element (e.g., a first element) is described as being "coupled with" or "connected with" (operably or communicatively) another element (e.g., a second element), it will be understood that it can be coupled or connected to the other element directly or through one or more other elements.

[0270] It should be understood that features, integers, properties, or groups described in connection with a particular aspect, embodiment, or example of the invention are applicable to any other aspect, embodiment, or example described herein, unless inconsistent therewith. All features disclosed in this specification (including any accompanying claims, abstract, and drawings), and / or all steps of any method or process so disclosed, may be combined in any combination, except combinations in which at least some of such features and / or steps are mutually exclusive. The invention is not limited to the details of the foregoing embodiments. The invention extends to any novel one or any novel combination of features disclosed in this specification (including any accompanying claims, abstract, and drawings), or any novel one or any novel combination of steps of any method or process so disclosed.

Claims

1. at least one p-type thin film transistor "TFT" and at least one further electronic device formed on a substrate; the at least one p-type TFT comprises a channel region formed from at least partially crystalline silicon, the partially crystalline silicon being formed from amorphous silicon using a process that maintains the substrate at a temperature less than 650°C; The channel region of the at least one p-type TFT has a thickness of 1 to 40 cm ２ 1. An integrated circuit (IC) formed from at least partially crystalline silicon having a charge carrier mobility within a range encompassing .times. ...

2. at least one p-type thin film transistor "TFT" and at least one further electronic device fabricated on a substrate; the at least one p-type TFT comprises a channel region formed from at least partially crystalline silicon, the partially crystalline silicon being formed from amorphous silicon using a process that maintains the substrate at a temperature less than 650°C; An integrated circuit (IC), wherein the at least one further electronic device comprises at least one n-type TFT, the at least one n-type TFT comprising a channel region formed from a semiconductor oxide.

3. 10. The IC of claim 1, wherein the at least one further electronic device comprises at least one n-type TFT, the at least one n-type TFT comprising a channel region formed from a semiconductor oxide.

4. 4. The IC of claim 2 or 3, wherein the channel region of the at least one p-type TFT is formed from at least partially crystalline silicon having a charge carrier mobility within a range of 1 to 20 times, optionally within a range of 1 to 15 times, within a range of 1 to 10 times, or within a range of 1 to 5 times, of the semiconducting oxide from which the channel region of the at least one n-type TFT is formed.

5. 5. The IC of claim 2, wherein the at least one p-type TFT has a first channel length and the at least one n-type TFT has a second channel length, the first channel length being greater than the second channel length.

6. The IC of claim 5 , wherein the second channel length is less than 0.6 μm in length.

7. 7. The IC of claim 5, wherein the first channel length and the second channel length are mutually configured to ensure that the minimum of a first maximum drain-source current for a given gate voltage magnitude for the p-type device and a second maximum drain-source current for the n-type device is within 25% of the maximum of the first maximum drain-source current and the second maximum drain-source current.

8. 8. The IC of claim 7, wherein the first channel length and the second channel length are mutually configured to ensure that the second maximum drain-source current is equal to or greater than the second maximum drain-source current.

9. The IC of any one of claims 5 to 8, wherein the first channel length is greater than 1 μm in length and the second channel length is less than 1 μm in length.

10. The IC of any one of claims 2 to 8, wherein the channel length of the at least one p-type TFT or the first channel length is between 0.05 μm and 0.6 μm.

11. 11. The IC of claim 2, wherein the at least one p-type TFT has a p-type TFT gate insulator and the at least one n-type TFT has an n-type TFT gate insulator formed from a different insulator layer than the first gate insulator.

12. 12. The IC of claim 11, wherein the p-type TFT gate insulator is a first thickness and the n-type TFT gate insulator is a second thickness different from the first thickness.

13. 13. The IC of claim 12, wherein the first thickness and the second thickness are mutually configured to ensure that a minimum of a first parasitic capacitance associated with the p-type TFT gate insulator and a second parasitic capacitance associated with the n-type TFT gate insulator is within 20% of a maximum of the first parasitic capacitance and the second parasitic capacitance.

14. 14. The IC of claim 11, wherein the p-type TFT first gate insulator is a first material having a first dielectric constant and the n-type TFT gate insulator is a second material having a second dielectric constant different from the first dielectric constant.

15. 15. The IC of claim 14, wherein the first material has a first dielectric constant and the second material has a second dielectric constant, the first and second dielectric constants being mutually configured to ensure that a minimum of a first parasitic capacitance associated with the p-type TFT gate insulator and a second parasitic capacitance associated with the n-type TFT gate insulator is within 20% of a maximum of the first and second parasitic capacitances.

16. 16. An IC according to any one of claims 2 to 15, wherein the at least one further electronic device comprises at least one resistor formed from a semiconductor oxide that forms part of a common fabrication layer with the semiconductor oxide in which the channel region of the n-type TFT is formed.

17. The IC of any one of claims 2 to 8, wherein the at least one p-type TFT and the at least one n-type TFT have their respective gate insulators formed from the same insulator layer.

18. 18. The IC of claim 2, wherein the at least one semiconductor oxide in which the channel region of the n-type TFT is formed is provided directly on the substrate or on a barrier layer formed directly on the substrate.

19. The IC according to any one of claims 2 to 17, wherein the at least one semiconductor oxide in which the channel region of the n-type TFT is formed is formed on an insulator layer provided between the substrate and the at least one semiconductor oxide.

20. An IC according to any one of claims 2 to 18, wherein source and drain regions of the at least one n-type TFT are formed from the at least one semiconductor oxide at either end of the channel region.

21. 21. The IC of claim 20, wherein the source and drain regions of the at least one n-type TFT are formed from respective regions of the at least one semiconductor oxide that have been irradiated with electromagnetic radiation to change electrical properties of these regions of the at least one semiconductor oxide to cause the regions of the at least one semiconductor oxide to become conductive.

22. The IC of any one of claims 2 to 21, wherein the at least one semiconductor oxide is a metal oxide semiconductor.

23. An IC according to any one of claims 2 to 22, wherein the at least one semiconductor oxide is indium gallium zinc oxide "IGZO".

24. 24. The IC of any one of claims 2 to 23, wherein the at least one p-type thin film transistor "TFT" and the at least one n-type thin film transistor are interconnected to form a circuit comprising at least one complementary metal oxide semiconductor "CMOS" circuit.

25. 25. The IC of claim 24, wherein the at least one CMOS circuit comprises at least one CMOS inverter circuit.

26. 26. The IC of claim 1, wherein the at least partially crystalline silicon in which the channel region of the p-type TFT is formed is formed directly on the substrate or on a barrier layer formed directly on the substrate.

27. An IC according to any preceding claim, wherein source and drain regions of the at least one p-type TFT are formed from the at least partially crystalline silicon at either end of the channel region.

28. 28. The IC of claim 27, wherein the source and drain regions of the at least one p-type TFT are formed from respective regions of the at least partial crystalline silicon, and the regions have been irradiated with electromagnetic radiation to change electrical properties of the partial crystalline silicon in those regions of the at least partial crystalline silicon to make them more conductive.

29. 29. The IC of claim 27 or 28, wherein the source and drain regions of the at least one p-type TFT are formed from respective regions of the at least partial crystalline silicon, the regions being doped to change the electrical properties of the partial crystalline silicon of those regions of the at least partial crystalline silicon to make them more conductive.

30. The IC of any one of claims 1 to 29, wherein the at least partially crystalline silicon comprises polycrystalline silicon.

31. 31. The IC of claim 30, wherein the polysilicon is low temperature polysilicon "LTPS."

32. The IC of any one of claims 1 to 31, wherein the at least partially crystalline silicon is formed from amorphous silicon using a laser.

33. 33. The IC of claim 32, wherein the at least partially crystalline silicon is formed from amorphous silicon using an excimer laser, or a blue light emitting diode (LED), or a blue solid state laser.

34. An IC according to any preceding claim, wherein the at least one further electronic device comprises at least one resistor.

35. 35. The IC of claim 34, wherein the at least one resistor comprises at least one resistor formed from at least partially crystalline silicon.

36. 36. The IC of claim 35, wherein the at least one resistor comprises at least one resistor formed from at least partially crystalline silicon that forms part of a common fabrication layer with the at least partially crystalline silicon in which the channel region of the at least one p-type TFT is formed.

37. The IC of any one of claims 34 to 36, wherein the at least one resistor comprises at least one resistor formed from a semiconductor oxide material.

38. 38. An IC as claimed in any one of claims 1 to 37, wherein the at least one further electronic device comprises at least one capacitor comprising a first capacitor plate, a second plate formed of metal, and a capacitor insulator provided between the first capacitor plate and the second capacitor plate.

39. 39. The IC of claim 38, wherein the at least one capacitor comprises at least one capacitor having the first capacitor plate formed from a semiconductor material and the second capacitor plate formed from a metallic material.

40. 40. The IC of claim 39, wherein the first capacitor plate is formed from at least partially crystalline silicon of the same type as the at least partially crystalline silicon in which the channel region of the at least one p-type TFT is formed.

41. 41. The IC of any one of claims 38 to 40, wherein the at least one capacitor comprises at least one capacitor in which the first capacitor plate and the second capacitor plate are each formed from a respective metallic material.

42. The IC of any one of claims 1 to 41, wherein the substrate is a flexible substrate.

43. 43. The IC of claim 42, wherein the substrate is formed from polyimide.

44. The IC of any one of claims 1 to 41, wherein the substrate is a rigid substrate.

45. 45. The IC of claim 42 or 44, wherein the substrate is formed from glass.

46. The IC of any one of claims 1 to 45, wherein a barrier layer is formed on the substrate.

47. 1. A method of manufacturing an integrated circuit (IC), comprising: providing a substrate and fabricating an IC on the substrate, the IC comprising at least one p-type thin film transistor "TFT" and at least one further electronic device; The at least one p-type TFT comprises: forming a first layer, the first layer comprising amorphous silicon; treating the first layer to convert the amorphous silicon to at least partially crystalline silicon using a process that maintains the substrate at a temperature less than 650°C; patterning the first layer, before or after the at least partial conversion to crystalline silicon, to form at least one semiconductor region; fabricating the at least one p-type TFT, wherein a channel region of the at least one p-type TFT is formed from the at least partially crystalline silicon of the at least one semiconductor region; Manufactured by The step of processing the first layer is 1 to 40 cm when the at least one p-type TFT is manufactured. ２ / V·s, a method configured to generate partial crystalline silicon in the at least one semiconductor region that forms the channel region of the at least one p-type TFT having a charge carrier mobility within the range including.

48. 1. A method of manufacturing an integrated circuit (IC), comprising: providing a substrate and fabricating an IC on the substrate, the IC comprising at least one p-type thin film transistor "TFT" and at least one further electronic device; The at least one p-type TFT comprises: forming a first layer, the first layer comprising amorphous silicon; treating the first layer to convert the amorphous silicon to at least partially crystalline silicon using a process that maintains the substrate at a temperature less than 650°C; patterning the first layer, before or after the at least partial conversion to crystalline silicon, to form at least one semiconductor region; fabricating the at least one p-type TFT, wherein a channel region of the at least one p-type TFT is formed from the at least partially crystalline silicon of the at least one semiconductor region; Manufactured by the at least one further electronic device comprises an n-type TFT, the at least one n-type TFT comprising: forming a second layer, the second layer comprising a semiconductor oxide; patterning the second layer to form at least one semiconductor oxide region; fabricating the at least one n-type TFT, wherein a channel region of the at least one n-type TFT is formed from the semiconductor oxide of the at least one semiconductor oxide region; Manufactured by the method.

49. the at least one further electronic device comprises an n-type TFT, the at least one n-type TFT comprising: forming a second layer, the second layer comprising a semiconductor oxide; patterning the second layer to form at least one semiconductor oxide region; fabricating the at least one n-type TFT, wherein a channel region of the at least one n-type TFT is formed from the semiconductor oxide of the at least one semiconductor oxide region; 48. The method of claim 47, wherein the compound is produced by

50. 50. The method of claim 49, wherein said treating of said first layer is configured to produce partially crystalline silicon in said at least one semiconductor region forming said channel region of said at least one p-type TFT having a charge carrier mobility in the range of 1 to 20 times, optionally in the range of 1 to 15 times, in the range of 1 to 10 times, or in the range of 1 to 5 times that of the semiconductor oxide in which said channel region of said at least one n-type TFT is formed.

51. 51. The method of any one of claims 47 to 50, wherein the at least one p-type thin film transistor "TFT" and the at least one n-type thin film transistor are interconnected to form a circuit comprising at least one complementary metal oxide semiconductor "CMOS" circuit.

52. 52. The IC of claim 51, wherein the at least one CMOS circuit comprises at least one CMOS inverter circuit.

53. A method of manufacturing an integrated circuit (IC), comprising providing a substrate and fabricating an IC according to any one of claims 1 to 46 on the substrate from a plurality of layers.

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