semiconductor devices

Abstract

The present application discloses a semiconductor device including a substrate, an epitaxial structure located on one side of the substrate, a gate located on a side of the epitaxial structure away from the substrate, extending along a first direction parallel to a plane in which the substrate is located and forming a Schottky contact with the epitaxial structure, and a gate connection structure including a first gate subconnection and a second gate subconnection connected to each other, the second gate subconnection being electrically connected to at least a portion of the gate. By providing the gate connection structure, the semiconductor device can reduce the effect of gate resistance, improve switching speed, and increase gain.

Description

[Technical Field]

[0001] This application relates to the field of semiconductors, and more particularly to semiconductor devices. [Background technology]

[0002] Gallium nitride semiconductor materials have advantages such as a large band gap width, a high electron saturation drift velocity, a high breakdown field strength, and high heat resistance, and are currently the focus of research.

[0003] In GaN RF power amplifiers, achieving both device power and gain characteristics is required by application circuits, and is also pursued in GaN RF chips. However, because the gate power supply is on one side of the device, the power supply on the other side of the gate is affected by the gate resistance and decreases. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a semiconductor device that can reduce the effect of gate resistance, improve gain, and increase the switching speed of the device. [Means for solving the problem]

[0005] According to a first aspect, the present application provides a semiconductor device including a substrate, an epitaxial structure, a gate, and a gate connection structure, wherein the epitaxial structure is located on one side of the substrate, the gate is located on a side of the epitaxial structure away from the substrate, the gate extends in a first direction parallel to a plane in which the substrate lies and includes a first gate sub-portion and a second gate sub-portion connected to each other and forming a Schottky contact with the epitaxial structure, and the gate connection structure includes a first gate sub-connection portion and a second gate sub-connection portion connected to each other, the second gate sub-connection portion being electrically connected to at least a portion of the gate.

[0006] In a possible implementation of the present application, the semiconductor device further includes an active region and a non-active region surrounding the active region, the second gate sub-connection portion is located in the active region, the first gate sub-portion is located in the active region, and the second gate sub-connection portion is electrically connected to at least a portion of the first gate sub-portion.

[0007] In a possible realization of the present application, the minimum distance between the second gate sub-connection and the edge of the active area is L1, where L1≦5 μm.

[0008] In a possible implementation of the present application, the semiconductor device further includes an active region and a non-active region surrounding the active region, the second gate sub-connection portion is located in the non-active region, the second gate sub-portion is located in the non-active region, and the second gate sub-connection portion is electrically connected to at least a portion of the second gate sub-portion.

[0009] In a possible realization of the present application, the first gate sub-connection at least partially overlaps the first gate sub-portion, and the second gate sub-connection at least partially overlaps the second gate sub-portion.

[0010] In a possible realization of the present application, the gate connection structure covers the gate along the thickness direction of the semiconductor device.

[0011] In a possible realization of the present application, the first gate sub-portion does not overlap the first gate sub-connection along the thickness direction of the semiconductor device.

[0012] In a possible implementation of the present application, the semiconductor device includes a source, which forms an ohmic contact with the epitaxial structure, and along the thickness direction of the semiconductor device, a first gate sub-connection overlaps the source and is insulatedly located.

[0013] In a possible implementation of the present application, the size of the first gate sub-connection in the second direction is smaller than the size of the source in the second direction, and the second direction intersects with the first direction and is parallel to the plane in which the substrate lies.

[0014] In a possible implementation of the present application, the semiconductor device further includes a source, which forms an ohmic contact with the epitaxial structure, and along the second direction, the first gate sub-connection is located on a side of the source away from the gate and the first gate sub-connection is located between two adjacent sources, and two adjacent transistor cells share the same first gate sub-connection, and the second direction intersects the first direction and is parallel to the plane in which the substrate is located.

[0015] In a possible realization of the present application, the gate connection structure further includes a third gate sub-connection portion, which is located in the active region and electrically connected to the first gate sub-connection portion and the first gate sub-portion, respectively.

[0016] In a possible implementation of the present application, the semiconductor device further includes a source and a source field plate, the source field plate including a field plate body and a field plate branch, the field plate branch being electrically connected to the field plate body and the source, respectively, and the field plate branch being offset from the third gate sub-connection.

[0017] In a possible implementation of the present application, the source field plate is positioned offset from the gate along the thickness direction of the semiconductor device, or the source field plate covers an edge portion of the gate away from the source along the thickness direction of the semiconductor device, and the overlap area between the source field plate and the gate is S1, the area of ​​the gate is S2, and S1 / S2≦20%.

[0018] In a possible implementation of the present application, the semiconductor device further includes a gate pad, wherein along a first direction, the gate pad is located in a non-active area on a first side of the active area, and the first gate sub-portion and the first gate sub-connection portion are both electrically connected to the gate pad.

[0019] In a possible implementation of the present application, the semiconductor device further includes a source and a source field plate, wherein the source field plate is electrically connected to the source, and the first gate sub-connection and the gate are located in the same layer, or the first gate sub-connection and the source field plate are located in the same layer, or the first gate sub-connection and the gate pad are located in the same layer, or the source field plate is located between the film layer in which the gate is located and the film layer in which the gate connection structure is located.

[0020] In a possible implementation of the present application, the semiconductor device further includes a first dielectric layer located between the film layer in which the source field plate is located and the film layer in which the gate is located, and a second dielectric layer located between the film layer in which the source field plate is located and the film layer in which the gate connection structure is located, wherein, along the thickness direction of the semiconductor device, the source field plate overlaps the first gate sub-portion and a thickness d1 of the first dielectric layer satisfies d1≧300 nm, and / or the source field plate overlaps the first gate sub-connection portion and a thickness d2 of the second dielectric layer satisfies d2≧300 nm.

[0021] In a possible implementation of the present application, along a second direction, the size of the first gate sub-connection portion is larger than the size of the first gate sub-portion, and the second direction intersects with the first direction and is parallel to the plane in which the substrate lies.

[0022] In a possible implementation of the present application, the gate connection structure is electrically connected to a gate located on one side of the first gate sub-connection along the second direction via a second gate sub-connection, or the semiconductor device includes multiple gates, the multiple gates being arranged along the second direction, and the gate connection structure is electrically connected to gates located on both sides of the first gate sub-connection along the second direction via the second gate sub-connection, the second direction intersecting the first direction and parallel to a plane in which the substrate is located.

[0023] In a possible realization of the present application, the included angle between the second gate sub-connection and the first gate sub-connection is α, where 80°≦α≦100°. [Effects of the Invention]

[0024] The semiconductor device according to the embodiment of the present application is provided with a gate connection structure, and the gate connection structure is electrically connected to at least a portion of the gate, thereby reducing the gate resistance, improving the gain of the gate, and increasing the switching speed of the device. [Brief explanation of the drawings]

[0025] In order to more clearly describe the technical solutions in the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. However, the drawings in the following description are only some embodiments of the present application, and it is obvious to those skilled in the art that other drawings can be obtained based on these drawings without any creative efforts. [Figure 1] 1 is a schematic diagram illustrating the configuration of a semiconductor device according to an embodiment of the present application. [Figure 2] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 3] 3 is a schematic cross-sectional view of the semiconductor device shown in FIG. 1 or 2 taken along line AA'. FIG. [Figure 4] 3 is a schematic cross-sectional view of the semiconductor device shown in FIG. 2 taken along line BB'. FIG. [Figure 5] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 6] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 7] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 8] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 9] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 10]FIG. 10 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 11] 11 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line AA'. FIG. [Figure 12] 11 is a schematic cross-sectional view of the semiconductor device shown in FIG. 10 taken along line BB'. FIG. [Figure 13] FIG. 1 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 14] FIG. 10 is a schematic diagram illustrating the configuration of a semiconductor device according to another embodiment of the present application. [Figure 15] 15 is a schematic cross-sectional view of the semiconductor device shown in FIG. 14 taken along line FF'. FIG. [Figure 16] FIG. 15 is a schematic cross-sectional view of the semiconductor device shown in FIG. 14 taken along line EE'. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, but it is clear that the described embodiments are only a part of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, all other embodiments that can be obtained by those skilled in the art without any creative efforts fall within the scope of protection of the present application.

[0027] In the description of the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood to indicate or imply relative importance or the number of technical features shown. Thus, a feature qualified by "first" or "second" may explicitly or implicitly include one or more features. In the description of the embodiments of the present application, "plurality" means two or more than two, unless expressly limited otherwise.

[0028] The following description is provided to enable any person skilled in the art to make and use the present application. In the following description, certain details are set forth for purposes of explanation. Those skilled in the art will be able to practice the present application without these specific details. In other instances, well-known processes are not described in detail so as to avoid obscuring the description of the embodiments of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed in the embodiments of the present application.

[0029] Gallium nitride semiconductor materials have been the focus of research due to their advantages, including a large band gap, high electron saturation drift velocity, high breakdown field strength, and high heat resistance. From the perspective of battery devices, gallium nitride materials are more suitable for the fabrication of high-temperature, high-frequency, high-voltage, and high-power devices than silicon and gallium arsenide, and show promising future applications.

[0030] In the 5G communications field, the bandwidth and high frequency requirements for semiconductor RF devices are extremely high, and the gate structure design and process flow are closely related to the frequency characteristics of semiconductor devices and directly affect the operating frequency of semiconductor devices. Therefore, gate structure design is particularly important in the design and manufacturing process of semiconductor devices and plays a key role in the reliability and stability of semiconductor device performance.

[0031] In GaN RF power amplifiers, achieving both device power and gain characteristics is a requirement for application circuits, and is also being pursued in GaN RF chips. Specifically, in conventional integrated circuit GaN RF chip designs, the gate power supply is located on one side of the device, resulting in a problem where the power supply on the other side of the gate is affected by gate resistance and reduced, resulting in a significant decrease in gain. Therefore, how to further improve the bandwidth and high-frequency performance of semiconductor devices while also improving semiconductor device gain and achieving a balance in power amplifier performance is an urgent issue that needs to be resolved.

[0032] The present application provides a semiconductor device, the semiconductor device including a substrate, an epitaxial structure, a gate, and a gate connection structure. The epitaxial structure is located on one side of the substrate. The gate is located on a side of the epitaxial structure away from the substrate. The gate extends along a first direction (the Y direction shown in FIG. 1 ) parallel to a plane in which the substrate is located. The gate includes a first gate sub-portion and a second gate sub-portion connected to each other and forms a Schottky contact with the epitaxial structure. The gate connection structure includes a first gate sub-connection portion and a second gate sub-connection portion connected to each other, and the second gate sub-connection portion is electrically connected to at least a portion of the gate. By providing the gate connection structure and electrically connecting the gate connection structure to at least a portion of the gate, it is possible to reduce gate resistance, improve gate gain, and increase the switching speed of the device.

[0033] For example, the substrate in the semiconductor device may be formed of at least one of silicon, sapphire, silicon carbide, and gallium arsenide. The epitaxial structure may be formed of one or more III-V nitrides, such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride, or indium aluminum gallium nitride. The gate contact structure may be composed of a conductive metal, e.g., a low-resistivity conductive material, thereby reducing gate resistance.

[0034] In some embodiments, a semiconductor device includes an active region and a non-active region surrounding the active region. The active region may be understood as a region below which two-dimensional electron gas, electrons, or holes reside, and whose operating state and characteristics are affected by an external circuit, and is the active operating region of the semiconductor device. The non-active region is involved in the operation of the semiconductor device, but whose operating state is not affected by the external circuit. For example, the non-active region may be provided with an extraction structure for an electrode of the active region, and the non-active region may be disposed surrounding the active region.

[0035] The gate connection structure and at least a portion of the gate may be electrically connected in the active region or in the non-active region. When the gate connection structure and at least a portion of the gate are electrically connected in the active region, the structure of the semiconductor device can be made more compact, contributing to the realization of a miniaturized semiconductor device. When the gate connection structure and at least a portion of the gate are electrically connected in the non-active region, on the one hand, the degree of freedom in the installation of the gate connection structure when electrically connected to the gate can be improved, and on the other hand, the influence on the installation method of the semiconductor device in the active region can be avoided, and the stability of the semiconductor device in the active region can be ensured. Therefore, those skilled in the art can choose whether the gate connection structure and at least a portion of the gate are electrically connected in the active region or the non-active region according to actual needs.

[0036] The semiconductor device of the present invention will be specifically described below with reference to several examples.

[0037] Fig. 1 is a schematic diagram of a semiconductor device according to an embodiment of the present application. Fig. 3 is a schematic cross-sectional diagram of the semiconductor device taken along line A-A' shown in Fig. 1. As shown in Figs. 1 and 3, a semiconductor device 10 includes an active region aa. The semiconductor device includes a substrate 110, an epitaxial structure 120 located on one side of the substrate 110, a gate 130 located on a side of the epitaxial structure 120 away from the substrate 110, extending along a first direction (the Y direction shown in FIG. 1) parallel to the plane in which the substrate 110 is located, the gate 130 including a first gate sub-portion and a second gate sub-portion connected to each other and forming a Schottky contact with the epitaxial structure 120, and at least one gate connection structure 140 including a first gate sub-connection portion 1401 and at least one second gate sub-connection portion 1402 connected to each other, and along the thickness direction of the semiconductor device 10 (the Z direction shown in FIG. 3), the gate 130 does not overlap with the first gate sub-connection portion 1401, and at least a portion of the gate 130 is electrically connected to the second gate sub-connection portion 1402 in the active region aa. For example, the first gate sub-portion is located in the active region aa, the second gate sub-connection portion 1402 is located in the active region aa, and at least a portion of the first gate sub-portion is electrically connected to the second gate sub-connection portion 1402 in the active region aa.

[0038] 1 illustrates an example in which semiconductor device 10 includes multiple gates, but it is understood that semiconductor device 10 may include only one gate 130. That is, it may have a single cell structure with source 150, gate 130, and drain 180.

[0039] The gate 130 forms good Schottky contact with the epitaxial structure 120 and, as a gate 130 structure of the semiconductor device 10, can control the conduction and blocking of the gate 130 in the semiconductor device 10, thereby controlling the operating state of the semiconductor device 10. The resistance of the gate 130 affects the charging and discharging speed of the junction capacitance, which in turn affects the switching speed of the semiconductor device 10. That is, the smaller the resistance of the gate 130, the faster the switching speed of the semiconductor device 10. In this embodiment, the first gate sub-connection 1401 is located in the active region aa and has a relatively large area. It serves as the main adjustment structure for the gain of the gate 130, optimizing the electric field of the gate 130, reducing the resistance of the gate 130, improving the gain of the gate 130, and improving the switching speed. The second gate sub-connection part 1402 is located in the active region aa and functions as a sub-connection part between the gate 130 and the gate connection structure 140, ensuring a normal connection between the gate 130 and the gate connection structure 140 and reducing the resistance of the gate 130, thereby contributing to the realization of a miniaturized design for the semiconductor device.

[0040] It should be noted that the gate 130 forms a Schottky contact with the epitaxial structure 120, while the gate connection structure 140 does not form a Schottky contact with the epitaxial structure 120. Specifically, the gate connection structure 140 does not directly contact a conductive groove (e.g., a two-dimensional electron gas) within the epitaxial structure 120.

[0041] Along the thickness direction Z of the semiconductor device 10, the gate 130 does not overlap with the first gate sub-connection portion 1401. That is, along the second direction (the X direction shown in FIG. 1), the first gate sub-portion does not overlap with the first gate sub-connection portion 1401. That is, they are arranged offset from each other.

[0042] For example, still referring to FIG. 1, the gate connection structure 140 includes at least a second gate sub-connection 1402 located at the edge of the active area aa, and at least a portion of the gate 130 is electrically connected to the second gate sub-connection 1402 located at the edge of the active area aa.

[0043] Optionally, the minimum distance between the second gate sub-connection 1402 and the edge of the active region aa is L1, where L1≦5 μm. Specifically, the minimum distance L1 between the second gate sub-connection 1402 and the edge of the active region aa can be understood as the minimum distance to the edge of the active region aa when the second gate sub-connection 1402 extends to the edge of the active region aa along the first direction Y. By setting the minimum distance between the second gate sub-connection 1402 and the edge of the active region aa to a relatively small value, the installation of the second gate sub-connection 1402 can be prevented from affecting the normal installation and performance of the semiconductor device 10 in the active region aa, ensuring the normal operation of the semiconductor device 10 and satisfying the semiconductor device manufacturing process.

[0044] Optionally, and continuing to refer to FIG. 1 , the size of the first gate sub-connection 1401 along the second direction X is larger than the size of the gate 130. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. Specifically, the size of the first gate sub-connection 1401 along the second direction X being larger than the size of the gate 130 can be understood as the width of the first gate sub-connection 1401 along the second direction X being larger than the width of the gate 130 along the second direction X. Due to the large size of the first gate sub-connection 1401, the resistance of the first gate sub-connection 1401 is reduced, and by forming an electrical connection between the gate connection structure 140 and the gate 130, the electric field of the gate 130 can be fully optimized, the resistance of the gate 130 can be reduced, and the gain of the semiconductor device 10 can be improved.

[0045] For example, the size of the first gate sub-connection 1401 along the second direction X can be 2, 3, 3.2 times, or the like, the size of the gate 130. The embodiments of the present application are not limited to these. It is sufficient that the size of the first gate sub-connection 1401 is larger than the size of the gate 130 and can reduce the resistance of the gate 130. Furthermore, on the premise that the size requirements of the semiconductor device 10 and the device design requirements of the active region aa are met, the size of the first gate sub-connection 1401 in the second direction X can be designed as large as possible to reduce the resistance of the gate 130 as much as possible, optimize the electric field of the gate 130, and improve the switching speed and gain of the semiconductor device 10.

[0046] Optionally, and continuing to refer to FIG. 1 , the size of the second gate sub-connection 1402 in the first direction Y is larger than the size of the gate 130 in the active region aa in the second direction X. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. Specifically, the size of the second gate sub-connection 1402 in the first direction Y is larger than the size of the gate 130 in the active region aa in the second direction X, thereby achieving sufficient electrical connection between the second gate sub-connection 1402 and the gate 130, reducing the resistance of the gate connection structure 140, and allowing current to be quickly transferred to the first gate sub-connection 1401, thereby improving the switching speed and gain of the semiconductor device 10.

[0047] 1 , in some embodiments, at least a portion of the gate 130 has a larger size in the second direction X in the non-active region bb than in the active region aa. For example, the gate region away from the active region aa has a larger size in the second direction X in the non-active region bb than in the active region aa. This can further optimize the electric field between the gate 130 and the source 150. Furthermore, the radius of curvature of the gate 130 in the non-active region bb along the second direction X can be larger than the width of the gate 130 in the active region aa along the second direction X. This can reduce the difficulty of developer penetration from the edge to the center of the gate 130, thereby reducing display difficulty. Furthermore, appropriate compensation can be provided for the gate 130 corresponding to the corner positions at both ends of the source and drain, thereby compensating for or completely eliminating the problem of the gate 130 becoming narrower due to light diffraction.

[0048] Optionally, and continuing to refer to FIG. 1 , the included angle between the second gate subconnection 1402 and the first gate subconnection 1401 is α, where 80°≦α≦100°. Specifically, since the magnitude of the included angle α between the second gate subconnection 1402 and the first gate subconnection 1401 determines the installation space of the active region aa, when the included angle α is approximately perpendicular, the space of the active region aa occupied by the second gate subconnection 1402 in the first direction Y can be reduced, thereby achieving a miniaturized semiconductor device 10. For example, the included angle α between the second gate subconnection 1402 and the first gate subconnection 1401 may be 80°, 90°, 100°, etc.

[0049] 1, the first gate sub-connection portion 1401 and the second gate sub-connection portion 1402 may be disposed on the same layer, thereby simplifying the film layer structure of the semiconductor device 10 and contributing to the realization of a thinner and lighter semiconductor device 10. Furthermore, the first gate sub-connection portion 1401 and the second gate sub-connection portion 1402 may be integrally formed in the same process, thereby simplifying the manufacturing process of the semiconductor device 10, reducing manufacturing difficulty, and improving manufacturing efficiency.

[0050] Optionally, and continuing to refer to FIGS. 1 and 3 , the semiconductor device 10 further includes a source 150, which forms an ohmic contact with the epitaxial structure 120. Along the thickness direction Z of the semiconductor device 10, a first gate sub-connection 1401 overlaps the source 150 and is insulated from the source 150. For example, the first gate sub-connection 1401 can be located above the source 150 and overlap with the projection of the source 150. On the other hand, the overlap of the first gate sub-connection 1401 with the source 150 does not affect the extraction of the gate 130 signal. On the other hand, the overlap of the first gate sub-connection 1401 with the source 150 can reduce the area of ​​the semiconductor device 10.

[0051] 1 and 3, the source 150 may be connected to the back surface of the semiconductor device 10 via a source through-hole C. For example, the source through-hole C may pass through the substrate 110 and the epitaxial structure 120. That is, the source 150 is connected to the source signal input electrode D located on the side of the substrate 110 away from the epitaxial structure 120. That is, the source 150 is electrically connected to the source signal input electrode D via the source through-hole C. Furthermore, the first gate sub-connection portion 1401 may be located above the source through-hole C, thereby ensuring the stability of the source through-hole C region and enabling the semiconductor device 10 to operate normally.

[0052] Optionally, and still referring to FIG. 1 , the size of the first gate sub-connection portion 1401 in the second direction X is smaller than the size of the source 150 in the second direction X. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. Specifically, the size of the first gate sub-connection portion 1401 in the second direction X is smaller than the size of the source 150 in the second direction X, thereby reducing the parasitic capacitance between the gate connection structure 140 and the source 150, reducing the impact on the performance of the semiconductor device 10, and ensuring the normal operation of the device.

[0053] Optionally, and continuing to refer to FIG. 1 , the semiconductor device 10 further includes a drain 180 and a drain pad 190 connected to each other. The drain 180 forms an ohmic contact with the epitaxial structure 120. Along the first direction Y, the drain pad 190 is located on a second side of the active region aa. Along the first direction Y, the second gate sub-connection 1402 is located on a side of the active region aa that is closer to the drain pad 190. For example, the drain 180 in the active region aa may be connected to the drain pad 190 of the non-active region bb through a drain interconnect metal. Specifically, along the first direction Y, the drain pad 190 is located on the second side of the active region aa (i.e., the side closer to the second gate sub-connection 1402), i.e., the drain 180 can receive a voltage signal of the drain 180 through the drain pad 190, ensuring the normal operation of the semiconductor device 10. Furthermore, along the first direction Y, the second gate sub-connection portion 1402 is located on the side of the active region aa closer to the drain pad 190, which can further reduce the area of ​​the active region aa and achieve miniaturization of the semiconductor device 10.

[0054] Optionally, and continuing to refer to Figure 3, epitaxial structure 120 includes a stacked nucleation layer 1201, a buffer layer 1202, a channel layer 1203, and a barrier layer 1204. Channel layer 1203 and barrier layer 1204 form a heterojunction structure.

[0055] For example, nucleation layer 1201 is located between substrate 110 and buffer layer 1202, and the material of nucleation layer 1201 may be aluminum nitride, which serves as an adhesive for the subsequently grown semiconductor material layer.

[0056] For example, the buffer layer 1202 is located on the side of the nucleation layer 1201 away from the substrate 110, and the material of the buffer layer 1202 may be gallium nitride, and the buffer layer 1202 may contain iron atoms, thereby realizing high resistivity properties of the buffer layer 1202, preventing vertical leakage current, and improving pinch-off performance of the semiconductor device.

[0057] For example, the channel layer 1203 is located on the side of the buffer layer 1202 away from the substrate 110, and the material of the channel layer 1203 is a group III nitride, for example, Al x Ga 1-x N (where 0≦x<1). That is, at the interface between the channel layer 1203 and the barrier layer 1204, the conduction band energy of the channel layer 1203 is less than the conduction band energy of the barrier layer 1204. For example, x=0 indicates that the channel layer 1203 is GaN. The channel layer 1203 may also be InGaN or other III-nitrides such as AlInGaN. The channel layer 1203 may be undoped or unintentionally doped. The channel layer 1203 may also be a multi-layer structure, such as a superlattice, a combination of GaN, or AlGaN.

[0058] For example, the barrier layer 1204 is located on the side of the channel layer 1203 away from the substrate 110. The barrier layer 1204 may be AlN, AlInN, AlGaN, or AlInGaN. The barrier layer 1204 is sufficiently thick and has a sufficiently high Al content so that doping occurs at the interface between the channel layer 1203 and the barrier layer 1204, forming a significant carrier concentration. For example, the thickness of the barrier layer 1204 may be 20 nm, and the doping concentration of the Al composition may be 25%.

[0059] For example, the channel layer 1203 may include GaN and the barrier layer 1204 may include AlGaN, i.e., the material of the barrier layer 1204 may have a higher bandgap than the material of the channel layer 1203, and the channel layer 1203 may have a higher electron affinity than the barrier layer 1204. Due to the bandgap difference between the barrier layer 1204 and the channel layer 1203 and the piezoelectric effect at the interface between the barrier layer 1204 and the channel layer 1203, a two-dimensional electron gas (2DEG) may be formed in the channel layer 1203 and the barrier layer 1204.

[0060] 1 and 3, it can be seen that the epitaxial structure 120 may further include a cap layer, which is located on a side of the barrier layer 1204 away from the substrate 110. The cap layer can reduce surface states, reduce surface leakage and suppress current collapse in subsequent semiconductor devices, thereby improving the performance and reliability of the epitaxial structure 120 and the semiconductor device 10.

[0061] In the embodiments of the present application, by providing at least one gate connection structure and electrically connecting at least a portion of the gate to the second gate sub-connection in the active region, the influence of the gate resistance can be reduced, and the switching speed and gain can be improved. Furthermore, by electrically connecting the gate connection structure to the active region rather than the non-active region, the structure of the semiconductor device can be made compact, contributing to the realization of miniaturized semiconductor devices.

[0062] FIG. 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional diagram of the semiconductor device shown in FIG. 2 taken along line B-B'. As shown in FIGS. 2 to 4, the semiconductor device 10 includes an active region aa and a non-active region bb surrounding the active region aa. The semiconductor device 10 includes a substrate 110, an epitaxial structure 120 located on one side of the substrate 110, and a gate 130 located on the side of the epitaxial structure 120 away from the substrate 110, extending along a first direction (the Y direction shown in FIG. 1) parallel to a plane in which the substrate 110 is located, the gate 130 including a first gate sub-portion 1301 forming a Schottky contact with the epitaxial structure 120 and a second gate sub-portion 1302 located in the non-active region bb, the gate 130 being connected to each other. and at least one gate connection structure 140 including a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 electrically connected to each other, the second gate sub-connection portion 1402 being located in the non-active region bb, wherein along the thickness direction of the semiconductor device 10 (the Z direction shown in FIG. 3 ), the first gate sub-portion 1301 does not overlap with the first gate sub-connection portion 1401, and at least a portion of the second gate sub-portion 1302 is electrically connected to the second gate sub-connection portion 1402.

[0063] 2 illustrates an example in which semiconductor device 10 includes multiple gates, but semiconductor device 10 may include only one gate 130. That is, it is understood that the cell structure may be a single cell structure having source 150, gate 130, and drain 180.

[0064] The gate 130 includes a first gate sub-portion 1301 and a second gate sub-portion 1302 connected to each other, and the gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other. The first gate sub-portion 1301 is located in the active region aa and includes a portion that forms a Schottky contact with the epitaxial structure 120 and further includes a portion that extends along the first direction Y and connects to the gate pad 170. The first gate sub-portion 1301 functions as the gate 130 structure of the semiconductor device 10 and controls the conduction and blocking of the gate 130 in the semiconductor device 10, thereby controlling the operating state of the semiconductor device 10. The first gate sub-connection portion 1401 is located in the active region aa and has a relatively large area. It functions as a main adjustment structure for the gain of the gate, reducing the resistance of the gate 130 and improving the gain of the gate 130. The second gate sub-portion 1302 and the second gate sub-connection portion 1402 are both located in the non-active region bb and function as sub-connections between the gate 130 and the gate connection structure 140, ensuring a normal connection between the gate 130 and the gate connection structure 140 and thereby reducing the resistance of the gate 130. Furthermore, the second gate sub-portion 1302 and the second gate sub-connection portion 1402 are electrically connected in the non-active region bb, which does not affect the installation manner of the semiconductor device 10 in the active region aa or the normal operation and performance of the active region aa, thereby ensuring stable performance of the semiconductor device 10. Furthermore, since the non-active region bb has a relatively large installation space, the second gate sub-portion 1302 and the second gate sub-connection portion 1402 located in the non-active region bb have a relatively large design freedom, which is convenient for improving the connection stability between the second gate sub-portion 1302 and the second gate sub-connection portion 1402.

[0065] It should be noted that the gate 130 forms a Schottky contact with the epitaxial structure 120, while the gate connection structure 140 does not form a Schottky contact with the epitaxial structure 120. Specifically, the gate connection structure 140 does not directly contact a conductive groove (e.g., a two-dimensional electron gas) in the epitaxial structure 120.

[0066] Note that the first gate sub-portion 1301 does not overlap the first gate sub-connection portion 1401 along the thickness direction Z of the semiconductor device 10. In other words, the first gate sub-portion 1301 does not overlap the first gate sub-connection portion 1401 along the second direction (the X direction shown in FIG. 2). In other words, they are arranged offset from each other.

[0067] Optionally, and continuing to refer to FIG. 2 , the size of the first gate sub-connection portion 1401 along the second direction X is larger than the size of the first gate sub-portion 1301. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. Specifically, the size of the first gate sub-connection portion 1401 along the second direction X is larger than the size of the first gate sub-portion 1301, which can be understood as the width of the first gate sub-connection portion 1401 along the second direction X being larger than the width of the first gate sub-portion 1301 along the second direction X. Due to the larger size of the first gate sub-connection portion 1401, the resistance of the first gate sub-connection portion 1401 is reduced, and by forming an electrical connection between the gate connection structure 140 and the gate 130, the gate resistance can be sufficiently reduced and the gain of the semiconductor device 10 can be improved.

[0068] For example, the size of the first gate sub-connection portion 1401 along the second direction X may be larger than the size of the first gate sub-portion 1301. For example, the size of the first gate sub-connection portion 1401 may be two times, three times, or 3.2 times the size of the first gate sub-portion 1301. The embodiments of the present application are not limited thereto. It is sufficient that the size of the first gate sub-connection portion 1401 is larger than the size of the first gate sub-portion 1301 and can reduce the resistance of the gate 130. Furthermore, the size of the first gate sub-connection portion 1401 in the second direction X is designed to be as large as possible, provided that the size requirements of the semiconductor device 10 and the device design requirements of the active region aa are met. This reduces the gate resistance as much as possible.

[0069] 5 is a schematic diagram of a semiconductor device according to another embodiment of the present application. The difference between FIG. 5 and FIG. 2 is the structure of the second gate sub-portion 1302. Referring to FIG. 5, along the first direction Y, the size of the second gate sub-portion 1302 is larger than the size of the second gate sub-connection portion 1402. The second gate sub-portion 1302 includes a first sub-portion 13021 and a second sub-portion 13022. The first sub-portion 13021 is located on the side of the second sub-portion 13022 away from the active region aa. Along the second direction X, the size of the first sub-portion 13021 is larger than the size of the second sub-portion 13022. The second gate sub-connection portion 1402 is electrically connected to the first sub-portion 13021. The second direction intersects with the first direction and is parallel to the plane in which the substrate lies.

[0070] Specifically, the size of the second gate sub-portion 1302 in the first direction Y is larger than the size of the second gate sub-connection portion 1402 in the first direction Y, thereby ensuring a contact area between the second gate sub-portion 1302 and the second gate sub-connection portion 1402. Furthermore, the second gate sub-portion 1302 includes a first sub-portion 13021 and a second sub-portion 13022, where the first sub-portion 13021 is located on a side of the second sub-portion 13022 away from the active region aa, and the size of the first sub-portion 13021 is larger than the size of the second sub-portion 13022 along the second direction X. The second gate sub-connection portion 1402 is electrically connected to the first sub-portion 13021, i.e., the connection position between the second gate sub-connection portion 1402 and the second gate sub-portion 1302 is set in a wider portion of the second gate sub-portion 1302, thereby improving the stability of the connection and facilitating a stronger connection and further stabilization of the structure, while reducing the connection resistance and difficulty of connection between the second gate sub-portion 1302 and the second gate sub-connection portion 1402.

[0071] Optionally, and still referring to FIG. 5 , the size of the second gate sub-connection portion 1402 in the first direction Y is smaller than the size of the first gate sub-connection portion 1401 in the second direction X. The second direction X intersects with the first direction Y and is parallel to the plane on which the substrate 110 is located. Specifically, the size of the second gate sub-connection portion 1402 in the first direction Y is smaller than the size of the first gate sub-connection portion 1401 in the second direction X, thereby reducing the installation space of the non-active region bb and contributing to the realization of a miniaturized semiconductor device 10.

[0072] Optionally, and continuing to refer to FIG. 2 , the included angle between the second gate subconnection 1402 and the first gate subconnection 1401 is α, where 80°≦α≦100°. Specifically, since the magnitude of the included angle α between the second gate subconnection 1402 and the first gate subconnection 1401 determines the installation space of the non-active region bb, if the included angle α is approximately perpendicular, the installation space of the non-active region bb can be reduced, thereby achieving a miniaturized semiconductor device 10. For example, the included angle α between the second gate subconnection 1402 and the first gate subconnection 1401 may be 80°, 90°, 100°, etc.

[0073] Optionally, and still referring to FIG. 2, the first gate sub-connection 1401 and the second gate sub-connection 1402 are located on the same layer.

[0074] Optionally, and continuing to refer to FIGS. 2 and 3 , the semiconductor device 10 further includes a source 150, which forms an ohmic contact with the epitaxial structure 120. Along the thickness direction Z of the semiconductor device 10, a first gate sub-connection 1401 overlaps the source 150 and is insulated from it. The source 150 may be connected to the back surface of the semiconductor device 10 via a source through-hole C. For example, the source through-hole C may penetrate the substrate 110 and the epitaxial structure 120. That is, the source 150 is connected to the source signal input electrode D on the side of the substrate 110 away from the epitaxial structure 120. That is, the source 150 is electrically connected to the source signal input electrode D via the source through-hole C. Optionally, and continuing to refer to FIG. 2 , the size of the first gate sub-connection 1401 in the second direction X is smaller than the size of the source 150 in the second direction X. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 lies.

[0075] Optionally, and continuing to refer to FIG. 2 , the semiconductor device 10 further includes a drain 180 and a drain pad 190 connected to each other. The drain 180 forms an ohmic contact with the epitaxial structure 120. The drain pad 190 is located on a second side of the active region aa along the first direction Y. The second gate sub-connection 1402 is located between the active region aa and the drain pad 190 along the first direction Y. For example, the drain 180 in the active region aa may be connected to the drain pad 190 in the non-active region bb through a drain interconnect metal. Specifically, the drain pad 190 is located on the second side of the active region aa along the first direction Y. That is, the drain 180 can receive a voltage signal from the drain 180 through the drain pad 190, ensuring the normal operation of the semiconductor device 10. Furthermore, along the first direction Y, the second gate sub-connection 1402 is located between the active area aa and the drain pad 190, reducing the area of ​​the non-active area bb, thereby reducing the area of ​​the semiconductor device 10 and achieving device miniaturization.

[0076] Optionally, and continuing to refer to FIG. 3, the epitaxial structure 120 includes a nucleation layer 1201, a buffer layer 1202, a channel layer 1203, and a barrier layer 1204, which are stacked one on top of the other. The channel layer 1203 and the barrier layer 1204 form a heterojunction structure. For a detailed description of the epitaxial structure 120, please refer to FIG. 1. This description will not be repeated in this example.

[0077] In summary, the semiconductor device according to the embodiment of the present application includes at least one gate connection structure electrically connected to at least a portion of the gate, thereby reducing gate resistance, improving gate gain, and reducing leakage current. Furthermore, the gate connection structure is electrically connected to the gate in the inactive region, which, on the one hand, improves the flexibility of the installation when the gate connection structure is electrically connected to the gate, and, on the other hand, avoids affecting the installation method of the semiconductor device in the active region, thereby ensuring the stability of the semiconductor device in the active region.

[0078] In some embodiments, the gate connection structure 140 is electrically connected to the gate 130 located on one side of the first gate sub-connection portion 1401 along the second direction X via the second gate sub-connection portion 1402. As shown in FIGS. 1 and 2, the shape of the gate connection structure 140 may be approximately "L" shaped. This ensures a simple installation method for the gate connection structure 140, while the gate connection structure 140 is electrically connected to the gate 130 located on one side thereof, thereby reducing the resistance of the gate 130 and optimizing the electric field of the gate 130.

[0079] In some embodiments, the semiconductor device includes multiple gates 130, arranged along a second direction X. The gate connection structure 140 is electrically connected to the gates 130 located on both sides of the first gate sub-connection 1401 along the second direction X via the second gate sub-connection 1402. As shown in FIG. 6 , the second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. FIG. 6 is a schematic diagram of a semiconductor device according to another embodiment of the present application. As shown in FIG. 6 , the second gate sub-connection 1402 is electrically connected to the gates 130 in the non-active region. As shown in FIG. 6 , the gate connection structure 140 is electrically connected to the gates 130 located on both sides of the first gate sub-connection 1401 along the second direction X via the second gate sub-connection 1402. For example, the shape of the gate connection structure 140 may be approximately "L" shaped. That is, one gate connection structure 140 forms an electrical connection with the gates 130 located on both sides of it. On the one hand, the number of gates 130 electrically connected to the gate connection structure 140 is increased, which can sufficiently reduce the resistance of the gates 130 and reduce the leakage current of the gates 130, and on the other hand, the installation method of the gate connection structure 140 is simplified, which can reduce the influence on other devices in the active region aa of the semiconductor device 10 and can also ensure a simplified manufacturing process of the gate connection structure 140. Although Figure 6 only illustrates the example where the second gate sub-connection portion 1402 is electrically connected to the gate 130 in the non-active region, it can be understood that the same applies when the second gate sub-connection portion 1402 is electrically connected to the gate 130 in the active region.

[0080] In another possible embodiment, the shape of the gate connection structure 140 may be approximately "L" shaped, in which case the two gate connection structures 140 can form an approximately "back-to-back" installation manner, thereby ensuring that any gate 130 can form an electrical connection with the gate connection structure 140, and can further reduce the gate resistance and gate leakage current.

[0081] 7 is a schematic diagram of a semiconductor device according to another embodiment of the present application. As shown in FIG. 7, the gate connection structure 140 further includes a third gate sub-connection portion 1403, which is located in the active region aa and electrically connected to the first gate sub-connection portion 1401 and the first gate sub-portion 1301, respectively. Specifically, the third gate sub-connection portion 1403 is located in the active region aa and electrically connected to the first gate sub-connection portion 1401 and the first gate sub-portion 1301, thereby improving the connection stability and reducing the connection resistance between the gate connection structure 140 and the gate 130. Optionally, if the gate connection structure 140 includes only one third gate sub-connection portion 1403, the third gate sub-connection portion 1403 is located away from the second gate sub-connection portion 1402. Optionally, when the gate connection structure 140 includes a plurality of third gate sub-connections 1403, the plurality of third gate sub-connections 1403 are evenly distributed in the active region aa, and at least one third gate sub-connection 1403 is located on the side away from the second gate sub-connection 1402. Although Figure 7 only illustrates the case where the second gate sub-connection 1402 is electrically connected to the gate 130 in the non-active region, it can be understood that the same applies when the second gate sub-connection 1402 is electrically connected to the gate 130 in the active region.

[0082] In some embodiments, the gate connection structure 140 is connected to the gate 130 through at least two channels, thereby connecting the gate connection structure 140 in parallel with the gate 130. Optionally, the gate connection structure 140 may be connected to the gate 130 through a second gate sub-connection 1402 and a gate pad 170 (as shown in FIG. 1 or FIG. 2). Optionally, the gate connection structure 140 may be connected to the gate 130 through at least two second gate sub-connections 1402 (as shown in FIG. 7). For example, the gate connection structure 140 may be connected to the gate 130 through a second gate sub-connection 1402 and a third gate sub-connection 1403. The second gate sub-connection 1402 is located in the active region aa or the non-active region bb, and the third gate sub-connection 1403 is located in the active region aa.

[0083] 8 is a schematic diagram of a semiconductor device according to another embodiment of the present application. As shown in FIG. 8, based on FIG. 7, semiconductor device 10 further includes source 150 and source field plate 160. Source field plate 160 includes field plate body 1601 and field plate branch 1602. One end of field plate branch 1602 is electrically connected to field plate body 1601, and the other end of field plate branch 1602 is electrically connected to source 150, thereby achieving electrical connection between source field plate 160 and source 150. Field plate branch 1602 is offset from third gate sub-connection 1403, i.e., their projections do not overlap, preventing overlap between field plate branch 1602 and third gate sub-connection 1403 and avoiding mutual interference. Although Figure 8 only illustrates an example in which the second gate sub-connection portion 1402 is electrically connected to the gate 130 in the inactive region, it can be understood that the same applies when the second gate sub-connection portion 1402 is electrically connected to the gate 130 in the active region.

[0084] Optionally, and continuing to refer to FIG. 8 , the field plate body 1601 may at least partially overlap the gate 130, for example, overlapping the side of the gate 130 closer to the drain 180, thereby allowing the source field plate 160 to extend toward the gate 130, further improving the modulation effect of the source field plate 160 on the electric field, reducing the electric field accumulation on the side of the gate 130 closer to the drain 180, reducing the probability of breakdown on the side of the gate 130 closer to the drain 180, and improving the reliability of the semiconductor device 10.

[0085] For example, along the thickness direction of semiconductor device 10, source field plate 160 covers the edge of gate 130 away from source 150, and the overlap area between source field plate 160 and gate 130 is S1, the area of ​​gate 130 is S2, and S1 / S2≦20%. That is, field plate body 1601 can overlap gate 130 partially at most.

[0086] Optionally, the source field plate 160 is offset from the gate along the thickness of the semiconductor device 10, thereby reducing electric field buildup on the side of the gate 130 closer to the drain 180, reducing the probability of breakdown on the side of the gate 130 closer to the drain 180 and improving the reliability of the semiconductor device.

[0087] Optionally, and continuing to refer to FIG. 8 , the semiconductor device 10 further includes a gate pad 170, which is located in the non-active region bb on a first side (i.e., the side away from the second gate sub-connection 1402) of the active region aa along the first direction Y, and the first gate sub-connection 1301 and the first gate sub-connection 1401 are both electrically connected to the gate pad 170. The semiconductor device 10 further includes a source field plate 160, which is electrically connected to the source 150. The first gate sub-connection 1401 and the gate 130 are located in the same layer, or the first gate sub-connection 1401 and the source field plate 160 are located in the same layer, or the first gate sub-connection 1401 and the gate pad 170 are located in the same layer. For example, along the first direction Y, the gate 130 (or the first gate sub-portion 1301) in the active region aa may be connected to the gate pad 170 in the non-active region bb through a gate interconnect metal. The gate 130 can receive a voltage signal for the gate 130 through the gate pad 170 to ensure the normal operation of the semiconductor device 10.

[0088] Specifically, the first gate subconnection 1401 and the gate 130 are disposed on the same layer, or the first gate subconnection 1401 and the source field plate 160 are disposed on the same layer, or the first gate subconnection 1401 and the gate pad 170 are disposed on the same layer, thereby simplifying the process flow and, on the one hand, avoiding the installation of unnecessary film layers and simplifying the mask process, and, on the other hand, being advantageous for realizing a thin and lightweight design of the semiconductor device 10. Note that, when the first gate subconnection 1401 and the source field plate 160 are disposed on the same layer, the field plate branch 1602 needs to be offset from the second gate subconnection 1402 (or the third gate subconnection 1403) to avoid overlapping between the field plate branch 1602 and the second gate subconnection 1402 (or the third gate subconnection 1403) and avoiding mutual interference.

[0089] 9 is a schematic diagram of a semiconductor device according to another embodiment of the present application. Although FIG. 9 illustrates an example in which the second gate sub-connection portion 1402 is electrically connected to the gate 130 in the non-active region, it can be understood that the same applies to the case in which the second gate sub-connection portion 1402 is electrically connected to the gate 130 in the active region.

[0090] 9, the second gate sub-connection 1402 is electrically connected to the gate 130 in the non-active region. As shown in FIG. 9, the semiconductor device 10 further includes a source 150, which forms an ohmic contact with the epitaxial structure 120. Along the second direction X, the first gate sub-connection 1401 is located on a side of the source 150 away from the gate 130, and the first gate sub-connection 1401 is located between two adjacent sources 150, such that two adjacent transistor cells share the same first gate sub-connection 1401. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. Along the second direction X, a constant distance is maintained between the first gate sub-connection 1401 and two adjacent sources 150, and the intervals are equal.

[0091] 9 , along the second direction X, the first gate sub-connection 1401 is located on the side of the source 150 away from the gate 130, and the first gate sub-connection 1401 is located between two adjacent sources 150, so that two adjacent transistor cells share the same first gate sub-connection 1401. As a result, the semiconductor device 10 does not have an arrangement in which adjacent transistor cells share a single source, but has an arrangement such as drain 180, gate 130, source 150, gate connection structure 140, source 150, gate 130, and drain 180. In other words, adjacent transistor cells share a single first gate sub-connection 1401, and each cell has a source 150, gate 130, and drain 180, which reduces the effect of gate resistance, improves gain, and reduces leakage current.

[0092] Optionally, and still referring to FIG. 9 , the size L of the source 150 along the second direction X satisfies L≦60 μm, which is smaller than the size of the source in the existing semiconductor device. It can be seen that the embodiment of the present application divides the source of the prior art into two source sub-portions, and the two adjacent source sub-portions accommodate the first gate sub-connection portion 1401 at a certain distance, thereby reducing the area and cost of the semiconductor device 10.

[0093] In the above embodiments, along the thickness direction of the semiconductor device, the gate 130 does not overlap with the first gate sub-connection 1401. In some embodiments, the first gate sub-connection 1401 can at least partially overlap with the gate 130 to reduce the area of ​​the semiconductor device. See the following examples for a detailed description.

[0094] Fig. 10 is a schematic diagram of a semiconductor device according to another embodiment of the present application. Fig. 11 is a schematic cross-sectional diagram of the semiconductor device shown in Fig. 10 taken along line A-A'. Fig. 12 is a schematic cross-sectional diagram of the semiconductor device shown in Fig. 10 taken along line B-B'. As shown in Figs. 10 to 12, the semiconductor device 10 includes an active region aa and a non-active region bb surrounding the active region aa. The semiconductor device 10 comprises a substrate 110, an epitaxial structure 120 located on a side of the epitaxial structure 120 remote from the substrate 110, a gate 130 located on the side of the epitaxial structure 120 remote from the substrate 110, extending in a first direction (the Y direction shown in FIG. 1 ) that intersects a second direction X and is parallel to a plane in which the substrate 110 is located, the gate 130 including a first gate sub-portion 1301 that forms a Schottky contact with the epitaxial structure 120 and a second gate sub-portion 1302 located in a non-active region bb, the first gate sub-portion 1301 and the second gate sub-portion 1302 being connected to each other, and at least one gate connection structure 140 located on the side of the gate 130 remote from the substrate 110. Further, the gate connection structure 140 includes a first gate sub-connection portion 1401 and a second gate sub-connection portion 1402 connected to each other, the second gate sub-connection portion 1402 is located in the non-active region bb, and along the thickness direction of the semiconductor device (the Z direction shown in FIG. 11 ), the first gate sub-connection portion 1401 at least partially overlaps with the first gate sub-portion 1301, the second gate sub-connection portion 1402 at least partially overlaps with the second gate sub-portion 1302, and the second gate sub-connection portion 1402 is electrically connected to at least a portion of the second gate sub-portion 1302.

[0095] 10 illustrates an example in which the semiconductor device 10 includes multiple gates 130, but it is understood that the semiconductor device 10 may include only one gate 130. That is, the cell structure may be a single cell structure having a source 150, a gate 130, and a drain 180.

[0096] Specifically, the gate 130 includes a first gate sub-portion 1301 and a second gate sub-portion 1302 connected to each other. The first gate sub-portion 1301 forms a Schottky contact with the epitaxial structure 120, and the second gate sub-portion 1302 is located in the inactive region bb and functions as the gate 130 structure of the semiconductor device 10, controlling the conduction and blocking of the gate 130 in the semiconductor device 10 and thereby controlling the operating state of the semiconductor device 10. The first gate sub-connection portion 1401 is located in the active region aa and has a relatively large area. It functions as the main adjustment structure for the gain of the gate 130, reducing the resistance of the gate 130 and improving the gain of the gate 130. The second gate sub-section 1302 and the second gate sub-connection section 1402 are both located in the non-active region bb and function as sub-connections between the gate 130 and the gate connection structure 140, ensuring a normal connection between the gate 130 and the gate connection structure 140 and thereby reducing the resistance of the gate 130. Furthermore, the second gate sub-connection section 1402 is electrically connected to at least a portion of the second gate sub-section 1302 and can reduce the resistance of the gate 130, thereby reducing the effect of the resistance of the gate 130, improving the gain, and increasing the switching speed of the device. Furthermore, along the thickness direction Z of the semiconductor device 10, the first gate sub-connection portion 1401 at least partially overlaps with the first gate sub-portion 1301, and the second gate sub-connection portion 1402 at least partially overlaps with the second gate sub-portion 1302, which, on the one hand, is advantageous in that the second gate sub-connection portion 1402 is electrically connected to at least a portion of the second gate sub-portion 1302, and, on the other hand, can reduce the area of ​​the semiconductor device 10, make the structure of the semiconductor device 10 compact, and contribute to realizing a miniaturized device design.

[0097] Optionally, and continuing to refer to FIGS. 10 and 12 , at least a portion of the second gate sub-portion 1302 is electrically connected to the second gate sub-connection portion 1402 through a connection via M. Along the second direction X, the size of the connection via M is smaller than the size of the second gate sub-portion 1302 and the size of the second gate sub-connection portion 1402. Specifically, at least a portion of the second gate sub-portion 1302 is electrically connected to the second gate sub-connection portion 1402 in the non-active region bb through the connection via M, which does not affect the installation manner of the semiconductor device 10 in the active region aa or the normal operation of the semiconductor device 10 in the active region aa, thereby ensuring stable performance of the semiconductor device 10. Furthermore, since the non-active region bb has a relatively large installation space, the second gate sub-portion 1302 and the second gate sub-connection portion 1402 have a relatively large design freedom, which is convenient for improving the connection stability between the second gate sub-portion 1302 and the second gate sub-connection portion 1402. Along the second direction X, the size of the connection via M is smaller than the size of the second gate sub-portion 1302 and the size of the second gate sub-connection portion 1402, thereby ensuring that the second gate sub-connection portion 1402 and the second gate sub-portion 1302 are fully electrically connected, and can further reduce the resistance of the gate 130 and the leakage current of the gate 130.

[0098] Optionally, and continuing to refer to FIGS. 10 and 11 , the source 150 may be connected to the back surface of the semiconductor device 10 via a source through-hole C. For example, the source through-hole C may pass through the substrate 110 and the epitaxial structure 120. That is, the source 150 is connected to the source signal input electrode D on the side of the substrate 110 away from the epitaxial structure 120. That is, the source 150 is electrically connected to the source signal input electrode D through the source through-hole C. Furthermore, the first gate sub-connection portion 1401 may be located above the source through-hole C, thereby ensuring the stability of the source through-hole C region and enabling the semiconductor device 10 to operate normally.

[0099] Optionally, and still referring to FIG. 10 , the semiconductor device 10 further includes a gate pad 170. The gate pad 170 is located in the non-active region bb on the first side of the active region aa along the first direction, and the first gate sub-unit 1301 and the first gate sub-connection unit 1401 are both electrically connected to the gate pad 170. The first gate sub-connection unit 1401 and the gate pad 170 are disposed in the same layer. For example, along the first direction Y, the gate 130 in the active region aa may be connected to the gate pad 170 in the non-active region bb through a gate interconnection metal. The first gate sub-unit 1301 receives a voltage signal of the gate 130 via the gate pad 170, which can ensure the normal operation of the semiconductor device 10. Specifically, the first gate sub-connection portion 1401 and the gate pad 170 are disposed on the same layer, which simplifies the process flow; on the one hand, the disposition of unnecessary film layers is avoided and the mask process is simplified; and on the other hand, it is advantageous for realizing a thin and lightweight design of the semiconductor device 10.

[0100] Optionally, and continuing to refer to FIG. 10 , the semiconductor device 10 further includes a drain 180 and a drain pad 190 connected to each other, where the drain 180 forms an ohmic contact with the epitaxial structure 120. Along the first direction Y, the pad of the drain 180 is located on a second side of the active region aa. Along the first direction Y, the second gate sub-connection 1402 is located between the active region aa and the drain pad 190. For example, the drain 180 in the active region aa may be connected to the drain pad 190 in the non-active region bb through a drain interconnect metal. Specifically, along the first direction Y, the drain pad 190 is located on the second side of the active region aa. That is, the drain 180 can receive a voltage signal of the drain 180 through the drain pad 190, ensuring the normal operation of the semiconductor device 10.

[0101] Furthermore, along the first direction Y, the second gate sub-connection portion 1402 is located between the active area aa and the drain pad 190, thereby reducing the area of ​​the non-active area bb, further reducing the area of ​​the semiconductor device 10, and achieving device miniaturization.

[0102] Optionally, and continuing to refer to FIG. 11 , the epitaxial structure 120 includes a nucleation layer 1201, a buffer layer 1202, a channel layer 1203, and a barrier layer 1204, which are stacked one on top of the other. The channel layer 1203 and the barrier layer 1204 form a heterojunction structure. For a detailed description of the epitaxial structure 120, please refer to the epitaxial structure 120 in FIG. 1 , and therefore, a redundant description will not be provided in this embodiment.

[0103] In summary, the semiconductor device according to the embodiment of the present application includes at least one gate connection structure electrically connected to at least a portion of the second gate sub-connection portion through the second gate sub-connection portion, thereby reducing the gate resistance, improving the gate gain, and increasing the switching speed of the device. Furthermore, the first gate sub-connection portion at least partially overlaps with the first gate sub-connection portion, thereby reducing the area of ​​the semiconductor device and making the structure of the semiconductor device more compact, which is advantageous for realizing a miniaturized device design.

[0104] Optionally, the gate connection structure 140 covers the gate 130 along the thickness direction of the semiconductor device. For example, the gate connection structure 140 can be located above the gate 130 and overlap the projection of the gate, which is beneficial for the electrical connection between the gate connection structure 140 and the gate 130, improves the stability of the electrical connection, and ensures the normal performance of the semiconductor device 10, while reducing the size of the active region aa along the second direction X and realizing the miniaturization of the semiconductor device 10.

[0105] 13 is a schematic diagram of a semiconductor device according to another embodiment of the present application. As shown in FIG. 13, the second gate sub-portion 1302 includes a first sub-portion 13021 and a second sub-portion 13022. The first sub-portion 13021 is located on the side of the second sub-portion 13022 away from the active region aa, and the size of the first sub-portion 13021 is larger than the size of the second sub-portion 13022 along the second direction X. The second direction X intersects with the first direction Y and is parallel to the plane in which the substrate 110 is located. The second gate sub-connection portion 1402 is electrically connected to the first sub-portion 13021. In other words, the connection position between the second gate sub-connection portion 1402 and the second gate sub-portion 1302 is set in a wider portion of the second gate sub-portion 1302, thereby improving the stability of the connection and facilitating a stronger connection and further stabilization of the structure, while reducing the connection resistance and difficulty of connection between the second gate sub-connection portion 1402 and the second gate sub-portion 1302.

[0106] 14 is a schematic diagram of a semiconductor device according to another embodiment of the present application. As shown in FIG. 14, the semiconductor device 10 further includes a source 150 and a source field plate 160, and the source field plate 160 is located between the film layer in which the gate 130 is located and the film layer in which the gate connecting structure 140 is located.

[0107] 14 , for example, source field plate 160 overlaps the side of gate 130 closer to drain 180, thereby causing source field plate 160 to extend toward gate 130, further improving the modulation effect of source field plate 160 on the electric field, reducing electric field accumulation on the side of gate 130 closer to drain 180, and reducing the probability of breakdown on the side of gate 130 closer to drain 180, thereby improving the reliability of semiconductor device 10. For example, source field plate 160 can include a field plate body 1601 and a field plate branch 1602 connected to each other, with one end of field plate branch 1602 electrically connected to field plate body 1601 and the other end of field plate branch 1602 electrically connected to source 150, thereby achieving electrical connection between source field plate 160 and source 150.

[0108] 15 is a schematic cross-sectional view taken along line F-F' of the semiconductor device shown in FIG. 14. Continuing to refer to FIGS. 14 and 15, the source field plate 160 is located between the film layer in which the source 150 is located and the film layer in which the gate 130 is located; that is, the gate 130, the source field plate 160, and the gate connecting structure 140 are all located in different layers. This ensures, on the one hand, a relatively large degree of freedom in the placement of different structures located in the active region aa, and, on the other hand, can reduce mutual interference.

[0109] Optionally, continuing to refer to FIG. 14 , along the first direction Y, the size of the second gate sub-portion 1302 is larger than the size of the source field plate 160 in the non-active region bb, and the size of the second gate sub-connection portion 1402 is larger than the size of the source field plate 160 in the non-active region bb. That is, along the first direction Y, the extension length of the second gate sub-portion 1302 and the second gate sub-connection portion 1402 in the non-active region bb is longer than the extension length of the source field plate 160 in the non-active region bb. That is, there is no need to consider the influence caused by the source field plate 160 covering the gate 130, and the size and position of the source field plate 160 and the gate connection structure 140 can be freely designed, thereby improving the connection stability between the gate connection structure 140 and the gate 130 and optimizing the performance of the device.

[0110] Optionally, FIG. 16 is a cross-sectional schematic diagram of the semiconductor device shown in FIG. 14 taken along line E-E'. As shown in FIGS. 16 and 16B, the semiconductor device 10 further includes a first dielectric layer 210 located between the film layer on which the source field plate 160 is located and the film layer on which the gate 130 is located, and a second dielectric layer 220 located between the film layer on which the source field plate 160 is located and the film layer on which the gate connecting structure 140 is located. That is, the source field plate 160, the gate 130, and the gate connecting structure 140 are located in different film layers, respectively, to avoid mutual interference. Along the thickness direction Z of the semiconductor device 10, the source field plate 160 overlaps the first gate sub-portion 1301, and the thickness d1 of the first dielectric layer 210 satisfies d1≧300 nm, and / or the source field plate 160 overlaps the first gate sub-connection portion 1401, and the thickness d2 of the second dielectric layer 220 satisfies d2≧300 nm. The overlap of source field plate 160 with first gate sub-section 1301 and / or the overlap of source field plate 160 with first gate sub-connection 1401 can reduce the area of ​​semiconductor device 10 and enable device miniaturization. In addition, increasing the thickness of first dielectric layer 210 or second dielectric layer 220 (e.g., d1≧300 nm and / or d2≧300 nm) can reduce the parasitic capacitance between source field plate 160 and first gate sub-section 1301 and / or first gate sub-connection 1401, thereby reducing the impact on the performance of semiconductor device 10 and ensuring normal operation of the device.

[0111] 16 only shows a technical solution in which the source field plate 160 overlaps both the first gate sub-section 1301 and the first gate sub-connection 1401. This is used for explanation purposes only and does not limit the present application. In other embodiments, the source field plate 160 overlaps only the first gate sub-section 1301, or the source field plate 160 intersects only the first gate sub-connection 1401.

[0112] Optionally, and continuing to refer to Figures 14 and 16, the gate connection structure 140 is electrically connected to the gate 130 via a connection pillar 200, and the connection pillar 200 includes a first connection pillar sub-section 201 located in the first dielectric layer 210 and a second connection pillar sub-section 202 located in the second dielectric layer 220, and the first connection pillar sub-section 201 and the second connection pillar sub-section 202 are integrally located and are integrally located with the gate connection structure 140, or the first connection pillar sub-section 201 and the source field plate 160 are integrally located, and the second connection pillar sub-section 202 and the gate connection structure 140 are integrally located.

[0113] Specifically, the gate connection structure 140 is electrically connected to the gate 130 through the connection pillar 200, thereby improving connection stability and reducing the resistance of the gate 130. Furthermore, in the first dielectric layer 210, the first connection pillar sub-portion 201 of the connection pillar 200 is electrically connected to the gate 130, and the first connection pillar sub-portion 201 is further electrically connected to the second connection pillar sub-portion 202 located in the second dielectric layer 220, thereby electrically connecting the gate connection structure 140 to the gate 130 through the connection pillar 200. As another possible embodiment, referring to FIG. 16 , the first connection pillar sub-portion 201 and the second connection pillar sub-portion 202 are integrally located and are integrally located in the gate connection structure 140, which can simplify the process flow of the semiconductor device 10 and contribute to improving the process reliability. In another possible embodiment, the first connection pillar sub-section 201 is integrally installed on the source field plate 160, and the second connection pillar sub-section 202 is integrally installed on the gate connection structure 140. Specifically, before forming the source field plate 160, first, an opening is formed in the first dielectric layer 210 above the gate 130 by etching to expose the gate 130, and during the process of forming the source field plate 160, the opening of the first dielectric layer 210 is electrically connected to the gate 130 through the first connection pillar sub-section 201. Then, a second dielectric layer 220 is deposited, and a hole is further formed in the opening above the gate 130. Then, the second connection pillar sub-section 202 is filled in the opening and above the second dielectric layer 220 to form the gate connection structure 140. That is, the connection pillar 200 here is not integrally formed, but is formed by a two-step process such that the first connection pillar sub-section 201 is integrally attached to the source field plate 160 and the second connection pillar sub-section 202 is integrally attached to the gate connection structure 140.

[0114] It should be understood that, from the viewpoint of semiconductor device design, the embodiments of the present application can reduce the influence of gate resistance, improve switching speed, and increase gain by providing a gate connection structure, thereby improving the reliability of the semiconductor device. The semiconductor devices include high-power high electron mobility transistors (HEMTs) that operate in high-voltage and high-current environments, silicon-on-insulator (SOI) transistors, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MFETs). The gate connection structure provided in the semiconductor device according to the embodiment of the present invention can be widely used in the manufacturing fields of semiconductor devices, such as high frequency microwave and power electronics. In particular, the advantages of gallium nitride electronic devices with large band gap width, high electron drift velocity, high breakdown field strength, and high heat resistance are more obvious, and they can better meet the high performance requirements in the rapidly developing electronics and communications field.

[0115] It should be noted that the above is merely a preferred embodiment of the present application and the technical principles applied thereto. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious modifications, adjustments, and substitutions are possible without departing from the scope of protection of the present application. Therefore, although the present application has been described in detail through the above embodiments, it is not limited to the above embodiments, and many other equivalent embodiments can be included within the scope of the present application. The scope of the present application is determined by the appended claims.

Claims

1. A semiconductor device comprising: A substrate; an epitaxial structure located on one side of the substrate; a gate located on a side of the epitaxial structure away from the substrate, extending along a first direction parallel to a plane in which the substrate lies, the gate including first and second gate sub-portions connected to each other and forming a Schottky contact with the epitaxial structure; a gate connection structure including a first gate sub-connection and a second gate sub-connection connected to each other, the second gate sub-connection being electrically connected to at least a portion of the gate.

2. the semiconductor device further includes an active region and a non-active region surrounding the active region; the second gate sub-connection portion is located in the active region, and the first gate sub-connection portion is located in the active region; 2. The semiconductor device of claim 1, wherein the second gate sub-connection is electrically connected to at least a portion of the first gate sub-portion.

3. 3. The semiconductor device of claim 2, wherein the minimum distance between the second gate sub-connection and the edge of the active area is L1, where L1≦5 μm.

4. the semiconductor device further includes an active region and a non-active region surrounding the active region; the second gate sub-connection portion is located in the non-active region, and the second gate sub-portion is located in the non-active region; 2. The semiconductor device of claim 1, wherein the second gate sub-connection is electrically connected to at least a portion of the second gate sub-portion.

5. 5. The semiconductor device of claim 1, wherein the first gate sub-connection portion at least partially overlaps the first gate sub-portion, and the second gate sub-connection portion at least partially overlaps the second gate sub-portion.

6. 6. The semiconductor device of claim 5, wherein the gate connection structure covers the gate along a thickness direction of the semiconductor device.

7. 5. The semiconductor device of claim 1, wherein the first gate sub-portion does not overlap the first gate sub-connection portion along the thickness direction of the semiconductor device.

8. the semiconductor device includes a source, the source forming an ohmic contact with the epitaxial structure; 8. The semiconductor device of claim 7, wherein the first gate sub-connection overlaps and is insulated from the source along the thickness direction of the semiconductor device.

9. the semiconductor device further includes a source, the source forming an ohmic contact with the epitaxial structure; 8. The semiconductor device of claim 7, wherein along a second direction, the first gate sub-connection is located on a side of the source away from the gate, and the first gate sub-connection is located between two adjacent sources, and the second direction intersects the first direction and is parallel to a plane in which the substrate is located.

10. 10. The semiconductor device of claim 1, wherein the gate connection structure further includes a third gate sub-connection portion, the third gate sub-connection portion being located in an active region and electrically connected to the first gate sub-connection portion and the first gate sub-portion, respectively.

11. the semiconductor device further includes a source and a source field plate; the source field plate includes a field plate body and a field plate branch, the field plate branch being electrically connected to the field plate body and the source, respectively; 11. The semiconductor device of claim 10, wherein the field plate branch is offset from the third gate sub-connection.

12. the source field plate is offset from the gate along a thickness direction of the semiconductor device; 12. The semiconductor device of claim 11, wherein the source field plate covers an edge portion of the gate away from the source along a thickness direction of the semiconductor device, an overlapping area between the source field plate and the gate is S1, an area of ​​the gate is S2, and S1 / S2≦20%.

13. 10. The semiconductor device of claim 1, further comprising a gate pad, wherein along the first direction, the gate pad is located in a non-active region on a first side of an active region, and the first gate sub-portion and the first gate sub-connection portion are both electrically connected to the gate pad.

14. the semiconductor device further includes a source and a source field plate, the source field plate being electrically connected to the source; the first gate sub-connection and the gate are located in the same layer, or the first gate sub-connection and the source field plate are located in the same layer, or the first gate sub-connection and the gate pad are located in the same layer, or 14. The semiconductor device of claim 13, wherein the source field plate is located between a film layer in which the gate is located and a film layer in which the gate connection structure is located.

15. the semiconductor device further includes a first dielectric layer located between the film layer in which the source field plate is located and the film layer in which the gate is located, and a second dielectric layer located between the film layer in which the source field plate is located and the film layer in which the gate connecting structure is located; the source field plate overlaps the first gate sub-portion along a thickness direction of the semiconductor device, and a thickness d1 of the first dielectric layer satisfies d1≧300 nm; and / or the source field plate overlaps the first gate sub-connection and the thickness d2 of the second dielectric layer satisfies d2≧300 nm.

16. 16. The semiconductor device of claim 1, wherein along a second direction, the size of the first gate sub-connection portion is larger than the size of the first gate sub-portion, and the second direction intersects with the first direction and is parallel to a plane in which the substrate lies.

17. the gate connection structure is electrically connected to the gate located on one side of the first gate sub-connection portion along the second direction via the second gate sub-connection portion; or the semiconductor device includes a plurality of gates, the plurality of gates being arranged along the second direction; 17. The semiconductor device of claim 1, wherein the gate connection structure is electrically connected to the gates located on both sides of the first gate sub-connection along the second direction via the second gate sub-connection, the second direction intersecting the first direction and being parallel to a plane in which the substrate is located.

18. 18. The semiconductor device of claim 1, wherein the included angle between the second gate sub-connection and the first gate sub-connection is α, where 80°≦α≦100°.

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