Light-emitting diode chip and manufacturing method thereof, and display device

Abstract

The present disclosure provides a light-emitting diode chip, a manufacturing method thereof, and a display device. The light-emitting diode chip includes a substrate and at least two light-emitting structures provided on the substrate, the at least two light-emitting structures being spaced apart and connected in series, and at least one light-emitting structure includes a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first insulating layer, a current spreading layer, and a first electrode, which are stacked in that order on the substrate, wherein the at least one light-emitting structure includes a first via hole located in the first insulating layer, the first electrode being electrically connected to the current spreading layer, and the current spreading layer being electrically connected to the second semiconductor layer through the first via hole, and an orthogonal projection of the first via hole on the substrate is within an orthogonal projection of the current spreading layer on the substrate, and an orthogonal projection of the current spreading layer on the substrate is within an orthogonal projection of the second semiconductor layer on the substrate.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a light-emitting diode chip, a manufacturing method thereof, and a display device. [Background technology]

[0002] Light-emitting diode (LED) technology has been developing for nearly three decades, and its range of applications is constantly expanding. For example, it can be used in the display field as a backlight for display devices or LED display panels. With technological developments, submillimeter light-emitting diodes (Mini LEDs) have become a research focus in the display technology field. For example, the technology of Mini LEDs driven by thin-film transistors (TFTs) offers advantages in productivity, cost, and backward compatibility with micro light-emitting diodes (Micro LEDs), gradually becoming the mainstream research direction in the display technology field. However, during use, Mini LEDs consume more current (μA level) than organic light-emitting diodes (OLEDs) (nA level), resulting in higher power consumption by the TFTs and higher overall power consumption, which is detrimental to the widespread use of products.

[0003] The above information disclosed in this section is only used to understand the background to the inventive concept of the present disclosure, and therefore the above information may include information that does not constitute prior art. Summary of the Invention [Means for solving the problem]

[0004] In order to solve at least one of the above problems, an embodiment of the present disclosure provides a light-emitting diode chip, a manufacturing method thereof, and a display device.

[0005] In one aspect, a semiconductor device includes a substrate and at least two light emitting structures provided on the substrate, wherein orthogonal projections of the at least two light emitting structures on the substrate have a gap therebetween, the at least two light emitting structures are connected in series in order, and at least one of the light emitting structures includes a first semiconductor layer provided on the substrate, a light emitting layer provided on a side of the first semiconductor layer away from the substrate, a second semiconductor layer provided on a side of the light emitting layer away from the substrate, a first insulating layer provided on a side of the second semiconductor layer away from the substrate, and a current insulating layer provided on a side of the first insulating layer away from the substrate. and a first electrode provided on a side of the current extension layer away from the substrate, wherein at least one of the light-emitting structures includes a first via hole located in the first insulating layer, the first electrode being electrically connected to the current extension layer, and the current extension layer being electrically connected to the second semiconductor layer through the first via hole, wherein an orthogonal projection of the first via hole on the substrate fits within an orthogonal projection of the current extension layer on the substrate, and an orthogonal projection of the current extension layer on the substrate fits within an orthogonal projection of the second semiconductor layer on the substrate.

[0006] According to some exemplary embodiments, the same light-emitting structure of the at least one light-emitting structure is provided with a plurality of first via holes located in the first insulating layer, the current expansion layer is electrically connected to the second semiconductor layer by the plurality of first via holes, and the orthogonal projections of the plurality of first via holes on the substrate all fall within the orthogonal projections of the current expansion layer on the substrate.

[0007] According to some demonstrative embodiments, the light-emitting diode chip further includes a bridge conductor provided on a side of the current spreading layer away from the substrate, the bridge conductor including a first portion and a second portion, the at least two light-emitting structures including adjacent first and second light-emitting structures, the first light-emitting structure and the second light-emitting structure being electrically connected via the bridge conductor, the first portion of the bridge conductor being electrically connected to a second semiconductor layer of the first light-emitting structure, and the second portion of the bridge conductor being electrically connected to a first semiconductor layer of the second light-emitting structure, wherein an orthogonal projection of the first portion of the bridge conductor on the substrate fits within an orthogonal projection of the second semiconductor layer of the first light-emitting structure on the substrate, and an orthogonal projection of the second portion of the bridge conductor on the substrate fits within an orthogonal projection of the first semiconductor layer of the second light-emitting structure on the substrate.

[0008] According to some exemplary embodiments, an orthogonal projection of the first portion of the bridge conductor on the substrate and an orthogonal projection of the current spreading layer of the first light emitting structure on the substrate at least partially overlap.

[0009] According to some example embodiments, an orthogonal projection of the first via hole on the substrate and an orthogonal projection of the first portion of the bridge conductor on the substrate at least partially overlap with each other.

[0010] According to some example embodiments, an orthogonal projection of at least one first via hole of the plurality of first via holes on the substrate and an orthogonal projection of a first portion of the bridge conductive portion on the substrate at least partially overlap.

[0011] According to some example embodiments, an orthogonal projection of the first via hole on the substrate and an orthogonal projection of the first portion of the bridge conductor on the substrate do not overlap.

[0012] According to some exemplary embodiments, the orthogonal projection of the first portion of the bridge conductive portion on the substrate and the orthogonal projection of the first via hole on the substrate are spaced apart, and the orthogonal projection of a partial region of the first portion of the bridge conductive portion on the substrate surrounds the orthogonal projection of the first via hole on the substrate.

[0013] According to some exemplary embodiments, the light-emitting diode chip further includes a first reflective layer located between the first insulating layer and the current extending layer, wherein the optical reflectivity of the first reflective layer is higher than the optical reflectivity of the bridge conductive portion, and the orthogonal projection of the first via hole on the substrate is within the orthogonal projection of the first reflective layer on the substrate.

[0014] According to some example embodiments, the light-emitting diode chip further includes a second reflective layer located on a side of the current spreading layer away from the substrate, the second reflective layer including a Bragg reflector.

[0015] According to some exemplary embodiments, the light-emitting diode chip further includes a second via hole located in the second reflective layer, the first electrode is electrically connected to the current spreading layer through the second via hole, and the orthogonal projection of the first via hole on the substrate is within the orthogonal projection of the second via hole on the substrate.

[0016] According to some exemplary embodiments, in the same light-emitting structure of at least one of the light-emitting structures, the orthogonal projections of the plurality of first via holes on the substrate are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect.

[0017] According to some exemplary embodiments, in at least one of the light emitting structures, the ratio of the area of ​​the current spreading layer as orthogonally projected on the substrate to the area of ​​the second semiconductor layer as orthogonally projected on the substrate is less than 0.1.

[0018] According to some exemplary embodiments, in at least one of the light emitting structures, the ratio of the area of ​​the orthogonal projection of each of the plurality of first via holes on the substrate to the area of ​​the orthogonal projection of the second semiconductor layer on the substrate is less than 0.1, and / or in at least one of the light emitting structures, the orthogonal projection of the current spreading layer on the substrate and the orthogonal projection of the second semiconductor layer on the substrate essentially overlap.

[0019] According to some exemplary embodiments, the orthogonal projection of the first via hole on the substrate is circular, the orthogonal projection of a partial region of the first part of the bridge conductive portion on the substrate is annular, and the annular partial region of the first part of the bridge conductive portion and the circular first via hole are essentially concentric.

[0020] According to some exemplary embodiments, an orthogonal projection of the first reflective layer on the substrate and an orthogonal projection of the first portion of the bridge conductor on the substrate at least partially overlap.

[0021] According to some exemplary embodiments, the light-emitting diode chip further includes a second electrode and a third via hole located in the second reflective layer, the second electrode is electrically connected to the first semiconductor layer of one of the light-emitting structures through the third via hole, and the orthogonal projection of the third via hole on the substrate and the orthogonal projection of the first via hole on the substrate are spaced apart.

[0022] According to some exemplary embodiments, the light-emitting diode chip includes three or more of the light-emitting structures, each of the light-emitting structures includes a first via hole located in the first insulating layer, the first electrode is electrically connected to the current expansion layer, the current expansion layer is electrically connected to the second semiconductor layer through the first via hole, an orthogonal projection of the first via hole on the substrate is within an orthogonal projection of the current expansion layer on the substrate, and an orthogonal projection of the current expansion layer on the substrate is within an orthogonal projection of the second semiconductor layer on the substrate.

[0023] In another aspect, there is provided a display device comprising the light emitting diode chip described above.

[0024] In yet another aspect, a method for manufacturing a light-emitting diode chip includes providing a substrate; and forming at least two light-emitting structures on the substrate, the at least two light-emitting structures being spaced apart and connected in series in sequence, wherein forming the at least two light-emitting structures on the substrate includes forming a first semiconductor layer on the substrate; forming a light-emitting layer on a side of the first semiconductor layer remote from the substrate; forming a second semiconductor layer on a side of the light-emitting layer remote from the substrate; forming a first insulating layer on a side of the second semiconductor layer remote from the substrate; forming a first via hole in the first insulating layer by an etching process; forming a current extension layer on a side of the first insulating layer remote from the substrate; and forming a first electrode on the side of the current extension layer remote from the substrate, wherein the first electrode is electrically connected to the current extension layer and the current extension layer is electrically connected to the second semiconductor layer through the first via hole; an orthogonal projection of the first via hole on the substrate is within an orthogonal projection of the current extension layer on the substrate; and an orthogonal projection of the current extension layer on the substrate is within an orthogonal projection of the second semiconductor layer on the substrate.

[0025] The following description of the present disclosure, taken in conjunction with the accompanying drawings, will make other objects, features, and advantages of the present disclosure more apparent and will help to provide a thorough understanding of the present disclosure. [Brief explanation of the drawings]

[0026] [Figure 1A] FIG. 1A is a schematic cross-sectional view of a light-emitting diode chip according to some exemplary embodiments of the present disclosure. [Figure 1B] FIG. 1B is a cross-sectional schematic diagram of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure. [Figure 1C]FIG. 1C is a schematic plan view of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure. [Figure 2] FIG. 2 is a partially enlarged schematic cross-sectional view of a light-emitting diode chip according to some exemplary embodiments of the present disclosure. [Figure 3] FIG. 3 is a schematic cross-sectional view of a light-emitting diode chip according to some other exemplary embodiments of the present disclosure. [Figure 4A] FIG. 4A is a cross-sectional view of a connection structure between a bridge conductive portion and a first light-emitting structure according to some other exemplary embodiments of the present disclosure. [Figure 4B] FIG. 4B is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to some other exemplary embodiments of the present disclosure. [Figure 5] FIG. 5 is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to some further exemplary embodiments of the present disclosure. [Figure 6] FIG. 6 is a plan view comparing connection structures between a bridge conductive portion and a first light emitting structure according to two exemplary embodiments of the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view of a connection structure between a bridge conductive portion and a first light emitting structure according to some further exemplary embodiments of the present disclosure. [Figure 8] FIG. 8 is a schematic diagram of a display device according to some example embodiments of the present disclosure. [Figure 9A] FIG. 9A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 9B] FIG. 9B is a schematic plan view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 10A] FIG. 10A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 10B]FIG. 10B is a schematic plan view of a structure formed after some steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 11A] FIG. 11A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 11B] FIG. 11B is a schematic plan view of a structure formed after some steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 12A] FIG. 12A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 12B] FIG. 12B is a schematic plan view of a structure formed after some steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 13A] FIG. 13A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 13B] FIG. 13B is a schematic plan view of a structure formed after some steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 14A] FIG. 14A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 14B] FIG. 14B is a schematic plan view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 15A] FIG. 15A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 15B]FIG. 15B is a schematic plan view of a structure formed after some steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 16A] FIG. 16A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 16B] FIG. 16B is a schematic plan view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 17A] FIG. 17A is a schematic cross-sectional view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. [Figure 17B] FIG. 17B is a schematic plan view of a structure formed after some steps of a method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure are performed. DETAILED DESCRIPTION OF THE INVENTION

[0027] It should be noted that in the figures used to illustrate the embodiments of the present disclosure, dimensions of layers, structures, or regions may be exaggerated or reduced for clarity, i.e., the figures are not drawn to scale.

[0028] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments. However, it will be apparent that various illustrative embodiments may be practiced without these specific details or with one or more equivalent configurations. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various illustrative embodiments. Also, various illustrative embodiments may vary, but are not necessarily exclusive. For example, the specific shape, configuration, and features of an illustrative embodiment may be used or implemented in other illustrative embodiments without departing from the inventive concept.

[0029] In the drawings, the size and relative size of elements may be exaggerated for clarity and / or explanation purposes. Therefore, the size and relative size of various elements are not necessarily limited to those shown in the figures. When the exemplary embodiments are implemented in different ways, the specific process sequence may be performed differently from the process sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of the described processes. Also, the same reference numerals refer to the same elements.

[0030] When an element is described as being "on," "connected to," or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled with the other element, or intervening elements may be present. However, when an element is described as being "directly on," "directly connected to," or "directly coupled with," there are no intervening elements. Other terms and expressions used to describe relationships between elements should be interpreted similarly. For example, "between" and "directly between," "adjacent" and "directly adjacent," or "to" and "directly to," etc. Furthermore, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Furthermore, the X, Y, and Z axes are not limited to the three axes of a Cartesian coordinate system but may be interpreted more broadly. For example, the X, Y, and Z axes may be perpendicular to one another or may represent different directions that are not perpendicular to one another. For purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be described as X only, Y only, Z only, or any combination of two or more of X, Y, Z, such as XYZ, XYY, YZ, ZZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Herein, terms such as "first," "second," etc. may be used to describe different elements, but it should be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the exemplary embodiments.

[0032] In this specification, inorganic light emitting diodes refer to light emitting devices made of inorganic materials, and LEDs are inorganic light emitting devices that are different from OLEDs. Specifically, inorganic light emitting devices include submillimeter light emitting diodes (Mini LEDs) and micro light emitting diodes (Micro LEDs). Among them, submillimeter light emitting diodes (i.e., Mini LEDs) refer to small light emitting diodes whose grain size is between Mini LEDs and conventional LEDs, and the grain size of Mini LEDs is generally 100 to 300 microns.

[0033] Figure 1A is a schematic cross-sectional view of a light-emitting diode chip according to some exemplary embodiments of the present disclosure, Figure 1B is a schematic cross-sectional view of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure, and Figure 1C is a schematic plan view of a series-connected light-emitting structure according to some exemplary embodiments of the present disclosure.

[0034] Some exemplary embodiments of the present disclosure provide a light-emitting diode chip, a manufacturing method thereof, and a display device. Referring to FIGS. 1A, 1B, and 1C, the light-emitting diode chip includes a substrate 1 and at least two light-emitting structures 2 disposed on the substrate 1, the at least two light-emitting structures 2 being spaced apart and connected in series. In the embodiments of the present disclosure, the light-emitting diode chip may include multiple light-emitting structures connected in series, i.e., a high-voltage chip may be formed, thereby reducing its power consumption while reducing the line current. While the power consumption of the light-emitting diode remains essentially unchanged, the line current is reduced, the power consumption of the driving circuit is reduced, and the power consumption of the entire light-emitting diode chip is reduced.

[0035] Here, "at least two light emitting structures 2 are spaced apart" means that the orthogonal projections of the at least two light emitting structures 2 on the substrate 1 have a gap therebetween.

[0036] In the embodiments of the present disclosure, the type of the light-emitting diode chip is not particularly limited, and for example, the light-emitting diode chip may be a submillimeter light-emitting diode chip or a micro light-emitting diode chip.

[0037] For example, there may be multiple types of substrate 1, and the types may be selectively set according to actual needs. For example, substrate 1 may be a glass substrate, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, a silicon substrate, a silicon carbide substrate, a sapphire substrate, etc.

[0038] In an embodiment of the present disclosure, at least one light-emitting structure 2 includes a first semiconductor layer 211 disposed on a substrate 1, a light-emitting layer 212 disposed on a side of the first semiconductor layer 211 away from the substrate 1, a second semiconductor layer 213 disposed on a side of the light-emitting layer 212 away from the substrate 1, a first insulating layer 214 disposed on a side of the second semiconductor layer 213 away from the substrate 1, a current spreading layer 215 disposed on a side of the first insulating layer 214 away from the substrate 1, and a first electrode 216 disposed on a side of the current spreading layer 215 away from the substrate 1. The inventors have found through research that driving a light-emitting diode with a small current reduces the current density, which correspondingly increases the variation in the optical performance of the light-emitting diode chip itself. In an embodiment of the present disclosure, a current spreading layer is added to spread the current so that as many charges (e.g., positive charges) as possible can pass through the channel to the light-emitting layer so that light can be emitted by recombination with negative charges injected into another semiconductor layer (e.g., an N-type layer).

[0039] In an embodiment of the present disclosure, at least one light-emitting structure 2 includes a first via hole 217 located in the first insulating layer 214, the first electrode 216 is electrically connected to the current expansion layer 215, the current expansion layer 215 is electrically connected to the second semiconductor layer 213 through the first via hole 217, the orthogonal projection of the first via hole 217 on the substrate 1 is within the orthogonal projection of the current expansion layer 215 on the substrate 1, and the orthogonal projection of the current expansion layer 215 on the substrate 1 is within the orthogonal projection of the second semiconductor layer 213 on the substrate 1.

[0040] For example, the current spreading layer 215 may be formed of a transparent conductive material. In an actual manufacturing process, a transparent conductive material layer is first formed on the entire surface, and then the transparent conductive material layer is etched using a wet etching process to form the current spreading layer 215. The inventors discovered through research that etching the transparent conductive material layer using a wet etching process can cause lateral erosion problems (i.e., a large lateral etching amount), resulting in a large etching tolerance. For example, the single-sided etching tolerance can reach 5 microns. This limits the minimum area of ​​the current spreading layer 215, for example, the minimum area of ​​the current spreading layer 215 is 700 square microns or more. In an embodiment of the present disclosure, an insulating layer (e.g., the first insulating layer 214) is first formed on the entire surface, and then holes are opened in the corresponding positions and the current spreading layer is deposited. The via holes are formed in the insulating layer using a dry etching process, so the etching tolerance is small, for example, the etching tolerance on one side is about 1 to 2 microns. The diameter of the via hole is the actual light-emitting area, and the actual light-emitting area is reduced, for example, to less than 300 square microns, which can further increase the current density and accordingly further improve the uniformity of the LED chip under low grayscale conditions.

[0041] In the embodiment of the present disclosure, by using at least two light-emitting structures 2 connected in series, when the same luminous intensity is reached, the current of the light-emitting diode chip can be reduced, and by providing the first insulating layer 214 and the first via hole 217, the actual light-emitting area of ​​the light-emitting diode chip can be reduced, the working current density of the light-emitting diode chip can be increased, and the optical performance of the light-emitting diode chip can be optimized.

[0042] 1B and 1C, a light-emitting diode chip according to an embodiment of the present disclosure may include a substrate 1 and at least two light-emitting structures 2 provided on the substrate 1. For example, the substrate 1 may be a sapphire substrate, and the light-emitting structure 2 may include a first light-emitting structure 21 and a second light-emitting structure 22 connected in series.

[0043] For example, the first light emitting structure 21 and the second light emitting structure 22 are turned on to emit light via a second electrode connected to the first semiconductor layer 211 of the second light emitting structure 22 and a first electrode 216 connected to the second semiconductor layer 213 of the first light emitting structure 21, respectively. The light emitting diode chip may be any of an R (red) chip, a G (green) chip, and a B (blue) chip.

[0044] It is understood that the first light emitting structure 21 and the second light emitting structure 22 can be obtained by etching from a light emitting structure having a size larger than the first light emitting structure 21. The first light emitting structure 21 may also be etched to obtain a sub-light emitting structure having a size smaller than the first light emitting structure 21.

[0045] In the above embodiment, the light-emitting area of ​​the LED chip can be reduced by drilling holes in the first insulating layer 214. In some embodiments, if the size of the LED chip is constant, drilling only two holes for light emission may result in non-uniform light emission. Therefore, the LED chip can be etched to obtain more light-emitting structures 2 without reducing the operating current density of the LED chip.

[0046] According to an embodiment of the present disclosure, the light-emitting diode chip includes, for example, three or more light-emitting structures 2. Each light-emitting structure 2 includes a first via hole 217 located in the first insulating layer 214. The first electrode 216 is electrically connected to the current spreading layer 215. The current spreading layer 215 is electrically connected to the second semiconductor layer 213 through the first via hole 217. The orthogonal projection of the first via hole 217 on the substrate 1 is within the orthogonal projection of the current spreading layer 215 on the substrate 1, and the orthogonal projection of the current spreading layer 215 on the substrate 1 is within the orthogonal projection of the second semiconductor layer 213 on the substrate 1. The three or more light-emitting structures 2 have three or more first via holes 217. The number of light-emitting structures 2 in the light-emitting diode chip can be set according to actual needs to achieve uniform light emission.

[0047] FIG. 2 is a partially enlarged schematic cross-sectional view of a light-emitting diode chip according to some exemplary embodiments of the present disclosure.

[0048] For example, as shown in FIG. 2 , the second light-emitting structure 22 includes a first semiconductor layer 211 provided on the substrate 1, a light-emitting layer 212 provided on the side of the first semiconductor layer 211 away from the substrate 1, a second semiconductor layer 213 provided on the side of the light-emitting layer 212 away from the substrate 1, a first insulating layer 214 provided on the side of the second semiconductor layer 213 away from the substrate 1, and a current spreading layer 215 provided on the side of the first insulating layer 214 away from the substrate 1.

[0049] For example, the first semiconductor layer 211 and the second semiconductor layer 213 may be an N-type layer and a P-type layer, respectively, or a P-type layer and an N-type layer, respectively. The light-emitting layer 212 is a quantum well layer. Under the action of a current, the P-type layer injects positive charges into the quantum well layer, and the N-type layer injects negative charges into the quantum well layer. The positive and negative charges recombine in the quantum well layer to emit light.

[0050] According to an embodiment of the present disclosure, the light emitting layer 212 may include, but is not limited to, a multiple quantum well (MQW) structure in which gallium nitride (GaN) and indium gallium nitride (InGaN) are alternately and periodically arranged.

[0051] For example, the first insulating layer 214 is a PV (polyvinyl, polyethylene) layer. The current spreading layer 215 is an ITO (indium tin oxide) layer. The first insulating layer 214 covers the second semiconductor layer 213, and light emitted from the light emitting layer 212 is transferred upward through a first via hole 217 on the first insulating layer 214. The light emitting area of ​​the light emitting structure 2 can be controlled by controlling the size of the first via hole 217. In this way, the current density of the light emitting diode chip operating under low current can be increased.

[0052] When the current of the light-emitting diode chip is reduced, the current density of the light-emitting diode chip during use will decrease, resulting in greater variation in the optical performance of the light-emitting diode chip. To solve this problem, the size of a single light-emitting structure 2 in the light-emitting diode chip can be reduced, thereby increasing the current density of the light-emitting diode chip during operation at a small current and improving the uniformity of light emission.

[0053] 1B , the size of the current spreading layer 215 can be controlled to control the light-emitting area of ​​the light-emitting diode chip. In at least one light-emitting structure 2, the ratio of the area of ​​the current spreading layer 215 orthogonally projected on the substrate 1 to the area of ​​the second semiconductor layer 213 orthogonally projected on the substrate 1 is less than 0.1. The first insulating layer 214, for example, completely covers the second semiconductor layer 213, and the current spreading layer 215 is electrically connected to the second semiconductor layer 213 through a first via hole 217 in the first insulating layer 214. The current spreading layer 215, for example, only covers the first via hole 217 and does not cover the other first insulating layers 214 that do not have a hole.

[0054] 1A, the light-emitting diode chip further includes a second reflective layer 220, for example, disposed on the side of the current spreading layer 215 away from the substrate 1. The second reflective layer 220 includes a Bragg reflector. The second reflective layer 220 is used to improve the brightness of the light-emitting diode chip and to insulate and encapsulate the PN junction.

[0055] Optionally, the second reflective layer 220 may be, for example, a distributed Bragg reflector (DBR) or a composite layer of DBR and PV. The DBR layer has a periodic structure formed by alternating two materials with different refractive indices, and the optical thickness of each layer of the alternating materials is ¼ of the central reflection wavelength. In one example, the materials with different refractive indices forming the DBR layer may be silicon dioxide (SiO2) and titanium dioxide (TiO2). That is, silicon dioxide and titanium dioxide are alternately arranged to form the DBR layer. In another example, although the materials with different refractive indices forming the DBR layer are formed of materials, other materials can also be used.

[0056] 1A , for example, the light-emitting diode chip further includes a second via hole 221 located in the second reflective layer 220, and the first electrode 216 is electrically connected to the current spreading layer 215 through the second via hole 221. The current spreading layer 215 directly contacts the second semiconductor layer 213 through the first via hole 217 to achieve electrical connection. The first electrode 216 is electrically connected to the second semiconductor layer 213 through the current spreading layer 215.

[0057] 1A , for example, the light-emitting diode chip further includes a second electrode 222 and a third via hole 223 located in the second reflective layer 220. The second electrode 222 is electrically connected to the first semiconductor layer 211 of one light-emitting structure 2 through the third via hole 223. The orthogonal projection of the third via hole 223 on the substrate 1 is spaced apart from the orthogonal projection of the first via hole 217 on the substrate 1. The second electrode 222 is in direct contact with and electrically connected to the first semiconductor layer 211 through the third via hole 223.

[0058] For example, the first electrode 216 and the second electrode 222 electrically connect the first P-type layer and the first N-type layer between two adjacent independent light-emitting structures, respectively, and the second P-type layer and the second N-type layer between the two adjacent independent light-emitting structures are electrically connected via metal parts, thereby realizing a series electrical connection path between the two adjacent independent light-emitting structures, and as a result, the two adjacent independent light-emitting structures emit light at the same current density.

[0059] In some exemplary embodiments of the present disclosure, the light-emitting diode chip may be a Mini LED chip. The Mini LED can be driven by a thin film transistor, as in an active matrix, or by a driver IC for a passive matrix. For example, an LED backlight can be driven by a thin film transistor. Specifically, the Mini LED chip can be applied to an LCD display panel to form a display panel.

[0060] It should be noted that although a rectangular frame is used to represent the LED chip in FIG. 1C, the LED chip in the embodiments of the present disclosure is not limited to a rectangular shape, and may be of other shapes such as a circle, a polygon, etc.

[0061] 1B , the light-emitting diode chip further includes a bridge conductor 218 disposed on the side of the current spreading layer 215 away from the substrate 1. The bridge conductor 218 includes a first portion 2181 and a second portion 2182. At least two light-emitting structures 2 include a first light-emitting structure 21 and a second light-emitting structure 22 adjacent to each other. The first light-emitting structure 21 and the second light-emitting structure 22 are electrically connected via the bridge conductor 218. The first portion 2181 of the bridge conductor 218 is electrically connected to the second semiconductor layer 213 of the second light-emitting structure 22, and the second portion 2182 of the bridge conductor 218 is electrically connected to the first semiconductor layer 211 of the first light-emitting structure 21. The first light-emitting structure 21 and the second light-emitting structure 22 are PN junctions that emit light independently, and the bridge conductor 218 electrically connects the P-type layer and the N-type layer between the two adjacent independent light-emitting structures.

[0062] In an embodiment of the present disclosure, the orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1 falls within the orthogonal projection of the second semiconductor layer 213 of the first light-emitting structure on the substrate 1, and the orthogonal projection of the second portion 2182 of the bridge conductive portion 218 on the substrate 1 falls within the orthogonal projection of the first semiconductor layer 211 of the second light-emitting structure on the substrate 1.

[0063] In the above embodiment, in order to achieve uniform light emission of the LED chip, the LED chip can be etched to obtain three or more light emitting structures 2. It is also possible to achieve uniform light emission of the LED chip by providing multiple holes in one light emitting structure 2 without increasing the number of light emitting structures 2, thereby reducing the difficulty of the process.

[0064] FIG. 3 is a schematic cross-sectional view of a light-emitting diode chip according to some other exemplary embodiments of the present disclosure.

[0065] According to an embodiment of the present disclosure, as shown in FIG. 3 , in at least one light emitting structure 2, a plurality of first via holes 217 are provided in the first insulating layer 214. The current spreading layer 215 is electrically connected to the second semiconductor layer 213 through the plurality of first via holes 217. The orthogonal projections of the plurality of first via holes 217 on the substrate 1 are all within the orthogonal projection of the current spreading layer 215 on the substrate 1. The plurality of first via holes 217 are provided in the first insulating layer 214. The current density within each first via hole 217 can be dispersed, preventing the current spreading layer 215 in the first via hole 217 from being damaged due to excessive current density in the first via hole 217, thereby improving the ESD (Electro-Static Discharge) performance of the light emitting diode chip. In addition, the plurality of first via holes 217 provide a plurality of light emitting channels, and when the plurality of first via holes 217 have a certain arrangement, the effect of uniformly emitting light from the light emitting diode chip can be achieved.

[0066] 12B , the arrangement of the first via holes 217 is such that, in at least one light emitting structure 2, the orthogonal projections of the first via holes 217 on the substrate 1 are arranged in an array along a first direction and a second direction, and the first direction intersects with the second direction. For example, the first direction and the second direction are perpendicular to each other, and the rows and columns in which the first via holes 217 are arranged are perpendicular to each other, thereby enabling the light emitting diode chip to emit light in an orderly and uniform manner.

[0067] 3 , the orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1 at least partially overlaps with the orthogonal projection of the current spreading layer 215 of the first light emitting structure 21 on the substrate 1. The first portion 2181 of the bridge conductive portion 218 is in direct contact with the current spreading layer 215, thereby achieving an electrical connection between the bridge conductive portion 218 and the P-type layer of the first light emitting structure 21.

[0068] For example, an orthogonal projection of the first via hole 217 on the substrate 1 and an orthogonal projection of the first portion 2181 of the bridge conductor 218 on the substrate 1 at least partially overlap. The current spreading layer 215 is electrically connected to the second semiconductor layer 213 of the first light emitting structure 21 through the first via hole 217. The first portion 2181 of the bridge conductor 218 is in direct contact with the current spreading layer 215 in the first via hole 217, and the first portion 2181 of the bridge conductor 218 at least partially covers the current spreading layer 215 in the first via hole 217. Because the charge transfer rate of the bridge conductive portion 218 is higher than that of the current spreading layer 215, the bridge conductive portion 218 covering the current spreading layer 215 in the first via hole 217 can transfer the charges of the current spreading layer 215 in the first via hole 217 in a timely manner, thereby reducing the accumulated charges in the current spreading layer 215 in the first via hole 217, and thereby improving the ESD performance of the light-emitting diode chip.

[0069] For example, an orthogonal projection of at least one of the multiple first via holes 217 on the substrate 1 at least partially overlaps with an orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1. When multiple first via holes 217 are provided in the first insulating layer 214, an orthogonal projection of the at least one first via hole 217 on the substrate 1 at least partially overlaps with an orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1, thereby achieving electrical connection between the bridge conductive portion 218 and the second semiconductor layer 213.

[0070] 3, the orthogonal projection of the first via hole 217 on the substrate 1 falls within the orthogonal projection of the second via hole 221 on the substrate 1. When a plurality of first via holes 217 are provided in the first insulating layer 214, the orthogonal projection of at least one first via hole 217 on the substrate 1 falls within the orthogonal projection of the second via hole 221 on the substrate 1, thereby achieving electrical connection between the first electrode 216 and the second semiconductor layer 213.

[0071] 4A and 4B are cross-sectional and plan views of a connection structure between a bridge conductive portion and a first light emitting structure according to some other exemplary embodiments of the present disclosure, respectively.

[0072] In some embodiments, the bridge conductor 218 is fabricated directly after the current spreading layer 215, and the reflectivity of the bridge conductor 218 is lower than that of the second reflective layer 220 fabricated thereafter, resulting in reduced brightness of the LED chip. To prevent a reduction in brightness of the LED chip, the first portion 2181 of the bridge conductor 218 may be configured not to cover the first via hole 217 and not to block light from emitting from the first via hole 217.

[0073] 4A and 4B, the orthogonal projection of the first via hole 217 on the substrate 1 does not overlap with the orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1. The first portion 2181 of the bridge conductive portion 218 does not cover the first via hole 217 and directly contacts the current spreading layer 215 that is not located within the first via hole 217 to achieve electrical connection.

[0074] In the above embodiment, multiple first via holes 217 are provided in one light emitting structure 2, thereby improving the uniformity of the light emission of the light emitting structure 2. In order to achieve a higher operating current density of the light emitting diode chip, the size of each first via hole 217 must be smaller than a size threshold.

[0075] For example, in the same light emitting structure 2 of at least one light emitting structure 2, the ratio of the area of ​​the orthogonal projection of each of the plurality of first via holes 217 on the substrate 1 to the area of ​​the orthogonal projection of the second semiconductor layer 213 on the substrate 1 is less than 0.1. And / or, in the same light emitting structure 2 of at least one light emitting structure 2, the orthogonal projection of the current spreading layer 215 on the substrate 1 and the orthogonal projection of the second semiconductor layer 213 on the substrate 1 essentially overlap. Because the light emitting structure 2 emits light through the first via holes 217, the size of the current spreading layer 215 does not affect the light emitting area, and the sizes of the current spreading layer 215 and the second semiconductor layer 213 can be set to be essentially the same. The first portion 2181 of the bridge conductor 218 is connected to the current spreading layer 215 and does not cover the first via holes 217, which avoids a decrease in brightness of the light emitting diode chip due to the reflectivity of the bridge conductor 218 being lower than that of the second reflective layer 220 to be fabricated subsequently.

[0076] In some embodiments, to avoid reducing the brightness of the LED chip, the first portion 2181 of the bridge conductive portion 218 does not cover the first via hole 217. Because the charge transfer rate of the bridge conductive portion 218 is greater than that of the current spreading layer 215, by designing the shape of the bridge conductive portion 218 and the connection manner between the bridge conductive portion 218 and the current spreading layer 215, charge accumulation in the current spreading layer 215 due to the difference in charge transfer rate between the two can be reduced, thereby improving the ESD performance of the LED chip.

[0077] FIG. 5 is a plan view of a connection structure between a bridge conductive portion and a first light emitting structure according to some further exemplary embodiments of the present disclosure.

[0078] According to an embodiment of the present disclosure, as shown in FIG. 5 , the orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1 is spaced apart from the orthogonal projection of the first via hole 217 on the substrate 1. The orthogonal projection of a partial region of the first portion 2181 of the bridge conductive portion 218 on the substrate 1 surrounds the orthogonal projection of the first via hole 217 on the substrate 1. The first portion 2181 of the bridge conductive portion 218 does not cover the first via hole 217 but surrounds the periphery of the first via hole 217, thereby promptly transferring charges in the current spreading layer 215 located within the first via hole 217 and reducing charge accumulation in the current spreading layer 215, thereby improving the ESD performance of the LED chip. At the same time, the first portion 2181 of the bridge conductive portion 218 does not cover the first via hole 217, ensuring that the brightness of the LED chip is not reduced.

[0079] 5 , the orthogonal projection of the first via hole 217 on the substrate 1 is circular, the orthogonal projection of the first portion 2181 of the bridge conductive portion 218 on the substrate 1 is annular, and the partial area of ​​the annular first portion 2181 of the bridge conductive portion 218 and the circular first via hole 217 are essentially concentric. The combination of the first via hole 217, which has a circular orthogonal projection on the substrate 1, and the first portion 2181 of the bridge conductive portion 218, which has an annular orthogonal projection on the substrate 1, can achieve high-speed transfer of charges in the current spreading layer 215 within the first via hole 217.

[0080] It should be understood that the orthogonal projection shape of the first via hole 217 on the substrate 1 may be other shapes besides a circle, such as a square, a diamond, an ellipse, etc., and the inner contour of the orthogonal projection shape of the first part 2181 of the bridge conductive portion 218 on the substrate 1 may be other shapes corresponding to the orthogonal projection shape of the first via hole 217 on the substrate 1.

[0081] FIG. 6 is a plan view comparing connection structures between a bridge conductive portion and a first light emitting structure according to two exemplary embodiments of the present disclosure.

[0082] In an embodiment of the present disclosure, as shown in FIG. 6 , in the case of a technical solution that combines a first via hole 217 that has a circular orthogonal projection on the substrate 1 with a first portion 2181 of a bridge conductive portion 218 that has an annular orthogonal projection on the substrate 1, charge can be uniformly transferred from the periphery of the first via hole 217 to a partial region of the first portion 2181 of the bridge conductive portion 218, and the charge transfer rate is superior to the technical solution that transfers charge in one direction from the first via hole 217 to the first portion 2181 of the bridge conductive portion 218.

[0083] In the above embodiment, in order to avoid a decrease in brightness of the LED chip due to the reflectivity of the first portion 2181 of the bridge conductive portion 218 being lower than that of the second reflective layer 220, the first portion 2181 of the bridge conductive portion 218 can be configured not to cover the first via hole 217. In addition, a metal layer with high reflectivity is provided under the first via hole 217 in the first via hole 217, thereby ensuring that the brightness of the LED chip is not decreased and the ESD performance of the LED chip is improved.

[0084] FIG. 7 is a cross-sectional view of a connection structure between a bridge conductive portion and a first light emitting structure according to some further exemplary embodiments of the present disclosure.

[0085] 7 , the light-emitting diode chip further includes, for example, a first reflective layer 219 located between the first insulating layer 214 and the current spreading layer 215. The optical reflectivity of the first reflective layer 219 is higher than that of the bridge conductive portion 218, and the orthogonal projection of the first via hole 217 on the substrate 1 is within the orthogonal projection of the first reflective layer 219 on the substrate 1.

[0086] For example, the first reflective layer 219 is metallic silver with high reflectivity, which can effectively increase the charge accumulation area of ​​the current spreading layer 215 in the first via hole 217, increasing the radius from 8 micrometers to 10 micrometers, thereby improving the ESD performance of the light-emitting diode chip.

[0087] For example, the orthogonal projection of the first reflective layer 219 on the substrate 1 at least partially overlaps with the orthogonal projection of the first portion 2181 of the bridge conductor 218 on the substrate 1. The first reflective layer 219 is disposed within the first via hole 217 and partially extends beyond the first via hole 217, covering the first via hole 217 but not covering the remaining portion of the first insulating layer 214 that does not have a hole. The current spreading layer 215 covers the first reflective layer 219 but does not cover the first insulating layer 214 of the first reflective layer 219. Because the optical reflectivity of the first reflective layer 219 is greater than that of the bridge conductor 218, the first portion 2181 of the bridge conductor 218 can cover the first via hole 217, thereby improving the ESD performance of the light-emitting diode chip component.

[0088] Some exemplary embodiments of the present disclosure also provide a display device. Figure 8 is a schematic diagram of a display device according to some exemplary embodiments of the present disclosure. Referring to Figure 8, the display device includes the above-mentioned light-emitting diode chip.

[0089] The display device may be any product or component with a display function, such as a smartphone, a mobile phone, a navigation device, a television (TV), a car audio unit, a laptop computer, a tablet computer, a portable multimedia player (PMP), or a personal digital assistant (PDA).

[0090] For example, in some Mini LED display modules using the light-emitting diode chips of the embodiments of the present disclosure, the current of the light-emitting diode chips can be reduced, thereby reducing the power consumption of the Mini LED display module and reducing costs.In addition, the thickness of the Cu substrate can be reduced to reduce the process difficulty, and the use of high-voltage light-emitting diode chips can ensure the yield of the display module, provided that the difficulty of the existing process remains unchanged.

[0091] It should be understood that the display device according to some embodiments of the present disclosure has all the features and advantages of the above-mentioned light-emitting diode chip, and for these features and advantages, please refer to the above description of the light-emitting diode chip, and the description will be omitted here.

[0092] Another exemplary embodiment of the present disclosure also provides a method for manufacturing a light-emitting diode chip. Figures 9A to 17A are schematic cross-sectional views of structures formed after performing several steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure. Figures 9B to 17B are schematic plan views of structures formed after performing several steps of the method for manufacturing a light-emitting diode chip according to some exemplary embodiments of the present disclosure.

[0093] 9A to 17B , a method for manufacturing a light-emitting diode chip includes providing a substrate 1 and forming at least two spaced-apart light-emitting structures 2 on the substrate 1. The at least two light-emitting structures 2 are sequentially connected in series. Here, forming the at least two light-emitting structures 2 on the substrate 1 includes forming a first semiconductor layer 211 on the substrate 1, forming a light-emitting layer 212 on a side of the first semiconductor layer 211 away from the substrate 1, forming a second semiconductor layer 213 on a side of the light-emitting layer 212 away from the substrate 1, forming a first insulating layer 214 on a side of the second semiconductor layer 213 away from the substrate 1, forming a first via hole 217 in the first insulating layer 214 by a dry etching process, forming a current spreading layer 215 on a side of the first insulating layer 214 away from the substrate 1, and forming a first electrode 216 on a side of the current spreading layer 215 away from the substrate 1. The first electrode 162 is electrically connected to the current expansion layer 215, the current expansion layer 215 is electrically connected to the second semiconductor layer 213 via the first via hole 217, the orthogonal projection of the first via hole 217 on the substrate 1 is within the orthogonal projection of the current expansion layer 215 on the substrate 1, and the orthogonal projection of the current expansion layer 215 on the substrate 1 is within the orthogonal projection of the second semiconductor layer 213 on the substrate 1.

[0094] For example, each layer of a light-emitting diode chip can be fabricated by combining metal-organic chemical vapor deposition (MOCVD) and etching.

[0095] Specifically, referring to FIGS. 9A and 9B, a first semiconductor layer 211, a light emitting layer 212 and a second semiconductor layer 213 are sequentially deposited on a substrate 1 to obtain a PN junction deposited on the substrate 1.

[0096] 10A and 10B, the second semiconductor layer 213 and the light emitting layer 212 are etched to obtain the basic shapes of the second semiconductor layer 213 and the light emitting layer 212.

[0097] 11A and 11B, etching of the first semiconductor layer 211 continues to result in two independent PN junctions in the substrate 1.

[0098] 12A and 12B, a first insulating layer 214 was obtained by depositing and etching the second semiconductor layer 213 of each PN junction, and a plurality of first vias 217 were etched into the first insulating layer 214, with their orthogonal projections arranged in an array along the first and second directions.

[0099] In the embodiment of the present disclosure, the size of the first via hole 217 can be controlled to control the light-emitting area of ​​the light-emitting structure 2. This can increase the current density of the LED chip during low-current operation. By providing multiple first via holes 217 in the first insulating layer 214, the current density within each first via hole 217 can be distributed to each first via hole 217, preventing damage to the current spreading layer 215 within each first via hole 217 due to excessive current density within the first via hole 217. This improves the electrostatic discharge (ESD) performance of the LED chip. Furthermore, the multiple first via holes 217 provide multiple light-emitting channels. A uniform arrangement of the multiple first via holes 217 can achieve uniform light emission from the LED chip.

[0100] Referring to FIGS. 13A and 13B, after the holes are drilled, a current spreading layer 215 is deposited on the first insulating layer 214 to obtain the first light emitting structure 21 and the second light emitting structure 22 .

[0101] In an embodiment of the present disclosure, a current spreading layer 215 is added to spread the current so that as many charges (e.g., positive charges) as possible have a channel from the second semiconductor layer 213 (e.g., a P-type layer) to the light emitting layer 212 so that they can recombine with the negative charges injected into the first semiconductor layer 211 (e.g., an N-type layer) and emit light.

[0102] Specifically, the first insulating layer 214 is formed by, for example, dry etching. After the first insulating layer 214 is manufactured, a hole is opened in the first insulating layer 214 to form the first via hole 217. Next, in a wet etching process, the current spreading layer 215 is deposited in the first via hole 217 to avoid lateral erosion problems when manufacturing the current spreading layer 215. Because the first insulating layer 214 uses a dry etching process, the etching tolerance is small (for example, 1 to 2 μm on one side), and the hole diameter of the first via hole 217 becomes the actual light-emitting area, which greatly reduces the actual light-emitting area (for example, if the light-emitting area is 300 μm2 This can significantly increase the current density of the light-emitting diode chip during use and further improve the uniformity of the light-emitting diode chip.

[0103] Referring to Figures 14A and 14B, an insulating layer is deposited in the AA region.

[0104] 15A and 15B , the bridge conductor 218 is deposited in the BB region, the insulating layer in the AA region isolates the bridge conductor 218 in the BB region from the first light emitting structure 21, and the first portion 2181 of the bridge conductor 218 contacts the current spreading layer 215 of the first light emitting structure 21, thereby achieving an electrical connection between the first portion 2181 of the bridge conductor 218 and the second semiconductor layer 213 of the first light emitting structure 21. The second portion 2182 of the bridge conductor 218 contacts the first semiconductor layer 211 of the second light emitting structure 22, thereby achieving an electrical connection between the second portion 2182 of the bridge conductor 218 and the first semiconductor layer 211 of the second light emitting structure 22. Therefore, the bridge conductor 218 realizes a series electrical connection between the first light emitting structure 21 and the second light emitting structure 22.

[0105] In the embodiment of the present disclosure, the first portion 2181 of the bridge conductive portion 218 may cover some of the plurality of first via holes 217, or may not cover any of the first via holes 217. Because the first portion 2181 of the bridge conductive portion 218 does not cover the first via holes 217, a decrease in brightness of the LED chip can be prevented. By designing the shape of the bridge conductive portion 218 and the connection method between the bridge conductive portion 218 and the current spreading layer 215, charge accumulation in the current spreading layer 215 due to the difference in charge transfer rate between the two can be reduced, thereby improving the ESD performance of the LED chip.

[0106] In the embodiment of the present disclosure, the LED chip includes a first light emitting structure 21 and a second light emitting structure 22 connected in series, i.e., a high-voltage chip can be formed. While the power consumption of the LED remains essentially unchanged, the line current can be reduced, the power consumption of the driving circuit can be reduced, and the overall power consumption of the LED chip can be reduced.

[0107] 16A and 16B, a second reflective layer 220 is deposited on the first light emitting structure 21 and the second light emitting structure 22, which are electrically connected in series, and the second reflective layer 220 is etched to form a second via hole 221 communicating with the current spreading layer 215 of the second light emitting structure 22, and a third via hole 223 communicating with the first semiconductor layer 211 of the first light emitting structure 21. The second reflective layer 220 improves the brightness of the light emitting diode chip and insulates and encapsulates the PN junction.

[0108] 17A and 17B, to obtain a light emitting diode chip according to another embodiment of the present disclosure, a first electrode 216 is deposited in the second via hole 221, and a second electrode 222 is deposited in the third via hole 223.

[0109] It should be noted that the steps of the above-described manufacturing method may be performed individually or in combination, may be performed in parallel or sequentially, and are not limited to the specific order of operations shown in the figures.

[0110] As used herein, the terms "essentially," "about," "approximately," and other similar terms are used as terms of approximation, not as terms of degree, and are intended to account for inherent bias in measurements or calculations that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variation, measurement issues, and errors associated with measuring a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, includes the stated value and means that the particular value, as determined by one of ordinary skill in the art, is within an acceptable range of variation. For example, "about" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0111] While several embodiments in accordance with the general concepts of the present disclosure have been shown and described, those skilled in the art will appreciate that various changes can be made to these embodiments without departing from the principles and spirit of the general inventive concepts of the present disclosure, the scope of the present disclosure being defined by the claims and their equivalents. [Explanation of symbols]

[0112] 1 board 2. Light-emitting structure 21 First light-emitting structure 22 Second light-emitting structure 211 First semiconductor layer 212 Light-emitting layer 213 Second semiconductor layer 214 First insulating layer 215 Current Extension Layer 216 1st electrode 217 Beer Hall No. 1

Claims

1. A substrate; at least two light emitting structures provided on the substrate; orthogonal projections of the at least two light emitting structures on the substrate have a gap therebetween, and the at least two light emitting structures are connected in series in sequence; At least one of the light emitting structures comprises: a first semiconductor layer provided on the substrate; a light emitting layer provided on a side of the first semiconductor layer away from the substrate; a second semiconductor layer provided on a side of the light emitting layer away from the substrate; a first insulating layer provided on a side of the second semiconductor layer away from the substrate; a current spreading layer disposed on a side of the first insulating layer away from the substrate; a first electrode disposed on a side of the current spreading layer away from the substrate; wherein at least one of the light emitting structures includes a first via hole located in the first insulating layer, the first electrode is electrically connected to the current extending layer, and the current extending layer is electrically connected to the second semiconductor layer through the first via hole; an orthogonal projection of the first via hole on the substrate fits within an orthogonal projection of the current spreading layer on the substrate, and an orthogonal projection of the current spreading layer on the substrate fits within an orthogonal projection of the second semiconductor layer on the substrate; Light emitting diode chip.

2. At least one of the light emitting structures has a plurality of first via holes located in the first insulating layer, and the current spreading layer is electrically connected to the second semiconductor layer through the plurality of first via holes; orthogonal projections of the plurality of first via holes on the substrate are all within an orthogonal projection of the current spreading layer on the substrate; The light-emitting diode chip according to claim 1 .

3. a bridge conductive portion provided on a side of the current spreading layer away from the substrate, the bridge conductive portion including a first portion and a second portion; the at least two light emitting structures include a first light emitting structure and a second light emitting structure adjacent to each other, the first light emitting structure and the second light emitting structure being electrically connected via the bridge conductive portion, a first portion of the bridge conductive portion being electrically connected to a second semiconductor layer of the first light emitting structure, and a second portion of the bridge conductive portion being electrically connected to a first semiconductor layer of the second light emitting structure; wherein an orthogonal projection of a first portion of the bridge conductor on the substrate falls within an orthogonal projection of a second semiconductor layer of the first light emitting structure on the substrate, and an orthogonal projection of a second portion of the bridge conductor on the substrate falls within an orthogonal projection of a first semiconductor layer of the second light emitting structure on the substrate. The light-emitting diode chip according to claim 1 .

4. an orthogonal projection of the first portion of the bridge conductor on the substrate and an orthogonal projection of the current spreading layer of the first light emitting structure on the substrate at least partially overlap each other; The light-emitting diode chip according to claim 3 .

5. an orthogonal projection of the first via hole on the substrate and an orthogonal projection of the first portion of the bridge conductive portion on the substrate at least partially overlap with each other; The light-emitting diode chip according to claim 1 .

6. an orthogonal projection of at least one of the plurality of first via holes on the substrate and an orthogonal projection of the first portion of the bridge conductive portion on the substrate at least partially overlap each other; The light-emitting diode chip according to claim 2 .

7. an orthogonal projection of the first via hole on the substrate and an orthogonal projection of the first portion of the bridge conductive portion on the substrate do not overlap; The light-emitting diode chip according to claim 1 .

8. an orthogonal projection of the first portion of the bridge conductive portion on the substrate and an orthogonal projection of the first via hole on the substrate are spaced apart from each other; an orthogonal projection of a partial region of the first portion of the bridge conductive portion on the substrate surrounds an orthogonal projection of the first via hole on the substrate; The light-emitting diode chip according to claim 7 .

9. a first reflective layer disposed between the first insulating layer and the current extending layer, the first reflective layer having a higher optical reflectivity than the bridge conductor; an orthogonal projection of the first via hole on the substrate is within an orthogonal projection of the first reflective layer on the substrate; The light-emitting diode chip according to claim 5 .

10. a second reflective layer positioned on a side of the current spreading layer away from the substrate; the second reflective layer includes a Bragg reflector; The light-emitting diode chip according to claim 1 .

11. further comprising a second via hole located in the second reflective layer; the first electrode is electrically connected to the current spreading layer through the second via hole; an orthogonal projection of the first via hole on the substrate is within an orthogonal projection of the second via hole on the substrate; The light-emitting diode chip according to claim 10.

12. In the same light-emitting structure of at least one of the light-emitting structures, orthogonal projections of the plurality of first via holes on the substrate are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect; The light-emitting diode chip according to claim 2 .

13. In at least one of the light emitting structures, a ratio of an area of ​​the current spreading layer orthogonally projected on the substrate to an area of ​​the second semiconductor layer orthogonally projected on the substrate is less than 0.

1. The light-emitting diode chip according to claim 1 .

14. In at least one of the light emitting structures, a ratio of an area of ​​an orthogonal projection of each of the plurality of first via holes on the substrate to an area of ​​an orthogonal projection of the second semiconductor layer on the substrate is less than 0.1; and / or In the same light emitting structure of at least one of the light emitting structures, an orthogonal projection of the current spreading layer on the substrate and an orthogonal projection of the second semiconductor layer on the substrate essentially overlap. The light-emitting diode chip according to claim 2 .

15. an orthogonal projection of the first via hole on the substrate is circular; an orthogonal projection of a partial region of the first part of the bridge conductive portion on the substrate has an annular shape; a partial region of the annular first portion of the bridge conductive portion and a circular first via hole are essentially concentric. The light-emitting diode chip according to claim 8 .

16. an orthogonal projection of the first reflective layer on the substrate and an orthogonal projection of the first portion of the bridge conductor on the substrate at least partially overlap with each other; The light-emitting diode chip according to claim 9 .

17. a second electrode and a third via hole located in the second reflective layer; the second electrode is electrically connected to the first semiconductor layer of one of the light emitting structures through a third via hole; an orthogonal projection of the third via hole on the substrate and an orthogonal projection of the first via hole on the substrate are spaced apart from each other; The light-emitting diode chip according to claim 11.

18. the light-emitting diode chip includes three or more of the light-emitting structures; Each of the light emitting structures includes a first via hole located in the first insulating layer, the first electrode is electrically connected to the current extending layer, and the current extending layer is electrically connected to the second semiconductor layer through the first via hole; an orthogonal projection of the first via hole on the substrate fits within an orthogonal projection of the current spreading layer on the substrate, and an orthogonal projection of the current spreading layer on the substrate fits within an orthogonal projection of the second semiconductor layer on the substrate; The light-emitting diode chip according to claim 1 .

19. A display device comprising the light-emitting diode chip according to any one of claims 1 to 18.

20. A method for manufacturing a light emitting diode chip, comprising: Providing a substrate; forming at least two spaced apart light emitting structures on the substrate, the light emitting structures being connected in series in sequence; forming at least two light emitting structures on the substrate; forming a first semiconductor layer on the substrate; forming a light emitting layer on a side of the first semiconductor layer away from the substrate; forming a second semiconductor layer on a side of the light emitting layer remote from the substrate; forming a first insulating layer on a side of the second semiconductor layer away from the substrate; forming a first via hole in the first insulating layer by a dry etching process; forming a current spreading layer on a side of the first insulating layer away from the substrate; forming a first electrode on a side of the current spreading layer remote from the substrate; wherein the first electrode is electrically connected to the current spreading layer, and the current spreading layer is electrically connected to the second semiconductor layer through the first via hole; an orthogonal projection of the first via hole on the substrate fits within an orthogonal projection of the current spreading layer on the substrate, and an orthogonal projection of the current spreading layer on the substrate fits within an orthogonal projection of the second semiconductor layer on the substrate; Manufacturing method.

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