Array substrate, display panel and display device

Abstract

The present invention provides an array substrate, a display panel, and a display device for reducing fine moiré. The array substrate includes a base substrate 015, subpixel units 08, first signal lines 016, and second signal lines 017. The first signal lines 016 and the second signal lines 017 cross each other to define aperture regions 08-1 of the subpixel units 08. The first signal lines 016 are arranged in a column direction Y, and the second signal lines 017 are arranged in a row direction X. Each second signal line 017 includes a plurality of first portions 029 and second portions 030 extending in the column direction Y. The second portions 030 include portions extending in a tilt direction Q, and the second portions 030 connect two first portions 029. The angle between the tilt direction Q and the row direction and the angle between the tilt direction Q and the column direction Y are greater than zero. The first portion 029) is adjacent to the opening region 08-1 of the subpixel unit 08 in the row direction X, and the multiple second portions 030 each at least partially pass through the region between two adjacent pixel repeat unit rows 013), and the distance between two first portions 029) connected to the second portions 030 in the row direction is greater than 0.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority based on a Chinese patent application filed with the China Patent Office on December 26, 2022, bearing application number 202211679554.X and entitled "Array substrate, display panel and display device," the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. [Background technology]

[0003] With the continuous development of display technology, three-dimensional (3D) display technology has attracted increasing attention. 3D display technology can make display screens appear more realistic and three-dimensional. The principle is that a person's left and right eyes receive left-eye and right-eye images with a certain parallax, respectively. After the two parallax images are received by the left and right eyes, the brain superimposes the 3D image and fuses the image information to create a 3D visual display effect. To achieve compatibility between super multi-view 3D display and light field display, the conventional sub-pixel is structured as a pixel island, with multiple sub-pixels in each pixel island. When multiple sub-pixels display different information and one eye views multiple perspectives, a conventional light field display can be realized. When multiple sub-pixels display different information and one eye views a single perspective, a super multi-view light field 3D display can be realized.

[0004] Conventional 3D display products suffer from moire problems. Summary of the Invention [Problem to be solved by the invention]

[0005] Embodiments of the present invention provide an array substrate, a display panel and a display device for reducing fine moire. [Means for solving the problem]

[0006] An embodiment of the present invention provides an array substrate, the array substrate including: a base substrate; a plurality of sub-pixel units, a plurality of first signal lines, and a plurality of second signal lines disposed on a side surface of the base substrate; the plurality of first signal lines and the plurality of second signal lines cross each other to define opening regions of the plurality of sub-pixel units; the plurality of subpixel units are arranged in an array along row and column directions, a plurality of subpixel units arranged at intervals along the row direction form pixel islands, a plurality of pixel islands arranged consecutively along the column direction form pixel repeat units, a row of pixel repeat units arranged along the row direction form a pixel repeat unit row, and aperture regions of the subpixel units arranged along the row direction form an aperture region row; The plurality of first signal lines are arranged in a column direction, and the plurality of second signal lines are arranged in a row direction; each second signal line includes a plurality of first portions extending along the column direction and a plurality of second portions, the second portions include portions extending along the oblique direction, the second portions connect two of the first portions, an included angle between the oblique direction and the column direction and an included angle between the oblique direction and the row direction are greater than 0; The first portion is adjacent to the aperture region of the subpixel in the row direction, and the multiple second portions each at least partially pass through the region between two adjacent pixel repeat unit rows, and the distance between two first portions connected to the second portion in the row direction is greater than 0.

[0007] In some embodiments, the plurality of first signal lines includes a plurality of first scan lines and a plurality of second scan lines, and the first scan lines and the second scan lines are arranged alternately in sequence; the subpixel units in the same row are electrically connected to one first scan line and one second scan line, and the first scan line and the second scan line that are electrically connected to the subpixel units in the same row in the column direction are disposed on both sides of the aperture region row in the column direction; the plurality of second signal lines include a plurality of data lines and a plurality of common electrode lines, the data lines and the common electrode lines being arranged alternately in sequence; Each data line is electrically connected to two adjacent columns of subpixel units in the row direction; The sub-pixel unit includes a thin film transistor, a gate electrode of the thin film transistor is electrically connected to the first signal line, and a source electrode of the thin film transistor is electrically connected to the data line; In the sub-pixel units of two adjacent rows, two thin film transistors electrically connected to the same data line share a source electrode.

[0008] In some embodiments, the active layers of two thin film transistors electrically connected to the second portion included in the data line are integrally connected, and the second portion included in the data line is electrically connected to the integrally connected active layers through only one first via hole.

[0009] In some embodiments, the second portion includes two first sub-portions extending parallel to each other along the inclined direction and a second sub-portion connecting the two first sub-portions, the second sub-portion extending along the column direction, and the two first sub-portions each connected to a different first portion.

[0010] In some embodiments, an orthogonal projection of one of the two first sub-portions on the base substrate overlaps with an orthogonal projection of a first scan line on the base substrate, and an orthogonal projection of the other of the two first sub-portions on the base substrate overlaps with an orthogonal projection of a second scan line on the base substrate; The second sub-partial orthogonal projection on the base substrate and the orthogonal projection of the first scan line on the base substrate do not overlap.

[0011] In some embodiments, each second signal line further includes a plurality of third portions, and the first portions other than the first portions connected via the second portions are connected via the third portions; the two first portions connected to the third portion are positioned on the same straight line in the column direction; the third portion includes a third sub-portion extending along the first inclination direction, a fourth sub-portion extending along the second inclination direction, and a fifth sub-portion extending along the column direction; two ends of the fifth sub-portion are electrically connected to the third sub-portion and the fourth sub-portion, respectively, and the third sub-portion and the fourth sub-portion are each electrically connected to two different first portions; the first tilt direction intersects with the second tilt direction; The two first portions connected to the third portion are positioned on the same straight line in the column direction.

[0012] In some embodiments, the orthogonal projection of the third sub-portion on the base substrate overlaps with the orthogonal projection of the first scan line on the base substrate, and the orthogonal projection of the fourth sub-portion on the base substrate overlaps with the orthogonal projection of the second scan line on the base substrate; The orthogonal projection of the fifth sub-portion on the base substrate and the orthogonal projection of the first scan line on the base substrate do not overlap.

[0013] In some embodiments, the active layers of two thin film transistors electrically connected to the third portion are integrally connected, and the third portion is electrically connected to the integrally connected active layers through only one first via hole.

[0014] In some embodiments, the aperture regions of the sub-pixels in any two adjacent pixel repeat unit rows are staggered in the row direction; an orthogonal projection of the second portion on the base substrate overlaps with an orthogonal projection of an area between two adjacent rows of aperture areas, the rows being respectively located in two different pixel repeat unit rows on the base substrate; The orthogonal projection of the third portion on the base substrate overlaps with the orthogonal projection of the region between two adjacent rows of aperture regions located in the same pixel repeat unit row on the base substrate.

[0015] In some embodiments, in the row direction, the ratio of the width of the aperture region of the subpixel unit to the width of the pixel island is i / M, where M is an integer greater than 1 and i is an integer greater than or equal to 1 and less than M; the plurality of pixel repeat unit rows are divided into a plurality of pixel repeat unit groups, each pixel repeat unit group including M pixel repeat unit rows; In each pixel repeat unit group, the ratio of the misalignment vector of the first portion corresponding to the jth pixel repeat unit row in the row direction to the first portion corresponding to the first pixel repeat unit row in the row direction and the width of the aperture region of the subpixel unit in the row direction is Jj=±E / M, where j is an integer greater than 1 and less than M, and E is an integer greater than 1 and less than M.

[0016] In some embodiments, the sub-pixel unit further comprises a pixel electrode connected to the thin film transistor; an orthogonal projection of the pixel electrode on the base substrate is non-rectangular, and an edge of the pixel electrode adjacent to the second signal line has a fold line shape; The pixel electrode is divided into a sixth portion adjacent to the first portion and a seventh portion connected to the sixth portion and adjacent to the second portion or the third portion, an edge of the seventh portion adjacent to the second signal line extends along the column direction, and an included angle between at least a part of the edge of the sixth portion adjacent to the second signal line and the column direction is greater than 0°.

[0017] In some embodiments, the array substrate further includes a common electrode electrically connected to the common electrode line; the common electrode is located on a side of the pixel electrode that is farther from the base substrate; the common electrode includes a first pattern layer and a second pattern layer located on a side of the first pattern layer away from the base substrate, the first pattern layer being electrically connected to the second pattern layer; the first pattern layer includes a plurality of first stripe portions arranged along a row direction and extending along a column direction, and first opening regions located between the first stripe portions; the second pattern layer includes second stripe portions arranged along a plurality of rows and extending along a column direction, and a distance between the first stripe portions and the second stripe portions in the row direction is greater than 0; The orthogonal projection of the first stripe portion on the base substrate covers the orthogonal projection of the second signal line on the base substrate, the orthogonal projection of the first stripe portion on the base substrate and the orthogonal projection of the pixel electrode on the base substrate do not overlap each other, and the orthogonal projection of the second stripe portion on the base substrate overlaps with the orthogonal projection of the pixel electrode on the base substrate.

[0018] In some embodiments, the distance between the pixel electrode and the first stripe portion in the row direction is greater than zero.

[0019] In some embodiments, the first stripe portion includes a first sublayer and a second sublayer stacked in a direction perpendicular to the base substrate, the second sublayer being located on the side of the first sublayer away from the base substrate, the width of the first sublayer being greater than the width of the second sublayer in the row direction, and the orthogonal projection of the second sublayer on the base substrate being within the range of the orthogonal projection of the first sublayer on the base substrate.

[0020] In some embodiments, the second sub-layer has a thickness in a direction perpendicular to the base substrate of at least 0.1 micrometers and at most 2 micrometers.

[0021] In some embodiments, the first pattern layer further includes a third stripe portion extending along the row direction and connected to the plurality of first stripe portions, and the second pattern layer further includes a fourth stripe portion extending along the row direction and connected to the plurality of second stripe portions; an orthogonal projection of the fourth stripe portion on the base substrate overlaps with an orthogonal projection of the third stripe portion on the base substrate, and the second pattern layer covers an edge of the third stripe portion on a side closer to the first opening region; In some embodiments, in the column direction, the orthogonal projections of the two third stripe portions on both sides of the first opening region on the base substrate overlap with the orthogonal projections of the pixel electrodes on the base substrate.

[0022] In some embodiments, the orthogonal projection of the common electrode on the base substrate and the orthogonal projection of the gate electrode of the thin film transistor on the base substrate do not overlap each other.

[0023] In some embodiments, the first patterned layer is a light-shielding conductive layer and the second patterned layer is a transparent conductive layer.

[0024] The display panel provided by the embodiment of the present invention includes an array substrate provided by the embodiment of the present invention, an opposing substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposing substrate.

[0025] The display device provided by the embodiment of the present invention includes a display panel provided by the embodiment of the present invention.

[0026] In some embodiments, the display device comprises: The display panel further includes a light dividing assembly located on the display side thereof, the light dividing assembly including a plurality of light dividing repeat units extending along the column direction and arranged consecutively along the row direction, the light dividing repeat unit including M light dividing structures extending along the column direction and arranged consecutively along the row direction, each light dividing repeat unit corresponding to N columns of subpixel units in a pixel repeat unit row, M and N being integers greater than 1, and M and N being relatively prime. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a schematic diagram illustrating the configuration of a conventional display device. [Figure 2] FIG. 1 is a schematic diagram showing the relative luminance distribution of a conventional display device. [Figure 3] FIG. 1 is a schematic diagram showing the visual sensation distribution of a conventional display device. [Figure 4] 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention; [Figure 5] 5 is a schematic diagram of region c of FIG. 4 provided by an embodiment of the present invention. [Figure 6]5 is a schematic diagram of region a of FIG. 4 provided by an embodiment of the present invention. [Figure 7] 5 is a schematic diagram of region b of FIG. 4 provided by an embodiment of the present invention. [Figure 8] FIG. 10 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention. [Figure 9] FIG. 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present invention. [Figure 10] FIG. 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present invention. [Figure 11] FIG. 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present invention. [Figure 12] FIG. 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present invention. [Figure 13] 13 is a cross-sectional view taken along line A-A' of FIG. 12 provided in accordance with an embodiment of the present invention. [Figure 14] 1 is a schematic diagram of a display panel provided by an embodiment of the present invention; [Figure 15] 1 is a schematic diagram of a display device provided by an embodiment of the present invention; [Figure 16] FIG. 10 is a schematic diagram of another display device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part, not all, of the embodiments of the present invention. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0029] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning understood by those skilled in the art to which this invention belongs. The terms "first," "second," and similar terms used herein do not denote order, quantity, or importance, but are used only to distinguish between different components. Terms such as "comprise" or "contain" mean that the element or thing preceding the term includes the elements or things listed thereafter and their equivalents, without excluding other elements or things. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. Terms such as "top," "bottom," "left," and "right" are only used to express relative positions, and if the absolute positions of the described objects change, the relative positions may also change accordingly.

[0030] The size and shape of each figure in the drawings do not reflect actual dimensions, but are merely for the purpose of explaining the present invention. Throughout the drawings, the same or similar reference numerals indicate the same or similar elements, or elements having the same or similar functions.

[0031] In the prior art, as shown in Figure 1, a display device includes multiple pixel islands S and multiple cylindrical lenses Z arranged at intervals along the row direction X and column direction Y. Each pixel island S includes multiple subpixels O8 arranged at intervals along the row direction X. M cylindrical lenses Z cover N columns of subpixels, which solves the macro-moiré problem but creates the micro-moiré problem. In a unit with a period of M=5, the areas corresponding to each cylindrical lens have different brightness at different viewing angles in space, and the brightness of the five cylindrical lens areas viewed at any viewing angle is also different. Figure 2 shows the relative brightness distribution of the five areas viewed from a certain angle. The visual sensory effect on people is shown in Figure 3. Every five areas has one area with the lowest brightness, called a dark area. These dark areas connect to form thin stripes, but the spacing between the thin stripes is wide (approximately 727.2 μm), making them easily noticeable to the human eye, resulting in subtle moiré.

[0032] An embodiment of the present invention provides an array substrate, as shown in Figures 4, 5 and 6. The array substrate includes a base substrate 015, a plurality of sub-pixel units 08 located on one side of the base substrate 015, a plurality of first signal lines 016 and a plurality of second signal lines 017.

[0033] The plurality of first signal lines 016 and the plurality of second signal lines 017 intersect with each other to define an aperture region 08-1 of the subpixel unit 08.

[0034] The subpixel units 08 are arranged in an array along the row direction X and the column direction Y, and the subpixel units 08 arranged at intervals along the row direction X form a pixel island S. The pixel islands S arranged consecutively along the column direction Y form a pixel repeating unit 04. A pixel repeating unit group 014 arranged in one row along the row direction X forms a pixel repeating unit row 013. An aperture region 08-1 of the subpixel units 08 arranged in one row along the row direction X forms an aperture region row 018.

[0035] The first signal lines 016 are arranged in the column direction Y, and the second signal lines 017 are arranged in the row direction X.

[0036] Each second signal line 017 includes a plurality of first portions 029 and a plurality of second portions 030 extending along the column direction Y. The second portions 030 include a portion extending along the inclined direction Q. The second portions 030 connect two first portions 029, and the included angle between the inclined direction Q and the column direction Y and the included angle between the inclined direction Q and the row direction X are greater than zero.

[0037] The first portion 029 is adjacent to the aperture region of the subpixel in the row direction X, and each of the multiple second portions 030 at least partially passes through the region between two adjacent pixel repeat unit rows 013, and the distance H in the row direction X between the two first portions 029 connected to the second portions 030 is greater than 0.

[0038] In the array substrate provided by the embodiment of the present invention, each of the plurality of second portions at least partially passes through the region between two adjacent pixel repeat unit rows, and the distance between two first portions connected to the second portion in the row direction is greater than 0, so that the aperture regions of the subpixels in the two at least partially adjacent pixel repeat unit rows are arranged with a shift in the row direction. When the array substrate is applied to a display device having light dividing repeat units, the distribution of the dark areas corresponding to the light dividing repeat units is disturbed, which causes the shift in the position of the dark areas and the formation of thin stripes in the column direction due to the continuous dark areas can be avoided, and the problem of fine moire can be alleviated.

[0039] It should be noted that only the aperture region 08-1 of the subpixel unit is shown in Fig. 4. Fig. 5 is a schematic structural diagram of region c in Fig. 4. In Fig. 5, the second portion 030 includes a portion extending along the first tilt direction Q1. Fig. 6 is a schematic structural diagram of region a in Fig. 4, in which the second portion 030 includes a portion extending along the second tilt direction Q2.

[0040] In some embodiments, as shown in Figures 4 and 5, the orthogonal projection of the second portion 030 on the base substrate 015 overlaps with the orthogonal projection of the area between two offset rows of opening areas 018 on the base substrate 015.

[0041] In some embodiments, as shown in FIG. 4, within one pixel repeating unit 04, sub-pixel units 08 of the same pixel island S have the same display color, and sub-pixel units 08 of different pixel islands S have different display colors.

[0042] 4, one pixel repeating unit 04 includes a first pixel island 05, a second pixel island 06, and a third pixel island 07. The first pixel island 05 includes a plurality of red subpixel units R, the second pixel island 06 includes a plurality of green subpixel units G, and the third pixel island 07 includes a plurality of blue subpixel units B.

[0043] In some embodiments, as shown in FIG. 4, the sub-pixel units S08 in a pixel island S in one row have the same display color.

[0044] 5 and 6, the plurality of first signal lines 016 includes a plurality of first scan lines 019 and a plurality of second scan lines 020. The first scan lines 019 and the second scan lines 020 are arranged alternately, that is, the present invention adopts a dual gate electrode design.

[0045] The subpixel units 08 in the same row are electrically connected to one first scan line 019 and one second scan line 020, and in the column direction Y, the first scan lines 019 and second scan lines 020 that are electrically connected to the subpixel units 08 in the same row are located on both sides of the aperture region row 018. That is, between two adjacent aperture region rows 08-1, there is one first scan line 019 and one second scan line 020, and the first scan line 019 and the second scan line 020 are each electrically connected to the subpixel units 08 corresponding to different aperture region rows 08-1.

[0046] The plurality of second signal lines 017 includes a plurality of data lines 021 and a plurality of common electrode lines 022, and the data lines 021 and the common electrode lines 022 are arranged alternately.

[0047] Each data line 021 is electrically connected to two adjacent columns of sub-pixel units 08 in the row direction X.

[0048] The sub-pixel unit 08 includes a thin film transistor TFT. A gate electrode G of the thin film transistor TFT is electrically connected to a first signal line 016. A source electrode S of the thin film transistor TFT is electrically connected to a data line 021.

[0049] In the sub-pixel units of two adjacent rows, two thin film transistors electrically connected to the same data line share a source electrode.

[0050] In the array substrate provided by the embodiment of the present invention, a dual gate electrode design is adopted, so that two thin film transistors electrically connected to the same data line in two adjacent rows of subpixel units share a source electrode, which facilitates reducing the non-aperture area of ​​the subpixel units, i.e., reducing the area of ​​the non-aperture area, and promoting the improvement of the aperture ratio of the subpixels.

[0051] In some embodiments, as shown in FIGS. 5 and 6, the second portion 030 included in the data line 021 is reused as the source electrode S of the thin film transistor TFT.

[0052] Among the plurality of second signal lines, the data lines are electrically connected to the thin film transistors, and the common electrode lines are not electrically connected to the thin film transistors.

[0053] In some embodiments, as shown in Figures 5 and 6, the active layers 023 of two thin film transistors TFTs electrically connected to the second portions 030 included in the data line 021 are connected together, and the second portions 030 included in the data line 021 are electrically connected to the active layers 023 connected together only through the first via holes 034.

[0054] In the array substrate provided by the embodiment of the present invention, two thin film transistors electrically connected to the same data line in two adjacent rows of subpixel units share a source electrode, and the active layers of the two transistors are integrally connected, so that the shared source electrode only needs to be electrically connected to the integrally connected active layer through one first via hole, thereby reducing the area of ​​the non-aperture region and facilitating an improvement in aperture ratio. In addition, the parasitic capacitance generated by the active layer and the source electrode ensures that the capacitances of the two scan lines are constant, thereby avoiding signal delays caused by the charging and discharging process of the resistor (R) controlling the capacitor (C), i.e., avoiding display defects caused by RC delay mismatch.

[0055] In some embodiments, the orthogonal projection of the second portion on the base substrate has the shape of the fold line.

[0056] 5 and 6, the second portion 030 includes two first sub-portions 024 extending parallel to each other along the inclination direction Q and a second sub-portion 025 connecting the two first sub-portions 024. The second sub-portion 025 extends along the column direction Y, and the two first sub-portions 024 are each connected to a different first portion 029.

[0057] In some embodiments, as shown in FIGS. 5 and 6, the orthogonal projection of the drain electrode D of the thin film transistor TFT on the base substrate is disposed in an area surrounded by the first scan line 019, the second scan line 020 and two second sub-portions 025 adjacent to each other in the row direction X.

[0058] In the array substrate provided by the embodiment of the present invention, the second portion has a fold line shape, and the two first portions electrically connected to the second portion via two first sub-portions extending in the oblique direction and two second sub-portions extending in the column direction are staggered, thereby staggering the subpixel units. In addition, in the second portion, the portions extending in the oblique direction and the portions extending in the column direction are alternately connected, and a rectangular or nearly rectangular region still exists between two adjacent second portions in the row direction, thereby preventing an increase in the difficulty of wiring the thin film transistors.

[0059] It should be noted that in FIG. 5 the first sub-portion 024 extends along a first inclined direction Q1, and in FIG. 6 the first sub-portion 024 extends along a second inclined direction Q2.

[0060] In some embodiments, the angle between the first tilt direction and the column direction X and the angle between the second tilt direction and the column direction X can be selected according to actual needs.

[0061] 5 and 6, the orthogonal projection of one of the two first sub-portions 024 on the base substrate 015 overlaps with the orthogonal projection of the first scan line 019 on the base substrate 015. The orthogonal projection of the other of the two first sub-portions 024 on the base substrate 015 overlaps with the orthogonal projection of the second scan line 020 on the base substrate 015.

[0062] The orthogonal projection of the second sub-portion 025 on the base substrate 015 and the orthogonal projection of the first signal line 016 on the base substrate 015 do not overlap each other.

[0063] 7, each second signal line 017 further includes a plurality of third portions 031. The remaining first portions 029 other than the first portions 029 connected via the second portions 030 are connected via the third portions 031.

[0064] The two first portions 029 connected via the third portion 031 are on the same straight line in the column direction Y.

[0065] The third portion 031 includes a third sub-portion 026, a fourth sub-portion 027, and a fifth sub-portion 028 extending along the column direction Y.

[0066] The two ends of the fifth sub-portion 028 are electrically connected to the third sub-portion 026 and the fourth sub-portion 027, respectively. The third sub-portion 026 and the fourth sub-portion 027 are electrically connected to two different first portions 029, respectively.

[0067] The inclination direction Q includes a first inclination direction Q1 and a second inclination direction Q2. One of the third sub-portion 026 and the fourth sub-portion 027 extends along the first inclination direction Q1, and the other of the third sub-portion 026 and the fourth sub-portion 027 extends along the second inclination direction Q2. The first inclination direction Q1 intersects with the second inclination direction Q2.

[0068] The two first portions 029 connected via the third portion 031 are on the same straight line in the column direction Y.

[0069] It should be noted that the first portions other than those connected via the second portions are connected via the third portions, i.e., in the regions that are not staggered between adjacent rows of opening regions, the first portions are connected via the third portions.

[0070] In the array substrate provided by the embodiment of the present invention, the third portion is composed of a third sub-portion, a fourth sub-portion, and a fifth sub-portion extending along the column direction, each of which has a different inclination direction. That is, the orthogonal projection of the third portion on the base substrate has a fold line shape and a raised fold line shape. Therefore, the two first portions connected through the third portion are collinear in the column direction, that is, the two first portions connected through the third portion are not misaligned. This ensures that the RC delays of the transistors corresponding to the adjacent subpixel units, the third portion, and the second portion are consistent, thereby avoiding display defects caused by RC delay mismatches.

[0071] 7 is an enlarged schematic view of region b in FIG.

[0072] 7, the orthogonal projection of the third sub-portion 026 on the base substrate 015 overlaps with the orthogonal projection of the first scan line 019 on the base substrate 015. The orthogonal projection of the fourth sub-portion 027 on the base substrate 015 overlaps with the orthogonal projection of the second scan line 020 on the base substrate 015.

[0073] The orthogonal projection of the fifth sub-portion 028 on the base substrate 015 and the orthogonal projection of the first signal line 016 on the base substrate 015 do not overlap each other.

[0074] In some embodiments, as shown in FIG. 7, the active layers 023 of two thin film transistors TFT electrically connected to the third portion 031 are integrally connected, and the third portion 031 is electrically connected to the active layers 023 that are integrally connected through only one first via hole 034.

[0075] That is, the third portion is reused as the source electrode of the thin film transistor, and the two thin film transistors corresponding to the third portion share the source electrode, which reduces the area of ​​the non-aperture region and makes it easier to improve the aperture ratio.

[0076] 7 shows an example in which the third sub-portion 026 extends along the first inclination direction Q1 and the fourth sub-portion 027 extends along the second inclination direction Q2. In some embodiments, as shown in FIG. 8, the fourth sub-portion 027 may extend along the first inclination direction Q1 and the third sub-portion 026 may extend along the second inclination direction Q2. Furthermore, as shown in FIG. 8, in some third portions 031, the third sub-portion 026 may extend along the first inclination direction Q1 and the fourth sub-portion 027 may extend along the second inclination direction Q2, and in the remaining third portions 031, the fourth sub-portion 027 may extend along the first inclination direction Q1 and the third sub-portion 026 may extend along the second inclination direction Q2.

[0077] In some embodiments, as shown in Figures 8 and 9, the subpixel unit 08 further includes a pixel electrode 037 electrically connected to the thin film transistor TFT, and the pixel electrode 037 is electrically connected to the drain electrode D of the thin film transistor TFT through a second via hole 035.

[0078] The orthogonal projection of the pixel electrode 037 on the base substrate is non-rectangular, and the edge of the pixel electrode adjacent to the second signal line 017 has the shape of a fold line.

[0079] The pixel electrode 037 is divided into a sixth portion 038 adjacent to the first portion 029, and a seventh portion 039 connected to the sixth portion 038 and adjacent to the second portion 030 or the third portion 031. The edge of the seventh portion 039 adjacent to the second signal line 017 extends along the column direction Y, and the included angle between the edge of the sixth portion adjacent to the second signal line 017 and the column direction Y is greater than 0.

[0080] In the array substrate provided by the embodiment of the present invention, the second signal line includes a second portion and a third portion having a fold line shape, each pixel electrode includes a sixth portion covering the aperture area and adjacent to the first portion, and a seventh portion located in the non-aperture area, the seventh portion being regarded as a portion bent relative to the sixth portion, and the pattern of a portion of the pixel electrode electrically connected to the thin film transistor coincides with the region between two adjacent second portions in the row direction or the region between two adjacent third portions in the row direction, thereby ensuring consistency in storage capacitance of subpixel units at different locations.

[0081] In some embodiments, the thin film transistor may have a bottom-gate structure or a top-gate structure. Taking the top-gate structure as an example, the array substrate further includes a light-shielding layer 033 disposed between the active layer 023 and the base substrate, a buffer layer 040 disposed between the active layer 023 and the light-shielding layer 033, a gate insulating layer 041 disposed between the active layer 023 and the gate electrode G, an interlayer insulating layer 042 disposed between the gate electrode G and the source electrode S and the drain electrode D, and a first passivation layer 043 disposed between the source electrode S, the drain electrode D, and the pixel electrode 037. The pixel electrode 037 is electrically connected to the drain electrode D through a second via hole 035 penetrating the first passivation layer 043. The source electrode S is electrically connected to the active layer 023 through a first via hole 034 penetrating the interlayer insulating layer 042 and the gate insulating layer 041. The drain electrode D is electrically connected to the active layer 023 through a third via hole 036 that penetrates the interlayer insulating layer 042 and the gate insulating layer 041 .

[0082] In some embodiments, in the row direction X, the ratio of the width h1 of the aperture region of the subpixel unit to the width of the pixel island S is i / M, where M is an integer greater than 1 and i is an integer greater than or equal to 1 and less than M.

[0083] As shown in Figure 4, a plurality of pixel repeat unit rows 013 are divided into a plurality of pixel repeat unit groups 014, and each pixel repeat unit group 014 includes M pixel repeat unit rows 013. In Figure 4, M = 5 is taken as an example for illustration purposes.

[0084] In some embodiments, for each pixel repeat unit group, the ratio of the misalignment vector of the first portion corresponding to the j-th pixel repeat unit row in the row direction to the first portion corresponding to the 1st pixel repeat unit row in the row direction and the width of the aperture area of ​​the subpixel unit in the row direction is Jj=±E / M, where j is an integer greater than 1 and less than or equal to M, and E is an integer greater than or equal to 1 and is not equal to M or an integer multiple of M.

[0085] Note that the misalignment vector of the first portion corresponding to the jth pixel repeat unit row in the row direction relative to the first portion corresponding to the first pixel repeat unit row in the row direction is equal to the misalignment vector of the dth sub-pixel unit in the jth pixel repeat unit row relative to the dth sub-pixel unit in the first pixel repeat unit row in the row direction X, where d is an integer greater than or equal to 1 and less than or equal to N. Therefore, as shown in Figure 4, the ratio of the misalignment vector Hj of the dth sub-pixel unit 08 in the jth pixel repeat unit row 013 relative to the dth sub-pixel unit 08 in the first pixel repeat unit row 013 in the row direction X to the width h1 of the sub-pixel unit 08 in the row direction X is also Jj.

[0086] That is, in an embodiment of the present invention, in each pixel repeat unit group, each sub-pixel in the second pixel repeat unit row through each sub-pixel in the Mth pixel repeat unit row are all arranged with a shift of Jj×h1 relative to the sub-pixels in the first pixel repeat unit row.

[0087] 4 takes the row direction X as an example, and the row direction X is the extension direction in the left-right direction in the figure. The sub-pixel units 08 in the jth pixel repeat unit row 013 may be shifted to the left relative to the sub-pixel units 08 in the first pixel repeat unit row 013, in which case Hj is positive, i.e., the misalignment vector of the first portion corresponding to the jth pixel repeat unit row in the row direction relative to the first portion corresponding to the first pixel repeat unit row in the row direction is positive, i.e., Jj=+E / M. Also, the sub-pixel units 08 in the jth pixel repeat unit row 013 may be shifted to the right relative to the sub-pixels 08 in the first pixel repeat unit row 013, in which case Hj is negative, and the misalignment vector of the first portion corresponding to the jth pixel repeat unit row in the row direction relative to the first portion corresponding to the first pixel repeat unit row in the row direction is negative, Jj=-E / M.

[0088] In some embodiments, in the 2nd to Mth pixel repeat unit rows, the Jj corresponding to any two pixel repeat unit rows are not equal, and the absolute value of the difference between the Jj corresponding to any two pixel repeat unit rows is not an integer greater than or equal to 1. In this way, in one pixel repeat unit group, the dark areas are not on the same column in the column direction, and the distance between two dark areas aligned in the column direction can be increased, thereby avoiding the appearance of thin lines in the column direction that can be easily detected by the human eye.

[0089] In some embodiments, when M=5, Jj can be -11 / 5, -6 / 5, -4 / 5, -3 / 5, -2 / 5, -1 / 5, 1 / 5, 2 / 5, 3 / 5, 4 / 5, 6 / 5, 11 / 5, etc. The difference between two values ​​of Jj is M or an integer multiple of M. For example, when Jj is -6 / 5 and -1 / 5, respectively, the number of brightness areas between the dark areas of the current row and the dark areas of the first row is the same as the number of brightness areas between the dark areas of the current row and the dark areas of the first row when Jj is -1 / 5. Therefore, E can be set to an integer greater than or equal to 1 and less than M. That is, the misalignment vector of the first portion corresponding to the jth pixel repeat unit row in the row direction relative to the first portion corresponding to the first pixel repeat unit row in the row direction does not exceed the width of one subpixel in the row direction X. Therefore, the distribution of the dark areas is disrupted, avoiding excessive misalignment distances between subpixel units and leading to rational utilization of the space on the array substrate.

[0090] When M=5 and E is an integer greater than or equal to 1 and less than M, Jj is one of the following: -4 / 5, -3 / 5, -2 / 5, -1 / 5, 1 / 5, 2 / 5, 3 / 5, 4 / 5.

[0091] In some embodiments, when M is 5, J2 is -2 / 5 or 3 / 5, J3 is 1 / 5 or -4 / 5, J4 is -1 / 5 or 4 / 5, and J5 is 2 / 5 or -3 / 5.

[0092] In some embodiments, for example, J2 is -2 / 5, J3 is 1 / 5, J4 is -1 / 5, and J5 is 2 / 5. The displacement vector of the first portion corresponding to the second pixel repeat unit row relative to the first portion corresponding to the first pixel repeat unit row in the row direction is (-2 / 5)h1. The displacement vector of the first portion corresponding to the third pixel repeat unit row relative to the first portion corresponding to the first pixel repeat unit row in the row direction is (1 / 5)h1. The displacement vector of the first portion corresponding to the fourth pixel repeat unit row relative to the first portion corresponding to the first pixel repeat unit row in the row direction is (-1 / 5)h1. The displacement vector of the first portion corresponding to the fifth pixel repeat unit row relative to the first portion corresponding to the first pixel repeat unit row in the row direction is (2 / 5)h1. Therefore, as shown in Figure 4, H2 = (-2 / 5) h1, H3 = (1 / 5) h1, H4 = (-1 / 5) h1, and H5 = (2 / 5) h1.

[0093] Of course, in some embodiments, J2 may be 3 / 5, J3 may be -4 / 5, J4 may be 4 / 5, and J5 may be -3 / 5.

[0094] 4, the aperture regions 08-1 of the sub-pixels 08 in any two adjacent pixel repeat unit rows 013 are arranged with a shift in the row direction X. That is, the difference ΔJ between the Jj corresponding to any two adjacent pixel repeat unit rows 013 is not zero.

[0095] Note that when E is an integer greater than or equal to 1 and less than M, if Jj corresponding to the jth pixel repeat unit row to Jj-1 corresponding to the j-1th pixel repeat unit row is greater than 0, i.e., if ΔJ is greater than 0, the j-1th pixel repeat unit row is shifted to the right relative to the jth pixel repeat unit row. If Jj corresponding to the jth pixel repeat unit row to Jj-1 corresponding to the j-1th pixel repeat unit row is less than 0, i.e., if ΔJ is less than 0, the j-1th pixel repeat unit row is shifted to the left relative to the jth pixel repeat unit row. If ΔJ is greater than 0, the second portion includes a portion extending along the first tilt direction Q1. If ΔJ is less than 0, the second portion includes a portion extending along the second tilt direction Q2.

[0096] Note that Figure 5 shows the area between the second pixel repeat unit row 013 and the first pixel repeat unit row 013. In Figure 5, the distance between two first portions 029 connected via second portions 030 is H' = H2 = (-2 / 5) h1. Figure 6 shows the area between the second pixel repeat unit row 013 and the third pixel repeat unit row 013. In Figure 5, the distance between two first portions 029 connected via second portions 030 is H' = |H3 - H2| = (3 / 5) h1.

[0097] In some embodiments, when the aperture regions of the sub-pixels in any two adjacent pixel repeat unit rows are arranged staggered in the row direction, the orthogonal projection of the second portion on the base substrate overlaps with the orthogonal projection of the area between two adjacent aperture region rows located in two different pixel repeat unit rows on the base substrate, and the orthogonal projection of the third portion on the base substrate overlaps with the orthogonal projection of the area between two adjacent aperture region rows 018 in the same pixel repeat unit row on the base substrate.

[0098] 11 , the array substrate further includes a common electrode 044 electrically connected to the common electrode line. The common electrode 044 is located on a side of the pixel electrode 037 that is away from the base substrate 015. The common electrode 044 includes a first pattern layer 045 and a second pattern layer 046 located on a side of the first pattern layer 045 that is away from the base substrate 015. The first pattern layer 045 is electrically connected to the second pattern layer 046.

[0099] As shown in FIG. 12, the first pattern layer 045 includes a plurality of first stripe portions 047 arranged in the row direction X and extending in the column direction Y, and first opening regions 053 located between the first stripe portions 047.

[0100] 12, the second pattern layer 046 includes a plurality of second stripe portions 048 arranged in the row direction X and extending in the column direction Y. In the row direction X, the distance between the first stripe portions 047 and the second stripe portions 048 is greater than zero.

[0101] The orthogonal projection of the first stripe portion 047 on the base substrate 015 covers the orthogonal projection of the second signal line 017 on the base substrate 015. The orthogonal projection of the first stripe portion 047 on the base substrate 015 and the orthogonal projection of the pixel electrode 037 on the base substrate 015 do not overlap each other. The orthogonal projection of the second stripe portion 048 on the base substrate 015 overlaps with the orthogonal projection of the pixel electrode 037 on the base substrate 015.

[0102] In some embodiments, as shown in FIG. 11, the array substrate further includes a second passivation layer 052 located between the common electrode 044 and the pixel electrode 037.

[0103] In some embodiments, the first patterned layer is a light-shielding conductive layer and the second patterned layer is a transparent conductive layer.

[0104] In some embodiments, the material of the first pattern layer is a black or low-reflectivity metallic material, such as molybdenum, and the material of the second pattern layer and pixel electrodes is, for example, indium tin oxide (ITO).

[0105] Note that when the pixel electrode is located on the side of the common electrode away from the base substrate, the positions of the common electrode and pixel electrode are swapped in Figure 11. To avoid affecting the wrapping effect, the pixel electrode is electrically connected to the thin-film transistor through a transfer electrode located on the same layer as the common electrode. The transfer electrode is then electrically connected to the drain electrode through a via hole between the pixel electrode and the transfer electrode. The pixel electrode is electrically connected to the transfer electrode through a via hole that penetrates the second passivation layer. To ensure a flat surface beneath the via hole and avoid wrapping defects, the orthographic positions of these two via holes on the base substrate are different. Due to the limited size of the non-aperture area, the via hole electrically connecting the pixel electrode and the transfer electrode is usually located within the display area, which affects the aperture ratio of the subpixel unit.

[0106] In the array substrate provided by the embodiment of the present invention, the common electrode is disposed on the side of the pixel electrode away from the base substrate, thereby avoiding the need for via holes electrically connecting the pixel electrode and the transfer electrode within the display area and thereby preventing the aperture ratio of the subpixel unit from being affected. Furthermore, the second signal line is blocked by the first pattern layer, preventing light leakage between adjacent subpixel units. The second pattern layer overlapping the pixel electrode is a light-transmitting layer, preventing the light transmittance of the subpixel unit from being affected.

[0107] In some embodiments, as shown in FIG. 11, the distance h2 between the pixel electrode 037 and the first stripe portion 047 in the row direction X is greater than 0.

[0108] In order to increase the aperture ratio of the subpixel units, the width of the first stripe portion in the row direction is narrow, and if the pixel electrode extends to the underside of the first stripe portion in the row direction, short circuits are likely to occur between the pixel electrodes of adjacent subpixel units.

[0109] In the array substrate provided by the embodiment of the present invention, the pixel electrode and the orthogonal projection of the first stripe portion do not overlap each other in the row direction, and the distance between the pixel electrode and the first stripe portion is greater than 0, thereby preventing the electric field of the pixel electrode from crosstalking to adjacent subpixel units.

[0110] In some embodiments, for example, h2 is the minimum distance between the pixel electrode and the first stripe portion that is feasible in consideration of process conditions and alignment errors.

[0111] 11 , the first stripe portion 047 includes a first sublayer 050 and a second sublayer 051 stacked in a direction perpendicular to the base substrate 015. The second sublayer 051 is located on the side of the first sublayer 050 that is away from the base substrate 015. In the row direction X, the width of the first sublayer 050 is greater than the width of the second sublayer 051, and the orthogonal projection of the second sublayer 051 on the base substrate 015 is within the range of the orthogonal projection of the first sublayer 050 on the base substrate 015. The distance between the edge of the orthogonal projection of the second sublayer 051 on the base substrate 015 and the edge of the orthogonal projection of the first sublayer 050 on the base substrate 015 is greater than zero. That is, the cross section of the first stripe portion has a staircase structure.

[0112] In the array substrate provided by the embodiment of the present invention, the first pattern layer is a light-shielding conductive layer, and the cross section of the first stripe portion has a stepped structure, which is equivalent to the thickness of the first stripe portion decreasing near the side of the aperture region of the subpixel unit. The transmittance of the region of the first stripe portion not covered by the second sublayer is higher than the transmittance of the region of the first stripe portion covered by the second sublayer, and since the region not covered by the second sublayer is close to the aperture region of the subpixel unit, the aperture ratio of the subpixel unit is preferably high.

[0113] When the array substrate is applied to a liquid crystal display panel, it is necessary to provide a counter substrate disposed opposite the array substrate and a liquid crystal layer positioned between the array substrate and the counter substrate, and to provide spacers on the counter substrate to support the liquid crystal cell. The array substrate needs to be provided with an alignment film to align the liquid crystal in the liquid crystal layer, but if the spacer slips, the alignment film is easily damaged, and if the alignment film in the opening region of the subpixel unit is damaged, it can cause light leakage defects.

[0114] In the array substrate provided by the embodiment of the present invention, the cross section of the first stripe portion has a staircase structure, so that when the liquid crystal display panel is pressurized and the spacer slides significantly, the spacer slides up to the step formed by the second sub-layer and the first sub-layer, blocking the spacer and preventing the spacer from sliding to the opening region of the sub-pixel unit and damaging the alignment layer in this region.

[0115] In some embodiments, the thickness of the second sub-layer 051 in a direction perpendicular to the base substrate 015 is between 0.1 micrometers and 2 micrometers.

[0116] In some embodiments, as shown in FIG. 12 , the first pattern layer 045 further includes a third stripe portion 049 extending along the row direction X and connected to the plurality of first stripe portions 047, and the second pattern layer 046 further includes a fourth stripe portion 052 extending along the row direction X and connected to the plurality of second stripe portions 048.

[0117] 13, the orthogonal projection of the fourth stripe portion 052 onto the base substrate 015 overlaps with the orthogonal projection of the third stripe portion 049 onto the base substrate 015. The second pattern layer 046 covers the edge of the third stripe portion 049 on the side closer to the first opening region.

[0118] Note that Fig. 13 is a cross-sectional view taken along line A-A' in Fig. 12. In Fig. 12, the region surrounded by the third stripe portion 049 and the first stripe portion 047 is the first opening region 053, which corresponds to the opening region of a sub-pixel unit (not shown).

[0119] In some embodiments, in the column direction Y, as shown in FIG. 13, the orthogonal projections of the two third stripe portions 049 on either side of the first opening region 053 on the base substrate 015 overlap with the orthogonal projections of the pixel electrodes 037 on the base substrate 015.

[0120] In the array substrate provided by the embodiment of the present invention, the pixel electrode extends to the underside of the third stripe portion, and the second pattern layer covers the edge of the third stripe portion closer to the first opening region. That is, the second pattern layer wraps around the third stripe portion, thereby preventing the arc-shaped edge of the third stripe portion from occurring at the edge of the first opening region due to the resolution of the etching and exposure processes. When the array substrate is applied to a liquid crystal display panel, the formation of a vertical electric field can be avoided, and light leakage from the liquid crystal can be prevented.

[0121] In some embodiments, the orthogonal projection of the common electrode on the base substrate and the orthogonal projection of the gate electrode of the thin film transistor on the base substrate do not overlap each other. Specifically, as shown in Figure 13, the common electrode 044 has a second opening region 054 in an area corresponding to the gate electrode G of the thin film transistor. In the array substrate provided in the embodiments of the present invention, the common electrode is hollowed out above the gate electrode of the thin film transistor, thereby reducing the RC delay of the gate electrode of the thin film transistor and the gate electrode, and preventing an increase in the delay amount from affecting the charging of the pixel when the gate electrode is turned on.

[0122] In some embodiments, as shown in FIG. 12, the first pattern layer 045 further includes fifth stripe portions 058 between the second open areas 054 .

[0123] The second aperture region is disposed in a non-aperture region other than the aperture region of the subpixel unit s, i.e., a region corresponding to the second portion or the third portion. The second portion or the third portion has a folded line shape, and the gate electrode is located between two adjacent second portions or two adjacent third portions in the row direction and is aligned with the position of the gate electrode. Therefore, as shown in FIG. 12 , the distance between the nearest fifth stripe portion 058 and the nearest first stripe portion 047 in the row direction X is greater than 0.

[0124] Based on the same inventive idea, an embodiment of the present invention further provides a display panel, which includes an array substrate 055 provided by the embodiment of the present invention, an opposing substrate 056 disposed opposite the array substrate 055, and a liquid crystal layer 057 located between the array substrate 055 and the opposing substrate 056, as shown in FIG.

[0125] Based on the same inventive idea, an embodiment of the present invention further provides a display device. As shown in Figure 15, the display device includes a display panel 01 provided by an embodiment of the present invention.

[0126] In some embodiments, as shown in Figure 15, the display device further includes a light dividing assembly 02 located on the display side of the display panel 01. As shown in Figure 16, the light dividing assembly includes a plurality of light dividing repeat units 03 extending along a column direction Y and arranged consecutively along a row direction X. The light dividing repeat unit 03 includes M light dividing structures A extending along the column direction Y and arranged consecutively along the row direction X. Each light dividing repeat unit 03 corresponds to N columns of subpixel units in a pixel repeat unit row 013. Both M and N are integers greater than 1, and M and N are relatively prime.

[0127] The display device provided by the embodiment of the present invention can be applied to a three-dimensional (3D) display and can also switch between a 3D display and a 2D display. A pixel island can be used as a sub-pixel of a 2D display. Because one pixel island contains multiple sub-pixels, the same resolution as a 2D display can be maintained in 3D display mode. Combining human eye-tracking with a 3D display with a high pixel per inch (ppi) can realize a multi-view display with a wide viewing angle. It can also achieve more information and reduced color crosstalk between adjacent views.

[0128] In some embodiments, the light dividing structure is used to control the light emission angle of each sub-pixel to emit light in a directional manner.

[0129] In some embodiments, the display panel may be one of a liquid crystal display panel (LCD), an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED), a micro inorganic light emitting diode (micro LED) display panel, and a mini light emitting diode (mini LED) display panel.

[0130] In some embodiments, the display device further includes a spacer dielectric layer 09 located between the light-splitting assembly 02 and the display panel 01, as shown in FIG.

[0131] In some embodiments, the light-splitting structure is a cylindrical lens.

[0132] 15, the cylindrical lens 010 includes a first resin layer 011 having a protrusion and a flat resin layer 012 located on the side of the first resin layer 011 away from the display panel 01. The refractive index of the flat resin layer 012 is smaller than that of the first resin layer 011.

[0133] Alternatively, in some embodiments, the cylinder lens is a liquid crystal lens.

[0134] Of course, in some embodiments, the light-splitting structure may be a geometric lens, a diffractive lens, a liquid lens, and other structural devices that can control the light emission direction of the sub-pixels.

[0135] In some embodiments, the display device further comprises a human eye tracking system for determining the position of the user's eyes in real time.

[0136] The display device provided by the embodiment of the present invention is a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, and other products or components having a display function. Other essential components of the display device should be understood by those skilled in the art and are not described herein or used as limitations of the present invention. The implementation of the display device can be seen in the above embodiments of the array substrate and the display panel, and will not be repeated here.

[0137] In summary, in the array substrate, display panel, and display device provided by the embodiments of the present invention, each of the plurality of second portions at least partially passes through the region between two adjacent pixel repeat unit rows, and the distance between two first portions connected to the second portion in the row direction is greater than 0. As a result, the aperture regions of the subpixels in two at least partially adjacent pixel repeat unit rows are arranged with a shift in the row direction. When the array substrate is applied to a display device having a light dividing repeat unit, the distribution of the dark areas corresponding to the light dividing repeat unit is disrupted, which prevents the dark areas from being misaligned and the formation of thin stripes in the column direction due to the continuous dark areas, and reduces the problem of fine moire.

[0138] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they understand the basic inventive concept. Therefore, the appended claims should be interpreted to include not only the preferred embodiments, but also all changes and modifications that fall within the scope of the present invention.

[0139] Obviously, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention. Therefore, if such modifications and changes of the present invention fall within the scope of the claims of the present invention and for the equivalent techniques thereof, the present invention intends to cover such modifications and changes. [Explanation of symbols]

[0140] 01 Display panel 02 Optical splitter assembly 03 Optical division repeating unit 04 Pixel repeat unit 05 1st Pixel Island 06 2nd Pixel Island 07 3rd Pixel Island 08 Subpixel Unit 08-1 Opening area 09 Spacer dielectric layer 010 Cylinder Lens 011 First resin layer 012 Flat resin layer 013 Unit Line 014 Unit Group 015 Base board 016 First signal line 017 Second signal line 018 Opening area row 019 1st scan line 020 2nd scan line 021 Data line 022 Common electrode line 023 Active layer 024 First Subpart 025 Second Subpart 026 Third Subpart 027 4th subsection 028 5th Subpart 029 Part 1 030 Part 2 031 Part 3 033 Light blocking layer 034 Beer Hall No. 1 035 Second Beer Hall 036 3rd Beer Hall 037 pixel electrode 038 Part 6 039 Part 7 040 Buffer layer 041 Gate insulating layer 042 Interlayer insulation layer 043 First passivation layer 044 Common electrode 045 1st pattern layer 046 Second pattern layer 047 First Stripe 048 Second Stripe 049 Third Stripe 050 1st Sub-Layer 051 Second Sub-Layer 052 Second passivation layer 052 4th Stripe 053 1st opening area 054 Second opening area 055 Array board 056 Opposing substrate 057 Liquid crystal layer 058 5th Stripe

Claims

1. Array substrate, The array substrate comprises a base substrate and The base substrate includes a plurality of subpixel units located on one side, a plurality of first signal lines, and a plurality of second signal lines, The plurality of first signal lines and the plurality of second signal lines intersect each other to define the aperture region of the subpixel unit. The plurality of subpixel units are arranged in an array along the row and column directions, the plurality of subpixel units arranged at intervals along the row direction form a pixel island, the plurality of pixel islands arranged continuously in the column direction form a pixel repeating unit, one row of the pixel repeating units arranged along the row direction forms a pixel repeating unit row, and the opening regions of one row of the subpixel units arranged along the row direction form an opening region row. The plurality of first signal lines are arranged along the column direction, and the plurality of second signal lines are arranged along the row direction. Each of the aforementioned second signal lines includes a plurality of first portions and a plurality of second portions extending along the column direction, the second portions include portions extending along the inclination direction, the second portions connect two of the aforementioned first portions, and the angle between the inclination direction and the row direction and the angle between the inclination direction and the column direction are greater than 0. An array substrate in which the first portion is adjacent to the aperture region of the subpixel in the row direction, and the plurality of second portions each pass through the region between at least partially adjacent rows of the pixel repeating unit, and the distance between two of the first portions connected to the second portions in the row direction is greater than 0.

2. The plurality of first signal lines include a plurality of first scan lines and a plurality of second scan lines, and the first scan lines and the second scan lines are arranged sequentially and alternately. Each subpixel unit in the same row is electrically connected to one first scan line and one second scan line, and in the column direction, each of the first and second scan lines electrically connected in correspondence with the subpixel units in the same row is located on both sides of the aperture region row. The plurality of second signal lines include a plurality of data lines and a plurality of common electrode lines, and the data lines and the common electrode lines are arranged sequentially and alternately. Each of the data lines is electrically connected to two adjacent rows of the subpixel units in the row direction. The subpixel unit includes a thin-film transistor, the gate electrode of the thin-film transistor is electrically connected to the first signal line, and the source electrode of the thin-film transistor is electrically connected to the data line. The array substrate according to claim 1, wherein in two adjacent rows of the subpixel units, two thin-film transistors electrically connected to the same data line share a source electrode.

3. The array substrate according to claim 2, wherein the active layers of two thin-film transistors electrically connected to the second portion included in the data line are integrally connected, and the second portion included in the data line is electrically connected to the integrally connected active layer via only one first via hole.

4. The array substrate according to claim 2 or 3, wherein the second portion includes two first sub-parts extending parallel to each other along the inclination direction and a second sub-part connecting the two first sub-parts, the second sub-part extending along the column direction, and each of the two first sub-parts being connected to a different first portion.

5. The orthographic projection of one of the two first subparts on the base substrate coincides with the orthographic projection of the first scan line on the base substrate, and the orthographic projection of the other of the two first subparts on the base substrate coincides with the orthographic projection of the second scan line on the base substrate. The array substrate according to claim 4, wherein the orthographic projection of the second sub-portion on the base substrate and the orthographic projection of the first signal line on the base substrate do not overlap with each other.

6. Each of the aforementioned second signal lines further comprises a plurality of third parts, the remaining first parts other than the first parts connected via the second parts, and the third parts are connected The two first parts connected via the third part are in the same straight line in the column direction, The third portion includes a third sub-part extending along a first inclination direction, a fourth sub-part extending along a second inclination direction, and a fifth sub-part extending along the row direction. Each of the two ends of the fifth sub-part is electrically connected to the third sub-part and the fourth sub-part, and each of the third sub-part and the fourth sub-part is electrically connected to two different first parts. The first inclination direction intersects with the second inclination direction, The array substrate according to claim 2, claim 3, or claim 5, wherein the two first portions connected via the third portion are in the same straight line in the column direction.

7. The orthographic projection of the third sub-portion on the base substrate overlaps with the orthographic projection of the second scan line on the base substrate, and the orthographic projection of the fourth sub-portion on the base substrate overlaps with the orthographic projection of the first scan line on the base substrate. The array substrate according to claim 6, wherein the orthographic projection of the fifth sub-portion on the base substrate and the orthographic projection of the first signal line on the base substrate do not overlap with each other.

8. The array substrate according to claim 6, wherein the active layers of two thin-film transistors electrically connected to the third portion are integrally connected, and the third portion is electrically connected to the integrally connected active layers via only one first via hole.

9. Any two adjacent rows of the pixel repeating unit are arranged offset from each other in the row direction, The orthographic projection of the second portion on the base substrate overlaps with the orthographic projection of the region between two adjacent rows of the aperture region located in two different rows of the pixel repeating unit on the base substrate. The array substrate according to claim 6, wherein the orthographic projection of the third portion on the base substrate overlaps with the orthographic projection of the region between two adjacent rows of the aperture region within the same row of repeating pixel units on the base substrate.

10. In the row direction, the ratio of the width of the aperture region of the subpixel unit to the width of the pixel island is i / M, where M is an integer greater than 1, and i is an integer between 1 and M. The aforementioned plurality of pixel repeating unit rows are divided into a plurality of pixel repeating unit groups, and each of the aforementioned pixel repeating unit groups contains M pixel repeating unit rows. The array substrate according to claim 9, wherein in each of the pixel repeating unit groups, the ratio of the shift vector of the first portion corresponding to the j-th pixel repeating unit row with respect to the first portion corresponding to the first pixel repeating unit row in the row direction to the width of the aperture region of the subpixel unit in the row direction is Jj = ±E / M, where j is an integer greater than 1 and less than or equal to M, and E is an integer between 1 and M.

11. The subpixel unit further includes a pixel electrode electrically connected to the thin-film transistor, The orthographic projection of the pixel electrode on the base substrate is non-rectangular, and the edge of the pixel electrode adjacent to the second signal line has the shape of a folded line. The array substrate according to claim 6, wherein the pixel electrode is divided into a sixth portion adjacent to the first portion and a seventh portion connected to the sixth portion and connected to the second portion or the third portion, the edge of the seventh portion adjacent to the second signal line extends along the column direction, and the angle between at least a portion of the edge of the sixth portion adjacent to the second signal line and the column direction is greater than 0.

12. The array substrate further includes a common electrode electrically connected to the common electrode wire, The common electrode is located on the side of the pixel electrode that is away from the base substrate. The common electrode includes a first pattern layer and a second pattern layer located on the side of the first pattern layer away from the base substrate, and the first pattern layer is electrically connected to the second pattern layer. The first pattern layer includes a plurality of first stripe portions arranged along the row direction and extending along the column direction, and a first opening region located between the first stripe portions. The second pattern layer includes a plurality of second stripe portions arranged along the row direction and extending along the column direction, wherein the distance between the first stripe portion and the second stripe portion in the row direction is greater than 0. The array substrate according to claim 11, wherein the orthographic projection of the first stripe portion on the base substrate covers the orthographic projection of the second signal line on the base substrate, the orthographic projection of the first stripe portion on the base substrate and the orthographic projection of the pixel electrode on the base substrate do not overlap with each other, and the orthographic projection of the second stripe portion on the base substrate overlaps with the orthographic projection of the pixel electrode on the base substrate.

13. The array substrate according to claim 12, wherein the distance between the pixel electrode and the first stripe portion in the row direction is greater than 0.

14. The array substrate according to claim 12 or 13, wherein the first stripe portion includes a first sublayer and a second sublayer stacked in a direction perpendicular to the base substrate, the second sublayer is located on the side of the first sublayer away from the base substrate, the width of the first sublayer is greater than the width of the second sublayer in the row direction, and the orthographic projection of the second sublayer on the base substrate is within the range of the orthographic projection of the first sublayer on the base substrate.

15. The array substrate according to claim 14, wherein the thickness of the second sub-layer in a direction perpendicular to the base substrate is 0.1 micrometers or more and 2 micrometers or less.

16. The first pattern layer further includes third stripe portions extending along the row direction and connected to the plurality of first stripe portions, and the second pattern layer further includes fourth stripe portions extending along the row direction and connected to the plurality of second stripe portions, The array substrate according to claim 12, wherein the orthographic projection of the fourth stripe portion on the base substrate overlaps with the orthographic projection of the third stripe portion on the base substrate, and the second pattern layer covers the edge of the third stripe portion on the side closer to the first opening region.

17. The array substrate according to claim 16, wherein, in the column direction, the orthographic projections of the two third stripe portions located on both sides of the first aperture region on the base substrate overlap with the orthographic projection of the pixel electrodes on the base substrate.

18. The array substrate according to any one of claims 12, 13, 15 to 17, wherein the orthographic projection of the common electrode on the base substrate and the orthographic projection of the gate electrode of the thin-film transistor on the base substrate do not overlap with each other.

19. The array substrate according to any one of claims 12, 13, 15 to 17, wherein the first pattern layer is a light-shielding conductive layer and the second pattern layer is a transparent conductive layer.

20. It is a display panel, A display panel comprising an array substrate according to any one of claims 1 to 19, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

21. A display device including the display panel described in claim 20.

22. The aforementioned display panel further includes an optical splitting assembly on the display side, The display device according to claim 21, wherein the optical division assembly includes a plurality of optical division repeating units extending along the column direction and arranged continuously along the row, the optical division repeating unit includes M optical division structures extending along the column direction and arranged continuously along the row, each of the optical division repeating units corresponds to the subpixel units in N columns within the row of the pixel repeating unit, where M and N are both integers greater than 1, and M and N are relatively prime.

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