Vertical field-effect transistor with self-aligned backside trench epitaxy.

Abstract

The semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a lower source / drain region of a field effect transistor. The lower source / drain region includes a trench epitaxy layer positioned below a bottom surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the lower source / drain region by a lower spacer. An upper source / drain region is positioned above a top surface of the channel fin. The upper source / drain region is separated from the high-k metal gate by an upper spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to and vertically aligned with the lower source / drain region.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor devices, and more particularly to vertical field-effect transistors (VFETs). [Background technology]

[0002] VFETs have been pursued as a potential device option for scaling complementary metal-oxide semiconductors (CMOS) to the 5-nanometer (nm) node and beyond. In contrast to planar CMOS devices, VFETs are vertically oriented with vertical fins or nanowires extending upward from a substrate. The fins or nanowires form the transistor's channel region. Source and drain regions are located in electrical contact with the upper and lower ends of the channel region, while a gate is disposed on one or more of the fin or nanowire sidewalls. Thus, in a VFET, the direction of current flow between the source and drain regions is perpendicular to the major surface of the substrate. Generally, forming the lower source and drain junctions in a VFET can be a difficult task due to control challenges during epitaxial growth. Therefore, improved techniques for forming the lower source and drain junctions of a VFET would be desirable. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a semiconductor structure comprises: a channel fin extending vertically from a lower source / drain region of a field effect transistor, the lower source / drain region including a trench epitaxy layer positioned below a bottom surface of the channel fin; a high-k metal gate stack disposed along sidewalls of the channel fin, the high-k metal gate being separated from the lower source / drain region by a bottom spacer; and upper source / drain regions positioned above a top surface of the channel fin, the upper source / drain region being separated from the high-k metal gate by an top spacer.

[0004] According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes forming a channel fin extending vertically from a lower source / drain region of a field effect transistor, the lower source / drain region including a trench epitaxy layer located below a bottom surface of the channel fin; forming a high-k metal gate stack disposed along sidewalls of the channel fin, the high-k metal gate being separated from the lower source / drain region by a bottom spacer; and forming upper source / drain regions located above a top surface of the channel fin, the upper source / drain region being separated from the high-k metal gate by an top spacer. [Brief explanation of the drawings]

[0005] The following detailed description is given by way of example, and is not intended to be limiting of the invention only, and is best understood in conjunction with the accompanying drawings, in which:

[0006] [Figure 1]1A-1C are top views of a semiconductor structure at intermediate stages during a semiconductor manufacturing process, showing different cross-sectional views used to explain embodiments of the present disclosure.

[0007] [Figure 2] FIG. 2A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the formation of a first sacrificial layer and a first semiconductor layer according to one embodiment of the present disclosure.

[0008] FIG. 2B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0009] [Figure 3] FIG. 3A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the patterning of multiple channel fin structures according to one embodiment of the present disclosure.

[0010] FIG. 3B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0011] [Figure 4] 4A is a cross-sectional view of a semiconductor structure taken along line XX shown in FIG. 1 illustrating the front-end-of-line processing stages, completion of middle-of-line contact patterning and metallization, and formation of a back-end-of-line interconnect level and carrier wafer according to one embodiment of the present disclosure.

[0012] FIG. 4B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0013] [Figure 5] FIG. 5A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating substrate removal according to one embodiment of the present disclosure.

[0014] FIG. 5B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0015] [Figure 6] FIG. 6A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the removal of the first sacrificial layer according to one embodiment of the present disclosure.

[0016] FIG. 6B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0017] [Figure 7] FIG. 7A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the formation of a first backside interlayer dielectric according to one embodiment of the present disclosure.

[0018] FIG. 7B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0019] [Figure 8] FIG. 8A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the formation of multiple backside contact openings according to one embodiment of the present disclosure.

[0020] FIG. 8B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0021] [Figure 9] FIG. 9A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the formation of a trench epitaxy layer according to one embodiment of the present disclosure.

[0022] FIG. 9B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0023] [Figure 10] FIG. 10A is a cross-sectional view of a semiconductor structure taken along line XX shown in FIG. 1, showing backside contact metallization according to one embodiment of the present disclosure.

[0024] FIG. 10B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0025] [Figure 11] FIG. 11A is a cross-sectional view of the semiconductor structure taken along line XX shown in FIG. 1 illustrating the formation of a backside interconnect structure according to one embodiment of the present disclosure.

[0026] FIG. 11B is a cross-sectional view of the semiconductor structure taken along line YY shown in FIG. 1 according to one embodiment of the present disclosure.

[0027] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements. DETAILED DESCRIPTION OF THE INVENTION

[0028] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0029] Hereinafter, for purposes of description, terms such as "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and variations thereof, refer to the disclosed structures and methods as oriented within the depicted figures. Terms such as "above," "overlying," "top," "above," "positioned on," or "positioned on top of" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0030] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined with each other for purposes of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description will instead focus on distinctive features or elements of various embodiments of the present invention.

[0031] Some non-planar transistor device architectures, such as VFETs, employ semiconductor fins and side gates that can be contacted outside the active area, thereby increasing device density over lateral devices. In VFETs, current from source to drain flows in a direction perpendicular to the main surface of the substrate. For example, in known VFET configurations, the main substrate surface is horizontal and a vertical fin extends upward from the substrate surface. The fin forms the transistor's channel region. Source and drain regions are positioned to electrically contact the upper and lower ends of the channel region, while a gate is disposed on one or more of the fin sidewalls. A lower junction is formed at the interface between the channel fin and the lower source / drain (S / D) region, and an upper junction is formed at the interface between the channel fin and the upper S / D region. As mentioned above, forming the lower source / drain region in a VFET device can be a difficult task due to control challenges during epitaxial growth.

[0032] Accordingly, embodiments of the present invention provide VFET devices and methods for fabricating the same in which lower source / drain regions are formed using a backside interconnect process. Specifically, the proposed VFET structure includes a backside trench epitaxy region formed under each semiconductor channel fin, with a first side of the backside trench epitaxy region in direct contact with the semiconductor channel fin and a second side (opposite the first side) of the backside trench epitaxy region in direct contact with a backside metal contact aligned with the backside trench epitaxy region to wire the VFET device to a backside interconnect. The backside trench epitaxy region provides the lower source / drain regions for the VFET device. Therefore, by using a backside interconnect process, the lower source / drain contacts (CRs) of the VFET can be eliminated, thereby providing significant density and device performance improvements for VFET-based technologies. Furthermore, omitting the lower source / drain modules during the frontside process simplifies the manufacturing process while improving device performance and reliability.

[0033] Embodiments by which a VFET device with backside trench epitaxy may be formed are described in detail below with reference to the accompanying drawings of FIGS. 1-11B.

[0034] Referring now to FIG. 1 , a top view of a semiconductor structure 100 at an intermediate stage during a semiconductor fabrication process is shown, in accordance with one embodiment of the present disclosure. In particular, FIG. 1 shows different cross-sectional views of the semiconductor structure 100 that will be used to explain embodiments of the present disclosure. The cross-sectional views are taken along lines XX and YY. As shown in the figure, line XX represents a cut line across the nano-sheet fin structure 20 of the semiconductor structure 100, while line YY represents a cut line along the nano-sheet fin structure 20 positioned within the NFET region 12 and PFET region 16 of the semiconductor structure 100.

[0035] In this embodiment, the cross-sectional view taken along line YY further includes a view of the NFET region 12 and / or the PFET region 16, and the area between the NFET and PFET regions 12, 16 (NP boundary) 14.

[0036] 2A-2B, cross-sectional views of the semiconductor structure 100 are shown after forming a first sacrificial layer 104 and a first semiconductor layer 106, according to one embodiment of the present disclosure. In this embodiment, FIG. 2A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 2B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0037] In the illustrated embodiment, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 positioned over the substrate 102, and a first semiconductor layer 106 disposed over the first sacrificial layer 104. According to one embodiment, the first sacrificial layer 104 and the first semiconductor layer 106 are vertically stacked one above the other in a direction perpendicular to the substrate 102, as shown.

[0038] The substrate 102 may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide or indium gallium phosphide. Typically, but not by way of limitation, the substrate 102 may be on the order of several hundred microns thick. In other embodiments, the substrate 102 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, in which a buried insulator layer separates a base substrate from an upper semiconductor layer.

[0039] According to one embodiment, the first sacrificial layer 104 may be formed on the substrate 102 using an epitaxial growth process. For example, the first sacrificial layer 104 may be formed by epitaxially growing a layer of SiGe having a germanium concentration ranging from about 15 atomic percent to about 35 atomic percent. In some embodiments, the first sacrificial layer 104 may be made of epitaxially grown SiGe having a germanium concentration of about 30 atomic percent. In other embodiments, the first sacrificial layer 104 may be made of silicon dioxide (SiO2). In such an embodiment, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 is an SOI wafer, and the first sacrificial layer 104 is a buried oxide (BOX) having a thickness ranging from about 20 nm to about 100 nm, including any range therebetween. The first sacrificial layer 104 may act as an etch stop layer during subsequent substrate removal.

[0040] The first semiconductor layer 106 may be formed by epitaxially growing a Si layer from the first sacrificial layer 104 to a thickness that varies from about 30 nm to about 250 nm, although other thicknesses are within the contemplated scope of the present invention.

[0041] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the semiconductor material being grown has the same or substantially similar crystalline properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around the surface and orient themselves to the crystalline structure of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystalline properties as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystalline surface will adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to formation on semiconductor surfaces and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0042] Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metalorganic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can cause crystalline defects and film cracking.

[0043] A number of different precursors may be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas source for deposition of the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source, including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source, including, but not limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of these gas sources may be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, helium, and argon may be used.

[0044] 3A-3B, cross-sectional views of the semiconductor structure 100 are shown after patterning a plurality of channel fin structures 304 (hereafter "channel fins"), according to one embodiment of the present disclosure. In this embodiment, FIG. 3A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 3B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0045] Patterning the channel fins 304 includes forming a hard mask layer 302 over the first semiconductor layer 106 (FIGS. 2A-2B) by depositing a hard mask material (e.g., silicon nitride) using, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any suitable technique for dielectric deposition. By way of example only, the hard mask layer 302 may be formed having a thickness ranging from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm may also be used.

[0046] After depositing the hard mask layer 302, photolithographic patterning is then performed on the deposited hard mask layer 302 to form a plurality of individual fin hard masks. According to an exemplary embodiment, reactive ion etching (RIE) may be used to etch through the first semiconductor layer 106 (FIGS. 2A-2B) to form the channel fins 304. The etching process may continue until the top surface of the first sacrificial layer 104 is exposed.

[0047] 4A-4B, cross-sectional views of semiconductor structure 100 are shown after completing front-end-of-line (FEOL) processing steps, middle-of-line (MOL) contact patterning and metallization to form back-end-of-line (BEOL) interconnect level 430 and carrier wafer 440, according to an embodiment of the present disclosure. In this embodiment, FIG. 4A is a cross-sectional view of semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 4B is a cross-sectional view of semiconductor structure 100 taken along line YY shown in FIG. 1.

[0048] Known semiconductor fabrication operations are used to form the semiconductor structure 100 shown in Figures 4A-4B. Accordingly, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Furthermore, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in manufacturing semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will be only briefly mentioned herein or omitted entirely without providing details of the well-known processes.

[0049] In the illustrated embodiment, the semiconductor structure 100 includes a lower spacer 402 formed over the first sacrificial layer 104 and adjacent a lower portion of the channel fin 304. The lower spacer 402 may include a dielectric material such as, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN, SiOxNy, and combinations thereof. The dielectric material may be a low-k material having a dielectric constant less than about 7, less than about 5, or even less than about 2.5. The lower spacer 402 may be formed using a combination of known deposition and etching processes, such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, and etching processes including reactive ion etching (RIE), wet etching, or isotropic gas-phase dry etching.

[0050] The semiconductor structure 100 may further include a high-k metal gate stack 406 formed along and in direct contact with each sidewall of the channel fins 304. For ease of illustration, the high-k metal gate stack 406 is shown as being only one layer. However, as known to those skilled in the art, the high-k metal gate stack 406 may include a gate dielectric and a gate conductor / metal (e.g., a work function metal (WFM)) deposited on the lower spacer 402 and adjacent a portion of the channel fin 304. The high-k metal gate stack 406 may be conformally deposited on the semiconductor structure 100 using, for example, ALD.

[0051] The gate dielectric (not shown) can be formed from one or more gate dielectric films. The gate dielectric film can be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0, for example. Non-limiting examples of suitable materials for the high-k dielectric film include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials having a dielectric constant greater than 7.0 include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric film can further include dopants such as lanthanum and aluminum. The gate dielectric film may be formed by a suitable deposition process, such as CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes. The thickness of the gate dielectric film may vary depending on the deposition process and the composition and number of high-k dielectric materials used.

[0052] The gate conductor (not shown) of the high-k metal gate stack 406 may comprise doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material may further comprise dopants incorporated during or after deposition. In some embodiments, the gate conductor may be a WFM deposited on the gate dielectric film by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering. The type of WFM depends on the type of transistor and may differ between n-FET and p-FET devices. The p-type WFM includes compositions such as titanium nitride (TiN), ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. The n-type WFM includes compositions such as titanium carbide (TiC), titanium aluminum carbide (TiAlC), hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The gate conductor may further include tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), or nickel (Ni) material on the WFM layer of the gate conductor. The gate conductor may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering.

[0053] After forming the high-k metal gate stack 406, a patterning process is performed on the semiconductor structure 100 to remove excess material.

[0054] In one or more embodiments, a first layer of interlevel dielectric 425 may be formed to fill voids between gate structures and other existing devices within semiconductor structure 100. Interlevel dielectric 425 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming interlevel dielectric 425 may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0055] Typically, after depositing the interlevel dielectric 425 , a chemical mechanical polishing (CMP) process is performed on the semiconductor structure 100 to expose the top surfaces of the channel fins 304 .

[0056] 4A-4B , as shown, after removing the hard mask layer 302 ( FIGS. 3A-3B ), a high-k metal gate stack 406 may be recessed below the top surface of the channel fin 304. A top spacer 408 may then be conformally deposited over and in direct contact with the high-k metal gate stack 406. In such an embodiment, the top spacer 408 may be deposited using, for example, CVD, PECVD, radio-frequency CVD (RFCVD), PVD, ALD, molecular layer deposition (MLD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), sputtering, and / or plating. Non-limiting examples of materials forming the top spacer 408 may include silicon nitride (SiN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), or silicon oxycarbonitride (SiOCN).

[0057] According to one embodiment, the upper spacers 408 may be recessed using a suitable etching technique (e.g., RIE) to expose the upper surface of the channel fin 304. Upper source / drain regions 410 may then be formed from the exposed upper surface of the channel fin 304 using an epitaxial growth process similar to that described above with respect to the first sacrificial layer 104 and the first semiconductor layer 106. As shown, the upper spacers 408 may cover the upper source / drain regions 410 to electrically isolate each of the upper source / drain regions 410 from the high-k metal gate stack 406. As known to those skilled in the art, the upper source / drain regions 410 are formed within corresponding NFET and PFET regions 12, 16 (shown in FIG. 1 ) of the semiconductor structure 100. Thus, in an embodiment in which the semiconductor structure 100 is a PFET device, the upper source / drain regions 410 may comprise, for example, epitaxially grown Si:B. In embodiments in which the semiconductor structure 100 is an NFET device, the upper source / drain regions 410 may comprise, for example, epitaxially grown Si:P.

[0058] It should be noted that although the bottom spacer 402 and the top spacer 408 are shown on adjacent sides of the channel fin 304, the bottom spacer 402 and the top spacer 408 surround the entire surface of the channel fin 304. The bottom spacer 402 and the top spacer 408 may determine the location of the pn junction within the semiconductor structure 100.

[0059] To continue the fabrication process, a second layer of interlevel dielectric 425 may be formed in semiconductor structure 100, followed by a planarization process. Note that for ease of illustration, only one layer of interlevel dielectric 425 is shown in the figures.

[0060] 4A-4B , a plurality of conductive structures, including metal contacts 420, may subsequently be formed within the semiconductor structure 100 to electrically connect the FEOL devices to subsequently formed metal levels. The process for forming the metal contacts 420 is standard and well known in the art. Typically, the process involves forming a trench (not shown) within the interlevel dielectric 425 and then filling the trench with a conductive material or combination of conductive materials to form the metal contacts 420. In one or more embodiments, the conductive material filling the metal contacts 420 may include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy, etc.), a metal adhesion liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0061] The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the upper surface of the semiconductor structure 100. In the example shown, the metal contacts 420 include upper source / drain contacts that extend to the top surface of each of the upper source / drain regions 410 and a gate contact to the high-k metal gate stack 406.

[0062] BEOL interconnect levels 430 may then be formed above FEOL device levels 30. Although not shown in the figures, as would be known to one skilled in the art, BEOL interconnect levels 430 typically include contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. As mentioned above, the various steps in manufacturing semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will be mentioned only briefly herein or omitted entirely without providing details of well-known processes.

[0063] According to one embodiment, after forming the BEOL interconnect level 430, the semiconductor structure 100 (i.e., the semiconductor wafer) is bonded to a carrier wafer (or support substrate) 440. The carrier wafer 440 may function as a stiffening substrate to provide mechanical strength during processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 440 may be achieved by a conventional wafer bonding process, such as dielectric-to-dielectric bonding or Cu-to-Cu bonding.

[0064] Therefore, the carrier wafer 440 may include a silicon oxide layer or a SiCN layer, or any other layer applicable to the direct bonding technique applied in prior art packaging technologies. The bonding of the device wafer and the carrier wafer 440 is performed by such known direct bonding techniques, thus obtaining the assembly shown in Figures 4A-4B.

[0065] 5A-5B, cross-sectional views of semiconductor structure 100 after substrate removal are shown, according to an embodiment of the present disclosure. In this embodiment, FIG. 5A is a cross-sectional view of semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 5B is a cross-sectional view of semiconductor structure 100 taken along line YY shown in FIG. 1.

[0066] In the illustrated embodiment, after the wafer is flipped (not shown), the substrate 102 may be removed using a selective etching process, including conventional grinding, CMP, and wet or dry etching techniques. According to one embodiment, the grinding process is performed until the substrate 102 is substantially removed from the semiconductor structure 100, leaving only a few microns of Si. An optional CMP process may then be further used to reduce thickness variations, and finally, a highly selective Si etching process is used to remove the remaining substrate 102 from the semiconductor structure 100. In the illustrated embodiment, during the highly selective Si removal process, the first sacrificial layer 104 acts as an etch stop to prevent excessive Si etching, which could damage the channel fins 304 and the high-k metal gate stack 406.

[0067] 6A-6B, cross-sectional views of the semiconductor structure 100 after removing the first sacrificial layer 104 are shown, according to an embodiment of the present disclosure. In this embodiment, FIG. 6A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 6B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0068] In the illustrated embodiment, any suitable etching technique may be used to remove the first sacrificial layer 104 (FIGS. 5A-5B). In embodiments in which the first sacrificial layer 104 (FIGS. 5A-5B) is made of SiGe, a hot SC1 or dry HCl etch may be used to remove the first sacrificial layer 104. In embodiments in which the first sacrificial layer 104 (FIGS. 5A-5B) is made of SiO2, a DHF wet clean may be used to remove the first sacrificial layer 104.

[0069] 7A-7B, cross-sectional views of the semiconductor structure 100 are shown after forming a first backside interlayer dielectric (BILD) 750, according to one embodiment of the present disclosure. In this embodiment, FIG. 7A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 7B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0070] The first BILD 750 is formed using standard methods and materials, such as those used to form the interlevel dielectric 425 described above with reference to Figures 4A-4B. As shown, the first BILD 750 is disposed above and in direct contact with the bottom surface of the channel fin 304 and the bottom surface of the lower spacer 402. In an exemplary embodiment, the thickness of the first BILD 750 may vary from about 40 nm to about 300 nm, and ranges therebetween. In one or more embodiments, after forming the first BILD 750, a planarization process (e.g., CMP) may be performed on the semiconductor structure 100.

[0071] 8A-8B, cross-sectional views of the semiconductor structure 100 are shown after forming a plurality of backside contact openings 810 (hereafter "backside contact openings"), according to one embodiment of the present disclosure. In this embodiment, FIG. 8A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 8B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0072] As known to those skilled in the art, patterning the first BILD 750 to form the backside contact opening 810 involves exposing a pattern on a photoresist layer (not shown) and transferring the exposed pattern to the first BILD 750. After transferring the pattern and forming the backside contact opening 810, the photoresist layer may be removed using any photoresist stripping method known in the art, including, for example, plasma ashing. As shown, the backside contact opening 810 exposes the bottom surface of the channel fin 304 and a portion of the bottom spacer 402.

[0073] 9A-9B, cross-sectional views of the semiconductor structure 100 are shown after forming a trench epitaxy layer 920 on the exposed portions of the channel fin 304, according to one embodiment of the present disclosure. In this embodiment, FIG. 9A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 9B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0074] In one or more embodiments, the trench epitaxy layer 920 can be epitaxially grown using, for example, VPE, MBE, or LP. A low-temperature epitaxy process is highly desirable because temperatures above about 500° C. induce a large threshold voltage shift in the formed gate. In some embodiments, the trench epitaxy layer 920 comprises a similar material and the same dopant concentration as the upper source / drain regions 410. In other words, the trench epitaxy layer 920 is matched to the respective upper source / drain regions 410; that is, if the upper source / drain regions 410 are n-type (NFET), the trench epitaxy layer 920 is also n-type, and if the upper source / drain regions 410 are p-type (PFET), the trench epitaxy layer 920 is also p-type.

[0075] For example, the trench epitaxy layer 920 may be formed to have the crystalline structure of the underlying layer. In this case, the trench epitaxy layer 920 may be grown to have the crystalline structure of the channel fin 304, with the trench epitaxy layer 920 being the lower source / drain region of the transistor. In an exemplary embodiment, for an NFET device, the trench epitaxy layer 920 may be formed as silicon doped with phosphorus (Si:P), silicon doped with arsenic (Si:As), etc. For a PFET device, the trench epitaxy layer 920 may be formed as silicon doped with boron (Si:B), germanium doped with boron (Ge:B), silicon germanium doped with boron (SiGe:B), etc.

[0076] Thus, trench epitaxy layer 920 provides lower source / drain regions 940 in semiconductor structure 100. As can be seen in the figure, (backside) trench epitaxy layer 920 contacts a first (bottom) surface of channel fin 304, opposite a second (top) surface of channel fin 304 that contacts upper source / drain regions 410. In an exemplary embodiment, trench epitaxy layer 920 may be formed to a thickness ranging from about 10 nm to about 50 nm, although other thicknesses are within the contemplated scope of the present invention. In one or more embodiments, trench epitaxy layer 920 is in partial contact with lower spacer 402. Note that in some embodiments, depending on design requirements, backside contact opening 810 ( FIGS. 8A-8B ) may expose an area corresponding to two adjacent channel fins 304, as shown in FIG. 8A . In such cases, as shown in FIG. 9A, after forming the trench epitaxy layer 920, a space or gap 960 may remain between adjacent channel fins 304.

[0077] As would be known to one skilled in the art, the diamond / triangular shape observed in the trench epitaxy layer 920 forming the lower source / drain regions 940 may be the result of different growth rates during the epitaxial deposition process that are inherent to each crystal orientation plane of the material forming the trench epitaxy layer 920. The diamond shape provides a larger surface area for physical contact with the trench epitaxy layer 920. In other embodiments, the trench epitaxy layer 920 may have a shape other than the diamond shape shown in FIG.

[0078] 10A-10B, cross-sectional views of a semiconductor structure 100 after backside contact metallization are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 10A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 10B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0079] In this embodiment, a backside metal contact 1012 may be formed in the semiconductor structure 100 by depositing a conductive material that substantially fills the backside contact opening 810 (FIGS. 8A-8B) and the space 960 (FIG. 9A) between adjacent channel fins 304. The backside metal contact 1012 may be formed using similar conductive materials and similar deposition processes as those used to form the metal contact 420. In some embodiments, the backside metal contact 1012 may be formed by depositing a silicide liner such as Ti, Ni, NiPt, an adhesion metal liner such as TiN, and a layer of a low-resistivity metal such as Ru, Co, W, or Cu.

[0080] In one or more embodiments, the backside metal contact 1012 may be formed on and in direct contact with adjacent lower source / drain regions 940 (channel fins 304≧2) positioned in the N2N space of the NFET region 12 (shown in FIG. 1 ) or the P2P space of the PFET region 16 (also shown in FIG. 1 ) of the semiconductor structure 100. In such embodiments, the conductive material forming the backside metal contact 1012 is deposited between adjacent lower source / drain regions 940 to substantially fill the space 960 (shown in FIG. 9A ) between adjacent channel fins 304. By filling the space 960 (shown in FIG. 9A ) between adjacent channel fins 304, the backside metal contact 1012 can partially wrap around a portion of the trench epitaxy layer 920 (i.e., the lower source / drain regions 940) to increase the contact area. Thus, the backside metal contact 1012 at least partially surrounds the adjacent lower source / drain regions 940.

[0081] 11A-11B, cross-sectional views of the semiconductor structure 100 after forming a backside interconnect structure 1130 are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 11A is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. FIG. 11B is a cross-sectional view of the semiconductor structure 100 taken along line YY shown in FIG. 1.

[0082] The simplified backside interconnect structure 1130 may include, for example, Cu-based metal lines and vias fabricated according to known techniques. According to one embodiment, a backside metal contact 1012 may be electrically connected to the backside interconnect structure 1130. Specifically, the backside metal contact 1012 contacts the bottom surface of the backside interconnect structure 1130.

[0083] The resulting semiconductor structure 100 includes a VFET device with self-aligned backside trench epitaxy that provides lower source / drain regions to the semiconductor structure 100. Embodiments of the present disclosure provide additional options for forming the lower source / drain regions of the VFET device using backside interconnect processes. In proposed embodiments, backside interconnect processes may not be limited to power supplies; they may also be used for signal routing.

[0084] The embodiments described thus far provide a semiconductor structure and methods for making the same, including a channel fin extending vertically from a lower source / drain region of a field effect transistor, the lower source / drain region including a trench epitaxy layer positioned below a bottom surface of the channel fin, a high-k metal gate stack disposed along sidewalls of the channel fin, the high-k metal gate being separated from the lower source / drain region by a lower spacer, and an upper source / drain region positioned above a top surface of the channel fin, the upper source / drain region being separated from the high-k metal gate by an upper spacer.

[0085] In one or more embodiments, a first side of the trench epitaxy layer is in direct contact with the channel fin, and a second side of the trench epitaxy layer opposite the first side is in direct contact with the backside metal contact. In one or more embodiments, the trench epitaxy layer is epitaxially grown using a low-temperature epitaxial process, and the trench epitaxy layer comprises a similar material and dopant concentration as the upper source / drain regions.

[0086] An embodiment of the present disclosure includes a front-end-of-line level having a field effect transistor, the front-end-of-line level electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level, the field effect transistor including a vertical field effect transistor, and further including a backside interlayer dielectric surrounding a lower source / drain region and located on a second side of the front-end-of-line level opposite the first side of the front-end-of-line level.

[0087] Embodiments of the present disclosure further include a metal contact within the interlevel dielectric, the metal contact electrically contacting the top surface of the upper source / drain region, and a backside metal contact within the backside interlayer dielectric, the backside metal contact electrically connecting to and vertically aligned with the lower source / drain region, the backside metal contact being comprised of a conductive material including at least one of Ru, Cu, Co, W, and Al.

[0088] In one or more embodiments, the backside metal contact fills an area located between two adjacent lower source / drain regions and partially surrounds a portion of the two adjacent lower source / drain regions.

[0089] In one or more embodiments, the semiconductor structure further comprises a backside interconnect structure electrically connected to the backside metal contact, and a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposite the upper source / drain regions and the metal contact.

[0090] Methods such as those described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads secured to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing the integrated circuit chip, ranging from toys and other low-cost applications to sophisticated computer products with displays, keyboards or other input devices, and central processors.

[0091] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances in which the event occurs as well as instances in which it does not occur.

[0092] Spatially relative terms such as "inside," "outside," "below," "lower," "upper," "upper," "top," "lower," and the like may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature for ease of description. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in a figure were turned over, elements described as "below" or "below" other elements or features would now be oriented "above" such other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. A device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0093] As used herein throughout the specification and claims, approximation may be applied to modify any quantitative expression that may vary appreciably without causing a change in the basic function to which it is related. Thus, values ​​modified by one or more terms such as "about," "approximately," and "substantially" should not be limited to the exact value specified. In at least some cases, approximation may correspond to the precision of the instrument for measuring the value. Here, and throughout the specification and claims, range limitations may be combined and / or interchanged, and such ranges are specified and include all subranges contained therein, unless the context or language indicates otherwise. "Approximately," as applied to a particular value in a range, applies to both values ​​and may indicate + / - 10% of the stated value, unless otherwise dependent on the precision of the instrument for measuring the value.

[0094] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a channel fin extending vertically from a lower source / drain region of a field effect transistor, the lower source / drain region including a trench epitaxy layer positioned below a lowermost surface of the channel fin; a high-k metal gate stack disposed along a sidewall of the channel fin, the high-k metal gate being separated from the lower source / drain regions by a lower spacer; and an upper source / drain region positioned above a top surface of the channel fin, the upper source / drain region being separated from the high-k metal gate by an upper spacer; 1. A semiconductor structure comprising:

2. a front-end-of-line level having the field-effect transistor, the front-end-of-line level being electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level, the field-effect transistor being a vertical field-effect transistor; and a backside interlayer dielectric surrounding the lower source / drain regions and positioned on a second side of the front end of the line level opposite the first side of the front end of the line level; 10. The semiconductor structure of claim 1 further comprising:

3. a metal contact within the interlevel dielectric, the metal contact electrically contacting a top surface of the upper source / drain region; 3. The semiconductor structure of claim 2 further comprising:

4. a backside metal contact within the backside interlayer dielectric, the backside metal contact electrically connected to and vertically aligned with the lower source / drain region; 3. The semiconductor structure of claim 2 further comprising:

5. 5. The semiconductor structure of claim 4, wherein said backside metal contact fills an area located between two adjacent lower source / drain regions and partially surrounds a portion of said two adjacent lower source / drain regions.

6. 5. The semiconductor structure of claim 4 further comprising a backside interconnect structure electrically connected to said backside metal contact.

7. 4. The semiconductor structure of claim 3 further comprising a carrier wafer in contact with a surface of said back-end-of-line interconnect level opposite said upper source / drain regions and said metal contacts.

8. 5. The semiconductor structure of claim 4 wherein said backside metal contact is comprised of a conductive material comprising at least one of Ru, Cu, Co, W, and Al.

9. 5. The semiconductor structure of claim 4, wherein a first side of said trench epitaxy layer is in direct contact with said channel fin, and a second side of said trench epitaxy layer opposite said first side is in direct contact with said backside metal contact.

10. 10. The semiconductor structure of claim 1, wherein said trench epitaxy layer is epitaxially grown using a low temperature epitaxial process, said trench epitaxy layer comprising a similar material and dopant concentration as said upper source / drain regions.

11. forming a channel fin extending vertically from a lower source / drain region of a field effect transistor, the lower source / drain region including a trench epitaxy layer positioned below a bottom surface of the channel fin; forming a high-k metal gate stack disposed along a sidewall of the channel fin, the high-k metal gate being separated from the lower source / drain regions by a lower spacer; and forming upper source / drain regions positioned above a top surface of the channel fin, the upper source / drain regions separated from the high-k metal gate by upper spacers.

1. A method of forming a semiconductor structure, comprising:

12. forming a front-end-of-line level including the field effect transistor, the front-end-of-line level being electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level, the field effect transistor being a vertical field effect transistor; and forming a backside interlevel dielectric surrounding the lower source / drain regions and positioned on a second side of the front end of line level opposite the first side of the front end of line level; The method of claim 11 further comprising:

13. forming a metal contact within the interlevel dielectric, the metal contact being in electrical contact with a top surface of the upper source / drain region; The method of claim 12 further comprising:

14. forming a backside metal contact within the backside interlayer dielectric, the backside metal contact electrically connected to and vertically aligned with the lower source / drain region; The method of claim 12 further comprising:

15. 15. The method of claim 14, wherein the backside metal contact fills an area located between two adjacent lower source / drain regions and partially surrounds a portion of the two adjacent lower source / drain regions.

16. forming a backside interconnect structure electrically connected to the backside metal contact; The method of claim 14 further comprising:

17. forming a carrier wafer in contact with a surface of the back-end-of-line interconnect level opposite the upper source / drain regions and the metal contacts; The method of claim 13 further comprising:

18. 15. The method of claim 14, wherein the backside metal contact is comprised of a conductive material including at least one of Ru, Cu, Co, W, and Al.

19. 15. The method of claim 14, wherein a first side of the trench epitaxy layer is in direct contact with the channel fin, and a second side of the trench epitaxy layer opposite the first side of the trench epitaxy layer is in direct contact with the backside metal contact.

20. 12. The method of claim 11, wherein the trench epitaxy layer is epitaxially grown using a low temperature epitaxial process, and the trench epitaxy layer comprises a similar material and dopant concentration as the upper source / drain regions.

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