Resistive random access memory on buried bit lines.

Abstract

A semiconductor structure is provided that includes a resistive random access memory located on a surface of a bit line that is buried in a shallow trench isolation structure. The structure may further include a source line that is above the bit line or buried in the shallow trench isolation structure.

Description

[Background technology]

[0001] This application relates to semiconductor technology, and more particularly to semiconductor structures including resistive random access memory (ReRAM) located on buried bitlines.

[0002] Non-volatile memory (NVM) or non-volatile storage is a type of computer memory that can retain stored information even after power is removed. In contrast, volatile memory requires sustained power to retain data. NVM, such as ReRAM (or sometimes simply RRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM), has gained renewed attention for its potential applications in neuromorphic computing, with in-memory processing capabilities that significantly reduce power consumption and eliminate data busing time between the memory and central processing unit (CPU) of traditional complementary metal oxide semiconductor (CMOS)-based neuromorphic computing. ReRAM is considered a promising technology for electronic synaptic devices or memristors for neuromorphic computing, as well as for high-density and high-speed NVM applications. In neuromorphic computing applications, resistive memory devices such as ReRAM devices can be used as connections (i.e., synapses) between pre-neurons and post-neurons, where the connection weights are expressed in terms of device resistance. Summary of the Invention

[0003] A semiconductor structure is provided that includes a ReRAM located on top of a bit line that is buried in a shallow trench isolation structure. The structure may further include a source line that is above the bit line or buried in the shallow trench isolation structure.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a buried bit line buried in a shallow trench isolation structure, and a ReRAM located on a surface of the buried bit line, wherein the ReRAM is electrically connected to a source / drain region of at least one first transistor.

[0005] In this application, the ReRAM and buried bit lines are located at the same device level as the transistors (i.e., the front-end-of-the-line (FEOL) level). Such a semiconductor structure with buried bit lines and ReRAM at the same device level has a significant resistance reduction (approximately 5x to 20x) compared to conventional structures in which the ReRAM is located at the back-end-of-the-line (BEOL). Another advantage of such a structure is that improved bit line read and write operations are obtained. A still further advantage of such a structure is that it eliminates the need for forming multiple metal stack write levels for bit line connections. Yet a further advantage is that reduced IR (current-resistance) drop is realized, which may allow for a larger number of unit cells per block in the array. In such an embodiment, a larger memory block size may be realized.

[0006] In the present embodiment, the ReRAM and the buried bit lines are also buried within an interlayer dielectric material structure that resides above the shallow trench isolation structure.

[0007] In an embodiment of the present application, the at least one first transistor is a fin-type field effect transistor (finFET). In this application, a finFET includes a semiconductor fin as a device channel structure and a gate structure located on an upper portion of the semiconductor fin, and a lower portion of the semiconductor fin resides in a shallow trench isolation structure. This application is not limited to using finFETs, and therefore other types of transistors may be used, including, for example, planar transistors, nanosheet transistors, or semiconductor nanowire transistors.

[0008] In embodiments of the present application, the structure may further comprise a source line located above the at least one first transistor, the source line electrically connected to a source / drain region of at least one second transistor. In such embodiments, the ReRAM is electrically connected to the source / drain region of the at least one first transistor by a first source / drain contact structure, and the source line is electrically connected to the source / drain region of the at least one second transistor by a metal via structure and a second source / drain contact structure. In such embodiments, the buried bit line is connected to a sense amplifier, and the source line is connected to a common ground reference.

[0009] In embodiments of the present application, the structure may further comprise a buried source line embedded in the shallow trench isolation structure, wherein the buried source line is electrically connected to a source / drain region of at least one second transistor. In such embodiments, the ReRAM is electrically connected to the source / drain region of the at least one first transistor by a first source / drain contact structure, and the buried source line is electrically connected to the source / drain region of the at least one second transistor by a metal via structure and a second source / drain contact structure. In such embodiments, the buried bit line is connected to a sense amplifier, and the buried source line is connected to a common ground reference.

[0010] In any of the above-mentioned embodiments, the at least one second transistor may be a finFET, a planar transistor, a nanosheet transistor, a semiconductor nanowire transistor, or the like.

[0011] In an embodiment of the present application, the buried bitline extends below the top surface of the semiconductor substrate.

[0012] In an embodiment of the present application, the buried bit lines have an aspect ratio of 1:1 to 6:1, which may provide low resistance bit lines.

[0013] In an embodiment of the present application, the at least one first transistor includes a plurality of first transistors, and the ReRAM is electrically connected to a source / drain region of each of the plurality of first transistors.

[0014] In an embodiment of the present application, the buried bit line is located in a region adjacent to a first device region including the at least one first transistor and located between the first device region and a second device region.

[0015] In an embodiment of the present application, the buried bit line is a buried metal rail with a length greater than the length of the ReRAM.

[0016] In another aspect of the present application, a memory array is provided. In one embodiment, the memory array comprises: a plurality of buried bit lines buried in a shallow trench isolation structure; an ReRAM located on a surface of each of the buried bit lines of the plurality of buried bit lines, wherein the ReRAM is electrically connected to a source / drain region of each first transistor of a plurality of first transistors; and a plurality of source lines electrically connected to a source / drain region of each second transistor of a plurality of second transistors, wherein the plurality of first transistors are adjacent to the plurality of second transistors.

[0017] In embodiments of the present application, each source line of the plurality of source lines resides above the plurality of first transistors and the plurality of second transistors, In such embodiments, each buried bit line of the plurality of buried bit lines is connected to a sense amplifier, and each source line of the plurality of source lines is connected to a common ground reference.

[0018] In embodiments of the present application, each source line of the plurality of source lines is a buried source line buried within the shallow trench isolation structure, and in such embodiments, each buried bit line of the plurality of buried bit lines is connected to a sense amplifier, and each source line of the plurality of source lines is connected to a common ground reference. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a top view illustrating a device layout used herein to describe the semiconductor structure of the present application.

[0020] [Figure 2]2A, 2B, and 2C are cross-sectional views taken along section lines XX, Y1-Y1, and Y2-Y2 in FIG. 1, respectively, of an exemplary structure employed in the present application, the exemplary structure including a plurality of semiconductor fins extending upward from a surface of a semiconductor substrate, a shallow trench isolation structure located laterally adjacent to each semiconductor fin, a gate structure located on a first portion of each semiconductor fin, source / drain regions located on either side of the gate structure and on a second portion of each semiconductor fin, and a first interlayer insulating film material layer embedding at least each source / drain region.

[0021] [Figure 3] 3A, 3B, and 3C are cross-sectional views of the exemplary structures shown in FIGS. 2A, 2B, and 2C, respectively, after forming at least buried bitlines in a shallow trench isolation structure.

[0022] [Figure 4] 4A, 4B, and 4C are cross-sectional views of the exemplary structures shown in FIGS. 3A, 3B, and 3C, respectively, after forming ReRAM stacks on each buried bitline.

[0023] [Figure 5] 5A, 5B, and 5C are cross-sectional views of the example structures shown in FIGS. 4A, 4B, and 4C, respectively, after patterning the ReRAM stack to provide the ReRAM.

[0024] [Figure 6] 6A, 6B, and 6C are cross-sectional views of the example structures shown in FIGS. 5A, 5B, and 5C, respectively, after forming ReRAM spacers that protect the sidewalls of the ReRAM.

[0025] [Figure 7]7A, 7B, and 7C are cross-sectional views of the exemplary structures shown in FIGS. 6A, 6B, and 6C, respectively, after forming middle-of-the-line (MOL) contact structures and metal via structures.

[0026] [Figure 8] 1 is a cross-sectional view illustrating a ReRAM structure according to an embodiment of the present application;

[0027] [Figure 9] FIG. 9 is a top view of a memory array according to an embodiment of the present application, including a plurality of ReRAM structures as shown in FIG. 8.

[0028] [Figure 10] FIG. 9 is a top view of a multiplexed resistive memory array according to an embodiment of the present application, including a plurality of ReRAM structures as shown in FIG. 8.

[0029] [Figure 11] FIG. 11 is a circuit diagram of the multiple resistive memory array shown in FIG.

[0030] [Figure 12] 1 is a cross-sectional view illustrating a ReRAM structure according to an embodiment of the present application;

[0031] [Figure 13] FIG. 13 is a top view of a memory array according to an embodiment of the present application, including a plurality of ReRAM structures as shown in FIG. 12.

[0032] [Figure 14] FIG. 13 is a top view of a multiplexed resistive memory array according to an embodiment of the present application, including a plurality of ReRAM structures as shown in FIG. 12.

[0033] [Figure 15] FIG. 15 is a circuit diagram of the multiple resistive memory array shown in FIG. 14. DETAILED DESCRIPTION OF THE INVENTION

[0034] The present application will now be described in more detail by reference to the discussion below and the drawings that accompany this application. It should be noted that the drawings herein are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0035] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0036] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0037] As described above, the present application provides a semiconductor structure including a buried bit line embedded within a shallow trench isolation structure and a ReRAM located on the surface of the buried bit line, where the ReRAM is electrically connected to the source / drain region of at least one first transistor. In the present application, both the buried bit line and the ReRAM are located at the same device level (i.e., FEOL level) as the transistor. The present semiconductor structure has a significant resistance reduction (approximately 5x to 20x) compared to conventional structures in which the ReRAM is located in the BEOL. Another advantage of such a structure is that improved bit line read and write operations are obtained. A still further advantage of such a structure is that it eliminates the need for forming multiple metal stack write levels for bit line connections. Yet a further advantage is that reduced IR drop is achieved, which may enable a larger number of unit cells per block in the array. In such embodiments, larger memory book sizes may be realized. These and other aspects / advantages of the present application will now be described in more detail.

[0038] Referring first to FIG. 1 , this is a top view illustrating a device layout, which is used herein to describe the semiconductor structure of the present application. The device layout includes multiple semiconductor fins. Each semiconductor fin is labeled as a “Fin” in FIG. 1 . The semiconductor fins are oriented parallel to each other. In FIG. 1 , the two semiconductor fins located in the upper portion of the drawing are in a first device region, while the two semiconductor fins located in the lower portion of the drawing are in a second device region. These different device regions are separated by a region containing ReRAM. In the present application, this region located between the two device regions will also include a buried bitline (not shown) located below the ReRAM. FIG. 1 also includes cut lines XX, Y1-Y1, and Y2-Y2. Section line XX is along the longitudinal direction and passes through one of the semiconductor fins, section line Y1-Y1 is along the longitudinal direction and passes through the middle gate structure GS shown in Figure 1, and section line Y2-Y2 is in the area located between adjacent pairs of gate structures; in the two device regions, this area will include the source / drain regions. Figure 1 also includes a dotted circle highlighting the area of ​​the device layout that will be illustrated in Figures 2A-6C below.

[0039] It should be noted that each of Figures 2A, 3A, 4A, 5A, and 6A represents an exemplary structure through section line XX, each of Figures 2B, 3B, 4B, 5B, and 6B represents an exemplary structure through section line Y1-Y1, and each of Figures 2C, 3C, 4C, 5C, and 6C represents an exemplary structure through section line Y2-Y2.

[0040] 2A, 2B, and 2C, various cross-sectional views (i.e., XX, Y1-Y1, and Y2-Y2, respectively) illustrate an exemplary structure employed herein. The exemplary structure includes multiple semiconductor fins 10F extending upward from a surface of a semiconductor substrate 10, with a shallow trench isolation structure 12 laterally adjacent to each semiconductor fin 10F, a gate structure 16 located on a first portion of each semiconductor fin 10F, source / drain regions 22 located on either side of the gate structure 16 and on a second portion of each semiconductor fin 10F, and a first interlayer dielectric material layer 24 embedded in at least each source / drain region 22. Each gate structure 16 includes a gate dielectric material layer and a gate electrode. Although the gate dielectric material layer and the gate electrode are not separately shown in FIGS. 2A-2B, both are included in the gate structure 16. The exemplary structure also includes gate spacers 18, a gate cap 20, and a dielectric material layer 15. The dielectric material layer 15 is made of a dielectric material such as, for example, SiO, SiN, or SiON. The dielectric material layer 15 protects the semiconductor fin 10F and may therefore also be referred to herein as a dielectric protection layer.

[0041] The semiconductor substrate 10 shown in Figures 2A, 2B, and 2C is composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials used as the semiconductor substrate 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors.

[0042] Each semiconductor fin 10F is also composed of semiconductor materials, including those mentioned above with respect to the semiconductor substrate 10. The semiconductor material providing each semiconductor fin 10F can be compositionally the same as or different from the semiconductor material providing at least the upper portion of the semiconductor substrate 10. In embodiments where the semiconductor material providing each semiconductor fin 10F is compositionally the same as the semiconductor material providing at least the upper portion of the semiconductor substrate 10, a material interface does not exist between the semiconductor fin 10F and the semiconductor substrate 10. In embodiments where the semiconductor material providing each semiconductor fin 10F is compositionally different from the semiconductor material providing at least the upper portion of the semiconductor substrate 10, a material interface exists between the semiconductor fin 10F and the semiconductor substrate 10. In the figures herein, dotted lines are shown between the semiconductor fin 10F and the semiconductor substrate 10 to illustrate possible material interfaces that may exist between these two elements. Each semiconductor fin 10F can have a width of 5 nm to 25 nm, a height of 10 nm to 50 nm, and a length of 10 nm to 100 nm. The semiconductor fin 10F may be formed using a patterning process such as, for example, sidewall image transfer (SIT), lithography and etching, or a self-assembly process in which a self-assembling block copolymer is employed.

[0043] The shallow trench isolation structures 12 may include a trench dielectric material. The trench dielectric material may be composed of any trench dielectric material, such as, for example, silicon oxide. The shallow trench isolation structures 12 have a height that is less than the height of each semiconductor fin 10F. The shallow trench isolation structures 12 may be formed by deposition (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD)) and etching. In some embodiments, the shallow trench isolation structures 12 may extend below the top surface of the semiconductor substrate 10.

[0044] As mentioned above, the gate structure 16 includes a gate dielectric material layer and a gate electrode, both of which are not shown separately in the drawings but are intended to be within the region defined by the gate structure 16. The gate structure 16 is a component of a transistor; the transistor further includes source / drain regions 22 located on each side of the gate structure 16. As known to those skilled in the art, the gate dielectric material layer directly contacts the physically exposed surface of each semiconductor fin 10F, and the gate electrode is formed on the gate dielectric material layer. The gate dielectric material layer of the gate structure 16 is composed of a gate dielectric material having a dielectric constant of 4.0 or greater. All dielectric constants referred to herein are measured in a vacuum unless otherwise specified. Illustrative examples of gate dielectric materials include, but are not limited to, silicon dioxide, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaOSrTi), barium titanate (BaTiO), strontium titanate (SrTiO), yttrium oxide (YbO), aluminum oxide (AlO), lead tantalum scandium oxide (Pb(Sc,Ta)O), and / or lead zinc niobate (Pb(Zn,Nb)O), etc. The gate dielectric material may further include dopants such as La, Al, and / or Mg.

[0045] The gate electrode of gate structure 16 may include a conductive metal and an optional work function metal (WFM). The WFM may be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM may be selected to achieve an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM may be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that activates a semiconductor device, such as a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift" refers to a shift in the effective work function of a WFM-containing material toward the valence band of silicon in silicon-containing materials. Examples of materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. Conductive metals that provide the gate electrode may include, but are not limited to, Al, W, or Co. The gate structure 16 may be formed using a gate-first process or a gate-last process (in which a sacrificial gate structure is formed first, and then the sacrificial gate structure is replaced with the gate structure 16 after further device processing).

[0046] In this application, the transistors referred to above are fin-type field effect transistors (finFETs), which include a semiconductor fin 10F as a device channel structure, with a gate structure 16 located on an upper portion of the semiconductor fin 10F, and a lower portion of the semiconductor fin 10F residing within a shallow trench isolation structure 12 as shown in FIG. 2B. Although this application describes the use of a finFET, other types of transistors may be used, including, for example, a planar transistor, a nanosheet transistor, or a semiconductor nanowire transistor.

[0047] The gate spacer 18 is, for example, SiO x The gate spacers 18 may be formed by deposition and etching. Each gate cap 20 may be formed by deposition followed by chemical mechanical polishing (CMP). ... followed by etching. The gate spacers 18 may be formed by deposition followed by etching. The gate spacers 18 may be formed by deposition followed

[0048] The source / drain regions 22 comprise a semiconductor material and a dopant. As used herein, a "source / drain or S / D" region can be a source region or a drain region, depending on the subsequent wiring and the applied voltage during transistor operation. The dopant can be either an n-type dopant or a p-type dopant, both of which are defined herein below. The semiconductor material providing the source / drain regions 22 includes one of the semiconductor materials mentioned above to provide the semiconductor substrate 10. The semiconductor material providing the source / drain regions 22 can be compositionally the same as or different from the semiconductor material providing each semiconductor fin 10F. The term "n-type" refers to the addition of an impurity that provides free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of n-type or p-type dopants in the source / drain regions 22 is greater than or equal to 1×10 18 atoms / cm 3 ~1x10 21 atoms / cm 3 can range from 1x10 21 atoms / cm 3 Greater than or 1x10 18 atoms / cm 3 Dopant concentrations less than 10 ...

[0049] First interlayer dielectric material layer 24 may be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant less than 4.0. First interlayer dielectric material layer 24 may be formed by a deposition process such as, for example, CVD, PECVD, or spin-on coating.

[0050] 2A, 2B, and 2C may be formed utilizing any finFET processing techniques known in the art, and details regarding finFET processing will not be described in greater detail herein so as not to obscure the present methodology.

[0051] 3A, 3B, and 3C, the exemplary structures shown in FIGS. 2A, 2B, and 2C, respectively, are illustrated after forming buried bitlines 28 (two of which are shown as an example in FIG. 3C) within at least the shallow trench isolation structure 12. The buried bitlines 28 are formed within a region located between the two device regions mentioned above in connection with the device layout shown in FIG. 1. In some embodiments (not shown in FIG. 3C), the buried bitlines 28 may be completely embedded within the shallow trench isolation structure 12, such that the top surfaces of the buried bitlines 28 are flush with or below the top surface of the shallow trench isolation structure 12. In some embodiments (and as shown in FIG. 3C), the buried bitlines 28 are embedded within both the shallow trench isolation structure 12 and the first interlayer dielectric material layer 24. In one such embodiment, buried bitline 28 has a top surface that is located between the top and bottom surfaces of first interlayer dielectric material layer 24. In some embodiments (not shown in Figures 3A, 3B, and 3C), buried bitline 28 may extend below the top surface of semiconductor substrate 10. This aspect of the present application is shown, for example, in Figures 8 and 12.

[0052] The buried bitline 28 (which functions as a power rail herein) may be composed of any conductive metal-containing material, including, but not limited to, W, Co, Ru, Al, Cu, Pr, Rh, or Pb. A thin metal adhesion layer (e.g., TiN or TaN) may be present along the bottom and sidewalls of the conductive metal-containing material that provides the buried bitline 28. The buried bitline 28 may be formed by forming an opening 26 in the first interlayer dielectric material layer 24 and a portion of the shallow trench isolation structure 12. The opening 26 may be formed by lithography and etching. At least one of the conductive metal-containing materials mentioned above may then be deposited in the opening, and recess etching may follow the deposition of the conductive metal-containing material. The deposition of the conductive metal-containing material may include CVD, PECVD, atomic layer deposition (ALD), sputtering, or plating.

[0053] In some embodiments of the present application, buried bitlines 28 have an aspect ratio of 1:1 to 6:1. The term "aspect ratio" is used throughout this application to refer to the ratio of the height of buried bitlines 28 to the width of buried bitlines 28. The aspect ratios reported herein are high aspect ratios that are beneficial for providing low resistance bitlines.

[0054] Referring now to FIGS. 4A, 4B, and 4C, the exemplary structures shown in FIGS. 3A, 3B, and 3C, respectively, are illustrated after forming a ReRAM stack on each buried bit line 28. The ReRAM stack includes a first electrode 30, a filament-forming layer 32 (which may also be referred to herein as a dielectric switching layer), and a second electrode 34. The first electrode 30 may be composed of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Cu, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode 30 may have a thickness between 2 nm and 80 nm; other thicknesses are possible and may be used herein for the thickness of the first electrode 30. The filament-forming layer 32 is composed of a dielectric material, such as a dielectric metal oxide, having a dielectric constant of 4.0 or greater. The filament-forming layer 32 is electrically insulating at this point in the present application, and conductive filaments may form within the filament-forming layer 32 during operational use. Examples of dielectric metal oxides employed as the filament-forming layer 32 include, but are not limited to, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, or combinations thereof. In some embodiments, hydrogen may be present in the dielectric material providing the filament-forming layer 32. The filament-forming layer 32 may have a thickness of 1 nm to 50 nm; however, other thicknesses are contemplated and may be used as the thickness of the filament-forming layer 32. The second electrode 34 may include one of the conductive materials mentioned above with respect to the first electrode 30. The second electrode 34 may include a two-layer electrode stack, as shown in FIGS. 8 and 12, consisting of a lower second electrode 34A and an upper second electrode 34B. In some embodiments, the conductive material providing the second electrode 34 is compositionally the same as the conductive material providing the first electrode 30. In one example, the conductive material providing both the first electrode 30 and the second electrode 34 is composed of TiN. In other embodiments, the conductive material providing second electrode 34 is compositionally different from the conductive material providing first electrode 30. In one example, the conductive material providing first electrode 30 is comprised of TaN and the conductive material providing second electrode 34 is comprised of TiN.A hard mask cap 36 resides on the second electrode 34. The hard mask cap 36 is made of a hard mask material such as, for example, SiN or SiON.

[0055] The ReRAM stack and hard mask cap 36 are formed by deposition (e.g., CVD, PECVD, or ALD), followed by a planarization process such as CMP. The planarization process removes any ReRAM stack and hard mask cap 36 formed outside of the opening 26. At this point in the application, the first electrode 30, filament-forming layer 32, and second electrode 34 of the ReRAM stack are U-shaped, each with a top surface that is coplanar with one another. These coplanar top surfaces of the ReRAM stack are coplanar with the top surface of the hard mask cap 36.

[0056] 5A, 5B, and 5C, the exemplary structures shown in FIGS. 4A, 4B, and 4C, respectively, are illustrated after patterning the ReRAM stack to provide a ReRAM. The ReRAM includes remaining (i.e., unetched) portions of the ReRAM stack, including the remaining (unetched) portions of the first electrode 30, the filament-forming layer 32, and the second electrode 34. These remaining (unetched) portions of the first electrode 30, the filament-forming layer 32, and the second electrode 34 are stacked one on top of the other to provide a pillar-shaped ReRAM, as shown in FIG. 5C. Some tapering may be present in the pillar-shaped ReRAM formed during this patterning step. The remaining (unetched) portions of the hard mask cap 36 are present on the pillar-shaped ReRAM, as shown in FIG. 5C. The patterning of the ReRAM stack and hard mask cap 36 includes lithography and etching. Note that the pillar-shaped ReRAM that is formed resides only on a portion of the underlying buried bitline 28; the remaining portion of the buried bitline 28 will extend into and out of the drawing sheet that contains Figures 5A, 5B, and 5C. In the present embodiment, the buried bitline 28 is a buried metal rail that has a length that is greater than the length of the pillar-shaped ReRAM.

[0057] 6A, 6B, and 6C, the exemplary structures shown in FIGS. 5A, 5B, and 5C, respectively, are illustrated after forming ReRAM spacers 38 that protect the sidewalls of the ReRAM. As shown in FIG. 6C, the ReRAM spacers 38 laterally surround the ReRAM, overlie the physically exposed portions of the buried bitlines 28, and cover the entire sidewalls of the ReRAM. The ReRAM spacers 38 thus have a top surface that is flush with the remaining (i.e., unetched) portions of the top electrodes 34 of the pillar-shaped ReRAMs shown in FIG. 6C. The ReRAM spacers 38 may be composed of any dielectric spacer material, including, for example, silicon dioxide or silicon nitride, and may be formed by deposition of the dielectric spacer material followed by recess etching.

[0058] 7A, 7B, and 7C, the exemplary structures shown in FIGS. 6A, 6B, and 6C, respectively, are illustrated after forming MOL contact structures and metal via structures. The MOL contact structures include source / drain contact structures 40 and gate contact structures 42. The source / drain contact structures 40 are formed on the physically exposed surfaces of the source / drain regions 22, as shown in FIG. 7A, while the gate contact structures 42 are formed on the physically exposed surfaces of the gate structures, as also shown in FIG. 7A. As shown in FIG. 7C, the pillar-shaped ReRAM residing on the buried bitline 28 is electrically connected to one of the transistor's source / drain regions using one of the source / drain contact structures 40. During the formation of the MOL contacts, the remaining (i.e., unetched) portions of the hard mask cap 36 are removed to reveal the top surface of the ReRAM. In particular, the top surface of the ReRAM's second electrode 34 is now physically exposed, and one of the source / drain contact structures 40 is in physical contact with the exposed top surface of the ReRAM; this one source / drain contact structure 40 is also in physical contact with the source / drain region as shown in FIG. 7C.

[0059] The metal via structures include a first metal via structure 44 and a second metal via structure 46. The first metal via structure 44 contacts one of the gate contact structures 42, while the second metal via structure 46 contacts one of the source / drain contact structures 40. The metal via structures are embedded within an upper portion of an interlayer dielectric material structure 25, which includes a first interlayer dielectric material layer 24, and at least one additional interconnect dielectric material layer formed on the first interlayer dielectric material layer 24. The at least one additional interconnect dielectric material layer includes one of the dielectric materials mentioned above with respect to the first interlayer dielectric material layer 24. The at least one additional interlayer dielectric material layer may be formed using a deposition process such as, for example, CVD, PECVD, or spin-on coating.

[0060] The source / drain contact structures 40 and the gate contact structures 42 are composed of at least one contact conductor material. The contact conductor material may include, for example, a silicide liner such as Ni, Pt, or NiPt, an adhesion metal liner such as TiN, and a conductive metal such as W, Cu, Al, Co, Ru, Mo, Os, Ir, or Rh, or alloys thereof. The source / drain contact structures 40 and the gate contact structures 42 may also include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In one or more embodiments in which a contact liner is present, the contact liner (not shown) may include a silicide liner, such as Ti, Ni, NiPt, etc., and a diffusion barrier material, as defined above. The source / drain contact structures 40 and gate contact structures 42 may be formed by forming gate contact openings that physically expose the gate structure 16 and source / drain contact openings that physically expose the source / drain regions 22. These openings are then filled with at least one of the above-mentioned contact conductor materials, and a planarization process is then performed to provide the source / drain contact structures 40 and gate contact structures 42.

[0061] Metal via structures, including first metal via structure 44 and second metal via structure 45, are then formed by a metallization process that includes first forming at least one additional interlayer dielectric material layer on first interlayer dielectric material layer 34, forming a via opening, and filling the via opening with a conductive metal or metal alloy. Exemplary conductive metals used to provide the metal via structures include, but are not limited to, Cu, W, Al, or Co, while exemplary conductive metal alloys used to provide the metal via structures include Cu-Al alloys or Cu-W alloys.

[0062] 7A-7C illustrate a semiconductor structure according to one embodiment of the present application. The illustrated semiconductor structure includes a buried bit line 28 buried in a shallow trench isolation structure 12, and a ReRAM 30 / 32 / 34 located on the surface of the buried bit line 28, where the ReRAM 30 / 32 / 34 is electrically connected to one of the source / drain regions 22 of at least one first transistor. In the present application, the first transistor, the ReRAM 30 / 32 / 34, and the buried bit line 28 are located at the same device level (i.e., FEOL level).

[0063] 7A, 7B, and 7C, a BEOL structure (not shown) and a carrier wafer (also not shown) may be formed. The BEOL structure includes various metal levels, M1, M2, etc. The various metal levels include conductive structures (metal lines and vias) embedded within interconnect dielectric material layers.

[0064] Referring now to FIG. 8, an ReRAM structure according to one embodiment of the present application is illustrated. The ReRAM structure includes the various components mentioned above with respect to FIGS. 2A-7C. In particular, the ReRAM structure includes a buried bit line 28 embedded in the shallow trench isolation structure 12, with ReRAMs 30 / 32 / 34A / 34B located on the surface of the buried bit line 28, where the ReRAMs 30 / 32 / 34A / 34B are electrically connected to one of the source / drain regions 22 of at least one first transistor (where the ReRAM is electrically connected to the source / drain region of each first transistor among the plurality of first transistors). The ReRAM structure further includes a source line, SL, located above the at least one first transistor, where the source line, SL, is electrically connected to the source / drain region 22 of at least one second transistor. Here, the SL is in M1, and therefore, the SL is located in the BEOL. The source line is electrically connected to the source / drain region 22 of at least one second transistor by a metal via structure 46 and a second source / drain contact structure 41. The source line may be composed of a conductive metal or a conductive metal alloy. In one example, the source line is composed of Cu or W.

[0065] Referring now to FIG. 9, a top view of a memory array according to one embodiment of the present application is illustrated, including a plurality of ReRAM structures as shown in FIG. 8. In particular, FIG. 9 shows that continuous buried bit lines 28 extend horizontally with ReRAM devices located above them. In the region where the ReRAM devices are formed, the memory cells extend to the neighboring SL. The gate structures 16 are oriented perpendicular to the BL / SL. The source / drain contact structures 40 are middle-of-the-line connections. An important feature of this embodiment is that the buried bit lines 28 are buried, while the source lines are located at the M1 level.

[0066] 10, a top view of a multiplexed resistive memory array according to one embodiment of the present application is illustrated, which includes a plurality of the ReRAM structures shown in FIG. 8. In particular, FIG. 10 shows that buried bit lines 28 include memory element and M1 source lines, SL, running in the same orientation, where the transistor source / drains connect to the ReRAM devices and gate structures 16. In this embodiment, unlike FIG. 9, two source lines are adjacent to each other, with each pair of source lines separated by a buried bit line 28.

[0067] Referring now to FIG. 11, there is shown a circuit diagram of the multiplexed resistive memory array shown in FIG. 10. In this drawing, WL refers to a word line, which is the gate electrode of each gate structure, and BL represents a bit line, which is herein a buried bit line 28. In this drawing, each WL is hardwired to a word line decoder and driver 104, and each SL is hardwired to a common reference source 102. In particular, FIG. 11 shows a memory cell design with the notable feature that the BL and SL extend in the same direction, one buried and the other at M1. Both the BL and SL are perpendicular to the WL and may be located at a higher metal level than M1.

[0068] 12, an ReRAM structure according to one embodiment of the present application is illustrated. The ReRAM structure includes the various components mentioned above with respect to FIGS. 2A-7C. In particular, the ReRAM structure includes a buried bit line 28 buried in a shallow trench isolation structure 12, with ReRAMs 30 / 32 / 34A / 34B located on the surface of the buried bit line 28, where the ReRAMs 30 / 32 / 34A / 34B are electrically connected to one of the source / drain regions 22 of at least one first transistor (where the ReRAMs are electrically connected to the source / drain regions of each first transistor among the plurality of first transistors). The ReRAM structure further includes a SL located at the same level as the first transistor, where the SL is electrically connected to the source / drain region 22 of at least one second transistor. Here, the SL is equal to the buried line 29. The buried line 29 comprises the material mentioned above with respect to the buried bit line 28, and it is present at least within the shallow trench isolation structure 12. This source line SL is electrically connected to the source / drain region 22 of at least one second transistor by a metal via (via) and a second source / drain contact structure 41.

[0069] Referring now to Figure 13, there is illustrated a top view of a memory array according to one embodiment of the present application that includes a plurality of ReRAM structures as shown in Figure 12. The memory array shown in Figure 13 is similar to the memory array shown in Figure 9, except that in this drawing both the BL and SL are buried under the transistors, whereas in Figure 9 the BL is buried and the SL is at M1.

[0070] Referring now to Figure 14, there is shown a top view of a multiplexed resistive memory array according to one embodiment of the present application, which includes a plurality of ReRAM structures as shown in Figure 12. The memory array is similar to the memory array shown in Figure 10. The difference between the memory array shown in Figure 14 and the memory array shown in Figure 10 is that in Figure 14, the M1 track resides between the buried bit line 28 and the source line 29 and connects to the device level, while in Figure 10, the M1 track is omitted.

[0071] Referring now to Figure 15, there is illustrated a circuit diagram of the multiplexed resistive memory array shown in Figure 14. In this diagram, WL refers to a word line, which is the gate electrode of each gate structure, and BL represents a bit line, which is herein a buried bit line 28. In this diagram, each WL is hardwired to a word line decoder and driver 104, and each SL is hardwired to a common reference source 102. This circuit diagram is similar to the circuit diagram shown above in Figure 11. The primary difference between this diagram and that depicted in Figure 11 is that in Figure 15, both the BL and SL are buried, while in Figure 11, the BL is buried and the SL is at M1.

[0072] While the present application has been particularly shown and described in connection with its preferred embodiments, those skilled in the art will recognize that the foregoing and other changes in form and detail may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a buried bit line buried within the shallow trench isolation structure; and a resistive random access memory (ReRAM) located on the surface of the buried bit line, wherein the ReRAM is electrically connected to a source / drain region of at least one first transistor; 1. A semiconductor structure comprising:

2. 2. The semiconductor structure of claim 1, wherein the ReRAM and the buried bit line are also buried within an interlayer dielectric material structure that overlies the shallow trench isolation structure.

3. 2. The semiconductor structure of claim 1, wherein the at least one first transistor is a fin field effect transistor (finFET), the finFET having a semiconductor fin as a device channel structure and a gate structure located on an upper portion of the semiconductor fin, a lower portion of the semiconductor fin residing within the shallow trench isolation structure.

4. 10. The semiconductor structure of claim 1, further comprising: a source line located above the at least one first transistor, the source line electrically connected to a source / drain region of at least one second transistor.

5. 5. The semiconductor structure of claim 4, wherein the ReRAM is electrically connected to the source / drain regions of the at least one first transistor by a first source / drain contact structure, and the source line is electrically connected to the source / drain regions of the at least one second transistor by a metal via structure and a second source / drain contact structure.

6. 5. The semiconductor structure of claim 4, wherein the buried bit lines are connected to a sense amplifier and the source lines are connected to a common ground reference.

7. 10. The semiconductor structure of claim 1, further comprising: a buried source line buried within the shallow trench isolation structure, wherein the buried source line is electrically connected to a source / drain region of at least one second transistor.

8. 8. The semiconductor structure of claim 7, wherein the ReRAM is electrically connected to the source / drain regions of the at least one first transistor by a first source / drain contact structure, and the buried source line is electrically connected to the source / drain regions of the at least one second transistor by a metal via structure and a second source / drain contact structure.

9. The semiconductor structure of claim 8 , wherein the at least one second transistor is a finFET.

10. 8. The semiconductor structure of claim 7, wherein the buried bit lines are connected to a sense amplifier and the buried source lines are connected to a common ground reference.

11. 10. The semiconductor structure of claim 1, wherein said buried bitline extends below a top surface of a semiconductor substrate.

12. 10. The semiconductor structure of claim 1, wherein said buried bitlines have an aspect ratio of between 1:1 and 6:

1.

13. 2. The semiconductor structure of claim 1, wherein the at least one first transistor comprises a plurality of first transistors, and the ReRAM is electrically connected to a source / drain region of each first transistor of the plurality of first transistors.

14. 2. The semiconductor structure of claim 1, wherein the buried bit line is located within a region adjacent to a first device region including the at least one first transistor and located between the first device region and a second device region.

15. 2. The semiconductor structure of claim 1, wherein the buried bit line is a buried metal rail having a length greater than a length of the ReRAM.

16. a plurality of buried bit lines embedded within a shallow trench isolation structure; a resistive random access memory (ReRAM) located on a surface of each of the buried bit lines of the plurality of buried bit lines, the ReRAM being electrically connected to a source / drain region of each first transistor of the plurality of first transistors; and a plurality of source lines electrically connected to source / drain regions of each second transistor among the plurality of second transistors, wherein the plurality of first transistors are adjacent to the plurality of second transistors; 1. A memory array comprising:

17. 17. The memory array of claim 16, wherein each source line of the plurality of source lines resides above the plurality of first transistors and the plurality of second transistors.

18. 20. The memory array of claim 17, wherein each buried bit line of said plurality of buried bit lines is connected to a sense amplifier and each source line of said plurality of source lines is connected to a common ground reference.

19. 17. The memory array of claim 16, wherein each source line of the plurality of source lines is a buried source line buried within the shallow trench isolation structure.

20. 20. The memory array of claim 19, wherein each buried bit line of said plurality of buried bit lines is connected to a sense amplifier and each source line of said plurality of source lines is connected to a common ground reference.

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