Top contacts on resistive random access memories

Abstract

The memory device includes a trench into a first conductive structure; a first electrode of a conformal conductive material contained within the trench in electrical communication with the first conductive structure and residing on a sidewall of the trench; a switching layer residing in the trench over the first electrode and extending outside the trench; and a second electrode residing on the switching layer while overfilling the trench. The memory device also includes a contact positioned over a portion of the second electrode overfilling the trench such that the contact is horizontally offset from the first electrode residing in the trench (FIG. 1).

Description

[Background technology]

[0001] The present invention relates generally to memory devices, and more particularly to resistive switching memory stacks integrated with field effect transistors.

[0002] One example of non-volatile memory uses variable resistance memory elements that can be set to either a low or high resistance state and then remain in that state until reset to an initial condition. The variable resistance memory elements are individually connected between two intersecting, perpendicular conductors (e.g., bit and word lines) in a two-dimensional array. The state of such memory elements is often changed by applying appropriate voltages to the intersecting conductors.

[0003] Resistive memory stacks have been observed to be relatively thin. For example, resistive memory stacks may have thicknesses in the range of 30 nm to 50 nm, which may be susceptible to excessive plasma damage during top contact formation. Furthermore, resistive memory devices include thin bottom electrodes. The thin bottom electrodes of resistive random access memory devices may include hillocks, i.e., small raised portions, that contact the switching layer of the resistive memory stack. The presence of hillocks that contact the switching elements of the memory stack can degrade device performance. Furthermore, if the bottom electrode is composed of copper, the presence of copper hillocks can result in copper contamination downstream of the memory stack where the memory stack does not cover the hillocks. Summary of the Invention

[0004] In some embodiments, the aforementioned difficulties can be overcome by a method and structure for forming a top contact on a damascene-processed resistive random access memory (RRAM) stack, where the top contact is horizontally offset from the main switching area of ​​the device. Hillocks, e.g., copper hillocks, from the bottom electrode in conventional designs can cause short circuits in the resistive random access memory (RRAM) device. In a damascene-processed resistive random access memory device, where the top trench for the top electrode is horizontally offset from the switching element and bottom electrode, the possibility of a short circuit due to potential hillocks is avoided. By being offset, the top electrode may be considered to be located on the side of the switching element of the resistive random access memory (RRAM) device. The methods described herein enable patterning large top electrodes that allow sufficient landing of the top contact, which is advantageous for back-end of the line (BEOL) processing. In a damascene-formed resistive random access memory (RRAM) device, the area of ​​the switching layer can be increased. For example, the bottom electrode is contained within a trench formed by a damascene process, but the switching layer is not only in the trench with the bottom electrode but also extends outside the trench, e.g., the switching layer has a width greater than the bottom electrode. The extended resistive random access memory (RRAM) area for landing the top contact away from the main switching region avoids plasma damage resulting from device processing of the resistive random access memory device prior to the methods and structures of the present disclosure.

[0005] According to one aspect of the present invention, a memory device, e.g., a resistive random access memory (RRAM), is described, including a top contact that is horizontally offset from a switching element of the device. In one embodiment, the memory device includes a trench into a first conductive structure. A first electrode of a conformal conductive material is contained within the trench in electrical communication with the first conductive structure and resides on a sidewall of the trench. A switching layer resides within the trench over the first electrode and extends outside the trench. A second electrode resides on the switching layer while overfilling the trench. A contact is positioned over a portion of the second electrode that overfills the trench, such that the contact is horizontally offset from the first electrode that resides within the trench.

[0006] In another embodiment, a memory device, e.g., a resistive random access memory (ReRAM), is described that includes a top contact that is horizontally offset from a switching element of the device, where a first electrode may be deposited to reside at the base of a trench but not extend along the entire sidewall of the trench. In one example, the memory device includes a trench into a first conductive structure. A first electrode of a conductive material resides at the base of the trench in electrical communication with the first conductive structure. A switching layer of a conformal material resides over the trench on the first electrode, on the sidewall of the trench, and extends outside the trench. A second electrode resides on the switching layer while overfilling the trench. A contact is positioned over a portion of the second electrode that overfills the trench, such that the contact is horizontally offset from the first electrode that resides in the trench.

[0007] In another aspect, a method of forming a memory device is provided. The method includes forming a trench to a conductive structure at the base of the trench. Forming a first electrode in the trench. Filling the trench with a filler material including a bilayer consisting of a switching layer overlying the first electrode and a layer for a second electrode overlying the switching layer, wherein a portion of the bilayer extends outside the trench. Patterning the portion of the bilayer that extends outside the trench to provide a landing spot in the trench that is horizontally offset from the first electrode. Forming a contact to the landing spot.

[0008] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0009] The following description provides details of a preferred embodiment with reference to the following figures:

[0010] [Figure 1] FIG. 1 is a side cross-sectional view of a resistive random access memory device according to one embodiment of the present disclosure, wherein the bottom electrode of the device is confined within a trench formed using a damascene process and the top electrode includes a landing portion for contact that extends outside the trench, such that the contact to the second electrode is horizontally offset from the first electrode.

[0011] [Figure 2] FIG. 1 is a side cross-sectional view of a second embodiment of the present invention, showing a memory device, e.g., a resistive random access memory (ReRAM), including a top contact that is horizontally offset from a switching element of the device, where a first electrode may be deposited to reside at the base of a trench but does not extend along the entire sidewall of the trench.

[0012] [Figure 3] 2 is a cross-sectional side view illustrating the patterning of contact holes in an initial structure in a method for forming the structure shown in FIG. 1 according to one embodiment of the present disclosure.

[0013] [Figure 4] FIG. 2 is a cross-sectional side view illustrating a blanket deposition of a material layer for a first electrode and a sacrificial metal fill for a trench, according to one embodiment of the present disclosure.

[0014] [Figure 5] 5 is a cross-sectional side view illustrating planarization of the structure shown in FIG. 4 according to one embodiment of the present disclosure.

[0015] [Figure 6] 10A-10C are cross-sectional side views illustrating the removal of a sacrificial metal fill from a trench using an etching process, according to one embodiment of the present disclosure.

[0016] [Figure 7] FIG. 10 is a cross-sectional side view illustrating depositing a layer of material for a switching layer in a trench and depositing a layer of material for a second electrode according to one embodiment of the present disclosure.

[0017] [Figure 8] FIG. 10 is a cross-sectional side view illustrating patterning a second electrode and a switching layer and encapsulating the patterned portions of the second electrode and the switching layer in an encapsulating dielectric according to one embodiment of the present disclosure.

[0018] [Figure 9] 3 is a cross-sectional side view of an initial structure for forming the memory device shown in FIG. 2.

[0019] [Figure 10] 10 is a cross-sectional side view illustrating the formation of a first electrode at the base of the trench shown in FIG. 9 according to one embodiment of the present disclosure.

[0020] [Figure 11] 11 is a side cross-sectional view showing the formation of a material layer for a switching layer and a second electrode on the first electrode shown in FIG. 10. FIG.

[0021] [Figure 12] FIG. 10 is a cross-sectional side view illustrating patterning of a second electrode and a switching layer according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0022] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. Furthermore, each example shown in connection with various embodiments is intended to be illustrative, not limiting. Furthermore, the figures are not necessarily to scale, and some features may be exaggerated to show details of particular components. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to employ various aspects of the disclosed methods and structures. Hereinafter, for purposes of explanation, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the embodiments of the present disclosure as oriented in the drawings. The term "located on" means that a first element, such as a first structure, is present on a second element, such as a second structure, and an intervening element, such as an interface structure, e.g., an interface layer, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conducting, insulating, or semiconducting layer at the interface between the two elements.

[0023] The present disclosure relates to resistive memory devices, such as resistive random access memory (RRAM). As used herein, the term "memory device" refers to a structure that can change its electrical state and then retain it in the changed state, thus storing small amounts of information. Resistive random access memory (ReRAM or RRAM) is a type of non-volatile (NV) random access memory (RAM) that operates by changing the resistance across a dielectric solid-state material, often called a memristor. Resistive random access memory (ReRAM) devices may be suitable for use in applications such as non-volatile memory, and in low-voltage, high-endurance, and high-density applications. ReRAM is also suitable for crossbar arrays in neuromorphic applications.

[0024] Resistive random access memories (RRAMs) can be based on the reversible formation / destruction of conductive filaments in a resistive layer that provide low and high resistance states. Various classifications exist. Depending on the composition of the filaments, two types of RRAMs can be distinguished: OXRAMs, whose filaments are based on oxygen vacancies, and conductive bridging RAMs (CBRAMs), whose filaments result from the dissolution of the active electrodes, which can in most cases be made of silver (Ag) or copper (Cu).

[0025] Resistive memory stacks have been observed to be relatively thin. For example, resistive memory stacks may have thicknesses in the range of 30 nm to 50 nm, which may be susceptible to excessive plasma damage during top contact formation, which may result in the unintentional formation of devices such as parasitic devices. Thin bottom electrodes may contain hillocks, e.g., hillocks composed of copper, which may touch the switching layer and degrade device performance. Furthermore, the presence of hillocks may be a source of contamination, e.g., copper contamination if the hillocks are composed of copper, if the memory stack does not cover the entire hillock.

[0026] The methods and structures described herein overcome the aforementioned difficulties associated with damascene resistive random access memory (RRAM) devices that include bottom electrodes confined within damascene trenches. "Damascene" is a method for interconnecting metals, such as copper (Cu), to form wiring. In the damascene process, a dielectric layer is patterned and etched to provide trenches, which are then filled with a conductive material to provide the conductive wiring and / or interconnects.

[0027] After filling, a planarization process such as chemical mechanical planarization (CMP) is performed to remove any material that overfills the trench. The process is a damascene process, e.g., forming metal lines / vias using a single damascene. Dual damascene refers to two features formed using damascene methodology. A dual damascene process is characterized by patterning a via and a trench in such a way that the metal deposition fills both simultaneously. A damascene process generally fills and forms a single feature with copper per damascene step. A dual damascene process generally fills and forms two features at a time with copper; for example, dual damascene may be used to fill both trenches above a via with a single copper deposition.

[0028] As shown below, by confining the bottom electrode (referred to herein as the first electrode) within the tall damascene trench, so that it does not extend outside the trench, and by forming a contact to an extension of material for the top electrode (referred to herein as the second electrode), the methods and structures described herein eliminate the possibility of shorts between these conductive structures, e.g., the top and bottom contacts. Additionally, the tall trench damascene RRAM described herein can also provide advantages such as a larger switching area providing lower formation voltages, a more tolerant area for landing the top contact, and the ability to land the top contact off-center of the bottom active RRAM to avoid over-etching. The structures and methods of the present invention will now be discussed in more detail with reference to Figures 1-12.

[0029] FIG. 1 illustrates an embodiment of a resistive random access memory device in which the bottom electrode (hereafter referred to as the first electrode 10) of the device is confined within a trench 5 formed using a damascene process, and the top electrode (hereafter referred to as the second electrode 20) includes a landing portion 21 for a contact 25 that extends outside the trench 5, such that the contact 25 to the second electrode 20 is horizontally offset by H1 from the first electrode 10. The structure illustrated in FIG. 1 illustrates an embodiment of a memory device, e.g., a resistive random access memory (RRAM), and is described as including a top contact 25 that is horizontally offset by H1 from the device's switching element. The boundary of the switching element in the embodiment illustrated in FIG. 1 is defined by the presence of the first electrode 10.

[0030] In one embodiment, the memory device includes a trench 5 into a first conductive structure 3. The first conductive structure 3 may be a conductive line, e.g., a metal line such as a copper (Cu) line, or the first conductive structure 3 may be a metal via, e.g., a copper via. The first conductive structure 3 may reside within a dielectric material 4, e.g., a dielectric substrate or a dielectric interlevel layer. In some examples, the dielectric material 4 may be provided by a substrate of semiconductor material that is not doped in a manner to make it conductive, e.g., undoped silicon.

[0031] 1, a first electrode 10 of a conformal conductive material may be included within trench 5, where first electrode 10 is in electrical communication with first conductive structure 3. In some embodiments, first electrode 10 has a U-shaped configuration when viewed from a side cross section. Trench 5 may be present to extend through and into interlevel dielectric layer 9, for example. Interlevel dielectric layer 9 may be made of a material such as SiO2, Si3N4, SiO x Silicon-containing materials such as Ny, SiC, SiCO, SiCOH, and SiCH compounds, the above silicon-containing materials in which some or all of the Si has been replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, polyamides, or SiLK TM and other carbon-containing materials, organic-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as hydrogenated amorphous carbon (α-C:H).

[0032] In some embodiments, a barrier layer and / or etch stop layer (collectively referred to as interfacial layer 8) may be present between interlevel dielectric layer 9 and the underlying level of dielectric material 4 and conductive structure 3. In some embodiments, the barrier layer may comprise a composition that acts as a barrier to copper (Cu) diffusion, e.g., a metal nitride such as tantalum nitride. The etch stop layer provides for individual processing of a particular material layer. One example of an etch stop layer composition is silicon nitride.

[0033] The trench 5 may extend through both the interlevel dielectric layer 9 and the interfacial layer 8 , where the trench exposes the top surface of the conductive structure 3 .

[0034] The first electrode 10 may be composed of one or more layers of a metal nitride material. For example, the first electrode 10 may be composed of a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. In other embodiments, the first electrode 10 may be a multi-layer structure including a metal nitride layer and an aluminum-containing layer. For example, the first electrode 10 may also include an aluminum-containing alloy layer, such as titanium aluminum carbide (TiAlC).

[0035] In one example, the first electrode 10 is made of tantalum nitride (TaN) deposited using physical vapor deposition (PVD), or the first electrode 10 is made of titanium nitride (TiN) deposited using chemical vapor deposition (CVD).

[0036] The first electrode 10 may be present at the base of the trench 5 or on the sidewall S1 of the trench 5. The first electrode 10 may extend along the entire height of the sidewall S1 of the trench. However, the first electrode 10 is confined within the trench 5 and does not extend beyond the interior of the trench 5.

[0037] The thickness of the material layer for the first electrode 10 is substantially the same on the sidewalls S1 of the trench 5 as at the base of the trench. In some embodiments, the first electrode 10 has a conformal thickness. The term "conformal" refers to a layer having a thickness that does not deviate more or less than 30% of the average thickness of the layer.

[0038] 1, the switching layer 15 of the memory device 100a is also present in the trench 5, with the switching layer being present on the first electrode 10. In some embodiments, the switching layer 15 may be a metal oxide. The metal oxide providing the switching layer 15 may be one of hafnium oxide (HfOx), tantalum oxide (TaOx), titanium oxide (TiOx), and combinations thereof.

[0039] 1, the switching layer 15 is present at the base of the trench 5 over the portion of the first electrode 10 that is present at the base of the trench 5, and the switching layer 15 is present along the entire height of the trench 5 over the portion of the first electrode 10 that is present on the sidewalls S1 of the trench 5. The switching layer 15 is also present on top of a dielectric layer that provides a planarizing stop / barrier layer 22.

[0040] The top electrode 20 of the resistive random access memory device is also present in the contact. The top electrode 20 may be a layer of material that has a conformal thickness and is present in direct contact with the switching layer at the base and sidewalls of the contact via. The top electrode 20 includes a portion that extends outside the trench, i.e., an extension portion 21.

[0041] 1, the extension 21 of the top electrode resides on the top surface of a diffusion barrier layer 22 that resides on the top surface of the interlevel dielectric layer 9 in which the trench 5 is formed. In one embodiment, the extension 21 of the top electrode 20 (also referred to as the second electrode 20) resides in direct contact with the portion of the switching layer 15 that extends from the portion of the switching layer 15 that resides on the sidewall S1 of the trench 5 (the extension of the switching layer 15).

[0042] The diffusion barrier layer 22 has a composition that can function to block the diffusion of metal elements from conductive features that fill trenches for metal lines and vias. For example, the diffusion barrier layer 22 may act as a barrier to the diffusion of copper (Cu). In one example, the diffusion barrier layer 22 may be composed of, but is not limited to, silicon nitride SiNCH or SiCN.

[0043] The extension 21 of the switching layer 15 is in direct contact with the top surface of the diffusion barrier layer 22 that resides on the top surface of the interlevel dielectric layer 9 in which the trench 5 is formed. In the embodiment shown in Figure 1, the outermost edges of the extension 21 of the top electrode 20 (second electrode 20) are aligned with the outermost edges of the extension 21 of the switching layer 15.

[0044] The extension portion 21 includes a landing site for the top contact 25. The landing site is offset horizontally by H1 from the switching portion of the device. The width of the switching portion of the device is defined by the outermost edge of the first electrode 10 (i.e., bottom electrode) that resides on the sidewall S1 of the trench 5. The horizontal offset H1 is measured from the outer edge of the nearest portion of the first electrode portion (first electrode 10) that resides on the sidewall S1 of the trench 5 and the outer edge of the top contact 25 that is nearest to the trench 5.

[0045] 1 , contact 25 is positioned over a portion of second electrode 20 (also referred to as top electrode) that overfills trench 5, such that the contact is horizontally offset from first electrode 10 (also referred to as bottom electrode) that resides in trench 5. Contact 25 may be a metal via contact, which may be composed of copper (Cu). However, other metals such as tungsten or aluminum (Al) are also contemplated.

[0046] The device structure shown in FIG. 1 illustrates a top contact, i.e., contact 25, present on a damascene processed resistive random access memory stack (RRAM), where the top contact is horizontally offset by H1 from the main switching area of ​​the device. In a damascene processed resistive random access memory device, where the top contact 25 for the top electrode (second electrode 20) is horizontally offset by H1 from the switching element, contact to the bottom electrode 10 through the switching layer 15 is avoided. The bottom electrode (first electrode 10) formed in a tall trench avoids the possibility of shorting due to Cu hillocks from the bottom contact 3. By being offset, the top electrode may be considered to be located on the side of the switching element of the resistive random access memory (RRAM) device.

[0047] FIG. 2 illustrates a second embodiment of the present invention. In the embodiment illustrated in FIG. 2, a memory device, e.g., a resistive random access memory (ReRAM), includes a top contact 25 that is horizontally offset by H1 from the device's switching element. The switching element is defined by the location of a first electrode 10 (also referred to as a bottom or lower electrode). In the embodiment illustrated in FIG. 2, the first electrode 10 may be deposited to reside at the base of the trench, but not extend along the entire sidewall of the trench. In one example, the memory device includes a trench to a first conductive structure 3. A first electrode 10 of a conductive material resides at the base of the trench in electrical communication with the first conductive structure 3. A switching layer 15 of a conformal material resides within the trench on the first electrode 10, on the sidewalls of the trench, and extends outside the trench. A second electrode 20 (also referred to as a top or upper electrode) resides on the switching layer 15, overfilling the trench 5. The contact 25 is positioned on top of the portion of the second electrode 20 that overfills the trench (i.e., the portion that extends to the left), such that the contact is horizontally offset H1 from the first electrode 10 that is present in the bottom of the trench.

[0048] The first electrode 10 resides only at the base of the trench. The first electrode does not extend along the sidewalls of the trench upward from the portion of the first electrode 10 that resides on the base surface of the trench. For example, in one embodiment, no portion of the first electrode extends beyond the first quarter of the height of the trench. This is in contrast to the embodiment shown in FIG. 1, in which the first electrode 10 extends along the entire height of the trench.

[0049] It should be noted that the embodiment shown in Figure 2 includes some elements similar to the embodiment shown in Figure 1. In at least one embodiment, elements having reference numbers in Figure 2 may have the characteristics of similar elements having the same reference numbers in Figure 1. Thus, the description of elements having reference numbers in Figure 1 is suitable for providing a description of the characteristics of elements having the same reference numbers in Figure 2.

[0050] 3-8 illustrate one embodiment of a method for forming the structure shown in FIG. 1. Generally, a method for forming a memory device may include forming a trench 5 into a conductive structure present at the base of the trench 5; forming a first electrode 10 (also called a lower or bottom electrode) in the trench 5; filling the trench with a filler material including a bilayer 15, 20 comprised of a switching layer 15 present on the first electrode 10 and a layer for a second electrode 20 on the switching layer, where a portion of the bilayer (e.g., extension 21) extends outside the trench 5; patterning the portion of the bilayer that extends outside the trench 5 to provide a landing spot that is horizontally offset by H1 from the first electrode 10 in the trench 5; and forming a contact 25 to the landing spot.

[0051] 3 illustrates one embodiment of an initial structure of a method for forming the structure shown in FIG. 1. The initial structure illustrated in FIG. 3 includes patterning of a tall contact hole. More specifically, in one embodiment, the structure illustrated in FIG. 3 includes a trench 5 to a first conductive structure or bottom contact 3. The first conductive structure 3 may be a conductive line, e.g., a metal line such as a copper (Cu) line, or the first conductive structure 3 may be a metal via, e.g., a copper via. The first conductive structure 3 may reside within a dielectric material 4, e.g., a dielectric substrate or a dielectric interlevel layer.

[0052] The conductive structure 3 may be formed by forming trenches in a dielectric material using photoresist deposition, lithographic patterning, and an etching process using the patterned photoresist as an etch mask. After trench formation, the trench may be filled with a metal such as, but not limited to, copper, tungsten, or aluminum by employing, for example, electroplating, chemical vapor deposition, or physical vapor deposition processes with a barrier liner such as TaN. The structure is then planarized, for example, by using chemical mechanical planarization (CMP).

[0053] Dielectric layer deposition may be performed on the planarized surface, which may begin with an interfacial layer, reference numeral 8. Blanket deposition of successive dielectric materials may provide the interfacial layer 8, the interlevel dielectric layer 9, and the planarization stop layer / diffusion barrier layer 22. The deposition process may include chemical vapor deposition (CVD).

[0054] Following the aforementioned deposition sequence, a trench 5 is formed that provides an opening to the first conductive structure 3. The trench 5 may be formed using photolithography and etching processes. For example, a photoresist mask may be formed that exposes a portion of the dielectric material layer where the via opening is to be formed, where, after forming the photoresist mask, the via opening may be etched into the first dielectric layer 11 using an etching process such as reactive ion etch (RIE). The etching process may be timed and may be selective to the metal of the conductive structure, or the etching process may be terminated upon detecting that the conductive structure has been reached using an endpoint detection method.

[0055] 4 illustrates the blanket deposition of material layers for the first electrode 10 and the deposition of a sacrificial metal fill 11 for the trench 5. In one embodiment, the material layers for the first electrode 10 may be deposited using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). The one or more material layers for the first electrode 10 may be formed in direct contact with the conductive structure 3. In one embodiment, the material layers for the first electrode 10 may be comprised of tantalum nitride (TaN), and the material layers for the first electrode 10 may be formed with a deposition process that may include chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). In another embodiment, the material layer for first electrode 10 may be composed of titanium nitride, and the material layer for first electrode 10 may include a deposition process that may include chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). In some embodiments, first electrode 10 may have a thickness in the range of 5 nm to 200 nm. The blanket deposition of the material layer for first electrode 10 forms the first electrode material on the base of trench 5, the sidewalls of the trench, and the top surface of planarization stop layer / diffusion barrier layer 22.

[0056] 4 also illustrates filling trench 5 with sacrificial metal fill 11. In one example, sacrificial metal fill 11 may be composed of copper (Cu). In some embodiments, sacrificial metal layer 11 is formed by depositing a copper seed layer followed by a copper fill. The copper fill may be formed using a plating process, such as electroplating or electroless plating. In some embodiments, the copper fill for sacrificial metal fill 11 may overfill trench 5, extending over the portion of the material layer for first electrode 10 that resides above planarization stop / barrier layer 22.

[0057] 5, planarization of the structure shown in FIG. 4 is illustrated. The planarization method may be provided by chemical mechanical planarization (CMP). The planarization process may be continued to remove any sacrificial metal 11 that is not within trench 5 and expose the top surfaces of the barrier layer and / or etch stop layer (collectively referred to as interfacial layer 8).

[0058] The first electrode 10 contained within the trench 5 after the planarization process defines the portion of the switching device that is processed to be within the trench 5 using the damascene process sequence, i.e., the first electrode 10 is within the damascene.

[0059] 6 illustrates one embodiment of using an etching process to remove the sacrificial metal fill 11 from the trench 5. The etching process may be timed and selective to the metal of the first electrode 10, or the etching process may be terminated upon detecting the reaching of the first electrode using an endpoint detection method.

[0060] FIG. 7 illustrates one embodiment of depositing a material layer for the switching layer 15 in the trench 5 and a material layer for the second electrode 20. The switching layer 15 may be blanket deposited on the structure shown in FIG. 6. The switching layer 15 is deposited so as to be in direct contact with the material layer for the first electrode 10. The switching layer 15 may be a metal oxide, which may be deposited using a conformal deposition process. In some embodiments, the switching layer 15 is comprised of a composition selected from the group consisting of hafnium oxide (HfO), tantalum oxide (TaO), titanium oxide (TiO), tungsten oxide (WO), zirconium oxide (ZrO), aluminum oxide (AlO), strontium titanium oxide (SrTiO), and combinations thereof. The switching layer 15 may have a thickness ranging from 1 nm to 15 nm. In one example, the switching layer 15 may be composed of hafnium oxide (HfO2) and may have a thickness in the range of 3 nm to 10 nm.

[0061] The switching layer 15 can be formed using atomic layer deposition (ALD). Atomic layer deposition (ALD) is a thin film deposition method in which a film is grown on a substrate by exposing the substrate surface to alternating gas species (commonly called precursors). In contrast to chemical vapor deposition, precursors in ALD are not simultaneously present in the reactor; instead, they are introduced as a series of consecutive, non-overlapping pulses. In each pulse, precursor molecules react with the surface in a self-limiting manner until all reactive sites on the surface are consumed. As a result, the maximum amount of material deposited on the surface after a single exposure to all precursors (also known as an ALD cycle) is determined by the nature of the precursor-surface interaction. By varying the number of ALD cycles, materials can be grown uniformly and with precision on arbitrarily complex and large substrates, such as three-dimensional structures. For example, the switching layer 15 can be deposited by atomic layer deposition of HfO2 using subsequent pulses of HfCl4 and HO precursors at temperatures exceeding 200°C.

[0062] It should be noted that atomic layer deposition (ALD) is just one example of a deposition process for forming the switching layer 15. In some other embodiments, the deposition process may be chemical vapor deposition, such as plasma enhanced chemical vapor deposition (PECVD).

[0063] A blanket deposition of a layer of material for the switching layer 15 deposits material at the base of the trench 5 , on the sidewalls of the trench 5 , and on the top surface of the planarizing stop layer / diffusion barrier layer 22 .

[0064] 7 also illustrates the deposition of a material layer for the second electrode 20 (also referred to as the upper electrode or top electrode) directly on the switching layer 15. In one embodiment, the second electrode 20 is composed of titanium nitride (TiN). The titanium nitride (TiN) layer for the second electrode 20 can be deposited using chemical vapor deposition (CVD), such as plasma-enhanced chemical vapor deposition (PECVD) or metal organic chemical vapor deposition (MOCVD). In other embodiments, the metal composition for the second electrode 20 can be a titanium aluminum carbon-containing material, such as a titanium aluminum carbon (TiAlC) layer. The thickness of the material layer for the second electrode 20 can be deposited directly on the material layer for the switching layer and can be thick enough to fill the trench 5.

[0065] The blanket deposition of the material layer for the second electrode 20 deposits material directly onto the switch layer 15 at the base of the trench 5, directly onto the switch layer present on the sidewalls of the trench 5, and onto the portion of the switch layer 15 present on the top surface of the planarization stop layer / diffusion barrier layer 22.

[0066] 7 further illustrates the formation of a hard mask layer 30 over the layer of material that provides the second electrode 20. The hard mask layer 30 may be composed of a nitride-containing dielectric, such as silicon nitride. The hard mask layer 30 may be deposited using chemical vapor deposition (CVD).

[0067] 8 illustrates patterning the second electrode 20 and the switching layer 15 and encapsulating the patterned portions of the second electrode 20 and the switching layer 15 in an encapsulation dielectric 35, such as silicon nitride. Patterning the second electrode 20 and the switching layer 15 may begin with forming a photoresist mask on the hard mask layer 30. The photoresist mask covers the underlying portions of the second electrode 20 and the switching layer 15 and the portions of the hard mask layer 30 that are intended to remain for encapsulation by the encapsulation dielectric 35. A sequence of patterning and etching processes also defines the width of the extension portions 21 of the second electrode 20 and the switching layer 15.

[0068] After forming the etching mask, the hard mask layer 30 may be etched, followed by etching the material layer of the second electrode 20 and the material layer of the switching layer 15. The etching process may be a directional etch, for example, by reactive ion etching (RIE). The etching process may extend through the hard mask layer 30, the second electrode 20, and the material layers for the switching layer 15, but stop on the barrier layer 22.

[0069] 1 , the method may continue by encapsulating the first electrode 20 and the remaining portions of the switching layer 15 with an encapsulating dielectric 35, which may be silicon nitride, for example. The encapsulated dielectric may be deposited using any deposition process, such as chemical vapor deposition (CVD), and may be defined using an etch-back process.

[0070] 1 also illustrates the formation of an interlevel dielectric layer 40 and the formation of contact 25 (also called a top contact or upper contact). Interlevel dielectric layer 40 may be formed using a material such as SiO2, Si3N4, SiO x Silicon-containing materials such as Ny, SiC, SiCO, SiCOH, and SiCH compounds, the above silicon-containing materials in which some or all of the Si has been replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, polyamides, or SiLK TMThe interlevel dielectric layer 40 may be composed of a dielectric composition that may be selected from the group consisting of organic polymers such as SiO2, other carbon-containing materials, organic-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as hydrogenated amorphous carbon (α-C:H). The interlevel dielectric layer 40 may be deposited using any deposition process, such as chemical vapor deposition (CVD).

[0071] 1 also illustrates the formation of trenches for contacts 25 to second electrode 20 and extensions 21 of switching layer 15, which are horizontally offset by H1 from first electrode 10 present in trench 5. The trenches for contacts 25 may be etched into top inter-level dielectric layer 40 by forming a photoresist mask on top inter-level dielectric layer 40 using deposition and photolithography processes to form an etch mask having the shape of the trenches for contacts 25. After the photoresist mask is formed, the exposed portions of top inter-level dielectric layer 40 may be etched using an etching process such as an anisotropic etching process, e.g., reactive ion etching (RIE), to expose the top surface of second electrode 20 and provide openings for contacts 25.

[0072] The trench opening may then be filled with a metal for contact 25. For example, the contact metal may be copper (Cu). A copper seed layer followed by a copper fill may be deposited. The copper fill may be formed using a plating process, such as electroplating or electroless plating. In some embodiments, the trench may be overfilled with the copper fill for contact 25. The portion of the copper fill that overfills the trench may be removed using a planarization process. The planarization method may be provided by chemical mechanical planarization (CMP). Contact 25 may be tungsten or aluminum with an appropriate liner metal layer.

[0073] 9-12 illustrate several process steps for providing the memory device shown in FIG. 2. FIG. 9 illustrates an initial structure for forming the memory device 100 shown in FIG. 2. The initial structure includes trenches 5 that extend through an interlevel dielectric layer 9 and expose surfaces of electrical communication structures 3 that reside in a separate layer, e.g., dielectric material 4. Dielectric layer 9 may include a diffusion barrier layer 8. Note that elements having reference numbers shown in FIG. 9 are each described in previous embodiments above with reference to FIGS. 1-8, where elements having the same reference numbers may share the same description.

[0074] 10 illustrates the formation of a first electrode 10 at the base of the trench shown in FIG. 9. The first electrode 10 is formed using selective area deposition. Area-selective deposition, sometimes referred to as area-selective atomic layer deposition (ALD), may be employed so that the conductive material for the first electrode 10, e.g., a metal and / or a metal nitride such as tantalum nitride (TaN) or titanium nitride (TiN), is deposited only at the base of the trench 5; i.e., the material for the first electrode 10 does not extend upward along the sidewalls S1 of the trench 15.

[0075] Figure 11 illustrates the formation of material layers for the switching layer 15 and second electrode 20 on the first electrode 10 shown in Figure 10. Note that each of the elements having reference numbers shown in Figure 11 have been described in the previous embodiments discussed above with reference to Figures 1-8, where elements having the same reference numbers may share the same description. One difference between the embodiments shown in Figures 1-8 and the embodiment shown in Figure 11 is that in the embodiment shown in Figure 11, the switching layer 15 is formed in direct contact with the sidewall S1 of the trench 5.

[0076] Figure 12 illustrates one embodiment for patterning the second electrode 20 and the switching layer 15. The method steps illustrated in Figure 12 were described above with reference to Figure 8. Additionally, processing of the structure illustrated in Figure 12 to the structure illustrated in Figure 2 was also described above in the discussion of Figures 8 and 1. It should be noted that the embodiment illustrated in Figures 2 and 9-12 does not show some elements that were described in Figures 1-8. However, for purposes of simplicity and conciseness, some elements may be omitted in Figures 2 and 9-12, so that these elements may be present even though they are not shown.

[0077] Having described preferred embodiments of top contacts on resistive random access memories (intended as examples and not limitations), it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined in the appended claims. Thus, having described aspects of the invention with the detail and particularity required by the patent laws, what is claimed and what is desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. a trench into the first conductive structure; a first electrode of conformal conductive material contained within the trench in electrical communication with the first conductive structure and residing on a sidewall of the trench; a switching layer within the trench over the first electrode and extending outside the trench; a second electrode overlying the switching layer while overfilling the trench; and the contact is positioned over a portion of the second electrode that overfills the trench such that the contact is horizontally offset from the first electrode that resides in the trench. A memory device comprising:

2. The memory device of claim 1 , wherein the memory device is a resistive random access memory (ReRAM).

3. The memory device of claim 1 , wherein the first electrode has a U-shaped configuration when viewed from a side cross section.

4. The memory device of claim 1 , wherein a top surface of the first electrode on the sidewall of the trench is coplanar with the top surface of the trench.

5. The switching layer is made of hafnium oxide (HfO ２ ), tantalum oxide (Ta ２ O ５ ), titanium oxide (TiO ２ ), tungsten oxide (WO ３ ), zirconium oxide (ZrO ２ ), aluminum oxide (Al ２ O ３ ), strontium titanium oxide (SrTiO ３ 10. The memory device of claim 1, having a composition selected from the group consisting of:

6. 2. The memory device of claim 1, wherein a portion of the switching layer extends outside the trench and a portion of the second electrode overfilling the trench provides an extended portion of the switching layer and second electrode for a landing point for the contact.

7. a trench into the first conductive structure; a first electrode of conductive material at the base of the trench in electrical communication with the first conductive structure; a switching layer of conformal material present in the trench over the first electrode, the switching layer present on sidewalls of the trench, and the switching layer extending outside the trench; a second electrode overlying the switching layer while overfilling the trench; and the contact is positioned over a portion of the second electrode that overfills the trench such that the contact is horizontally offset from the first electrode that resides in the trench. A memory device comprising:

8. The memory device of claim 7 , wherein the memory device is a resistive random access memory (ReRAM).

9. The memory device of claim 7 , wherein no portion of the first electrode extends beyond a first quarter of the height of the trench.

10. The memory device of claim 7 , wherein the switching layer is in direct contact with the sidewalls of the trench.

11. The switching layer is made of hafnium oxide (HfO ２ ), tantalum oxide (Ta ２ O ５ ), titanium oxide (TiO ２ ), tungsten oxide (WO ３ ), zirconium oxide (ZrO ２ ), aluminum oxide (Al ２ O ３ ), strontium titanium oxide (SrTiO ３ 8. The memory device of claim 7, having a composition selected from the group consisting of: ), and combinations thereof.

12. 8. The memory device of claim 7, wherein a portion of the switching layer extends outside the trench and a portion of the second electrode overfilling the trench provides an extended portion of the switching layer and second electrode for a landing point for the contact.

13. forming a trench into a conductive structure present at the base of the trench; forming a first electrode in the trench; filling the trench with a filler material including a bilayer consisting of a switching layer overlying the first electrode and a layer for a second electrode overlying the switching layer, wherein a portion of the bilayer extends outside the trench; patterning a portion of the bilayer extending outside the trench to provide a landing spot that is horizontally offset from the first electrode within the trench; and forming a contact to the landing spot 1. A method of forming a memory device comprising:

14. 14. The method of claim 13, wherein the first electrode is comprised of a conformal conductive material contained within the trench in electrical communication with the first conductive structure and present on sidewalls of the trench.

15. The method of claim 14 , wherein the first electrode has a U-shaped configuration when viewed from a side cross section.

16. 16. The method of claim 15, wherein said forming said first electrode comprises depositing tantalum nitride by chemical vapor deposition.

17. 16. The method of claim 15, wherein said forming said first electrode comprises depositing titanium nitride by physical vapor deposition.

18. 14. The method of claim 13, wherein the first electrode is comprised of a conductive material present at the base of the trench in electrical communication with the first conductive structure.

19. 20. The method of claim 18, wherein no portion of the first electrode extends beyond the first quarter of the height of the trench.

20. 20. The method of claim 18, wherein the first electrode is formed using area-selective deposition.

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