Complementary field-effect transistor(CFET) with balanced N and P drive currents.

Abstract

Complementary field effect transistors (CFETs) with balanced n- and p-drive currents and methods for fabricating the same are disclosed. In one embodiment, the CFET structure includes an nFET having horizontal p-doped nanosheet channels arranged in a first vertical stack, each horizontal p-doped nanosheet channel having a width W1 and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L1. The CFET structure further includes a pFET having horizontal n-doped nanosheet channels arranged in a second vertical stack arranged on the first vertical stack, each horizontal n-doped nanosheet channel having a width W2 and connecting a second source contact to a second drain contact through a second GAA region having a length L2, where W2 / L2 is not equal to W1 / L1.

Description

[Technical Field]

[0001] 1. Field of Disclosure Aspects of the present disclosure relate generally to high performance devices, and more particularly to complementary field effect transistors (CFETs).

[0002] 2. Description of Related Technology Integrated circuit technology has achieved great advances in increasing computing power by miniaturizing components such as semiconductor transistors. Semiconductor advances have progressed from bulk substrate and planar CMOS, FinFETs, nanowires or nanoribbons (also called nanosheets), and FinFET 3D stacks to nanowire or nanoribbon 3D stacks. Semiconductor technology is primarily based on silicon. However, fabrication of silicon-based transistors can be problematic with further scaling, for example, down to a few nanometers. Therefore, there is a need for systems, apparatus, and methods that overcome the shortcomings of conventional devices, including the methods, systems, and apparatus provided herein. Summary of the Invention

[0003] The following presents a simplified summary of one or more aspects disclosed herein. As such, the following summary is not intended to be an extensive overview of all contemplated aspects, nor is it intended to identify key or critical elements of all contemplated aspects or to delineate the scope of any particular aspect. Thus, the sole purpose of the following summary is to present certain concepts of one or more aspects of the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

[0004] In one embodiment, a complementary field effect transistor (CFET) structure includes an n-channel field effect transistor (nFET) having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance D1, each horizontal p-doped nanosheet channel having a first width W1 and a first length L1, and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region connected to a first gate contact; and a p-channel field effect transistor (pFET) having a plurality of horizontal n-doped nanosheet channels arranged in parallel in a second vertical stack and separated from one another by a second vertical distance D2. and a pFET (transistor, pFET), wherein each horizontal n-doped nanosheet channel has a second width W2 and a second length L2 and connects a second source contact to a second drain contact through a second GAA region connected to a second gate contact, wherein the first vertical stack is disposed on the second vertical stack, and W2 / L2 is not equal to W1 / L1. In some embodiments, the ratio of (W2 / L2) to (W1 / L1) is selected such that the saturation current of the nFET is approximately equal to the saturation current of the pFET.

[0005] In one embodiment, a method for fabricating a CFET structure includes forming an nFET having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance D1, where each horizontal p-doped nanosheet channel has a first width W1 and a first length L1 and connects a first source contact to a first drain contact through a first GAA region connected to a first gate contact. The method also includes forming a pFET having a plurality of horizontal n-doped nanosheet channels arranged in parallel in a second vertical stack and separated from one another by a second vertical distance D2, where each horizontal n-doped nanosheet channel has a second width W2 and a second length L2 and connects a second source contact to a second drain contact through a second GAA region connected to a second gate contact. The first vertical stack is disposed on the second vertical stack, and W2 / L2 is not equal to W1 / L1. In some embodiments, the ratio of (W2 / L2) to (W1 / L1) is selected so that the saturation current of the nFET is approximately equal to the saturation current of the pFET.

[0006] Other objects and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description.

[0007] The accompanying drawings are presented to aid in the description of various aspects of the present disclosure and are provided only to illustrate, not limit, the aspects. [Brief explanation of the drawings]

[0008] [Figure 1] A nanosheet field effect transistor (FET) is shown. [Figure 2A] FIG. 1 is a cross-sectional view of a conventional monolithic complementary FET (CFET) comprising a pair of vertically stacked nanosheet FETs. [Figure 2B] FIG. 1 is a cross-sectional view of an exemplary wafer on which a CFET can be fabricated. [Figure 2C] 1 is a cross-sectional view of a wafer after vertical channels have been etched through the layers to leave columns of layers. [Figure 3A] 1A-1C show several diagrams of a CFET with balanced N and P drive currents, according to an embodiment of the present disclosure. [Figure 3B] 10A-10C show several diagrams of another CFET with balanced N and P drive currents according to an embodiment of the present disclosure. [Figure 4A] 1 illustrates process steps for fabricating the nFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 4B] 1 illustrates process steps for fabricating the nFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 4C] 1 illustrates process steps for fabricating the nFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 4D] 1 illustrates process steps for fabricating the nFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 4E] 1 illustrates process steps for fabricating the nFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 4F] 1 illustrates process steps for fabricating the nFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 5A] 1 illustrates process steps for fabricating the pFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 5B] 1 illustrates process steps for fabricating the pFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 5C] 1 illustrates process steps for fabricating the pFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 5D] 1 illustrates process steps for fabricating the pFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 5E] 1 illustrates process steps for fabricating the pFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 5F] 1 illustrates process steps for fabricating the pFET portion of a CFET device according to an embodiment of the present disclosure. [Figure 6] 1 is a flowchart of an exemplary process for fabricating a CFET with balanced N and P drive currents, according to an embodiment of the present disclosure. [Figure 7] 1 illustrates various electronic devices that may utilize one or more aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Complementary field effect transistors (CFETs) with balanced n- and p-drive currents and methods for fabricating the same are disclosed. In one embodiment, the CFET structure includes an nFET having horizontal p-doped nanosheet channels arranged in a first vertical stack, each of which has a width W1 and connects a first source contact to a first drain contact through a first gate-all-around (GAA) region having a length L1. The CFET structure further includes a pFET having horizontal n-doped nanosheet channels arranged in a second vertical stack disposed below the first vertical stack, each of which has a width W2 and connects a second source contact to a second drain contact through a second GAA region having a length L2. W2 / L2 is not equal to W1 / L1. In some embodiments, the ratio of (W2 / L2) to (W1 / L1) is selected so that the saturation current of the nFET is approximately equal to the saturation current of the pFET. In this description, the terms "drive current" and "saturation current" are treated as synonyms.

[0010] Aspects of the present disclosure are provided in the following description and related drawings, directed to various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of the present disclosure. Additionally, well-known elements of the present disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of the present disclosure.

[0011] The words "exemplary" and / or "example" are used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" and / or "example" is not necessarily to be construed as preferred or advantageous over other aspects. Likewise, the term "aspects of the present disclosure" does not require that all aspects of the present disclosure include the discussed feature, advantage or mode of operation.

[0012] Those skilled in the art will understand that the information and signals described below may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the following description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof, depending in part on the particular application, desired design, corresponding technology, etc.

[0013] Further, many aspects are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be appreciated that various actions described herein can be performed by specific circuitry (e.g., application specific integrated circuits (ASICs)), by program instructions executed by one or more processors, or by a combination of both. In addition, the sequence(s) of actions described herein may be considered to be embodied entirely in any form of non-transitory computer-readable storage medium storing a corresponding set of computer instructions, which, when executed, cause or instruct the associated processor(s) of a device to perform the functionality described herein. Accordingly, various aspects of the present disclosure may be embodied in several different forms, all of which are contemplated to be within the scope of the claimed subject matter. Additionally, for each aspect described herein, the corresponding form of any such aspect may be described herein as, for example, “logic configured to” perform the described actions.

[0014] Figure 1 shows a nanosheet field-effect transistor (FET) 100. The nanosheet FET 100 shown in Figure 1 is constructed on a silicon substrate 102 and includes a set of three nanosheets 104 extending through a gate-all-around-gate (GAA) structure 106. One end of the three nanosheets 104 is electrically connected together to form the FET source (S), and the other ends of the three nanosheets 104 are electrically connected together to form the FET drain (D). The gate structure is separated from the substrate 102 by an oxide channel 108.

[0015] FIG. 2A is a cross-sectional view of a conventional monolithic complementary FET (CFET) 200 including a pair of vertically stacked nanosheet FETs. FIG. 2A shows a cross-section of the gate structure, where current flows into or out of the page depending on the charge carriers. In the example shown in FIG. 2A, CFET 200 includes a nanosheet p-channel FET structure (pFET) 202 and a nanosheet n-channel FET structure (nFET) 204 separated by an insulating layer 206. pFET 202 includes three n-doped nanosheets 208 separated by a dummy layer 210. nFET 204 includes three p-doped nanosheets 212 separated by a dummy layer 210. Gate structure 214 surrounds both pFET 202 and nFET 204.

[0016] 2B is a cross-sectional view of a wafer 216 on which CFET 200 can be fabricated. Wafer 216 includes layers on which insulating layer 206, p-doped nanosheets 208, dummy layer 210, and n-doped nanosheets 212 are fabricated. In the exemplary wafer 216 shown in FIG. 2B, the stack of layers 206, 208, 210, and 212 is located on an oxide layer 218, which is located on a substrate 220.

[0017] 2C is a cross-sectional view of wafer 216 after vertically aligned channels have been etched through the layers to leave columns of layers. A CFET 200, such as that shown in FIG. 2A, can be constructed by surrounding one of these columns with gate material 214.

[0018] Unlike finFETs, which have vertically aligned channels, the nanosheet FET 100 and CFET 200 have horizontally aligned channels stacked vertically on top of each other. <110> The finFET has a (110) surface orientation, whereas the nanosheet FET has a (100) or (110) surface orientation for the larger top surface and a (100) or (110) surface orientation for the smaller side surface. <110> The nanosheet FET has a surface orientation of 100. As a result, the electron mobility of the (100) nanosheet FET is approximately 2.4 times greater than that of the finFET, and the hole mobility of the nanosheet FET is approximately 0.33 times less than that of the finFET. For the CFET 200 in particular, this leads to an imbalance between the drive current of the pFET 202 and the drive current of the nFET 204. For example, in some processes, the drive current of the nFET 204 is approximately 4.4 times greater than that of the pFET 202 of the same size. This drive current imbalance tends to worsen with the aging effects of CFET bias temperature instability (BTI). Therefore, a CFET with balanced N and P drive currents is needed.

[0019] Thus, a CFET with balanced drive current, as well as a method for fabricating the same, is presented herein.

[0020] FIG. 3A shows several views of a CFET 300 with balanced N and P drive currents according to an embodiment of the present disclosure. FIG. 3A includes a top view of a CFET 300 having a nanosheet n-channel FET (nFET) 302 stacked on a nanosheet p-channel FET (pFET) 303. In the example shown in FIG. 3A, the nFET 302 includes a pair of vertically stacked p-doped nanosheets 304, a portion of which is surrounded by a gate 306. One end of the nanosheet 304 includes a source 308, and the other end of the nanosheet 304 includes a drain 310. The nFET 302 includes a source contact 312, a gate contact 314, and a drain contact 316. In the example shown in FIG. 3A, the pFET 303 includes a pair of vertically stacked n-doped nanosheets 318, a portion of which is surrounded by a second gate 320. One end of n-doped nanosheet 318 includes a second source 322, and the other end of n-doped nanosheet 318 includes a second drain 324. pFET 303 includes a second source contact 326, a second gate contact 328, and a second drain contact 330.

[0021] As shown in FIG. 3A, the respective widths and lengths of the channels of nFET 302 and pFET 303 are selected to balance the drive current of nFET 302 and the drive current of pFET 303. In the example shown in FIG. 3A, nFET 302 has a channel with a first length L1 and a first width W1, and pFET 303 has a channel with a second length L2 and a second width W2. For example, the drive current of a FET is proportional to the carrier mobility multiplied by the ratio of its gate width to its gate length. Thus, using the example above, where the drive current of nFET 302 is 4.4 times greater than the drive current of an equivalent-sized pFET 303, this imbalance can be compensated for by adjusting the ratio of gate width to gate length of pFET 303 so that it is 4.4 times greater than the ratio of gate width to gate length of nFET 302. 3A, this means that W1, L1, W2, and L2 should be selected such that W2 / L2 = 4.4 * (W1 / L1), or an approximation thereof. It will be understood that for other processes, feature sizes, and / or operating conditions, the ratio of nFET drive current to pFET drive current for FETs of the same size may be other than 4.4, in which case the ratio of (W2 / L2) to (W1 / L1) should be adjusted accordingly to compensate. For example, if the nFET saturation current of an nFET is 3.7 times greater than the saturation current of a similarly sized pFET, then the dimensions W1, L1, W2, and L2 should be selected such that (W2 / L2) is 3.7 times greater than (W1 / L1), such that the magnitude of the nFET drive current is approximately the same as the magnitude of the pFET drive current in CFET 300.

[0022] 3B shows several views of another CFET 332 having balanced N and P drive currents according to embodiments of the present disclosure. Elements in FIG. 3B are equivalent to those similarly numbered elements in FIG. 3A, and therefore their descriptions will not be repeated here. However, while FIG. 3A shows a CFET 300 in which the nFET 302 is vertically centered above the pFET 303, FIG. 3B shows a layout variation in which the pFET 303 is offset in the X and / or Y directions relative to the nFET 302 so that the second source contact 326, the second gate contact 328, and / or the second drain contact 330 can be located on the same side of the device as the source contact 312, the gate contact 314, and the drain contact 316.

[0023] 4A-4F illustrate process steps for fabricating an nFET portion of a CFET device according to an embodiment of the present disclosure, and FIGURES 5A-5F illustrate process steps for fabricating a pFET portion of a CFET device according to an embodiment of the present disclosure, each of which illustrates a pair of cross-sectional views taken along the Y-axis (left) and the X-axis (right).

[0024] FIG. 4A shows layers of a multi-layer epitaxial wafer 400 including a silicon substrate 402, an oxide layer 404, a SiGe layer 406, a p-doped layer 408 (e.g., Si, Ge, SiGe), a high Ge dose SiGe layer 410, and an n-doped layer 412 (e.g., Si, Ge, SiGe).

[0025] 4B shows wafer 400 after upper device slab patterning (e.g., photolithography, etching, etc.), which leaves a stack of alternating n-doped layers 412 and SiGe layers 406 having a first width W1 and a first length L1.

[0026] FIG. 4C shows wafer 400 after depositing and patterning a dummy polysilicon (“poly”) layer 414, depositing and patterning a SiN layer 416, and replacing a portion of high Ge-dose SiGe layer 410 with oxide 418.

[0027] FIG. 4D shows wafer 400 after replacing the remainder of high Ge dose SiGe layer 410 with oxide 418, recessing SiGe layer 406, depositing SiN in the recess, etch-back to form inner spacers, and depositing source and drain epitaxial layers 420.

[0028] FIG. 4E shows wafer 400 after depositing field inter-layer-dielectric (F-ILD) oxide 422, performing a chemical-mechanical polishing (CMP) step, then replacing dummy poly layer 414 with a high-k and metal gate 424, and performing another CMP step.

[0029] FIG. 4F shows wafer 400 after depositing a second F-ILD oxide 426 to form gate contact 428, source contact 430, and drain contact 432, followed by depositing a field inter-metal-dielectric (F-IMD) oxide 434 and forming a first metal layer structure, such as gate metal contact 436, source metal contact 438, and drain metal contact 440.

[0030] FIG. 5A shows wafer 400 after it has been inverted and attached to a carrier wafer (not shown).

[0031] 5B shows wafer 400 after removal of silicon substrate 402 and oxide layer 404 and lower device slab patterning, leaving a stack of alternating p-doped layers 408 and SiGe layers 406 having a second width W2 and a second length L2.

[0032] FIG. 5C shows wafer 400 after a second dummy poly layer 442 has been deposited and patterned, and a second SiN layer 444 has been deposited and patterned.

[0033] FIG. 5D shows wafer 400 after recessing SiGe layer 406, depositing SiN in the recess, and etching back to form inner spacers, and depositing source and drain epitaxial layers 446.

[0034] FIG. 5E shows the wafer 400 after depositing a third F-ILD oxide 448, performing a chemical-mechanical polishing (CMP) step, then replacing the second dummy poly layer 442 with a second high-k and metal gate 450 and performing another CMP step.

[0035] FIG. 5F shows the wafer 400 after depositing a fourth F-ILD oxide 452 and forming a second gate contact 454, a second source contact 456, and a second drain contact 458, followed by depositing a second field inter-metal dielectric (F-IMD) oxide 460 and forming a first metal layer structure, such as a second gate metal contact 462, a second source metal contact 464, and a second drain metal contact 466.

[0036] The wafer 400 is then removed from the carrier wafer to complete the process. The resulting CFET device has an nFET with parallel channels of width W1 and length L1, and a pFET with parallel channels of width W2 and length L2.

[0037] While the processes illustrated in FIGS. 4A-4F and 5A-5F illustrate processes that result in CFET devices such as, for example, CFET 300, with the nFET and pFET vertically centered and with contacts for the nFET and contacts for the pFET on opposite sides of the device, it will be understood that the same construction principles can be used to create CFET devices such as CFET 332, for example, with the nFET and pFET offset from each other in the X and / or Y plane, with at least some of the contacts for the nFET device on the same side as the contacts for the pFET device, or vice versa.

[0038] FIG. 6 is a flowchart of an exemplary process 600 for fabricating a CFET with balanced N and P drive currents according to an embodiment of the present disclosure.

[0039] 6, the process 600 may include, at block 602, forming an nFET having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance D1. Each horizontal p-doped nanosheet channel has a first width W1 and connects a first source contact to a first drain contact through a first GAA region having a first length L1. The first GAA region is connected to a first gate contact.

[0040] 6, the process 600 may include, at block 604, forming a pFET having a plurality of horizontal n-doped nanosheet channels arranged in parallel in a second vertical stack and separated from one another by a second vertical distance D2. Each horizontal n-doped nanosheet channel has a second width W2 and connects a second source contact to a second drain contact through a second GAA region having a second length L2. The second GAA region is connected to a second gate contact. The first vertical stack is disposed on the second vertical stack, and W2 / L2 is not equal to W1 / L1.

[0041] In some embodiments, the first vertical stack is formed horizontally about a first vertical axis and the second vertical stack is formed horizontally about a second vertical axis different from the first vertical axis, or the first vertical stack and the second vertical stack are formed horizontally about a common shared vertical axis.

[0042] In some embodiments, a first source contact, a first gate contact, and a first drain contact are formed on a first surface of the CFET structure, and a second source contact, a second gate contact, and a second drain contact are formed on a second surface of the CFET structure opposite the first surface of the CFET structure.

[0043] In some embodiments, the first source contact, the first gate contact, the first drain contact, and at least one of the second source contact, the second gate contact, and the second drain contact are formed on a first surface of the CFET structure.

[0044] In some embodiments, at least one of the plurality of horizontal p-doped nanosheet channels and the plurality of horizontal n-doped nanosheet channels comprises Si, Ge, or SiGe.

[0045] In some embodiments, the first GAA region, the second GAA region, or both are formed to include a high-k dielectric or a metal gate.

[0046] In some embodiments, each of the plurality of horizontal p-doped nanosheet channels is separated from a first GAA region by an insulating layer formed between the p-doped nanosheet channel and the first GAA region. In some embodiments, each of the plurality of horizontal n-doped nanosheet channels is separated from a second GAA region by an insulating layer formed between the n-doped nanosheet channel and the second GAA region. In some embodiments, the first GAA region is formed in direct contact with the second GAA region.

[0047] Process 600 may include additional implementations, such as any single implementation or any combination of implementations described below and / or with respect to one or more other processes described elsewhere herein. While Figure 6 illustrates example blocks of process 600, in some implementations, process 600 may include additional, fewer, different, or differently configured blocks than those shown in Figure 6. Additionally or alternatively, two or more of the blocks of process 600 may be performed in parallel.

[0048] It will be understood that the foregoing manufacturing process and related discussion are provided merely as general illustrations of some of the aspects of the present disclosure and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details of the manufacturing process known to those skilled in the art may be omitted or combined in summary process sections to facilitate understanding of the various aspects disclosed without detailed description of each and every detail and / or every possible process variation. Furthermore, it will be understood that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of inductors, metallization structures may have more or fewer conductive and insulating layers, cavity orientation, size, whether formed of multiple cavities, whether closed or open, and other aspects may have variations driven by specific application design features such as the number of antennas, antenna type, frequency range, power, etc. Therefore, the foregoing illustrative examples and associated figures should not be construed as limiting the various aspects disclosed and claimed herein.

[0049] 7 illustrates various electronic devices 700 that may be integrated with any of the aforementioned devices according to various aspects of the present disclosure. For example, a mobile phone device 702, a laptop computer device 704, and a fixed location terminal device 706 may each be generally considered user equipment (UE) and may include one or more CFET structures (e.g., 300, 302) as described herein. The devices 702, 704, 706 illustrated in FIG. 7 are merely exemplary. Other electronic devices may also include RF filters, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), Internet of things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0050] The devices and functions disclosed above may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a manufacturer that produces devices based on such files. The resulting product may include a semiconductor wafer that is later cut into semiconductor dies and packaged with an antenna on a glass device. The antenna on the glass device may then be used in the devices described herein.

[0051] In the above detailed description, it can be seen that different features are grouped together in the examples. This manner of disclosure should not be understood as an intention that the exemplary clauses have more features than are expressly stated in each clause. Rather, various aspects of the present disclosure may include fewer than all features of each disclosed exemplary clause. Accordingly, the following clauses should be considered incorporated into the description, and each clause may stand alone as a separate example. Although each dependent clause may refer to a specific combination with one of the other clauses within that clause, the aspect(s) of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of the aspect(s) of the dependent clause with the subject matter of any other dependent clause or independent clause, or any combination of features with other dependent clauses and independent clauses. The various aspects disclosed herein expressly include specific combinations (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor) unless these combinations are expressly expressed or can be readily inferred to be unintended. It is further contemplated that aspects of a clause may be included in any other independent clause, even if the clause is not directly dependent on the independent clause.

[0052] Example implementations are described in the following numbered clauses.

[0053] Clause 1. An n-channel field effect transistor (nFET) having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance (D1), each horizontal p-doped nanosheet channel having a first width (W1) and a first length (L1), and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region connected to a first gate contact; and a second nFET arranged in parallel in a second vertical stack and separated from one another by a second vertical distance (D1). a p-channel field effect transistor (pFET) having a plurality of horizontal n-doped nanosheet channels separated from each other by a distance (D2), each horizontal n-doped nanosheet channel having a second width (W2) and a second length (L2), and connecting a second source contact to a second drain contact through a second GAA region connected to a second gate contact; and a complementary field effect transistor (CFET) structure, wherein a first vertical stack is disposed on a second vertical stack, and W2 / L2 is not equal to W1 / L1.

[0054] Clause 2. The CFET structure of clause 1, wherein the magnitude of the saturation current of the nFET is approximately equal to the magnitude of the saturation current of the pFET.

[0055] Clause 3. The CFET structure of clause 1 or 2, wherein the ratio of (W2 / L2) to (W1 / L1) is 4.4 or less.

[0056] Clause 4. The CFET structure of any one of clauses 1 to 3, wherein the first vertical stack is horizontally disposed about a first vertical axis and the second vertical stack is horizontally disposed about a second vertical axis different from the first vertical axis, or the first vertical stack and the second vertical stack are horizontally disposed about a common shared vertical axis.

[0057] Clause 5. The CFET structure of any one of clauses 1 to 4, wherein a first source contact, a first gate contact, and a first drain contact are disposed on a first surface of the CFET structure, and a second source contact, a second gate contact, and a second drain contact are disposed on a second surface of the CFET structure opposite the first surface of the CFET structure.

[0058] Clause 6. The CFET structure of any one of clauses 1 to 4, wherein the first source contact, the first gate contact, the first drain contact, and at least one of the second source contact, the second gate contact, and the second drain contact are disposed on a first surface of the CFET structure.

[0059] Clause 7. The CFET structure of any one of clauses 1 to 6, wherein at least one of the plurality of horizontal p-doped nanosheet channels and the plurality of horizontal n-doped nanosheet channels comprises Si, Ge, or SiGe.

[0060] Clause 8. The CFET structure of any one of clauses 1 to 7, wherein each of the plurality of horizontal p-doped nanosheet channels is separated from the first GAA region by an insulating layer disposed between the plurality of horizontal p-doped nanosheet channels and the first GAA region.

[0061] Clause 9. The CFET structure of any one of clauses 1 to 8, wherein each of the plurality of horizontal n-doped nanosheet channels is separated from the second GAA region by an insulating layer disposed between the plurality of horizontal n-doped nanosheet channels and the second GAA region.

[0062] Clause 10. The CFET structure of any one of clauses 1 to 9, wherein the first GAA region is in direct contact with the second GAA region.

[0063] Clause 11. A method of fabricating a complementary field effect transistor (CFET) structure, comprising forming an n-channel field effect transistor (nFET) having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance (D1), each horizontal p-doped nanosheet channel having a first width (W1) and a first length (L1), and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region connected to a first gate contact; forming a p-channel field effect transistor (pFET) having a plurality of horizontal n-doped nanosheet channels arranged in parallel in two vertical stacks and separated from each other by a second vertical distance (D2), each horizontal n-doped nanosheet channel having a second width (W2) and a second length (L2), and connecting a second source contact to a second drain contact through a second GAA region connected to a second gate contact, wherein the first vertical stack is disposed on the second vertical stack, and W2 / L2 is not equal to W1 / L1.

[0064] Clause 12. The method of clause 11, wherein the magnitude of the saturation current of the nFET is approximately equal to the magnitude of the saturation current of the pFET.

[0065] Clause 13. The method according to clause 11 or 12, wherein the ratio of (W2 / L2) to (W1 / L1) is 4.4 or less.

[0066] Clause 14. A method according to any one of clauses 11 to 13, wherein the first vertical stack is formed horizontally around a first vertical axis and the second vertical stack is formed horizontally around a second vertical axis different from the first vertical axis, or the first vertical stack and the second vertical stack are formed horizontally around a common shared vertical axis.

[0067] Clause 15. The method of any one of clauses 11 to 14, wherein a first source contact, a first gate contact, and a first drain contact are formed on a first surface of the CFET structure, and a second source contact, a second gate contact, and a second drain contact are formed on a second surface of the CFET structure opposite the first surface of the CFET structure.

[0068] Clause 16. The method of any one of clauses 11 to 14, wherein the first source contact, the first gate contact, the first drain contact, and at least one of the second source contact, the second gate contact, and the second drain contact are formed on a first surface of the CFET structure.

[0069] Clause 17. The method of any one of clauses 11 to 16, wherein at least one of the plurality of horizontal p-doped nanosheet channels and the plurality of horizontal n-doped nanosheet channels comprises Si, Ge, or SiGe.

[0070] Clause 18. The method of any one of clauses 11 to 17, wherein each of the plurality of horizontal p-doped nanosheet channels is separated from the first GAA region by an insulating layer formed between the plurality of horizontal p-doped nanosheet channels and the first GAA region.

[0071] Clause 19. The method of any one of clauses 11 to 18, wherein each of the plurality of horizontal n-doped nanosheet channels is separated from the second GAA region by an insulating layer formed between the plurality of horizontal n-doped nanosheet channels and the second GAA region.

[0072] Clause 20. The method of any one of clauses 11 to 19, wherein the first GAA region is formed in direct contact with the second GAA region.

[0073] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0074] Furthermore, those skilled in the art will understand that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0075] The various illustrative logic blocks, modules, and circuits described in connection with aspects disclosed herein may be implemented or performed using a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0076] The methods, sequences, and / or algorithms described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., UE). Alternatively, the processor and the storage medium may reside as discrete components in the user terminal.

[0077] In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of medium. Disk and disc, as used herein, include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically using a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0078] While the above disclosure illustrates exemplary aspects of the present disclosure, it should be noted that various changes and modifications can be made herein without departing from the scope of the present disclosure, which is defined by the appended claims. The functions, steps, and / or actions of the method claims in accordance with the aspects of the present disclosure described herein need not be performed in any particular order. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. [Explanation of symbols]

[0079] 100 Nanosheet Field Effect Transistor (FET) 102 Circuit Board 104 Nanosheet 106 Structure 108 Oxide Channel 202 Structure (pFET) 204 Structure (nFET) 206 Insulating layer 208 p-doped nanosheets, n-doped nanosheets 210 Dummy Layer 212 p-doped nanosheets, n-doped nanosheets 214 Gate Structure 216 wafers 218 Oxide layer 220 board 304 p-doped nanosheets Gate 306 308 Source 310 Drain 312 Source Contact 314 Gate Contact 316 Drain Contact 318 n-doped nanosheets 320 Second Gate 322 Second Source 324 Second Drain 326 Second Source Contact 328 Second Gate Contact 330 Second drain contact 400 multilayer epitaxial wafer 402 Silicon substrate 404 Oxide layer 406 SiGe layer 408 p-doped layer 410 High Ge dose SiGe layer 412 n-doped layer 414 dummy polysilicon ("poly") layer 416 SiN layer 418 Oxide 420 drain epitaxial layer 424 Metal Gate 426 Second F-ILD oxide 428 Gate Contact 430 Source Contacts 432 Drain Contact 436 Gate Metal Contact 438 Source Metal Contact 440 drain metal contact 442 Second dummy poly layer 444 Second SiN layer 446 Drain epitaxial layer 448 Third F-ILD oxide 450 Metal Gate 452 Fourth F-ILD oxide 454 Second Gate Contact 456 Second Source Contact 458 Second Drain Contact 460 Oxides 462 Second gate metal contact 464 Second Source Metal Contact 466 Second drain metal contact 700 Electronic Devices 702 Mobile Phone Devices 704 Laptop Computer Devices 706 Fixed Location Terminal Device

Claims

1. an n-channel field effect transistor (nFET) having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance (D1), each horizontal p-doped nanosheet channel having a first width (W1) and a first length (L1), and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region connected to a first gate contact; a p-channel field effect transistor (pFET) having a plurality of horizontal n-doped nanosheet channels arranged in parallel in a second vertical stack and separated from one another by a second vertical distance (D2), each horizontal n-doped nanosheet channel having a second width (W2) and a second length (L2), and connecting a second source contact to a second drain contact through a second GAA region connected to the second gate contact; Equipped with the first vertical stack is disposed above the second vertical stack, and W2 / L2 is not equal to W1 / L1; Complementary field effect transistor (CFET) structure.

2. 2. The CFET structure of claim 1, wherein the magnitude of the saturation current of said nFET is approximately equal to the magnitude of the saturation current of said pFET.

3. 2. The CFET structure of claim 1, wherein the ratio of (W2 / L2) to (W1 / L1) is less than or equal to 4.

4.

4. the first vertical stack is horizontally arranged about a first vertical axis and the second vertical stack is horizontally arranged about a second vertical axis different from the first vertical axis; or the first vertical stack and the second vertical stack are horizontally arranged about a common shared vertical axis; The CFET structure of claim 1 .

5. 2. The CFET structure of claim 1, wherein the first source contact, the first gate contact, and the first drain contact are disposed on a first surface of the CFET structure, and the second source contact, the second gate contact, and the second drain contact are disposed on a second surface of the CFET structure opposite the first surface of the CFET structure.

6. 2. The CFET structure of claim 1 , wherein at least one of the first source contact, the first gate contact, the first drain contact, and the second source contact, the second gate contact, and the second drain contact are disposed on a first surface of the CFET structure.

7. 10. The CFET structure of claim 1, wherein at least one of the plurality of horizontal p-doped nanosheet channels and the plurality of horizontal n-doped nanosheet channels comprises Si, Ge, or SiGe.

8. 2. The CFET structure of claim 1, wherein each of the plurality of horizontal p-doped nanosheet channels is separated from the first GAA region by an insulating layer disposed between the plurality of horizontal p-doped nanosheet channels and the first GAA region.

9. 2. The CFET structure of claim 1, wherein each of the plurality of horizontal n-doped nanosheet channels is separated from the second GAA region by an insulating layer disposed between the plurality of horizontal n-doped nanosheet channels and the second GAA region.

10. The CFET structure of claim 1 , wherein the first GAA region is in direct contact with the second GAA region.

11. 1. A method for fabricating a complementary field effect transistor (CFET) structure, comprising: forming an n-channel field effect transistor (nFET) having a plurality of horizontal p-doped nanosheet channels arranged in parallel in a first vertical stack and separated from one another by a first vertical distance (D1), each horizontal p-doped nanosheet channel having a first width (W1) and a first length (L1), and connecting a first source contact to a first drain contact through a first gate-all-around (GAA) region connected to a first gate contact; forming a p-channel field effect transistor (pFET) having a plurality of horizontal n-doped nanosheet channels arranged in parallel in a second vertical stack and separated from one another by a second vertical distance (D2), each horizontal n-doped nanosheet channel having a second width (W2) and a second length (L2), and connecting a second source contact to a second drain contact through a second GAA region connected to a second gate contact; Including, the first vertical stack is disposed above the second vertical stack, and W2 / L2 is not equal to W1 / L1; method.

12. 12. The method of claim 11, wherein the magnitude of the saturation current of the nFET is approximately equal to the magnitude of the saturation current of the pFET.

13. 12. The method of claim 11, wherein the ratio of (W2 / L2) to (W1 / L1) is 4.4 or less.

14. the first vertical stack is formed horizontally about a first vertical axis and the second vertical stack is formed horizontally about a second vertical axis different from the first vertical axis; or the first vertical stack and the second vertical stack are horizontally formed about a common shared vertical axis; The method of claim 11.

15. 12. The method of claim 11 , wherein the first source contact, the first gate contact, and the first drain contact are formed on a first surface of the CFET structure, and the second source contact, the second gate contact, and the second drain contact are formed on a second surface of the CFET structure opposite the first surface of the CFET structure.

16. 12. The method of claim 11 , wherein at least one of the first source contact, the first gate contact, the first drain contact, and the second source contact, the second gate contact, and the second drain contact are formed on a first surface of the CFET structure.

17. 12. The method of claim 11, wherein at least one of the plurality of horizontal p-doped nanosheet channels and the plurality of horizontal n-doped nanosheet channels comprises Si, Ge, or SiGe.

18. 12. The method of claim 11 , wherein each of the plurality of horizontal p-doped nanosheet channels is separated from the first GAA region by an insulating layer formed between the plurality of horizontal p-doped nanosheet channels and the first GAA region.

19. 12. The method of claim 11 , wherein each of the plurality of horizontal n-doped nanosheet channels is separated from the second GAA region by an insulating layer formed between the plurality of horizontal n-doped nanosheet channels and the second GAA region.

20. 12. The method of claim 11, wherein the first GAA region is formed in direct contact with the second GAA region.

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