FET microelectronic device with large contact areas between the conducting channel and the source and drain regions - Patent Application 20070122997

Abstract

The FET microelectronic device (100) comprises a semiconductor layer (120) having a first region (122) forming a channel, a plurality of gates (110) disposed on the first region and spaced apart from one another, a gate dielectric layer (112), a dielectric spacer (114) disposed against a sidewall of the gate (110), and the source / drain (118) regions electrically coupled to the first region (122) through a second region (124) of the active layer extending between the source / drain (118) regions and the dielectric spacer (114), wherein the second region (124) forms a continuous layer with the first region (122).

Description

[Technical Field]

[0001] The present invention relates to the field of microelectronic devices applied in advanced CMOS technology. In particular, the present invention relates to FET ("Field Effect Transistor") microelectronic devices, especially RFET ("Reconfigurable Field Effect Transistor") microelectronic devices, especially those based on two-dimensional, or 2D, materials or semiconductor oxides, and to the fabrication of such microelectronic devices. [Background technology]

[0002] While the miniaturization of electronics is constantly progressing, the industry is currently approaching the scaling limits of traditional materials such as silicon. Recently, 2D materials have emerged as promising candidates for use in miniaturized electronic and optoelectronic devices due to their unique properties and the extremely thin layers of these materials, which can consist of a single layer of atoms or molecules.

[0003] Non-Patent Document 1 proposes fabricating a MOSFET transistor by integrating a MoS2 layer to form a conducting channel. This layer is connected to two metallic source and drain regions made of gold, palladium, TiN, tungsten, or nickel. The rear gate is formed by a doped silicon layer placed on the backside under a dielectric layer made of SiO2, HfO2, or Al2O3. [Prior art documents] [Patent documents]

[0004] [Non-Patent Document 1] Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering(KP O'Brien et al., 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp.7.1.1-7.1.4) [Patent Document 2] U.S. Patent Application Publication No. 2022 / 045176

[0005] To overcome the limitations associated with depositing metallic material for source and drain regions onto 2D materials, it is possible to form these regions on the sidewalls of the 2D material layer rather than on the top surface of the 2D material layer. Nevertheless, this configuration of so-called "side contacts" is problematic due to the small contact surface between the 2D material layer and the source and drain regions, which results in a significant contact resistance at the interface between the 2D material layer and the source and drain regions.

[0006] Patent Document 2 discloses several methods for fabricating "gate-last" FET transistors in which silicon portions serve as supports for the deposition of 2D material layers. In addition to drawbacks related to the fact that the fabricated transistors have a "side-contact" channel / source-drain interface, the silicon portions used to deposit the 2D material form potential barriers at the interface with the 2D material, which is undesirable because some charge transport may occur in these silicon portions but not in the 2D material. Summary of the Invention [Problem to be solved by the invention]

[0007] One object of the present invention is to propose a FET type microelectronic device, in particular an RFET type microelectronic device, the structure of which is compatible with various kinds of semiconductor materials, including 2D materials or other semiconductor oxide type materials, and which does not have the drawbacks of the "side contact" configuration. [Means for solving the problem]

[0008] To this end, the invention proposes a FET microelectronic device comprising at least: - Circuit board. - a semiconductor layer including at least one first region that forms an electrical conduction channel of a FET microelectronic device. - a plurality of separate electrostatic control gates spaced apart from one another and disposed over a first region of the semiconductor layer; a gate dielectric layer disposed between each electrostatic control gate and the first region of the semiconductor layer; - a dielectric spacer disposed against a sidewall of each electrostatic control gate; - a source / drain region electrically coupled to a first region of the semiconductor layer by a second region of the semiconductor layer, the second region of the semiconductor layer extending between the source / drain region and a dielectric spacer, wherein the second region of the semiconductor layer is not disposed directly relative to the electrostatic control gate but forms a continuous layer with the first region.

[0009] One embodiment provides a FET microelectronic device comprising at least: - Circuit board - a semiconductor layer including at least one first region that forms an electrically conducting channel of a FET microelectronic device; a plurality of separate electrostatic control gates spaced apart from one another and disposed over a first region of the semiconductor layer; - a gate dielectric layer disposed between each electrostatic control gate and the first region of the semiconductor layer; - a dielectric spacer disposed against the sidewall of each electrostatic control gate; a source / drain region electrically coupled to a first region of the semiconductor layer, the source / drain region having or formed by a second region of the semiconductor layer, the second region of the semiconductor layer extending between the source / drain contact and a dielectric spacer;

[0010] Typically, the second region of the semiconductor layer is not located directly relative to the electrostatic control gate, and advantageously forms a continuous layer with the first region.

[0011] The proposed microelectronic device is based on a FET-type architecture that does not include a "side contact" type interface between the channel and the source / drain regions, thanks to a second region of the semiconductor layer that provides electrical coupling between the channel formed by the first region of the semiconductor layer and the source / drain regions. These second regions of the semiconductor layer, which extend to the sidewalls of the source / drain contacts, or at least a portion of the sidewalls, form a large contact surface with the source / drain contacts, thereby reducing the source / drain contact resistance. Therefore, the current circulating in the channel is not reduced due to these contact resistances, which does not degrade the device's performance.

[0012] Furthermore, in the proposed architecture, the semiconductor layer can be fabricated immediately before fabricating the source / drain contacts or immediately before metal deposition for the source / drain contacts. Therefore, the semiconductor layer, the first region intended to form the conduction channel, is not damaged by the process of fabricating the source / drain contacts. This is particularly advantageous when the semiconductor layer includes 2D materials.

[0013] Furthermore, making such a device does not require preserving a silicon portion for depositing the semiconductor layer intended to form the channel, thereby eliminating the problem of potential barriers at the interface with the semiconductor layer material.

[0014] The semiconductor layer can comprise two-dimensional materials or any other semiconductor material deposited by MOCVD ("metal-organic chemical vapor deposition"), CVD ("chemical vapor deposition") or ALD ("atomic layer deposition"), in which case microelectronic devices can be fabricated with very small dimensions.

[0015] Advantageously, the FET microelectronic device may be: - each source / drain contact is disposed within a cavity having sidewalls formed by at least a dielectric spacer and an insulating dielectric material, or by one of said dielectric spacers and an insulating spacer of an adjacent microelectronic device; The second region of the semiconductor layer covers at least part of the wall of the cavity in which the source / drain contacts are arranged.

[0016] In the above configuration, the contact area between the source / drain contacts and the semiconductor layer is maximized by using the surface of the cavity walls, advantageously the entire surface of the cavity walls, to form contact between the second region of the semiconductor layer and the source / drain contacts, resulting in a very low source / drain region contact resistance and therefore a higher current flowing through the conduction channel of the device.

[0017] The microelectronic device has a plurality of separate electrostatic control gates spaced apart from one another and disposed over a first region of the active layer, and in this configuration, the microelectronic device has a "reconfigurable FET" type architecture.

[0018] The FET microelectronic device may further include at least one dielectric portion surrounded by the first region of the semiconductor layer, or the first region of the semiconductor layer may not surround the dielectric portion.

[0019] Advantageously, the present invention can be used to fabricate CMOS components for 5nm and sub-5nm technology nodes.

[0020] The present invention also provides a method for fabricating a FET microelectronic device, comprising at least the following steps: a) fabricating at least one temporary material portion on a substrate; then b) fabricating on at least the temporary material portion a plurality of separate electrostatic control gates spaced apart from one another and a dielectric spacer disposed against a sidewall of each electrostatic control gate; then c) etching the temporary material portion; then d) fabricating a semiconductor layer including at least one first region configured to function as an electrically conductive channel of the FET microelectronic device, the semiconductor layer being disposed beneath the electrostatic control gate and the dielectric spacer within at least one space formed by the etching of the temporary material portion, the semiconductor layer extending without discontinuity with the first region and covering at least a portion of the sidewall of the dielectric spacer to form a second region not directly disposed against the electrostatic control gate; and then e) fabricating on the substrate source / drain contacts electrically coupled to the first region of the semiconductor layer by the second region of the semiconductor layer, the second region of the semiconductor layer extending between the source / drain contact and the dielectric spacer.

[0021] The method may further comprise, before performing step c), depositing an insulating dielectric material around the dielectric spacers and then etching a cavity in the insulating dielectric material, such that the cavity comprises at least one sidewall formed by one of the dielectric spacers. wherein step d) is performed such that the second region of the semiconductor layer covers at least a portion of the sidewall of the cavity; Step e) above is carried out so that each source / drain contact is located in one of the cavities.

[0022] The fabrication method may further comprise the step of depositing a gate dielectric layer, which is carried out as follows. - between steps a) and b) above, a temporary material portion is carried out, and an electrostatic control gate is then fabricated on the gate dielectric layer; and / or - between steps c) and d) above, a semiconductor layer is then fabricated over the gate dielectric layer, below the electrostatic control gate and the dielectric spacer in at least one space formed by etching of the temporary material portion.

[0023] The present invention also relates to a method for fabricating a FET microelectronic device, comprising at least: a) fabricating at least one temporary material portion on a substrate, then b) fabricating on at least the temporary material portion a plurality of separate temporary gates spaced apart from one another and a dielectric spacer disposed against a sidewall of each temporary gate, then c) depositing an insulating dielectric material around the dielectric spacers, then d) etching the temporary gates and fabricating a plurality of electrostatic control gates in place of the temporary gates, the electrostatic control gates being separate and spaced apart from one another, then e) etching a cavity in the insulating dielectric material, the cavity comprising at least one sidewall formed by one of the dielectric spacers, then f) etching the temporary material portion, then g) fabricating a semiconductor layer including at least one first region configured to function as an electrically conducting channel of a FET microelectronic device, the semiconductor layer being disposed beneath the electrostatic control gate and the dielectric spacer within the at least one space formed by the etching of the temporary material portion, the semiconductor layer extending without discontinuity with the first region and covering at least a portion of the sidewalls of the dielectric spacers and forming a second region not disposed directly against the temporary gates, then h) fabricating source / drain contacts on the substrate, each disposed in one of the cavities and electrically coupled to the first region of the semiconductor layer by a second region of the semiconductor layer, such that the second region of the semiconductor layer extends between the source / drain contacts and the dielectric spacer;

[0024] The method may further comprise the step of depositing a gate dielectric layer, which is carried out as follows. - during step e) above, a process is carried out on the first region of the semiconductor layer, an electrostatic control gate being subsequently fabricated on the gate dielectric layer, and / or - between steps c) and d) above, a step is carried out below the temporary gate and dielectric spacers in at least one space formed by etching of the temporary material portion, and a semiconductor layer is then fabricated over the gate dielectric layer.

[0025] Throughout this document, the terms "above" and "below" are used regardless of the spatial orientation of the element to which they refer. For example, in the feature "on the surface of a first substrate," this surface of the first substrate is not necessarily oriented upward, but can correspond to a surface oriented in any direction. Furthermore, disposing a first element on a second element should be understood to be capable of corresponding to the first element being disposed directly relative to the second element, with no intermediate elements between them, or to corresponding to the first element being disposed on the second element with one or more intermediate elements disposed between them.

[0026] Throughout the document, the term "layer" can refer to a single layer or a stack of multiple layers.

[0027] Throughout the document, the phrase "electrically couple" is used to refer to an electrical connection, which may be direct or indirect (i.e., established through one or more intermediate electrical elements). [Brief explanation of the drawings]

[0028] The invention will be better understood from reading the description of non-limiting exemplary embodiments given by way of example only, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 shows diagrammatically the steps of the method for fabricating a microelectronic device that is the object of the present invention, according to one particular embodiment. [Figure 2] FIG. 2 shows diagrammatically the steps of the method for fabricating a microelectronic device that is the object of the present invention, according to one particular embodiment. [Figure 3]FIG. 3 shows diagrammatically the steps of the method for fabricating a microelectronic device that is the object of the present invention, according to one particular embodiment. [Figure 4] FIG. 4 shows diagrammatically the steps of the method for fabricating a microelectronic device that is the object of the present invention, according to one particular embodiment. [Figure 5] FIG. 5 shows diagrammatically the steps of the method for fabricating a microelectronic device that is the object of the present invention, according to one particular embodiment. [Figure 6] FIG. 6 shows diagrammatically a microelectronic device that is the object of the present invention according to an alternative embodiment.

[0029] Identical, similar or equivalent parts in the different figures described below have the same reference numbers to facilitate switching from one figure to another.

[0030] The various parts shown in the drawings are not necessarily drawn to uniform scale in order to make the drawings easier to read.

[0031] The various possibilities (alternatives and embodiments) are to be understood as not being mutually exclusive and can be combined. DETAILED DESCRIPTION OF THE INVENTION

[0032] A method for fabricating a "reconfigurable FET" type device 100 according to one particular embodiment is described below with reference to FIGS.

[0033] Etching of a semiconductor layer corresponding to the surface layer of, for example, an SOI type substrate 102 is performed to form temporary material portions 160 on the substrate 102 (on the buried dielectric layer 130 in the example described). Alternatively, the substrate 102 may be a bulk substrate.

[0034] A dielectric layer 112 and a plurality of electrostatic control gates 110 are fabricated on the temporary portion 160 and spaced apart from one another (see FIG. 1). In the example described here, the device 100 has two gates: a control gate and a polarity gate.

[0035] The gates 110 fabricated are separate and spaced apart from one another.

[0036] For example, layer 112 may include a high-K dielectric material (having a high dielectric constant) such as HfO2, or may include SiO2 or Al2O3 or any other suitable material or combination of materials.

[0037] For example, the control gate 110 is made by depositing one or more conductive materials on the layer 112, for example a first deposition of a thin TiN layer (thickness equal to 3 nm for example) on top of which a tungsten layer with a thickness equal to 200 nm for example is laminated. Alternatively, the gate 110 can include one or more materials other than TiN or W, for example doped polysilicon or any other metal (Mo, etc.).

[0038] Dielectric spacers 114 are fabricated on the sidewalls of the gate 110. For example, suitable materials for fabricating the dielectric spacers 114 correspond to SiN, SiCO or SiBCN. The thickness of the layer deposited to fabricate the dielectric spacers 114 is, for example, comprised between 5 nm and 15 nm.

[0039] After the spacers 114 are formed, an insulating dielectric material 128, e.g., SiO2, is then deposited and then planarized, stopping on a hard mask (not shown in the drawings) present on the gate 110. The insulating dielectric material 128 is deposited to a large thickness and then planarized until it reaches the hard mask. The hard mask is then removed, for example, by wet etching, e.g., using a dilute H3PO4 solution used at a temperature of 110°C.

[0040] The structure obtained at this stage of the process is shown in FIG. Next, cavities 150 are etched into the insulating dielectric material 128 (see FIG. 3). The cavities 150 include sidewalls formed by the dielectric spacers 114 and the remaining portions of the insulating dielectric material 128. These cavities 150 form spaces for fabricating the source and drain regions of the device 100. Portions of the gate 110, gate dielectric layer 112, and temporary portion 160 that are not covered by the dielectric spacers 114 and that are located at the bottom of the cavities are etched.

[0041] The gate 110, the gate dielectric layer 112, and the remaining portions of the temporary portion 160 covered by the dielectric spacers 114 are etched, and then the semiconductor layer 120 is deposited, such that a first region 122 of the semiconductor layer 120 forms a portion of semiconductor material disposed on the substrate 102, and the gate 110 and the gate dielectric layer 112 are disposed on this first region 122 of the semiconductor layer 120. Furthermore, in the example shown in FIG. 4, the dielectric layer 152 is deposited before the semiconductor layer 120.

[0042] Second regions 124 of the semiconductor layer 120 line the walls of the cavity 150. These second regions 124 form a continuous layer 120 with the first regions 122. These second regions 124 belong to or form the source and drain regions.

[0043] Advantageously, the semiconductor layer 120 comprises at least one 2D semiconductor material, for example a transition metal dichalcogenide such as MoS2, or WSe2, or WS2, or MoTe2. It is also possible that the material of the semiconductor layer 120 corresponds to IGZO, In2O3, IWO, ITO, or an amorphous semiconductor oxide, or any other suitable semiconductor material.

[0044] Source region contacts 116 and drain region contacts 118, also known as source contacts 116 and drain contacts 118, respectively, are fabricated within cavity 150 in the described example by depositing one or more metal materials within cavity 150. A graphene layer can be deposited within cavity 150 before the metal or metals are deposited, and the metal or metals are then deposited on the graphene layer. These source 116 and drain 118 contacts, shown in FIG. 5 , are electrically coupled to first region 122 of semiconductor layer 120 through second region 124 of semiconductor layer 120, which extends between the source 116 / drain 118 contacts and dielectric spacer 114 and also extends to the other wall of the source 116 / drain 118 contacts located within cavity 150. The material of these regions deposited outside cavity 150 is removed by performing a planarization process that stops at insulating dielectric material 128.

[0045] Advantageously, the source 116 and drain 118 contacts each comprise at least one metallic material, such as gold, palladium, TiN, W, or Ni. According to one exemplary embodiment, each source 116 / drain 118 contact comprises a TiN layer with a tungsten portion formed thereon. Different metals can be used to form the contacts 116, 118 to favor low contact resistance, such as S, Bi, Sn, Pd, Ru, Cu, Ni, Ti, TiN, W, or Au. These materials can also be subsequently modified (to improve their properties), for example, by a doping process.

[0046] In the above exemplary embodiment, the semiconductor layer 120 is such that the space previously occupied by the temporary portion 160 is completely filled with the material of the semiconductor layer 120. Alternatively, it is possible that the semiconductor layer 120 does not completely fill the space previously occupied by the temporary portion 160. In this case, after deposition of the semiconductor layer 120, the remaining space is filled with a dielectric material, forming a dielectric portion surrounded by the first region 122 of the semiconductor layer 120. To form this dielectric portion, one or more dielectric layers, for example comprising Al2O3 (or HfO2) and / or SiO2 (or low-k dielectrics, or having a low dielectric constant), are deposited and then isotropically etched to retain only the portions located in the remaining space.

[0047] Alternatively, device 100 can have a different number of gates. Thus, in the example shown in Figure 6, device 100 has three gates: two control gates and one polarity gate.

[0048] In the different examples above, the second region 124 of the semiconductor layer 120 covers all sidewalls and bottom walls of the source 116 and drain 118 contacts, completely covering these contacts, except for the top end portion opposite the bottom wall, which is preferably flush with the mouth of the cavity 150. In general, it is possible for the second region 124 of the semiconductor layer 120 to extend between the source 116 and drain 118 contacts and the dielectric spacer 114 and / or to extend to walls of the source and drain contacts that are different from those disposed relative to the dielectric spacer 114. Furthermore, the walls of the source 116 and drain 118 contacts may be only partially covered by the second region 124 of the semiconductor layer 120.

[0049] In the above first and second exemplary embodiments, the gate dielectric layer 112 and the electrostatic control gate 110 are fabricated on the temporary material portion 160 before the insulating dielectric material 128 is deposited and planarized (the so-called “gate-first” approach).

[0050] Alternatively, using a "gate-last" approach, instead of the gate dielectric layer 112 and electrostatic control gate 110, multiple temporary gates can be fabricated on temporary dielectric portions that are disposed on temporary material portions 160 before the insulating dielectric material 128 is deposited and planarized. The temporary dielectric portions comprise, for example, SiO2, and the temporary gates comprise, for example, polysilicon. These temporary elements are fabricated by depositing the desired material layers, planarizing the polysilicon layer, and etching these layers according to the desired shape of these temporary gates (similar to the shape of the final gates to be fabricated later). Dielectric spacers 114 are then fabricated on the sidewalls of the temporary gates. After the insulating dielectric material 128 is deposited and planarized, the temporary gates and temporary dielectric portions are removed by etching, and then the gate dielectric layer 112 and electrostatic control gate 110 are fabricated in the spaces formed by the etching of the temporary gates and temporary dielectric portions. The device 100 is then completed in a manner similar to that described above by performing the steps described with reference to Figures 3 through 5.

[0051] In the above exemplary embodiment, the gate dielectric layer 112 is fabricated immediately before fabricating the electrostatic control gate 110, regardless of whether a temporary gate is used. Alternatively, the electrostatic control gate 110 can be fabricated without prior fabrication of the gate dielectric layer 112. In this case, the gate dielectric layer 112 may be deposited at least on the walls of the spaces obtained by etching the temporary material portions 160 immediately before depositing the semiconductor layer 120. In this case, the layer 112 covers the different walls on which the material of the semiconductor layer 120 is intended to be deposited, thereby homogenizing the surface and therefore the interface on which the semiconductor layer 120 will subsequently be deposited.

[0052] According to another alternative, layer 112 can be deposited in two different steps: first just before fabricating gate 110 as described above with reference to FIG. 1, and then just before depositing semiconductor layer 120 in the space formed by etching portion 160 and in cavity 150. In this case, the portions of layer 112 located directly above gate 110 will be thicker than other portions of layer 112, since these portions will accumulate the thickness of material deposited during the two deposition steps.

Claims

1. A FET microelectronic device (100) comprising: a substrate (102), a semiconductor layer (120) comprising at least one first region (122) forming an electrical conduction channel of said FET microelectronic device (100); a plurality of separate electrostatic control gates (110) spaced apart from one another and positioned on said first regions (122) of said semiconductor layer (120); a gate dielectric layer (112) arranged between each of said electrostatic control gates (110) and said first region (122) of said semiconductor layer (120); a dielectric spacer (114) placed against the sidewall of each of said electrostatic control gates (110); a source (116) / drain (118) region electrically coupled to the first region (122) of the semiconductor layer (120), the source (116) / drain (118) region comprising or formed by a second region (124) of the semiconductor layer (120), the second region (124) of the semiconductor layer (120) extending between the source (116) / drain (118) contact and the dielectric spacer (114); a FET microelectronic device (100) in which said second region (124) of said semiconductor layer (120) is not arranged directly against said electrostatic control gate (110) but forms a continuous layer with said first region (122).

2. The FET microelectronic device (100) of claim 1, wherein the semiconductor layer (120) comprises a two-dimensional material.

3. each said source (116) / drain (118) contact is disposed in a cavity (150) with sidewalls formed by at least said dielectric spacer (114) and an insulating dielectric material (128) or by one of said dielectric spacers (114) and an insulating spacer of an adjacent microelectronic device; the second region (124) of the semiconductor layer (120) covers at least part of the wall of the cavity (150) in which the source (116) / drain (118) region contacts are located; FET microelectronic device (100) according to claim 1 or 2.

4. further comprising at least one dielectric portion surrounded by the first region (122) of the semiconductor layer (120); 4. A FET microelectronic device (100) according to any one of claims 1 to 3.

5. the second region (124) of the semiconductor layer (120) completely covers the sidewalls and bottom wall of each of the source (116) and drain (118) contacts; FET microelectronic device (100) according to any one of claims 1 to 4

6. A method for fabricating a FET microelectronic device (100), comprising: a) creating at least one temporary material portion (160) on a substrate (102); b) fabricating, on at least said temporary material portion (160), a plurality of separate electrostatic control gates (110) spaced apart from one another, and dielectric spacers (114) disposed against sidewalls of each of said electrostatic control gates (110); c) etching said temporary material portion (160); d) creating a semiconductor layer (120) including at least one first region (122) configured to function as an electrical conduction channel of the FET microelectronic device (100), the semiconductor layer (120) being disposed beneath the electrostatic control gate (110) and the dielectric spacer (114) within at least one space formed by etching of the temporary material portion (160), the semiconductor layer (120) extending without discontinuity with the first region (122) and covering at least a portion of a sidewall of the dielectric spacer (114), forming a second region (124) not disposed directly relative to the electrostatic control gate (110), the second region (124) forming a source / drain (118) region; e) fabricating on the substrate (102) the source (116) and drain (118) contacts electrically coupled to the first region (122) of the semiconductor layer (120) by the second region (124) of the semiconductor layer (120), such that the second region (124) of the semiconductor layer (120) extends between the source (116) / drain (118) contacts and the dielectric spacer (114), wherein the method also includes fabricating a gate dielectric layer disposed between each of the electrostatic control gates (110) and the first region (122) of the semiconductor layer (120); A method for fabricating a FET microelectronic device (100).

7. and before performing step c), further comprising the step of depositing an insulating dielectric material (128) around the dielectric spacers (114) and then etching a cavity (150) in the insulating dielectric material (128) so that the cavity (150) includes at least one sidewall formed by one of the dielectric spacers (114); - step d) is carried out so that the second region (124) of the semiconductor layer (120) covers at least part of the sidewalls of the cavity (150); said step e) is carried out so that each of these source (116) / drain (118) contacts is placed in one of the cavities (150); A method for fabricating the FET microelectronic device (100) of claim 6.

8. Between steps a) and b), a layer of temporary material (160) is carried out, and an electrostatic control gate (110) is then fabricated on said gate dielectric layer (112), - between steps c) and d) is carried out under the electrostatic control gate (110) and the dielectric spacer (114) in at least one space formed by etching of a portion of temporary material (160), said semiconductor layer (120) being subsequently fabricated over said gate dielectric layer (112); The method for fabricating a FET microelectronic device (100) according to any of claims 6 or 7, further comprising depositing a gate dielectric layer (112).

9. A method for fabricating a FET microelectronic device (100), comprising: a) creating at least one temporary material portion (160) on a substrate (102); b) fabricating, on at least said temporary material portion (160), a plurality of separate temporary gates arranged in a spaced-apart relation to one another, and a dielectric spacer (114) arranged against a sidewall of each temporary gate; c) depositing an insulating dielectric material (128) around said dielectric spacers (114); d) etching the temporary gates and creating a plurality of electrostatic control gates (110) in place of said temporary gates, said electrostatic control gates (110) being separate and spaced apart from one another; e) etching a cavity (150) in said insulating dielectric material (128) such that said cavity (150) includes at least one sidewall formed by one of said dielectric spacers (114); f) etching said temporary material portion (160); g) creating a semiconductor layer (120) including at least one said first region (122) configured to function as an electrical conduction channel of said FET microelectronic device (100), said semiconductor layer (120) being disposed beneath said electrostatic control gate (110) and dielectric spacer (114) within at least one space formed by etching of said temporary material portion (160), said semiconductor layer (120) extending without discontinuity with said first region (122) and covering at least a portion of a sidewall of said dielectric spacer (114), said second region (124) not disposed directly relative to the temporary gate, said second region (124) forming a source (116) / drain (118) region; h) fabricating on the substrate (102) the source / drain contacts, each disposed in one of the cavities (150), electrically coupled to the first region (122) of the semiconductor layer (120) by the second region (124) of the semiconductor layer (120), such that the second region (124) of the semiconductor layer (120) extends between the source / drain contacts and the dielectric spacer (114), the method also comprising fabricating the gate dielectric layer (112) disposed between each electrostatic control gate and the first region (122) of the semiconductor layer (120).

10. - during said step d), said electrostatic control gate (110) is then fabricated on said gate dielectric layer (112) in the space formed by etching of the temporary gate; - between steps c) and d) is carried out under the temporary gate and dielectric spacers (114) in at least one space formed by etching of said temporary material portion (160), said semiconductor layer (120) being subsequently fabricated over said gate dielectric layer (112); The method of fabricating a FET microelectronic device (100) according to claim 9, further comprising depositing said gate dielectric layer (112).

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