thin-film transistor

Abstract

A novel thin film transistor (TFT) includes a source-channel interface member between at least the source of the transistor and a semiconductor member in which the channel is formed. The TFT includes at least a source carrier reservoir in contact with the source and source end of the semiconductor member. The interaction of the source-channel interface member with the carrier reservoir provides the TFT with an increased threshold voltage for turning the TFT on and with reduced current leakage when the TFT is off, and the source carrier reservoir provides a source of charge carriers to suppress carrier depletion through the channel. The materials selected for forming the TFT also allow the TFT to be formed using MOL and / or BEOL processes on top of logic and other circuitry formed using conventional FEOL processes to obtain three-dimensional circuitry on the semiconductor die.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 435,118 (filed December 23, 2022, entitled "THIN FILM TRANSISTOR"), the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to transistors, and more particularly to novel thin film transistors. [Background technology]

[0003] Thin film transistors (TFTs) are now widely used in semiconductor devices. TFTs are so named because they are typically fabricated from very thin layers of semiconductor materials, metals, and insulators. One advantage of TFTs is that they can be substantially transparent to visible light and can be manufactured onto display screens and the like.

[0004] Because TFTs are constructed from thin layers of material, they can suffer from undesirable performance characteristics. For example, they typically do not turn off well, resulting in relatively high leakage currents and corresponding increases in power usage and thermal issues. TFTs often suffer from very low threshold voltages (the voltage at which the transistor turns on), and in many cases the threshold voltage can even be negative, requiring more complex circuit designs to turn the TFT off. These problems become worse as TFT sizes decrease.

[0005] To mitigate these challenges, when a sufficient voltage is applied to the gate of a TFT, the semiconductor layer that forms the channel is often engineered to be as thin as possible, which can improve off-state performance. However, thinning the channel layer also limits the total current throughput through the TFT due to subsequent carrier starvation in the adjacent source, thus limiting on-state performance and limiting available use cases for the TFT, especially at small gate lengths.

[0006] Furthermore, to date, TFTs have been manufactured using traditional front-end-of-line (FEOL) technology, which has limited their manufacture and use within a broader range of semiconductor manufacturing processes and use cases. Summary of the Invention

[0007] It is an object of the present invention to provide a novel thin film transistor that obviates or mitigates at least one of the disadvantages of the prior art.

[0008] According to a first aspect of the present invention, there is provided a thin film transistor comprising: an insulator; a source formed on the insulator; a drain formed on the insulator; an n-type semiconductor member; a source-channel interface member formed on the insulator and extending between at least the n-type semiconductor member and the source, wherein the source-channel interface member functions as a voltage-controlled electron transport barrier; a gate dielectric formed on the n-type semiconductor member; a gate formed on the gate dielectric; and an n-type semiconductor carrier reservoir formed in the source, wherein a channel is formed in the n-type semiconductor member when a threshold voltage is applied to the gate electrode, the channel conducts charge carriers through the n-type semiconductor member from the source to the drain, and the carrier reservoir provides a reservoir of negative charge carriers to alleviate carrier depletion through the channel in the n-type semiconductor member.

[0009] Preferably, the n-type semiconductor carrier reservoir has an effective electron mass of available electronic states similar to the electronic states of the n-type semiconductor material. Also, preferably, the thin film transistor can be fabricated in a middle-of-line (MOL) and / or back-end-of-line (BEOL) manufacturing process. Also, preferably, the thin film transistor can be fabricated in a lateral or vertical configuration.

[0010] According to another aspect of the present invention, there is provided a thin film transistor comprising: an n-type semiconductor member capable of forming a source, a drain, a gate and a channel; a source-channel interface member which is a p-type material, the source-channel interface member connecting the source to the semiconductor member and operable to establish a threshold voltage that enables a conductive channel to be formed from the source to the drain through the n-type semiconductor member when the threshold voltage is applied to the gate; and a source carrier reservoir in contact with the source and the n-type semiconductor member, the source carrier reservoir being an n-type semiconductor that provides a supply of charge carriers to the n-type semiconductor member when the threshold voltage is applied.

[0011] According to another aspect of the present invention, there is provided a thin film transistor comprising: an insulator; a source formed on the insulator; a drain formed on the insulator; an n-type semiconductor member; a p-type source-channel interface member formed on the insulator and extending between at least the n-type semiconductor member and the source; a gate dielectric formed on the n-type semiconductor member; a gate formed on the gate dielectric; an n-type semiconductor carrier reservoir formed on the source; a source electrode formed on the carrier reservoir; a gate electrode formed on the gate; and a drain electrode formed on the drain; wherein a channel is formed in the n-type semiconductor member when a threshold voltage is applied to the gate electrode, the channel conducting charge carriers through the n-type semiconductor member, the carrier reservoir providing a reservoir of negative charge carriers to alleviate carrier depletion through the channel in the n-type semiconductor member, and the source-channel interface member forming a depletion region in the n-type semiconductor member to substantially inhibit current flow through the n-type semiconductor member when no threshold voltage is applied to the gate.

[0012] The present invention provides novel thin film transistors that include a source-channel interface member for establishing a threshold voltage required to turn the transistor on and reducing or substantially eliminating off-state leakage current, and the transistor also includes a carrier reservoir for reducing or eliminating carrier depletion when the transistor is in the on-state. The transistors can be fabricated in mid-of-line and / or back-end-of-line semiconductor manufacturing processes. [Brief explanation of the drawings]

[0013] Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, which are not drawn to scale.

[0014] [Figure 1] FIG. 1 shows a schematic diagram of a cross section through a TFT according to one embodiment of the present invention.

[0015] [Figure 2] FIG. 2 shows the primary current path through the TFT of FIG. 1 when the TFT is in the on state.

[0016] [Figure 3] FIG. 3 shows a schematic cross-section through another TFT according to an embodiment of the present invention.

[0017] [Figure 4] FIG. 4 shows a schematic cross-section through another TFT according to an embodiment of the present invention.

[0018] [Figure 5] FIG. 5 shows a schematic cross-section through another TFT according to an embodiment of the present invention.

[0019] [Figure 6] FIG. 6 shows a schematic diagram of a cross section through a vertically formed TFT according to one embodiment of the present invention.

[0020] [Figure 7]FIG. 7 shows a schematic diagram of a cross section through a vertically formed TFT according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Fabrication of components and / or features of semiconductor devices is described herein as "forming," and as will be apparent to those skilled in the art, "forming" is intended to include, without limitation, all suitable and applicable semiconductor production techniques, including deposition (chemical, atomic layer, physical vapor, etc.), sputtering, PECVD (plasma enhanced chemical vapor deposition), implantation and annealing, oxidation, etc.

[0022] A TFT according to one embodiment of the present invention is generally indicated at 20 in Figure 1. The TFT 20 is formed on a substrate 24, such as an insulating substrate or an interlayer dielectric, which can be a layer of a suitable dielectric such as silicon dioxide, glass, plastic, etc.

[0023] All TFTs, including TFT 20, have the basic structure of a field-effect transistor and include a source 28, a drain 32, and a gate 36. In TFT 20, source 28 and drain 32 can be conductive elemental materials or compounds of materials, such as metals or degenerate (heavily doped) semiconductors. Examples of suitable materials that can be used as source 28 or drain 32 include nickel, tungsten, molybdenum, copper, cobalt, ruthenium, degenerate n-type silicon, or any III-V compound semiconductor with high conductivity that is predominantly n-type or electron transporting. The specific selection of material for source 28 is made in conjunction with the material selected for gate 36, and the selection of these two materials is a factor in determining the threshold voltage of TFT 20. The selection of these materials is within the capabilities of one skilled in the art of transistor design and fabrication.

[0024] The source 28 is connected to the source electrode 40 via a source carrier reservoir 28a. The source carrier reservoir 28a is preferably formed from an n-type semiconductor material that is much more highly n-type than the semiconductor member 48 (described below) and preferably has an allowed density of states similar to that of the semiconductor member 48, as described below. Examples of suitable materials for the source carrier reservoir 28a include heavily n-doped polysilicon or germanium, tin oxide, indium oxide, tungsten, or other materials that will occur to those skilled in the art that have an electron effective mass close to that of the semiconductor member 48.

[0025] Similarly, in TFT 20, drain 32 is connected to drain electrode 44 via drain reservoir 32a. The materials from which drain reservoir 32a and drain 32 are formed are preferably selected to provide efficient conduction of carriers from the channel in semiconductor member 48, and they may be the same material or, more generally, different materials.

[0026] The drain electrode 44 can be any suitable material that forms the desired electrical connection between the drain reservoir 32 a and other circuitry that connects to the TFT 20 .

[0027] As described above, the TFT 20 includes an n-type semiconductor member 48 formed to extend between the source 28 and the drain 32 and contact the carrier reservoir 28a and the drain reservoir 32a. The semiconductor member 48 may comprise any suitable metal oxide, such as zinc oxide, tin oxide, indium gallium zinc oxide (IGZO), gallium oxide, germanium oxide, or the like. The n-type semiconductor material from which the semiconductor member 48 is formed is preferably selected so that it can be formed and annealed at temperatures of about 400°C or less to ensure compatibility with middle-of-line ("MOL") and / or back-end-of-line ("BEOL") manufacturing processes.

[0028] A gate dielectric member 52, which may be any suitable dielectric material such as silicon dioxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or combinations thereof, is formed over the semiconductor member 48 to block free carrier flow, and the gate 36 is formed over the gate dielectric member 52. As will occur to those skilled in the art, the gate 36 is connected to a gate electrode 58, which may be any suitable material such as titanium, titanium nitride, chromium, hafnium, tantalum nitride, or any other single or bimetallic element or compound, and which is selected to provide a good electrical connection between the gate 36 and other circuitry connected to the TFT 20.

[0029] As known to those skilled in the art, when an electric field is applied to the gate 36, a conductive channel is formed through the semiconductor material 48, allowing current to flow through this channel from the source carrier reservoir 28a and source 28 to the drain reservoir 32a and drain 32.

[0030] The source electrode 40 is electrically insulated from the gate 36 and gate electrode 58 by a source dielectric spacer 62, and the drain electrode 44 is electrically insulated from the gate 36 and gate electrode 58 by a drain dielectric spacer 66. The source dielectric spacer 62 and drain dielectric spacer 66 may be any suitable dielectric material, such as silicon dioxide. In some cases, the source dielectric spacer 62 and drain dielectric spacer 66 are low-K dielectrics and the gate dielectric member 52 is a high-K dielectric, while in other cases the source dielectric spacer 62, drain dielectric spacer 66, and gate dielectric member 52 can be formed of the same material. It is contemplated that the source dielectric spacer 62 and / or the drain dielectric spacer 66 may be voids (e.g., absences of material), which can advantageously reduce parasitic capacitance in the TFT 20.

[0031] To improve the off-state performance of TFT 20, the inventors have determined and found that by providing a source-channel interface member 70, the threshold voltage at which TFT 20 turns on can be increased, allowing the transistor to operate in enhancement mode, thereby reducing leakage current through TFT 20 in the off-state.

[0032] Specifically, the source-channel interface material 70 is provided to create a repository of complementary excess negative charge that acts to deplete the channel in at least the regions of the semiconductor material 48 adjacent to the source 28 and carrier reservoir 28 a. In this manner, the source-channel interface material 70 functions as a voltage-controlled electron transport barrier, causing substantially no current flow through the semiconductor material 48 when the TFT 20 is in the “OFF” state.

[0033] Additionally, the source-channel interface material 70 also serves to reduce stress-induced leakage current (“SILC”) in the TFT 20 by inhibiting the formation of interlayer stress-induced defects between the semiconductor material 48 and the source 28 .

[0034] The source-channel interface member 70 can be formed in a variety of configurations, including p-type semiconductors, induced piezoelectric dipoles, controllable tunneling barriers, combinations thereof, or other mechanisms for modulating the injection current by an externally applied field.

[0035] For example, when implemented as a p-type semiconductor, the source-channel interface material 70 can be comprised of elemental germanium, or the source-channel interface material 70 can be formed by using p-type dopants in the relevant portion of the semiconductor material 48. In other cases, the source-channel interface material 70 can be comprised of an oxide or sulfide, or a metal ion paired with another element corresponding to Group VI (A) of the periodic table, such as ruthenium oxide, silicon nitride, nickel oxide, copper oxide, molybdenum oxide, iridium oxide, or a chalcogen, such as oxygen, sulfur, selenium, or tellurium compounds.

[0036] The source-channel interface member 70 may also be formed by catalytic growth of the material that forms the source 28, such as ruthenium and ruthenium oxide, tungsten and tungsten oxide, other metals that form self-limiting oxide layers, or degenerately doped polycrystalline silicon combined with a chemically limited silicon dioxide or nitride barrier layer. In such cases, oxygen may preferentially cross to the source-channel interface, creating the source-channel interface member 70. In other cases, the source-channel interface member 70 may be formed by depositing a p-type material, such as a p-type metal oxide or another semiconductor, by a deposition technique such as atomic layer deposition, sputtering physical vapor deposition, or chemical vapor deposition.

[0037] It has been discovered that the availability of source-channel interface member 70 in TFT 20 can cause TFT 20 to experience carrier depletion when in the on state. To provide a reservoir of negative charge carriers to alleviate such carrier depletion, source carrier reservoir 28a can be formed adjacent source 28 and semiconductor member 48 as a charge source, and drain reservoir 32a can be formed adjacent drain 32 and semiconductor member 48.

[0038] 1, as described above, source carrier reservoir 28a is formed adjacent to semiconductor member 48 between source 28 and source electrode 40. Source carrier reservoir 28a can be formed from the same material as source 28, although in other implementations, source carrier reservoir 28a is preferably formed from other suitable materials selected to minimize or form a gradually increasing gradient of electron barriers between channels formed in semiconductor member 48 and source carrier reservoir 28a and source 28, such that electrons do not experience a significant reflection probability when crossing the boundaries between reservoir 28a, source 28, and semiconductor member 48.

[0039] The source carrier reservoir 28a preferably has an effective electron mass or effective electron density of available electron states that is at a level similar to that of the channel material of the semiconductor member 48 itself. The source carrier reservoir 28a may be a monoatomic semiconductor such as degenerately doped silicon, germanium, or tin, or may be a binary, ternary, quaternary, etc., semiconductor material doped to produce a high degree of electrons. The drain reservoir 32a may be similarly selected and formed.

[0040] Generally, the source carrier reservoir 28a and the drain reservoir 32a (if present) should not be metallic because the density of states in a metal can give rise to reflections at the interface between the channel formed in the semiconductor material 48 and the pre-channel of the semiconductor material 48 due to an imbalance between the available electronic states.

[0041] 1, the drain reservoir 32a is formed adjacent to the semiconductor member 48 between the drain 32 and the drain electrode 44. The drain reservoir 32a functions as an electron receiver to enhance the outflow of electrons from the channel formed in the semiconductor member 48.

[0042] 2, when a voltage sufficient to turn TFT 20 on is applied to gate 36 (i.e., when a voltage equal to or exceeding the threshold voltage is applied to gate 36), most of the current through TFT 20 flows from source electrode 40 through carrier reservoir 28a to a channel formed in semiconductor member 48, as indicated by the thick arrows in FIG. 2. A relatively small amount of current also flows from source electrode 40 through carrier reservoir 28a to source 28 and then to a channel formed in semiconductor member 48, as indicated by the thin arrows in FIG.

[0043] TFT 20 can be fabricated in a variety of ways. For example, elements can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc., as will be apparent to those skilled in the art.

[0044] FIG. 3 shows another TFT 100 according to an embodiment of the present invention, in which like elements to those described above with reference to FIG. 1 are designated with like reference numerals.

[0045] Specifically, drain reservoir 32a is omitted in TFT 100. TFT 100 still offers improved threshold voltage levels as described above with reference to TFT 20, but has a different, higher breakdown voltage, which allows TFT 100 to be employed in a variety of applications, such as voltage regulators, that require higher voltage levels and for which prior art TFTs were not suitable.

[0046] FIG. 4 illustrates another TFT 200 according to one embodiment of the present invention, in which like elements as described above with reference to FIG. 1 are designated by like reference numerals. In this example, the performance characteristics of the TFT 200 are established by further forming reducing members 204 and 208 between the source carrier reservoir 28a and the source electrode 40 and between the drain reservoir 32a and the drain electrode 44, respectively. The reducing members 204 and 208 can be titanium, tin, hafnium, zirconium, and other metals that form conductive oxides in small forms. When annealed, the reducing members 204 and 208 function to draw oxygen from the source carrier reservoir 28a and / or the drain reservoir 32a (if present), and as oxygen deficiencies accumulate, the semiconductor material underlying the source carrier reservoir 28a and / or the drain reservoir 32a becomes more heavily n-type.

[0047] It is contemplated that reducing members 204 and 208 may be formed as layers of material on the order of 1-2 nm. It is contemplated that reducing member 208 may be omitted from TFT 200, if desired.

[0048] In some cases, sufficient oxygen can be drawn from regions of the semiconductor member 48 adjacent to the reducing member 204 and / or 208, resulting in this oxygen-depleted region forming carrier reservoir 28a and / or 32a. Figure 5 shows a TFT 250 in which the reducing member 208 is, for example, titanium, and oxygen is drawn from a semiconductor member 48, for example, tin oxide, to form carrier region 28a. When formed in this manner, carrier reservoir 28a is formed with a stoichiometric gradient from the oxide of semiconductor member 48 to the relatively oxygen-free region adjacent to the reducing member 208, thus producing a good ohmic contact to the semiconductor member 48.

[0049] In the above examples, TFTs according to embodiments of the invention are shown as devices formed laterally (i.e., horizontally), but the invention is not so limited and TFTs according to embodiments of the invention can also be advantageously formed as vertical (i.e., -+Z axis) devices.

[0050] FIG. 6 shows an example of a vertically mounted TFT 300 according to another embodiment of the present invention, in which similar components to those described above are designated with similar reference numerals, including a channel dielectric spacer 302 between the source 28 and drain 32.

[0051] As can be seen, TFT 300 is a vertical device, and connections to TFT 300 are achieved through vias 304. In particular, although not required, TFT 300 is shown as being formed between first and second interlevel dielectric layers 24 to allow layers of TFTs 300 to be stacked vertically one above the other to increase device density for a given semiconductor die area.

[0052] TFT 300 is what we call an "inverted" TFT because the source carrier reservoir 28a and source 28 are above the semiconductor member 48 and drain 32 (drain reservoir 32a is omitted from the illustrated embodiment of TFT 300, but can be included in other implementations of TFT 300 as desired).

[0053] 7 shows another example of a vertical TFT 400 according to another embodiment of the present invention, with like components shown and discussed with reference to FIG. 6 being designated with like reference numerals. TFT 400 is referred to by the inventors as a "forward-oriented" TFT because drain 32 is above semiconductor member 48, source 28, and source carrier reservoir 28a. Drain reservoir 32a is also omitted from this example, but could be included in other implementations of TFT 400 as desired.

[0054] As noted above, TFTs 20, 100, 200 and 250 can be formed in a stacked configuration with TFTs formed in one plane above another plane of TFTs, however, vertical implementation of TFTs in accordance with the present invention, such as TFTs 300 and 400, is often considered preferred due to ease of connection to other circuit elements and reduced die area requirements compared to laterally formed TFTs.

[0055] Another particular advantage of the present invention is that the materials and manufacturing processes employed with the above-described TFTs, as well as the methods of forming TFTs, are selected such that TFTs according to the present invention can be formed at relatively low temperatures as middle-of-line (MOL) and / or back-end-of-line (BEOL) processes.

[0056] For example, annealing of TFTs according to embodiments of the present invention can be performed at temperatures below about 400° C. Thus, in the illustrated example, insulating layer 24 can be, for example, a layer of silicon dioxide formed on top of CMOS circuitry otherwise fabricated by conventional front-end-of-line (FEOL) manufacturing processes, and one or more planes of TFTs according to the present invention can be formed on top of the planes of the CMOS circuitry.

[0057] By enabling the formation of TFT circuitry according to aspects of the present invention, true three-dimensional semiconductor die, circuits and devices can be fabricated on top of FEOL fabricated CMOS circuitry as a MOL and / or BEOL process.

[0058] It is believed that MOL and BEOL formed circuits including TFTs according to embodiments of the present invention are useful in a variety of applications including SRAM memory cells, implementing "dark silicon" power saving strategies and / or providing various non-core functionality such as voltage regulators, thus increasing the overall density of a semiconductor die to previously unobtainable levels.

[0059] The above-described embodiments of the invention are intended to be examples of the invention, and changes and modifications may be made by those skilled in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims

1. An insulator; a source formed on the insulator; a drain formed on the insulator; An n-type semiconductor member; a source-channel interface member formed on the insulator and extending between at least the n-type semiconductor member and the source, the source-channel interface member functioning as a voltage-controlled electron transport barrier; a gate dielectric formed on the n-type semiconductor member; a gate formed on the gate dielectric; an n-type semiconductor carrier reservoir formed in the source; Equipped with A channel is formed in the n-type semiconductor material when a threshold voltage is applied to a gate electrode, the channel conducting charge carriers through the n-type semiconductor material from the source to the drain, and the carrier reservoir providing a reservoir of negative charge carriers to alleviate carrier depletion through the channel in the n-type semiconductor material.

2. 10. The thin film transistor of claim 1, wherein the n-type semiconductor carrier reservoir has an effective electron mass in an available electronic state similar to an electronic state of the n-type semiconductor material.

3. 3. The thin film transistor of claim 2, further comprising an n-type semiconducting drain reservoir at the drain, the n-type semiconducting drain reservoir providing improved conduction of charge carriers from the channel in the n-type semiconductor material.

4. 4. The thin film transistor of claim 3, wherein the n-type semiconductor drain reservoir has an effective electron mass in available electronic states similar to an electronic state of the n-type semiconductor material.

5. 2. The thin film transistor of claim 1, further comprising a reducing material formed adjacent the n-type semiconductor material and the source to form the n-type semiconductor carrier reservoir in the source.

6. 4. The thin film transistor of claim 3, further comprising: a reducing member formed adjacent to the n-type semiconductor material and the source to form the carrier reservoir in the source; and a reducing member formed adjacent to the n-type semiconductor material and the drain to form an n-type drain reservoir.

7. 7. The thin film transistor of claim 5, wherein the reducing member is a metal selected from the group consisting of titanium, molybdenum, tin, hafnium, or zirconium.

8. The thin film transistor according to claim 1 , wherein the transistor is a lateral transistor.

9. The thin film transistor according to claim 1 , wherein the transistor is a vertical transistor.

10. 7. The thin film transistor of claim 1, 2, 3, 4, 5 or 6 formed in a mid-of-line manufacturing process.

11. 7. The thin film transistor of claim 1, 2, 3, 4, 5 or 6 formed in a back-end-of-line manufacturing process.

12. 7. The thin film transistor of claim 1, wherein the transistor is a lateral transistor and is formed in a mid-of-line manufacturing process.

13. 7. The thin film transistor of claim 1, wherein the transistor is a vertical transistor and is formed in a middle-of-line manufacturing process.

14. 7. The thin film transistor of claim 1, wherein the transistor is a lateral transistor and is formed in a back-end-of-line manufacturing process.

15. 7. The thin film transistor of claim 1, wherein the transistor is a vertical transistor and is formed in a back-end-of-line manufacturing process.

16. With sauce, Drain and Gate and an n-type semiconductor member capable of forming a channel; a source-channel interface member that is a p-type material, the source-channel interface member connecting the source to the semiconductor member and operable to establish a threshold voltage that, when applied to the gate, enables a conductive channel to form from the source to the drain through the n-type semiconductor member; a source carrier reservoir in contact with the source and the n-type semiconductor material, the source carrier reservoir being an n-type semiconductor that provides a supply of charge carriers to the n-type semiconductor material when the threshold voltage is applied; A thin film transistor comprising:

17. 17. The thin film transistor of claim 16, wherein the source carrier reservoir has an effective electron mass of an available electronic state similar to an electronic state of the n-type semiconductor material.

18. 17. The thin film transistor of claim 16, further comprising an n-type semiconducting drain reservoir in contact with the drain and the n-type semiconductor material, the drain reservoir at the drain, the drain reservoir providing improved conduction of charge carriers from the channel in the n-type semiconductor material.

19. 19. A thin film transistor according to any one of claims 16 to 18, wherein the source carrier reservoir has an effective electron mass of an available electronic state similar to an electronic state of the n-type semiconductor material.

20. 17. The thin film transistor of claim 16, wherein the transistor is formed as a lateral transistor.

21. 17. The thin film transistor of claim 16, wherein the transistor is formed as a vertical transistor.

22. 17. The thin film transistor of claim 16, wherein the transistor is formed as a lateral transistor and is formed in a mid-of-line manufacturing process.

23. 17. The thin film transistor of claim 16, wherein the transistor is formed as a lateral transistor and is formed in a back-end-of-line manufacturing process.

24. 17. The thin film transistor of claim 16, wherein the transistor is formed as a vertical transistor and is formed in a middle-of-line manufacturing process.

25. 17. The thin film transistor of claim 16, wherein the transistor is formed as a vertical transistor and is formed in a back-end-of-line manufacturing process.

26. An insulator; a source formed on the insulator; a drain formed on the insulator; An n-type semiconductor member; a p-type source-channel interface member formed on the insulator and extending at least between the n-type semiconductor member and the source; a gate dielectric formed on the n-type semiconductor member; a gate formed on the gate dielectric; an n-type semiconductor carrier reservoir formed on the source; a source electrode formed on the carrier reservoir; a gate electrode formed on the gate; a drain electrode formed on the drain; Equipped with a channel is formed in the n-type semiconductor material when a threshold voltage is applied to the gate electrode, the channel conducting charge carriers through the n-type semiconductor material; the carrier reservoir provides a reservoir of negative charge carriers to alleviate carrier depletion through the channel of the n-type semiconductor material; The source-channel interface member forms a depletion region in the n-type semiconductor member when the threshold voltage is not applied to the gate, thereby substantially inhibiting current flow through the n-type semiconductor member.

27. 27. The thin film transistor of claim 26, wherein the transistor is formed as a mid-of-line manufacturing process.

28. 27. The thin film transistor of claim 26, wherein the transistor is formed as a back-end-of-line manufacturing process.

29. 29. A thin film transistor according to claim 27 or 28, wherein the transistor is a lateral transistor.

30. 29. A thin film transistor according to claim 27 or 28, wherein the transistor is a vertical transistor.

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