Method of operation, semiconductor module, and manufacturing method

Abstract

In one embodiment, a method for operating a semiconductor module (10) includes: providing a semiconductor module (10), the semiconductor module (10) including a plurality of power semiconductor devices (1), the power semiconductor devices (1) arranged adjacent to one another in a top view, the power semiconductor devices (1) interconnected by bus lines (5), controlling a current through the power semiconductor devices (1) via a first voltage (Vg,bus) supplied by the bus lines (5), and supplying a control signal (Ucont) modulated as a second voltage to the first modulated voltage (Vg,bus) to the power semiconductor devices (1) via the bus lines (5).

Description

[Technical Field]

[0001] A method of operating a semiconductor module is provided. Also provided is a semiconductor module. Also provided is a method of manufacturing such a semiconductor module. [Background technology]

[0002] The document US Patent Application Publication No. 2015 / 0333737 refers to a control circuit for a gate driver circuit.

[0003] US Patent Application Publication No. 2013 / 0200927 discloses an over-temperature protection transistor. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved is to provide a robust semiconductor module with improved thermal behavior and a corresponding method of operation. [Means for solving the problem]

[0005] This object is achieved, inter alia, by an operating method, by a semiconductor module and by a manufacturing method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0006] For example, a semiconductor module as described herein and operated in accordance therewith may include a plurality of semiconductor devices interconnected by bus lines. A logic unit on a power semiconductor chip of each one of the semiconductor devices associated with the bus lines may, for example, ensure that the temperature of the power semiconductor chips is equal throughout the semiconductor module. This may be done, for example, by modulating temperature information onto gate voltages supplied to the individual power semiconductor chips of the semiconductor module.

[0007] Parallel connection of power semiconductor chips is limited due to asymmetric current sharing, asymmetric temperature, and asymmetric loss distribution between the individual power semiconductor chips. Alternative solutions include, for example, the use of gate resistors that slow down switching speed and increase losses, modular design with fewer space- and performance-constrained parasitics, careful pre-selection of expensive chips, or a combination of the above, or implementing switch controllers in CMOS on-chip logic on each individual SiC power semiconductor chip to individually control the switching behavior of each chip, thereby equalizing junction temperatures.

[0008] The operating method and semiconductor module described herein propose modulating information onto the gate signals used to set control parameters in a CMOS on-chip controller, thereby optimizing the design freedom and performance of parallel-connected power semiconductor chips.

[0009] In at least one embodiment, a method of operation is for operating a semiconductor module, and includes, for example, the following steps in the order listed: providing a semiconductor module, the semiconductor module comprising a plurality of power semiconductor devices, the power semiconductor devices being arranged adjacent to one another in a top view, and the power semiconductor devices being interconnected by bus lines; - controlling a current through a power semiconductor device via a first voltage provided by a bus line; - supplying a control signal modulated as a second voltage to the first modulated voltage via the bus line to the power semiconductor device;

[0010] Thus, the gate signal may be modulated to set control parameters of, for example, a CMOS on-chip control algorithm implemented on a SiC power semiconductor chip.

[0011] The approach presented herein allows for greater freedom in controller design. If control parameters such as thresholds and gains are hard-coded, semiconductor module and / or converter designers may not be able to adapt these parameters and may be forced to accept a suboptimal design. If control parameters can be accessed and / or set externally by converter designers, additional interfaces must be provided for connecting wires, which significantly increases complexity, space requirements, and cost.

[0012] If the parameters of the CMOS on-chip controller are externally programmable during the converter design stage, e.g. via a gate connection that can be set to program mode, then long-term energy storage on the chip is required, which is extremely limited due to the very small amount of space available.

[0013] The method described herein proposes modulating the control parameters onto the gate signals, which eliminates the need for additional wiring and / or interfaces, making it efficient, low-cost, and highly robust.

[0014] Essentially, one idea is to modulate information onto the gate signals used to set control parameters in a CMOS on-chip controller, i.e., a logic unit.

[0015] For example, while the gate voltage for on-state switching is typically set at approximately 15 V, using slightly higher voltage levels does not alter the switching or conduction behavior of the power semiconductor; see, for example, Infineon's datasheet "IKW50N65F5 650V DuoPack IGBT and Diode - High-speed switching series fifth generation" (rev. 2.1, May 5, 2015), especially Figure 5. Thus, the desired information is available by applying a small voltage that is subtracted, filtered, and amplified by a demodulator circuit in the CMOS on-chip logic unit, which is very efficient and allows the data to be limited to a single parameter value. Alternatively, different high-frequency signals, e.g., more than 10 times the gate's switching frequency, can be added, and the parameter information can be transmitted via the amplitude of these signals, which can be extracted by the demodulator circuit, e.g., by band-pass filtering.

[0016] Advantageous features of the methods of operation described herein include, for example: -Efficient, flexible and easy to use for designers; -Improvement of the performance of parallel-connected power semiconductor chips by setting optimized operating parameters; - Possible dynamic parameter changes during operation to optimize the behavior of parallel-connected chips, for example after load changes or at very low ambient temperatures, which increase switching overvoltages; - no additional wiring is required, thereby avoiding increased complexity or significant limitations due to space constraints, and / or; -Power semiconductor devices do not require long-term information storage in CMOS on-chip logic.

[0017] In summary, for example, the proposed method of operation uses a semiconductor device having a controller implemented as a CMOS on-chip logic unit of a power semiconductor chip, where one or several signals are modulated onto the on-signals of the gate drivers and retrieved via a demodulator circuit of the CMOS on-chip logic unit to provide demodulated values ​​which are used as parameter values ​​for at least one algorithm of a switch control unit which modifies the switching speed and / or delay to output switching signals of the respective power semiconductor chips to the gate electrode contact areas.

[0018] For example, the semiconductor module comprises at least 4, or at least 10 semiconductor devices. Alternatively or additionally, there are up to 150, or up to 100, or up to 30 semiconductor devices. By way of example, the semiconductor module includes at least 10 and up to 30 semiconductor devices, such as 16 semiconductor devices.

[0019] According to at least one embodiment, one or some or each of the power semiconductor devices comprises a power semiconductor chip, a logic unit, and a gate pad. The gate pads are interconnected by a bus line. One or some or each of the power semiconductor chips comprises a gate electrode contact region. The logic unit is electrically arranged between the gate electrode contact region and the assigned gate pad. In the following, the power semiconductor device may be simply referred to as a semiconductor device.

[0020] For example, the logic units are CMOS devices. The logic units do not need to be mechanically freestanding chips, but may be mechanically supported by power semiconductor chips. Therefore, the logic units can be relatively thin and include only a small number of electrical elements, such as resistors, transistors, and capacitors. For example, each logic unit can be up to 10 5 or up to 10 4 or up to 10 3The thickness of the logic unit may be at least 0.2 μm and / or may be at most 10 μm or at most 3 μm.

[0021] For example, the gate pad and / or gate electrode contact area is a metallization, i.e., the gate pad and / or gate electrode contact area may be made of one or more metals, e.g., at least 98% of the gate pad and / or gate electrode contact area is metal.

[0022] According to at least one embodiment, the gate pad is configured to supply a bus gate voltage to a gate electrode contact region of the semiconductor device. Therefore, the gate pad is connectable to the gate electrode contact region via a respective logic unit. Therefore, there may not be a direct electrical contact between the gate electrode contact region and the gate pad. For example, there may be at least one active electrical component, such as a variable resistor and / or a switch, between the gate electrode contact region and the gate pad.

[0023] According to at least one embodiment, in each one of the semiconductor devices, the logic units are configured to modify a bus gate voltage applied to the gate pad, such that the bus gate voltage may be at least temporarily different from a tip gate voltage applied to the gate electrode contact region, at least when the corresponding logic unit is powered and / or active.

[0024] According to at least one embodiment, in each of the semiconductor devices, the logic unit is configured so that the unit current passing therethrough is at most 1% of the chip current passing through the power semiconductor chip. For example, this value is at most 0.1%. By way of example, when this unit is turned on, the current passing through the logic unit is in each case at least 0.1 mA and / or at most 0.02 A.

[0025] According to at least one embodiment, in each one of the semiconductor devices, the logic units are geometrically partially or completely disposed between the gate electrode contact area and the gate pad. For example, at least 50%, at least 80%, or at least 95% of the volume of each logic unit is disposed between its assigned gate pad and gate electrode contact area. Alternatively, the logic units may be disposed outside the gap between the gate pad and its assigned gate electrode contact area.

[0026] According to at least one embodiment, the power semiconductor chips are each selected from the group: Metal-Insulator-Semiconductor Field Effect Transistor, MISFET, Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET, Insulated Gate Bipolar Transistor, IGBT, Reverse Conducting Insulated Gate Bipolar Transistor, RC-IGBT.

[0027] All power semiconductor chips in a semiconductor module may be of the same type, or there may be power semiconductor chips of different types, as well as logic units.

[0028] According to at least one embodiment, the power semiconductor chips are each configured such that a voltage between a first electrode and a second electrode of the power semiconductor chip is at least 0.6 kV or at least 1.2 kV, and / or at most 15 kV. Alternatively or additionally, the power semiconductor chips are each configured such that a current between a first electrode and a second electrode of the power semiconductor chip is at least 1 A or at least 0.01 kA or at least 0.1 kA, and / or at most 100 kA or at most 10 kA or at most 1 kA. That is, by means of the gate electrode and having respective voltages between the first electrode and the second electrode, the flow of current through the semiconductor device is controllable, and in particular can be switched on and off by turning the voltage at the gate electrode on and off.

[0029] According to at least one embodiment, in each of the semiconductor devices, the first electrode is a source electrode or an emitter electrode, and correspondingly, the second electrode is a drain electrode or a collector electrode of the respective power semiconductor chip.

[0030] According to at least one embodiment, the bus line supplies a bus gate voltage as a first voltage to all of the semiconductor devices simultaneously, where "simultaneously" means that there is no significant delay between the semiconductor devices, and a significant delay is, for example, up to 10 of 1 / f. -3 or up to 10 -4 or up to 10 -5 where f is the switching frequency of the gate signal at the gate pad. For example, the delay may be up to 0.1 μs, or up to 10 ns, or up to 1 ns. The delay may be determined by the execution time difference of the gate signals between the semiconductor devices.

[0031] In at least one embodiment, the bus line comprises a single line and / or a single channel. For example, the bus line comprises multiple bonding wires electrically connected in series by gate pads. The bus line may have no branches or at least one branch, depending on the layout pattern of the semiconductor devices, in order to shorten the overall length of the bus line.

[0032] According to at least one embodiment, the bus lines are the only direct electrical interconnections between all gate pads, however, there may be indirect electrical connections between gate pads and ground lines, such as source and emitter lines, via the internal power supplies of the semiconductor device.

[0033] According to at least one embodiment, in a top view of the semiconductor device, the logic unit is in each case equal to or smaller than the dimensions of the assigned gate pad, and therefore the logic unit can be relatively small in top view.

[0034] According to at least one embodiment, in each case the gate pad completely covers the assigned logic unit, i.e., the logic unit may be completely embedded under the metallic assigned gate pad.

[0035] According to at least one embodiment, the second voltage is, on time average, at most 1% of the first voltage. Therefore, modulating the second voltage onto the first voltage leaves the first voltage substantially unchanged. Therefore, the second voltage does not affect, or does not significantly affect, the switching behavior of the associated power semiconductor chip.

[0036] According to at least one embodiment, the second voltage is at most 0.5 V, or at most 0.2 V, or at most 0.1 V. Alternatively or additionally, on a time average, the second voltage is at least 1 mV or at least 5 mV.

[0037] According to at least one embodiment, the peak voltage of the first voltage is at least 3 V or at least 10 V. Alternatively or additionally, the peak voltage is up to 30 V or up to 20 V. The first voltage may be time-averaged to at least 2 V or at least 6 V and / or up to 15 V or up to 10 V.

[0038] In at least one embodiment, the semiconductor device receives and transmits signals over the bus line. In other words, bidirectional communication can occur over the bus line. For example, the semiconductor device receives control signals and transmits sensor signals.

[0039] According to at least one embodiment, the semiconductor module (10) further comprises one or more control units. The at least one control unit is external to the semiconductor devices, i.e., is a component separate from the semiconductor devices. Alternatively, the control unit may be an external component that is not part of the semiconductor module, in which case the control unit is connected to the semiconductor module and / or the semiconductor devices by a bus line. Alternatively, the control unit may be included in at least one of the semiconductor devices.

[0040] According to at least one embodiment, the at least one control unit provides control signals to the semiconductor devices, e.g., the at least one control unit collects sensor signals from all associated semiconductor devices and, e.g., calculates corresponding control signals based on the sensor signals.

[0041] Each one of the semiconductor devices may be provided with an individual control signal which is individualizable by the address contained in the control signal, or there may be a common control signal for all of the semiconductor devices.

[0042] According to at least one embodiment, each of the logic units includes a demodulator configured to receive the superposition of the first and second voltages and demodulate from the superposition a control voltage signal corresponding to the second voltage, the demodulator being capable of modulating the sensor signal onto the first voltage.

[0043] According to at least one embodiment, each of the logic units includes a switch controller that receives the control voltage signal from the demodulator and outputs a chip gate voltage to the gate of each power semiconductor chip based on the control voltage signal and the sensor signal.

[0044] According to at least one embodiment, each of the logic units comprises one or more sensors, and the switch controller receives at least one sensor signal from the at least one sensor.

[0045] According to at least one embodiment, the logic unit is configured to output the sensor signals to the bus line. Thus, one sensor signal per sensor may be present on the bus line. The sensor signals, e.g., one sensor signal per semiconductor device, may be output simultaneously so that an averaged or superimposed signal is present on the bus line. Alternatively, the sensor signals may be output in a time-division multiplexed manner, i.e., shifted in time.

[0046] According to at least one embodiment, the tip gate voltage still includes a second voltage. In other words, the second voltage may not be filtered out from the tip gate voltage applied at the gate electrode contact region. However, the second voltage may be attenuated, for example, by a resistor. The first voltage may be attenuated by the same resistor, so that the ratio of the first voltage to the second voltage may be the same at the gate pad and the gate electrode contact region. Alternatively, the second voltage may be filtered out to a voltage at the gate electrode contact region where only the first voltage, possibly attenuated by a resistor, is present.

[0047] According to at least one embodiment, the sensor is a temperature sensor. For example, the at least one sensor comprises or is a temperature-dependent electrical resistor. The resistor may have a positive or negative temperature characteristic, i.e., as the temperature increases, the electrical resistance may increase or decrease, respectively.

[0048] In at least one embodiment, the switch controller controls the switching behavior of the gates of each power semiconductor chip so that the junction temperatures of the power semiconductor chips are all the same, within a tolerance of up to 10K or up to 20K.

[0049] Thus, in one or several or each of the semiconductor devices, the logic units are configured to adjust the junction temperature of the corresponding power semiconductor chip, for example by adapting the turn-on time of the power semiconductor chip, which turn-on time, and likewise the turn-off time, can be adapted by having a variable resistor between the gate pad and the gate electrode contact area, which variable resistor is part of the respective logic unit and, for example, adjustable by the logic unit.

[0050] A semiconductor module is also provided, the method of operation of which causes the semiconductor module to operate as described in connection with at least one of the above-described embodiments. Accordingly, features of the semiconductor module are also disclosed in the method of operation, and vice versa.

[0051] In at least one embodiment, the semiconductor module comprises: a plurality of semiconductor devices, the semiconductor devices being arranged adjacent to one another in a top view; a bus line interconnecting all of the semiconductor devices; Here, the semiconductor devices are configured to receive a superposition g1 of a first voltage Vg,bus and a second voltage Ucont, the superposition g1 being provided by a bus line, the first voltage Vg,bus controlling the current through the respective semiconductor device and the second voltage Ucont adjusting the switching behavior of the respective semiconductor device; Each of the semiconductor devices is configured to demodulate the control signal Ucont from the superposition g1. Optionally, a switching signal g2 is generated within the semiconductor device and output to the corresponding gate.

[0052] There is also provided a method for manufacturing a semiconductor module, by which the semiconductor module is manufactured as shown in relation to at least one of the above-described embodiments, and therefore features of the semiconductor module are also disclosed in the method for manufacturing it as well as in its method of operation, and vice versa.

[0053] In at least one embodiment, a manufacturing method is for operating a semiconductor module and includes, for example, at least the following steps in the order listed: providing a power semiconductor chip and a logic unit; - in each case bonding at least one logic unit to the assigned power semiconductor chip, for example by wafer bonding; - in each case applying at least one gate pad across the assigned logical unit; - applying the semiconductor devices to a common carrier; - Interconnecting gate pads via bus lines.

[0054] The operation method, semiconductor module, and manufacturing method will be described in more detail below with reference to the drawings using exemplary embodiments. The same elements in the individual figures are designated by the same reference numerals. However, the relationships between the elements are not shown to scale, and rather, the individual elements may be exaggerated to facilitate understanding. [Brief explanation of the drawings]

[0055] [Figure 1] 1 is a schematic perspective view of an exemplary embodiment of a semiconductor module including a semiconductor device as described herein. [Figure 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 4] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 5] 1 is a schematic perspective view of an exemplary embodiment of a semiconductor module including a semiconductor device as described herein. [Figure 6] 1A-1D are schematic cross-sectional views of method steps of an exemplary method for manufacturing a semiconductor device as described herein. [Figure 7] 1A-1D are schematic cross-sectional views of method steps of an exemplary method for manufacturing a semiconductor device as described herein. [Figure 8] 1A-1D are schematic cross-sectional views of method steps of an exemplary method for manufacturing a semiconductor device as described herein. [Figure 9] 1A-1D are schematic cross-sectional views of method steps of an exemplary method for manufacturing a semiconductor device as described herein. [Figure 10] 1A-1D are schematic cross-sectional views of method steps of an exemplary method for manufacturing a semiconductor device as described herein. [Figure 11] 1A-1D are schematic cross-sectional views of method steps of an exemplary method for fabricating a semiconductor device as described herein. [Figure 12] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein. DETAILED DESCRIPTION OF THE INVENTION

[0056] 1 shows an exemplary embodiment of a semiconductor module 10. The semiconductor module 10 comprises a plurality of semiconductor devices 1. By way of example, while only three of the semiconductor devices 1 are shown in FIG. 1, the semiconductor module 10 may comprise many more semiconductor devices 1. For example, if more semiconductor devices 1 are present, they may be arranged in a two-dimensional array, such as a 4×4 array. Although all of the semiconductor devices 1 are of equal design in FIG. 1, it is also possible to combine different types of semiconductor devices 1 in the semiconductor module 10.

[0057] For example, all of the semiconductor devices 1 have second electrodes 62 mounted on a common second power line 72 of the semiconductor module 10. The second power line 72 is, for example, a metal cladding formed on the surface of a circuit board and has a structure such as a metal-insulator-metal substrate. The second power line 72 may be a drain D contact. The first electrode 61 of the semiconductor device 1 located on the side farther from the second power line 72 is electrically connected to the first power line 71, which may be disposed on the circuit board and may be a source S contact. For example, the first power line 71 is connected to the first electrode 61 by a pair of bond wires in each case. In top view, the first electrode 61 may be L-shaped. At a free corner of this L, there is a gate pad 4, which is, for example, realized by a metal cladding in each case.

[0058] All gate pads 4 are interconnected by a bus line 5. The bus line 5 supplies a voltage Vg,bus for the gate G of the semiconductor device 1. The bus line 5 supplies a voltage Ucont for the logic unit 3 of the semiconductor device 1. The bus line 5 can transmit at least one sensor signal Us sent by the semiconductor device 1. The bus line 5 can be realized by a chain of bond wires interconnected by the gate pads 4. Therefore, the bus line 5 can also consist of a single electric wire.

[0059] Optionally, a control unit 9 is present. The control unit 9 may be part of the semiconductor module 10 or may be an exterior component. Furthermore, the control unit 9 may be integrated into at least one of the semiconductor devices 1. The control unit 9 is connected via a bus line 5. The control signal Ucont and the voltage Vg,bus may be generated in or supplied by the control unit 9.

[0060] For example, the fill factor of the semiconductor devices 1 on the second power line 72 is at least 20% or at least 50%, and / or at most 90% or at most 70%. The fill factor is, for example, the ratio of the area of ​​all the semiconductor devices 1 combined to the area coverage within the shortest closed line that surrounds all the semiconductor devices 1, as viewed from above. That is, the semiconductor devices 1 can be arranged relatively closely.

[0061] Some examples of the internal configuration of semiconductor devices 1 are shown in Figures 2-4. In each case, semiconductor devices 1 include a power semiconductor chip 2 having a gate electrode contact region 24 and first and second electrodes 61, 62. Furthermore, semiconductor devices 1 each include a logic unit 3, such as a CMOS device, where CMOS stands for complementary metal-oxide semiconductor. For example, gate pads 4 are disposed completely or partially on the assigned gate electrode contact regions 24.

[0062] The logic units 3 are partially or completely geometrically arranged between the assigned gate pads 4 and the gate electrode contact areas 24. However, it is alternatively possible for the logic units 3 to be arranged outside the space between the pair of gate electrode contact areas 24 and the gate pads 4, and further alternatively or additionally possible for the gate pads 4 not to cover the assigned gate electrode contact areas 24 in top view.

[0063] In addition to what is shown in Figures 1 to 4, the gate pads 4 do not need to be located at the corners of the semiconductor device 1 when viewed from above, but may be located in the center of the power semiconductor chip 2 so that the first electrodes 61 can surround each gate pad 4.

[0064] 2, the logic unit 3 covers only a portion of the gate electrode contact region 24. The logic unit 3 is embedded in an electrically insulating material 81. The electrically insulating material 81 and the logic unit 3 may terminate at the same height on the surface opposite to the power semiconductor chip 2. A gate pad 4 is located on the logic unit 3 and the electrically insulating material 81. The gate pad 4 and the gate electrode contact region 24 may coincide in a top view.

[0065] Besides being shown, it is also possible for the gate pad 4 to be completely disposed on the logic unit 3. Furthermore, the gate pad 4 may be completely located within the gate electrode contact area 24 in a top view, and the gate electrode contact area 24 may be larger than the gate pad 4. Alternatively, the gate pad 4 may be larger than the gate electrode contact area 24 such that the gate electrode contact area 24 can fit within the gate pad 4 in a top view.

[0066] 2, the gate pad 4 may protrude beyond the first electrode 61 in a cross-sectional view, i.e., the thickness of the first electrode 61 may be less than the thickness of the stack of components 24, 3, 4. The second electrode 62 may completely or almost completely cover the side of the power semiconductor chip 2 remote from the logic unit 3.

[0067] According to the embodiment of FIG. 3, the logic unit 3 coincides with the gate electrode contact region 24 in a top view. Therefore, the electrically insulating material 81 of FIG. 2 may be omitted. Also, the stack of the gate electrode contact region 24, the logic unit 3, and the gate pad 4 may have the same thickness as the first electrode 61 so that the gate pad 4 and the first electrode 61 are flush with each other. The gate pad 4 may be disposed completely on top of the logic unit 3. The second electrode 62 on the bottom surface of the power semiconductor chip 2 may not reach the edge of the bottom surface. These modifications are also possible in the semiconductor device 1 of FIG. 2.

[0068] 4, logic unit 3 is disposed along gate electrode contact region 24 so that logic unit 3 and gate electrode contact region 24 do not overlap in top view. Optionally, gate pad 4 is disposed on logic unit 3 as well as on electrically insulating material 81.

[0069] Alternatively, the same applies to Figure 1 as to Figures 2 to 4, and vice versa. The design of the semiconductor device 1 is shown from a manufacturing point of view in Figure 5. On the left side of Figure 5, the power semiconductor chip 2 is shown. The gate electrode contact region 24 and the first electrode 61 may terminate flush in a direction away from the semiconductor body of the power semiconductor chip 2.

[0070] 5, an electrically insulating material 81 is applied over, for example, a power semiconductor chip 2. A logic unit 3 is applied to the electrically insulating material 81. The gate pad 4 is not shown in FIG. 5 for simplicity of the drawing.

[0071] Furthermore, the logic unit 3 and the gate electrode contact region 24 may be connected by one or more electrical feedthroughs 82 through the electrically insulating material 81. Although not shown, there may be a plurality of electrical feedthroughs 82 on the first electrode 61 for connecting the first electrode 61 to the first power line 71, as shown in FIG.

[0072] 6-11 show a method for manufacturing the semiconductor device 1 for the semiconductor module 10 in more detail. According to FIG. 6, a logic unit 3 is provided. The logic unit 3 comprises a first carrier 83, which may be, for example, Si and may be considered a donor. The first carrier 83 is followed by a first insulating layer 84, which may be, for example, a buried oxide layer, such as a silicon dioxide layer. Then, there is a logic unit functional semiconductor layer 85, for example, made of Si. In this layer 85, at least one logic structure 86 is formed. The logic structure 86 may comprise, for example, a plurality of FETs. Finally, on top of the logic structure 86, there is a second insulating layer 87, for example, silicon dioxide.

[0073] As shown in Figure 7, a second carrier 88, such as a silicon processing substrate, is mounted on top of the second insulating layer 87. Next, referring to Figure 8, the first carrier 83 is removed to expose the first insulating layer 84.

[0074] 9, a first bonding layer 89 is applied onto the first insulating layer 84. The first bonding layer 89 is, for example, silicon nitride, and therefore shares major components of the crystal lattices of, for example, SiC and Si of the power semiconductor chip 2 and the logic unit 3, respectively.

[0075] 10, a power semiconductor chip 2 is provided. In this exemplary embodiment, the power semiconductor chip 2 comprises a power chip functional semiconductor layer 27 made of, for example, 4H-SiC. The power chip functional semiconductor layer 27 is provided with a chip structure 26 comprising, for example, transistor units, which are shown only schematically and in a highly simplified manner, as are logic structures 86. For example, the power chip functional semiconductor layer 27 and the chip structure 26 each include a source region, a plug region, a well region, a drift region, a gate insulator, a gate electrode structure, and a first electrode structure portion corresponding to a first electrode 61 (not shown), so that the chip structure 26 can correspond to a FET or an IGBT.

[0076] Optionally, at least one additional semiconductor layer 28, e.g., a buffer layer and a drain or collector layer, is present on the side of the power chip functional semiconductor layer 27 away from the chip structure 26. Furthermore, a second electrode 62, not shown, may be present on the side of the additional semiconductor layer 28.

[0077] The chip structure 26 is covered by an upper insulating layer 25, such as a silicon dioxide layer. The upper insulating layer 25 is followed by a second bonding layer 22. The first and second bonding layers 22, 89 are, for example, made of the same material. These layers 22, 89 will be connected to each other, for example by wafer bonding, at a common interface indicated by the dashed line.

[0078] The resulting semiconductor device 1 is shown in Figure 11. The power semiconductor chip 2 and the logic unit 3 are therefore connected by a total bonding layer 23 consisting of the first and second bonding layers 22, 89.

[0079] 11 does not show the electrical feedthrough 82, the electrodes 61, 62, 24, or the gate pad 4. However, the gate pad 4 and the first electrode 61 may be present on the side of the second insulating layer 87 remote from the chip structure 26, and there may be an electrical feedthrough 82 from the first electrode 61 to the chip structure 26, as well as at least one further electrical feedthrough 82 from the gate pad 4 to the logic structure 86.

[0080] To manufacture the semiconductor module 10, in a further method step not shown, a plurality of semiconductor devices 1 are mounted on a circuit board and the semiconductor devices 1 are interconnected by bus lines 5. Optionally, the semiconductor devices 1 and the bus lines 5 may then be covered, for example with a plastic material, in a casting or molding step.

[0081] Alternatively, the same applies to FIGS. 1 to 5 as to FIGS. 6 to 11, and vice versa. 12 shows an exemplary circuit structure of the semiconductor device 1. For input to the logic unit 3, there is a gate line G that supplies a bus gate voltage Vg,bus as a first voltage and a control signal Ucont as a second voltage. These voltages Vg,bus and Ucont are supplied as a superposition g1. This signal g1 is received by a modulator / demodulator 37 and, optionally, by a switch control 34. The modulator / demodulator 37 extracts the control signal Ucont from the superposition g1, and the value gx is sent to the switch control 34.

[0082] Based on the control signal Ucont, represented by the value gx, the switch control unit 34 adjusts the bus gate voltage Vg,bus to produce a tip gate voltage g2, which may be an attenuated or even amplified version of the superimposed g1, such that the control signal Ucont is still somehow present in the tip gate voltage g2.

[0083] Optionally, the logic unit 3 comprises a sensor 31 that can supply a sensor signal Us to the switch control 34. The tip gate voltage g2 can therefore be a function of both the control signal Ucont and the sensor signal Us via a value gx that can be a voltage value.

[0084] The logic unit 3 is powered by an internal power supply 35, which may for example comprise an auxiliary capacitor Caux and an auxiliary diode Daux providing an auxiliary voltage Uaux. The internal power supply 35 is powered by a bus gate voltage Vg,bus with respect to a source S, which may for example be a ground voltage.

[0085] For example, as in all other embodiments, the power semiconductor chip 2 may be a power FET or power IGBT based on SiC, Si or GaN and may be configured for a current I between the first electrode 61 and the second electrode 62 of, for example, 0.1 kA, corresponding to S and D, at a voltage V of 1.2 kV. The current Iunit through the logic unit 3 is, for example, about 10 mA. The maximum bus gate voltage Vg,bus is, for example, about 15 V. The average voltage of the control signal Ucont is, for example, about 0.1 V.

[0086] Thus, a single-value parameter information, such as a 15V signal, is sent on the gating signal. The demodulator can subtract such signals, perform low-pass filtering, and amplify the resulting signal. Alternatively, multi-value parameter information is added to the gating signal in the form of amplitudes at different frequencies, all of which can be at least an order of magnitude higher than the switching frequency. The demodulator then uses band-pass filtering and rectification to retrieve the original parameter information.

[0087] Optionally, the controller parameters may be dynamically changed during converter operation, for example in response to load changes. As a further option, the controller parameters may be dynamically changed depending on junction temperature, for example during converter start-up in a cold environment, allowing slower switching at low temperatures, reducing switching overvoltages at low temperatures, and increasing the lifetime and / or reliability of the converter.

[0088] 13 shows a more detailed example of a logic unit 3. In this example, the bus gate voltage Vg,bus is adjusted to the chip gate voltage g2 by a variable internal gate resistor RGi. The resistance of the gate resistor RGi is adjusted by a sensor signal UTj, which is representative of the junction temperature Tj of the power semiconductor chip 2, for example, by a sensor 31, which is a temperature-dependent resistor.

[0089] Function F2 converts the temperature dependent resistance of sensor 31 into a voltage, i.e., sensor signal Us. For example, sensor signal Us is supplied to an adder / subtractor 36, which can output a junction temperature deviation ΔUTj that is converted by function F1 into a resistance change Δr applied to switch control 37 and / or internal gate resistor RGi. Alternatively, the switch control 37 may completely absorb the functionality of adder / subtractor 36, and adder / subtractor 36 may be omitted.

[0090] Furthermore, FIG. 13 shows that the sensor signal Us is the output value of the switch control unit 37 onto the bus line 5, so that other semiconductor devices 1 of the semiconductor module 10 can also use the sensor signal Us to adjust their switching behavior.

[0091] Alternatively, the same applies to FIGS. 1 to 11 as to FIGS. 12 to 13, and vice versa.

[0092] Components shown in the figures illustratively follow one another directly above the other in the order indicated, unless otherwise indicated. Components that are not touching in the figures are illustratively spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the drawn components relative to one another are accurately reproduced in the figures.

[0093] It should be noted that the invention described herein is not limited by the description based on the embodiments, but rather the invention encompasses any novel feature and any combination of features, including any combination of features in the claims, even if this feature or this combination itself is not explicitly specified in the claims or exemplary embodiments. [Explanation of symbols]

[0094] Explanation of symbols 1. Semiconductor devices 2. Power semiconductor chips 22 Second bonding layer 23 All bonding layers 24 gate electrode contact area 25 Upper insulating layer 26 Chip structure 27 Power chip functional semiconductor layer 28 Additional Semiconductor Layer 3 Logical Units 31 Sensors 34 Switch control section 35 Internal power supply 36 Adder / Subtractor 37 Modulator / Demodulator 4 Gate Pad 5 Bus Lines 61 First electrode (source electrode or emitter electrode) 62 Second electrode (drain electrode or collector electrode) 71 First power line 72 Second power line 81 Electrical insulating layer 82 Electrical feedthrough joint 83 First Career 84 First insulating layer 85 Logic unit functional semiconductor layer 86 Logical Structures 87 Second insulating layer 88 Second Career 89 First bonding layer 9. Control Unit 10 Semiconductor Module Caux Auxiliary capacitor D Drain Daux auxiliary diode Forex Function G Gate g. Voltage signal Ice Current between the first and second electrodes Ichip power semiconductor chip current Iunit Unit current through the logical unit Rgi Variable Gate Input Resistor Rs Sensor resistor S sauce Tj junction temperature Uaux Auxiliary voltage Ucont control signal Us sensor signal Vce: Voltage between the first and second electrodes Vg,bus Bus gate voltage Δr resistance change ΔUtj Junction temperature deviation

Claims

1. A method of operating a semiconductor module (10), comprising: - providing the semiconductor module (10), the semiconductor module (10) comprising a plurality of power semiconductor devices (1), the power semiconductor devices (1) being arranged adjacent to one another in a top view, and the power semiconductor devices (1) being interconnected by bus lines (5); - controlling the current through said power semiconductor device (1) via a first voltage (Vg,bus) provided by said bus line (5); - supplying a control signal (Ucont) modulated as a second voltage to the modulated first voltage (Vg,bus) via the bus line (5) to the power semiconductor device (1).

2. Each of the power semiconductor devices (1) comprises a power semiconductor chip (2), a logic unit (3), and a gate pad (4); The gate pads (4) are interconnected by the bus lines (5), In each case, the power semiconductor chip (2) comprises a gate electrode contact area (24), 10. The method of claim 9, wherein in each case the logic unit (3) is electrically disposed between the gate electrode contact region (24) and the gate pad (4).

3. The power semiconductor chips (2) are each selected from the group consisting of a metal-insulator-semiconductor field effect transistor, a MISFET, a metal-oxide-semiconductor field effect transistor, a MOSFET, an insulated gate bipolar transistor, an IGBT, a reverse conducting insulated gate bipolar transistor, and a RC-IGBT; Each of the power semiconductor chips (2) is configured such that a voltage (Vce) between the first electrode (61) and the second electrode (61) of the power semiconductor chip (2) is at least 0.6 kV and at most 15 kV, and further such that a current (Ice) between the first electrode (61) and the second electrode (62) is at least 1 A; 10. The method of claim 9, wherein in each case the first electrode (61) is a source electrode or an emitter electrode and the second electrode (62) is a drain electrode or a collector electrode of the respective power semiconductor chip (2).

4. - in each one of said power semiconductor devices (1), said logic unit (3) is geometrically arranged partially between said gate electrode contact area (24) and said gate pad (4), The method according to any one of the two preceding claims, wherein the bus line (5) supplies a bus gate voltage as the first voltage (Vg,bus) to all the power semiconductor devices (1) simultaneously.

5. The method according to any one of claims 2 to 4, wherein said bus line (5) consists of a single line and is the only direct electrical interconnection between all said gate pads (4).

6. 6. The method according to claim 2, wherein in a top view of the power semiconductor device (1), in each case the logic unit (3) is smaller than or equal to the dimensions of the gate pad (4), and the gate pad (4) completely covers the logic unit (3).

7. 10. A method according to any one of the preceding claims, wherein, on time average, the second voltage (Us) is at most 1% of the first voltage (Vg,bus).

8. 10. A method according to any one of the preceding claims, wherein the second voltage (Us) is at most 0.2V and the first voltage (Vg,bus) has a peak voltage of at least 3V and at most 30V.

9. 10. The method according to any one of the preceding claims, wherein the power semiconductor device (1) receives and transmits signals via the bus line (5) such that bidirectional communication takes place via the bus line (5).

10. The semiconductor module (10) further includes at least one control unit (9) external to the power semiconductor device (1), or the bus line (5) of the semiconductor module (10) is connected to at least one external control unit (9); 10. The method according to any one of the preceding claims, wherein said at least one control unit (9) provides said control signal (Ucont).

11. The method according to any one of the preceding claims, wherein at least one of the power semiconductor devices (1) supplies the control signal (Ucont) to all other power semiconductor devices (1).

12. - each of said logic units (23) comprises a demodulator (37) for receiving a superposition (g1) of said first and second voltages (Vg, bus, Ucont) and for demodulating from said superposition (g1) a control voltage signal (gx) corresponding to the second voltage (Ucont); - each of said logic units (23) comprises a switch control (34) receiving said control voltage signal (gx) from said demodulator (37); - said logic units (23) each comprise a sensor (31), said switch control (34) receiving a sensor signal from said sensor (31); The method according to any one of the preceding claims, wherein the switch control unit (34) outputs a chip gate voltage (g2) to the gate of each of the power semiconductor chips (2) based on the control voltage signal (gx) and the sensor signal (Us).

13. 10. The method of claim 9, wherein the tip gate voltage (g2) still comprises the second voltage (Ucont).

14. 10. The method according to claim 1, wherein the sensor (31) is a temperature sensor and the switch control unit (34) controls the switching behavior of the gate of each of the power semiconductor chips (2) so that the junction temperatures of the power semiconductor chips (2) are all the same with a tolerance of up to 10 K.

15. A semiconductor module (10), a plurality of power semiconductor devices (1), the power semiconductor devices (1) being arranged adjacent to one another in a top view; a bus line (5) interconnecting all said power semiconductor devices (1), the power semiconductor devices (1) are configured to receive a superposition (g1) of a first voltage (Vg,bus) and a second voltage (Ucont), the superposition (g1) being provided by the bus line (5), the first voltage (Vg,bus) controlling the current through each of the power semiconductor devices (1) and the second voltage (Ucont) adjusting the switching behavior of each of the power semiconductor devices (1); A semiconductor module (10) configured to perform a method according to any one of the preceding claims, wherein each of the power semiconductor devices (1) is configured to demodulate a control signal (Ucont) from the superposition (g1).

16. A method for manufacturing a semiconductor module (10) according to the preceding claim, adapted for the method according to claim 2, said method comprising: - providing said power semiconductor chip (2) and said logic unit (3), - in each case bonding one logic unit (3) to the assigned power semiconductor chip (2), in particular by wafer bonding; - implementing in each case one gate pad (4) across each of said logic units (3); - mounting said power semiconductor devices (1) on a common carrier (72); interconnecting said gate pads (4) via said bus lines (5).

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