Semiconductor memory device

Abstract

To improve the yield of a semiconductor memory device.SOLUTION: The semiconductor memory device 3 according to the embodiment includes the interconnect layer 21, the plurality of interconnect layers 23, and the plurality of interconnect layers 24 which are provided so as to overlap in this order in the Z direction across the lead area HA and the memory area MA1 arranged in the X direction, the lead area HA includes the lead areas HA1 and HA2 arranged in the Y direction, and the plurality of interconnect layers 23 are provided so as not to overlap the upper interconnect layer 23 in the Z direction in the lead area HA2. For example, the plurality of interconnect layers 24 include a plurality of terrace portions, one of which is connected to the first contact CC, and a bridge portion HA1 extending in the Y direction in the hookup area BRG2, and the plurality of interconnect layers 24 are provided so as not to overlap the upper interconnect layers 24 in the Z direction in the hookup area HA1, and include a plurality of terrace portions, one of which is connected to the second contact CC, and a bridge portion HA2 extending in the Y direction in the hookup area BRG1.SELECTED DRAWING: Figure 15

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